projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge commit 'v2.6.34-rc2' into perf/core
[linux-2.6-block.git] / drivers / net / e100.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/100 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
05479938
JB		 5
6 This program is free software; you can redistribute it and/or modify it
0abb6eb1
AK		 7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
05479938 9
0abb6eb1 10 This program is distributed in the hope it will be useful, but WITHOUT
05479938
JB		 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
05479938 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
05479938 18
0abb6eb1
AK		 19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
05479938 21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
0abb6eb1 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
0a0863af 97 * IV. Receive
1da177e4
LT		 98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
7734f6e6
DA		 109 * In order to keep updates to the RFD link field from colliding with
110 * hardware writes to mark packets complete, we use the feature that
111 * hardware will not write to a size 0 descriptor and mark the previous
112 * packet as end-of-list (EL). After updating the link, we remove EL
113 * and only then restore the size such that hardware may use the
114 * previous-to-end RFD.
115 *
1da177e4
LT		 116 * Under typical operation, the receive unit (RU) is start once,
117 * and the controller happily fills RFDs as frames arrive. If
118 * replacement RFDs cannot be allocated, or the RU goes non-active,
119 * the RU must be restarted. Frame arrival generates an interrupt,
120 * and Rx indication and re-allocation happen in the same context,
121 * therefore no locking is required. A software-generated interrupt
122 * is generated from the watchdog to recover from a failed allocation
0a0863af 123 * scenario where all Rx resources have been indicated and none re-
1da177e4
LT		 124 * placed.
125 *
126 * V. Miscellaneous
127 *
128 * VLAN offloading of tagging, stripping and filtering is not
129 * supported, but driver will accommodate the extra 4-byte VLAN tag
130 * for processing by upper layers. Tx/Rx Checksum offloading is not
131 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
132 * not supported (hardware limitation).
133 *
134 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
135 *
136 * Thanks to JC (jchapman@katalix.com) for helping with
137 * testing/troubleshooting the development driver.
138 *
139 * TODO:
140 * o several entry points race with dev->close
141 * o check for tx-no-resources/stop Q races with tx clean/wake Q
ac7c6669
OM		 142 *
143 * FIXES:
144 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
145 * - Stratus87247: protect MDI control register manipulations
72001762
AM		 146 * 2009/06/01 - Andreas Mohr <andi at lisas dot de>
147 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs
1da177e4
LT		 148 */
149
1da177e4
LT		 150#include <linux/module.h>
151#include <linux/moduleparam.h>
152#include <linux/kernel.h>
153#include <linux/types.h>
d43c36dc 154#include <linux/sched.h>
1da177e4
LT		 155#include <linux/slab.h>
156#include <linux/delay.h>
157#include <linux/init.h>
158#include <linux/pci.h>
1e7f0bd8 159#include <linux/dma-mapping.h>
98468efd 160#include <linux/dmapool.h>
1da177e4
LT		 161#include <linux/netdevice.h>
162#include <linux/etherdevice.h>
163#include <linux/mii.h>
164#include <linux/if_vlan.h>
165#include <linux/skbuff.h>
166#include <linux/ethtool.h>
167#include <linux/string.h>
9ac32e1b 168#include <linux/firmware.h>
1da177e4
LT		 169#include <asm/unaligned.h>
170
171
172#define DRV_NAME "e100"
4e1dc97d 173#define DRV_EXT "-NAPI"
b55de80e 174#define DRV_VERSION "3.5.24-k2"DRV_EXT
1da177e4 175#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
4e1dc97d 176#define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
1da177e4
LT		 177#define PFX DRV_NAME ": "
178
179#define E100_WATCHDOG_PERIOD (2 * HZ)
180#define E100_NAPI_WEIGHT 16
181
9ac32e1b
JSR		 182#define FIRMWARE_D101M "e100/d101m_ucode.bin"
183#define FIRMWARE_D101S "e100/d101s_ucode.bin"
184#define FIRMWARE_D102E "e100/d102e_ucode.bin"
185
1da177e4
LT		 186MODULE_DESCRIPTION(DRV_DESCRIPTION);
187MODULE_AUTHOR(DRV_COPYRIGHT);
188MODULE_LICENSE("GPL");
189MODULE_VERSION(DRV_VERSION);
9ac32e1b
JSR		 190MODULE_FIRMWARE(FIRMWARE_D101M);
191MODULE_FIRMWARE(FIRMWARE_D101S);
192MODULE_FIRMWARE(FIRMWARE_D102E);
1da177e4
LT		 193
194static int debug = 3;
8fb6f732 195static int eeprom_bad_csum_allow = 0;
27345bb6 196static int use_io = 0;
1da177e4 197module_param(debug, int, 0);
8fb6f732 198module_param(eeprom_bad_csum_allow, int, 0);
27345bb6 199module_param(use_io, int, 0);
1da177e4 200MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
8fb6f732 201MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
27345bb6 202MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
1da177e4
LT		 203#define DPRINTK(nlevel, klevel, fmt, args...) \
204 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
205 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
b39d66a8 206 __func__ , ## args))
1da177e4
LT		 207
208#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
209 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
210 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
a3aa1884 211static DEFINE_PCI_DEVICE_TABLE(e100_id_table) = {
1da177e4
LT		 212 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
213 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
214 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
215 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
216 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
217 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
218 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
219 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
220 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
221 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
222 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
223 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
224 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
225 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
226 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
227 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
228 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
229 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
230 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
231 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
232 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
233 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
234 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
235 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
236 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
237 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
238 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
239 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
240 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
241 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
042e2fb7
MC		 242 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
243 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
244 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
245 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
246 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
b55de80e 247 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
1da177e4
LT		 248 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
249 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
250 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
251 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
252 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
042e2fb7 253 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
1da177e4
LT		 254 { 0, }
255};
256MODULE_DEVICE_TABLE(pci, e100_id_table);
257
258enum mac {
259 mac_82557_D100_A = 0,
260 mac_82557_D100_B = 1,
261 mac_82557_D100_C = 2,
262 mac_82558_D101_A4 = 4,
263 mac_82558_D101_B0 = 5,
264 mac_82559_D101M = 8,
265 mac_82559_D101S = 9,
266 mac_82550_D102 = 12,
267 mac_82550_D102_C = 13,
268 mac_82551_E = 14,
269 mac_82551_F = 15,
270 mac_82551_10 = 16,
271 mac_unknown = 0xFF,
272};
273
274enum phy {
275 phy_100a = 0x000003E0,
276 phy_100c = 0x035002A8,
277 phy_82555_tx = 0x015002A8,
278 phy_nsc_tx = 0x5C002000,
279 phy_82562_et = 0x033002A8,
280 phy_82562_em = 0x032002A8,
281 phy_82562_ek = 0x031002A8,
282 phy_82562_eh = 0x017002A8,
b55de80e 283 phy_82552_v = 0xd061004d,
1da177e4
LT		 284 phy_unknown = 0xFFFFFFFF,
285};
286
287/* CSR (Control/Status Registers) */
288struct csr {
289 struct {
290 u8 status;
291 u8 stat_ack;
292 u8 cmd_lo;
293 u8 cmd_hi;
294 u32 gen_ptr;
295 } scb;
296 u32 port;
297 u16 flash_ctrl;
298 u8 eeprom_ctrl_lo;
299 u8 eeprom_ctrl_hi;
300 u32 mdi_ctrl;
301 u32 rx_dma_count;
302};
303
304enum scb_status {
7734f6e6 305 rus_no_res = 0x08,
1da177e4
LT		 306 rus_ready = 0x10,
307 rus_mask = 0x3C,
308};
309
ca93ca42
JG		 310enum ru_state {
311 RU_SUSPENDED = 0,
312 RU_RUNNING = 1,
313 RU_UNINITIALIZED = -1,
314};
315
1da177e4
LT		 316enum scb_stat_ack {
317 stat_ack_not_ours = 0x00,
318 stat_ack_sw_gen = 0x04,
319 stat_ack_rnr = 0x10,
320 stat_ack_cu_idle = 0x20,
321 stat_ack_frame_rx = 0x40,
322 stat_ack_cu_cmd_done = 0x80,
323 stat_ack_not_present = 0xFF,
324 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
325 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
326};
327
328enum scb_cmd_hi {
329 irq_mask_none = 0x00,
330 irq_mask_all = 0x01,
331 irq_sw_gen = 0x02,
332};
333
334enum scb_cmd_lo {
335 cuc_nop = 0x00,
336 ruc_start = 0x01,
337 ruc_load_base = 0x06,
338 cuc_start = 0x10,
339 cuc_resume = 0x20,
340 cuc_dump_addr = 0x40,
341 cuc_dump_stats = 0x50,
342 cuc_load_base = 0x60,
343 cuc_dump_reset = 0x70,
344};
345
346enum cuc_dump {
347 cuc_dump_complete = 0x0000A005,
348 cuc_dump_reset_complete = 0x0000A007,
349};
05479938 350
1da177e4
LT		 351enum port {
352 software_reset = 0x0000,
353 selftest = 0x0001,
354 selective_reset = 0x0002,
355};
356
357enum eeprom_ctrl_lo {
358 eesk = 0x01,
359 eecs = 0x02,
360 eedi = 0x04,
361 eedo = 0x08,
362};
363
364enum mdi_ctrl {
365 mdi_write = 0x04000000,
366 mdi_read = 0x08000000,
367 mdi_ready = 0x10000000,
368};
369
370enum eeprom_op {
371 op_write = 0x05,
372 op_read = 0x06,
373 op_ewds = 0x10,
374 op_ewen = 0x13,
375};
376
377enum eeprom_offsets {
378 eeprom_cnfg_mdix = 0x03,
72001762 379 eeprom_phy_iface = 0x06,
1da177e4
LT		 380 eeprom_id = 0x0A,
381 eeprom_config_asf = 0x0D,
382 eeprom_smbus_addr = 0x90,
383};
384
385enum eeprom_cnfg_mdix {
386 eeprom_mdix_enabled = 0x0080,
387};
388
72001762
AM		 389enum eeprom_phy_iface {
390 NoSuchPhy = 0,
391 I82553AB,
392 I82553C,
393 I82503,
394 DP83840,
395 S80C240,
396 S80C24,
397 I82555,
398 DP83840A = 10,
399};
400
1da177e4
LT		 401enum eeprom_id {
402 eeprom_id_wol = 0x0020,
403};
404
405enum eeprom_config_asf {
406 eeprom_asf = 0x8000,
407 eeprom_gcl = 0x4000,
408};
409
410enum cb_status {
411 cb_complete = 0x8000,
412 cb_ok = 0x2000,
413};
414
415enum cb_command {
416 cb_nop = 0x0000,
417 cb_iaaddr = 0x0001,
418 cb_config = 0x0002,
419 cb_multi = 0x0003,
420 cb_tx = 0x0004,
421 cb_ucode = 0x0005,
422 cb_dump = 0x0006,
423 cb_tx_sf = 0x0008,
424 cb_cid = 0x1f00,
425 cb_i = 0x2000,
426 cb_s = 0x4000,
427 cb_el = 0x8000,
428};
429
430struct rfd {
aaf918ba
AV		 431 __le16 status;
432 __le16 command;
433 __le32 link;
434 __le32 rbd;
435 __le16 actual_size;
436 __le16 size;
1da177e4
LT		 437};
438
439struct rx {
440 struct rx *next, *prev;
441 struct sk_buff *skb;
442 dma_addr_t dma_addr;
443};
444
445#if defined(__BIG_ENDIAN_BITFIELD)
446#define X(a,b) b,a
447#else
448#define X(a,b) a,b
449#endif
450struct config {
451/*0*/ u8 X(byte_count:6, pad0:2);
452/*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
453/*2*/ u8 adaptive_ifs;
454/*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
455 term_write_cache_line:1), pad3:4);
456/*4*/ u8 X(rx_dma_max_count:7, pad4:1);
457/*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
458/*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
459 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
460 rx_discard_overruns:1), rx_save_bad_frames:1);
461/*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
462 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
463 tx_dynamic_tbd:1);
464/*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
465/*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
466 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
467/*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
468 loopback:2);
469/*11*/ u8 X(linear_priority:3, pad11:5);
470/*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
471/*13*/ u8 ip_addr_lo;
472/*14*/ u8 ip_addr_hi;
473/*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
474 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
475 pad15_2:1), crs_or_cdt:1);
476/*16*/ u8 fc_delay_lo;
477/*17*/ u8 fc_delay_hi;
478/*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
479 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
480/*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
481 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
482 full_duplex_force:1), full_duplex_pin:1);
483/*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
484/*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
485/*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
486 u8 pad_d102[9];
487};
488
489#define E100_MAX_MULTICAST_ADDRS 64
490struct multi {
aaf918ba 491 __le16 count;
1da177e4
LT		 492 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
493};
494
495/* Important: keep total struct u32-aligned */
496#define UCODE_SIZE 134
497struct cb {
aaf918ba
AV		 498 __le16 status;
499 __le16 command;
500 __le32 link;
1da177e4
LT		 501 union {
502 u8 iaaddr[ETH_ALEN];
aaf918ba 503 __le32 ucode[UCODE_SIZE];
1da177e4
LT		 504 struct config config;
505 struct multi multi;
506 struct {
507 u32 tbd_array;
508 u16 tcb_byte_count;
509 u8 threshold;
510 u8 tbd_count;
511 struct {
aaf918ba
AV		 512 __le32 buf_addr;
513 __le16 size;
1da177e4
LT		 514 u16 eol;
515 } tbd;
516 } tcb;
aaf918ba 517 __le32 dump_buffer_addr;
1da177e4
LT		 518 } u;
519 struct cb *next, *prev;
520 dma_addr_t dma_addr;
521 struct sk_buff *skb;
522};
523
524enum loopback {
525 lb_none = 0, lb_mac = 1, lb_phy = 3,
526};
527
528struct stats {
aaf918ba 529 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
1da177e4
LT		 530 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
531 tx_multiple_collisions, tx_total_collisions;
aaf918ba 532 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
1da177e4
LT		 533 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
534 rx_short_frame_errors;
aaf918ba
AV		 535 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
536 __le16 xmt_tco_frames, rcv_tco_frames;
537 __le32 complete;
1da177e4
LT		 538};
539
540struct mem {
541 struct {
542 u32 signature;
543 u32 result;
544 } selftest;
545 struct stats stats;
546 u8 dump_buf[596];
547};
548
549struct param_range {
550 u32 min;
551 u32 max;
552 u32 count;
553};
554
555struct params {
556 struct param_range rfds;
557 struct param_range cbs;
558};
559
560struct nic {
561 /* Begin: frequently used values: keep adjacent for cache effect */
562 u32 msg_enable ____cacheline_aligned;
563 struct net_device *netdev;
564 struct pci_dev *pdev;
72001762 565 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
1da177e4
LT		 566
567 struct rx *rxs ____cacheline_aligned;
568 struct rx *rx_to_use;
569 struct rx *rx_to_clean;
570 struct rfd blank_rfd;
ca93ca42 571 enum ru_state ru_running;
1da177e4
LT		 572
573 spinlock_t cb_lock ____cacheline_aligned;
574 spinlock_t cmd_lock;
575 struct csr __iomem *csr;
576 enum scb_cmd_lo cuc_cmd;
577 unsigned int cbs_avail;
bea3348e 578 struct napi_struct napi;
1da177e4
LT		 579 struct cb *cbs;
580 struct cb *cb_to_use;
581 struct cb *cb_to_send;
582 struct cb *cb_to_clean;
aaf918ba 583 __le16 tx_command;
1da177e4
LT		 584 /* End: frequently used values: keep adjacent for cache effect */
585
586 enum {
587 ich = (1 << 0),
588 promiscuous = (1 << 1),
589 multicast_all = (1 << 2),
590 wol_magic = (1 << 3),
591 ich_10h_workaround = (1 << 4),
592 } flags ____cacheline_aligned;
593
594 enum mac mac;
595 enum phy phy;
596 struct params params;
1da177e4
LT		 597 struct timer_list watchdog;
598 struct timer_list blink_timer;
599 struct mii_if_info mii;
2acdb1e0 600 struct work_struct tx_timeout_task;
1da177e4
LT		 601 enum loopback loopback;
602
603 struct mem *mem;
604 dma_addr_t dma_addr;
605
98468efd 606 struct pci_pool *cbs_pool;
1da177e4
LT		 607 dma_addr_t cbs_dma_addr;
608 u8 adaptive_ifs;
609 u8 tx_threshold;
610 u32 tx_frames;
611 u32 tx_collisions;
612 u32 tx_deferred;
613 u32 tx_single_collisions;
614 u32 tx_multiple_collisions;
615 u32 tx_fc_pause;
616 u32 tx_tco_frames;
617
618 u32 rx_fc_pause;
619 u32 rx_fc_unsupported;
620 u32 rx_tco_frames;
621 u32 rx_over_length_errors;
622
1da177e4
LT		 623 u16 leds;
624 u16 eeprom_wc;
aaf918ba 625 __le16 eeprom[256];
ac7c6669 626 spinlock_t mdio_lock;
7e15b0c9 627 const struct firmware *fw;
1da177e4
LT		 628};
629
630static inline void e100_write_flush(struct nic *nic)
631{
632 /* Flush previous PCI writes through intermediate bridges
633 * by doing a benign read */
27345bb6 634 (void)ioread8(&nic->csr->scb.status);
1da177e4
LT		 635}
636
858119e1 637static void e100_enable_irq(struct nic *nic)
1da177e4
LT		 638{
639 unsigned long flags;
640
641 spin_lock_irqsave(&nic->cmd_lock, flags);
27345bb6 642 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
1da177e4 643 e100_write_flush(nic);
ad8c48ad 644 spin_unlock_irqrestore(&nic->cmd_lock, flags);
1da177e4
LT		 645}
646
858119e1 647static void e100_disable_irq(struct nic *nic)
1da177e4
LT		 648{
649 unsigned long flags;
650
651 spin_lock_irqsave(&nic->cmd_lock, flags);
27345bb6 652 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
1da177e4 653 e100_write_flush(nic);
ad8c48ad 654 spin_unlock_irqrestore(&nic->cmd_lock, flags);
1da177e4
LT		 655}
656
657static void e100_hw_reset(struct nic *nic)
658{
659 /* Put CU and RU into idle with a selective reset to get
660 * device off of PCI bus */
27345bb6 661 iowrite32(selective_reset, &nic->csr->port);
1da177e4
LT		 662 e100_write_flush(nic); udelay(20);
663
664 /* Now fully reset device */
27345bb6 665 iowrite32(software_reset, &nic->csr->port);
1da177e4
LT		 666 e100_write_flush(nic); udelay(20);
667
668 /* Mask off our interrupt line - it's unmasked after reset */
669 e100_disable_irq(nic);
670}
671
672static int e100_self_test(struct nic *nic)
673{
674 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
675
676 /* Passing the self-test is a pretty good indication
677 * that the device can DMA to/from host memory */
678
679 nic->mem->selftest.signature = 0;
680 nic->mem->selftest.result = 0xFFFFFFFF;
681
27345bb6 682 iowrite32(selftest | dma_addr, &nic->csr->port);
1da177e4
LT		 683 e100_write_flush(nic);
684 /* Wait 10 msec for self-test to complete */
685 msleep(10);
686
687 /* Interrupts are enabled after self-test */
688 e100_disable_irq(nic);
689
690 /* Check results of self-test */
f26251eb 691 if (nic->mem->selftest.result != 0) {
1da177e4
LT		 692 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
693 nic->mem->selftest.result);
694 return -ETIMEDOUT;
695 }
f26251eb 696 if (nic->mem->selftest.signature == 0) {
1da177e4
LT		 697 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
698 return -ETIMEDOUT;
699 }
700
701 return 0;
702}
703
aaf918ba 704static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
1da177e4
LT		 705{
706 u32 cmd_addr_data[3];
707 u8 ctrl;
708 int i, j;
709
710 /* Three cmds: write/erase enable, write data, write/erase disable */
711 cmd_addr_data[0] = op_ewen << (addr_len - 2);
712 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
aaf918ba 713 le16_to_cpu(data);
1da177e4
LT		 714 cmd_addr_data[2] = op_ewds << (addr_len - 2);
715
716 /* Bit-bang cmds to write word to eeprom */
f26251eb 717 for (j = 0; j < 3; j++) {
1da177e4
LT		 718
719 /* Chip select */
27345bb6 720 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 721 e100_write_flush(nic); udelay(4);
722
f26251eb 723 for (i = 31; i >= 0; i--) {
1da177e4
LT		 724 ctrl = (cmd_addr_data[j] & (1 << i)) ?
725 eecs | eedi : eecs;
27345bb6 726 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 727 e100_write_flush(nic); udelay(4);
728
27345bb6 729 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 730 e100_write_flush(nic); udelay(4);
731 }
732 /* Wait 10 msec for cmd to complete */
733 msleep(10);
734
735 /* Chip deselect */
27345bb6 736 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 737 e100_write_flush(nic); udelay(4);
738 }
739};
740
741/* General technique stolen from the eepro100 driver - very clever */
aaf918ba 742static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
1da177e4
LT		 743{
744 u32 cmd_addr_data;
745 u16 data = 0;
746 u8 ctrl;
747 int i;
748
749 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
750
751 /* Chip select */
27345bb6 752 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 753 e100_write_flush(nic); udelay(4);
754
755 /* Bit-bang to read word from eeprom */
f26251eb 756 for (i = 31; i >= 0; i--) {
1da177e4 757 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
27345bb6 758 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
1da177e4 759 e100_write_flush(nic); udelay(4);
05479938 760
27345bb6 761 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
1da177e4 762 e100_write_flush(nic); udelay(4);
05479938 763
1da177e4
LT		 764 /* Eeprom drives a dummy zero to EEDO after receiving
765 * complete address. Use this to adjust addr_len. */
27345bb6 766 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
f26251eb 767 if (!(ctrl & eedo) && i > 16) {
1da177e4
LT		 768 *addr_len -= (i - 16);
769 i = 17;
770 }
05479938 771
1da177e4
LT		 772 data = (data << 1) | (ctrl & eedo ? 1 : 0);
773 }
774
775 /* Chip deselect */
27345bb6 776 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 777 e100_write_flush(nic); udelay(4);
778
aaf918ba 779 return cpu_to_le16(data);
1da177e4
LT		 780};
781
782/* Load entire EEPROM image into driver cache and validate checksum */
783static int e100_eeprom_load(struct nic *nic)
784{
785 u16 addr, addr_len = 8, checksum = 0;
786
787 /* Try reading with an 8-bit addr len to discover actual addr len */
788 e100_eeprom_read(nic, &addr_len, 0);
789 nic->eeprom_wc = 1 << addr_len;
790
f26251eb 791 for (addr = 0; addr < nic->eeprom_wc; addr++) {
1da177e4 792 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
f26251eb 793 if (addr < nic->eeprom_wc - 1)
aaf918ba 794 checksum += le16_to_cpu(nic->eeprom[addr]);
1da177e4
LT		 795 }
796
797 /* The checksum, stored in the last word, is calculated such that
798 * the sum of words should be 0xBABA */
aaf918ba 799 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
1da177e4 800 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
8fb6f732
DM		 801 if (!eeprom_bad_csum_allow)
802 return -EAGAIN;
1da177e4
LT		 803 }
804
805 return 0;
806}
807
808/* Save (portion of) driver EEPROM cache to device and update checksum */
809static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
810{
811 u16 addr, addr_len = 8, checksum = 0;
812
813 /* Try reading with an 8-bit addr len to discover actual addr len */
814 e100_eeprom_read(nic, &addr_len, 0);
815 nic->eeprom_wc = 1 << addr_len;
816
f26251eb 817 if (start + count >= nic->eeprom_wc)
1da177e4
LT		 818 return -EINVAL;
819
f26251eb 820 for (addr = start; addr < start + count; addr++)
1da177e4
LT		 821 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
822
823 /* The checksum, stored in the last word, is calculated such that
824 * the sum of words should be 0xBABA */
f26251eb 825 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
aaf918ba
AV		 826 checksum += le16_to_cpu(nic->eeprom[addr]);
827 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
1da177e4
LT		 828 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
829 nic->eeprom[nic->eeprom_wc - 1]);
830
831 return 0;
832}
833
962082b6 834#define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
e6280f26 835#define E100_WAIT_SCB_FAST 20 /* delay like the old code */
858119e1 836static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
1da177e4
LT		 837{
838 unsigned long flags;
839 unsigned int i;
840 int err = 0;
841
842 spin_lock_irqsave(&nic->cmd_lock, flags);
843
844 /* Previous command is accepted when SCB clears */
f26251eb
BA		 845 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
846 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
1da177e4
LT		 847 break;
848 cpu_relax();
f26251eb 849 if (unlikely(i > E100_WAIT_SCB_FAST))
1da177e4
LT		 850 udelay(5);
851 }
f26251eb 852 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
1da177e4
LT		 853 err = -EAGAIN;
854 goto err_unlock;
855 }
856
f26251eb 857 if (unlikely(cmd != cuc_resume))
27345bb6
JB		 858 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
859 iowrite8(cmd, &nic->csr->scb.cmd_lo);
1da177e4
LT		 860
861err_unlock:
862 spin_unlock_irqrestore(&nic->cmd_lock, flags);
863
864 return err;
865}
866
858119e1 867static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
1da177e4
LT		 868 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
869{
870 struct cb *cb;
871 unsigned long flags;
872 int err = 0;
873
874 spin_lock_irqsave(&nic->cb_lock, flags);
875
f26251eb 876 if (unlikely(!nic->cbs_avail)) {
1da177e4
LT		 877 err = -ENOMEM;
878 goto err_unlock;
879 }
880
881 cb = nic->cb_to_use;
882 nic->cb_to_use = cb->next;
883 nic->cbs_avail--;
884 cb->skb = skb;
885
f26251eb 886 if (unlikely(!nic->cbs_avail))
1da177e4
LT		 887 err = -ENOSPC;
888
889 cb_prepare(nic, cb, skb);
890
891 /* Order is important otherwise we'll be in a race with h/w:
892 * set S-bit in current first, then clear S-bit in previous. */
893 cb->command |= cpu_to_le16(cb_s);
894 wmb();
895 cb->prev->command &= cpu_to_le16(~cb_s);
896
f26251eb
BA		 897 while (nic->cb_to_send != nic->cb_to_use) {
898 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
1da177e4
LT		 899 nic->cb_to_send->dma_addr))) {
900 /* Ok, here's where things get sticky. It's
901 * possible that we can't schedule the command
902 * because the controller is too busy, so
903 * let's just queue the command and try again
904 * when another command is scheduled. */
f26251eb 905 if (err == -ENOSPC) {
962082b6
MC		 906 //request a reset
907 schedule_work(&nic->tx_timeout_task);
908 }
1da177e4
LT		 909 break;
910 } else {
911 nic->cuc_cmd = cuc_resume;
912 nic->cb_to_send = nic->cb_to_send->next;
913 }
914 }
915
916err_unlock:
917 spin_unlock_irqrestore(&nic->cb_lock, flags);
918
919 return err;
920}
921
72001762
AM		 922static int mdio_read(struct net_device *netdev, int addr, int reg)
923{
924 struct nic *nic = netdev_priv(netdev);
925 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
926}
927
928static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
929{
930 struct nic *nic = netdev_priv(netdev);
931
932 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
933}
934
935/* the standard mdio_ctrl() function for usual MII-compliant hardware */
936static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
1da177e4
LT		 937{
938 u32 data_out = 0;
939 unsigned int i;
ac7c6669 940 unsigned long flags;
1da177e4 941
ac7c6669
OM		 942
943 /*
944 * Stratus87247: we shouldn't be writing the MDI control
945 * register until the Ready bit shows True. Also, since
946 * manipulation of the MDI control registers is a multi-step
947 * procedure it should be done under lock.
948 */
949 spin_lock_irqsave(&nic->mdio_lock, flags);
950 for (i = 100; i; --i) {
27345bb6 951 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
ac7c6669
OM		 952 break;
953 udelay(20);
954 }
955 if (unlikely(!i)) {
956 printk("e100.mdio_ctrl(%s) won't go Ready\n",
957 nic->netdev->name );
958 spin_unlock_irqrestore(&nic->mdio_lock, flags);
959 return 0; /* No way to indicate timeout error */
960 }
27345bb6 961 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
1da177e4 962
ac7c6669 963 for (i = 0; i < 100; i++) {
1da177e4 964 udelay(20);
27345bb6 965 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
1da177e4
LT		 966 break;
967 }
ac7c6669 968 spin_unlock_irqrestore(&nic->mdio_lock, flags);
1da177e4
LT		 969 DPRINTK(HW, DEBUG,
970 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
971 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
972 return (u16)data_out;
973}
974
72001762
AM		 975/* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */
976static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
977 u32 addr,
978 u32 dir,
979 u32 reg,
980 u16 data)
981{
982 if ((reg == MII_BMCR) && (dir == mdi_write)) {
983 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
984 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id,
985 MII_ADVERTISE);
986
987 /*
988 * Workaround Si issue where sometimes the part will not
989 * autoneg to 100Mbps even when advertised.
990 */
991 if (advert & ADVERTISE_100FULL)
992 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
993 else if (advert & ADVERTISE_100HALF)
994 data |= BMCR_SPEED100;
995 }
996 }
997 return mdio_ctrl_hw(nic, addr, dir, reg, data);
1da177e4
LT		 998}
999
72001762
AM		 1000/* Fully software-emulated mdio_ctrl() function for cards without
1001 * MII-compliant PHYs.
1002 * For now, this is mainly geared towards 80c24 support; in case of further
1003 * requirements for other types (i82503, ...?) either extend this mechanism
1004 * or split it, whichever is cleaner.
1005 */
1006static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
1007 u32 addr,
1008 u32 dir,
1009 u32 reg,
1010 u16 data)
1011{
1012 /* might need to allocate a netdev_priv'ed register array eventually
1013 * to be able to record state changes, but for now
1014 * some fully hardcoded register handling ought to be ok I guess. */
1015
1016 if (dir == mdi_read) {
1017 switch (reg) {
1018 case MII_BMCR:
1019 /* Auto-negotiation, right? */
1020 return BMCR_ANENABLE |
1021 BMCR_FULLDPLX;
1022 case MII_BMSR:
1023 return BMSR_LSTATUS /* for mii_link_ok() */ |
1024 BMSR_ANEGCAPABLE |
1025 BMSR_10FULL;
1026 case MII_ADVERTISE:
1027 /* 80c24 is a "combo card" PHY, right? */
1028 return ADVERTISE_10HALF |
1029 ADVERTISE_10FULL;
1030 default:
1031 DPRINTK(HW, DEBUG,
1032 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1033 dir == mdi_read ? "READ" : "WRITE", addr, reg, data);
1034 return 0xFFFF;
1035 }
1036 } else {
1037 switch (reg) {
1038 default:
1039 DPRINTK(HW, DEBUG,
1040 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1041 dir == mdi_read ? "READ" : "WRITE", addr, reg, data);
1042 return 0xFFFF;
1043 }
b55de80e 1044 }
72001762
AM		 1045}
1046static inline int e100_phy_supports_mii(struct nic *nic)
1047{
1048 /* for now, just check it by comparing whether we
1049 are using MII software emulation.
1050 */
1051 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1da177e4
LT		 1052}
1053
1054static void e100_get_defaults(struct nic *nic)
1055{
2afecc04
JB		 1056 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1057 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1da177e4 1058
1da177e4 1059 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
44c10138 1060 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
f26251eb 1061 if (nic->mac == mac_unknown)
1da177e4
LT		 1062 nic->mac = mac_82557_D100_A;
1063
1064 nic->params.rfds = rfds;
1065 nic->params.cbs = cbs;
1066
1067 /* Quadwords to DMA into FIFO before starting frame transmit */
1068 nic->tx_threshold = 0xE0;
1069
0a0863af 1070 /* no interrupt for every tx completion, delay = 256us if not 557 */
962082b6
MC		 1071 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1072 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1da177e4
LT		 1073
1074 /* Template for a freshly allocated RFD */
7734f6e6 1075 nic->blank_rfd.command = 0;
1172899a 1076 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1da177e4
LT		 1077 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
1078
1079 /* MII setup */
1080 nic->mii.phy_id_mask = 0x1F;
1081 nic->mii.reg_num_mask = 0x1F;
1082 nic->mii.dev = nic->netdev;
1083 nic->mii.mdio_read = mdio_read;
1084 nic->mii.mdio_write = mdio_write;
1085}
1086
1087static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1088{
1089 struct config *config = &cb->u.config;
1090 u8 *c = (u8 *)config;
1091
1092 cb->command = cpu_to_le16(cb_config);
1093
1094 memset(config, 0, sizeof(struct config));
1095
1096 config->byte_count = 0x16; /* bytes in this struct */
1097 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1098 config->direct_rx_dma = 0x1; /* reserved */
1099 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1100 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1101 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1102 config->tx_underrun_retry = 0x3; /* # of underrun retries */
72001762
AM		 1103 if (e100_phy_supports_mii(nic))
1104 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */
1da177e4
LT		 1105 config->pad10 = 0x6;
1106 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1107 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1108 config->ifs = 0x6; /* x16 = inter frame spacing */
1109 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1110 config->pad15_1 = 0x1;
1111 config->pad15_2 = 0x1;
1112 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1113 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1114 config->tx_padding = 0x1; /* 1=pad short frames */
1115 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1116 config->pad18 = 0x1;
1117 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1118 config->pad20_1 = 0x1F;
1119 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1120 config->pad21_1 = 0x5;
1121
1122 config->adaptive_ifs = nic->adaptive_ifs;
1123 config->loopback = nic->loopback;
1124
f26251eb 1125 if (nic->mii.force_media && nic->mii.full_duplex)
1da177e4
LT		 1126 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1127
f26251eb 1128 if (nic->flags & promiscuous || nic->loopback) {
1da177e4
LT		 1129 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1130 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1131 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1132 }
1133
f26251eb 1134 if (nic->flags & multicast_all)
1da177e4
LT		 1135 config->multicast_all = 0x1; /* 1=accept, 0=no */
1136
6bdacb1a 1137 /* disable WoL when up */
f26251eb 1138 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1da177e4
LT		 1139 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1140
f26251eb 1141 if (nic->mac >= mac_82558_D101_A4) {
1da177e4
LT		 1142 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1143 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1144 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1145 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
44e4925e 1146 if (nic->mac >= mac_82559_D101M) {
1da177e4 1147 config->tno_intr = 0x1; /* TCO stats enable */
44e4925e
DG		 1148 /* Enable TCO in extended config */
1149 if (nic->mac >= mac_82551_10) {
1150 config->byte_count = 0x20; /* extended bytes */
1151 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1152 }
1153 } else {
1da177e4 1154 config->standard_stat_counter = 0x0;
44e4925e 1155 }
1da177e4
LT		 1156 }
1157
1158 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1159 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1160 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1161 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1162 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1163 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1164}
1165
2afecc04
JB		 1166/*************************************************************************
1167* CPUSaver parameters
1168*
1169* All CPUSaver parameters are 16-bit literals that are part of a
1170* "move immediate value" instruction. By changing the value of
1171* the literal in the instruction before the code is loaded, the
1172* driver can change the algorithm.
1173*
0779bf2d 1174* INTDELAY - This loads the dead-man timer with its initial value.
05479938 1175* When this timer expires the interrupt is asserted, and the
2afecc04
JB		 1176* timer is reset each time a new packet is received. (see
1177* BUNDLEMAX below to set the limit on number of chained packets)
1178* The current default is 0x600 or 1536. Experiments show that
1179* the value should probably stay within the 0x200 - 0x1000.
1180*
05479938 1181* BUNDLEMAX -
2afecc04
JB		 1182* This sets the maximum number of frames that will be bundled. In
1183* some situations, such as the TCP windowing algorithm, it may be
1184* better to limit the growth of the bundle size than let it go as
1185* high as it can, because that could cause too much added latency.
1186* The default is six, because this is the number of packets in the
1187* default TCP window size. A value of 1 would make CPUSaver indicate
1188* an interrupt for every frame received. If you do not want to put
1189* a limit on the bundle size, set this value to xFFFF.
1190*
05479938 1191* BUNDLESMALL -
2afecc04
JB		 1192* This contains a bit-mask describing the minimum size frame that
1193* will be bundled. The default masks the lower 7 bits, which means
1194* that any frame less than 128 bytes in length will not be bundled,
1195* but will instead immediately generate an interrupt. This does
1196* not affect the current bundle in any way. Any frame that is 128
1197* bytes or large will be bundled normally. This feature is meant
1198* to provide immediate indication of ACK frames in a TCP environment.
1199* Customers were seeing poor performance when a machine with CPUSaver
1200* enabled was sending but not receiving. The delay introduced when
1201* the ACKs were received was enough to reduce total throughput, because
1202* the sender would sit idle until the ACK was finally seen.
1203*
1204* The current default is 0xFF80, which masks out the lower 7 bits.
1205* This means that any frame which is x7F (127) bytes or smaller
05479938 1206* will cause an immediate interrupt. Because this value must be a
2afecc04
JB		 1207* bit mask, there are only a few valid values that can be used. To
1208* turn this feature off, the driver can write the value xFFFF to the
1209* lower word of this instruction (in the same way that the other
1210* parameters are used). Likewise, a value of 0xF800 (2047) would
1211* cause an interrupt to be generated for every frame, because all
1212* standard Ethernet frames are <= 2047 bytes in length.
1213*************************************************************************/
1214
05479938 1215/* if you wish to disable the ucode functionality, while maintaining the
2afecc04
JB		 1216 * workarounds it provides, set the following defines to:
1217 * BUNDLESMALL 0
1218 * BUNDLEMAX 1
1219 * INTDELAY 1
1220 */
1221#define BUNDLESMALL 1
1222#define BUNDLEMAX (u16)6
1223#define INTDELAY (u16)1536 /* 0x600 */
1224
9ac32e1b
JSR		 1225/* Initialize firmware */
1226static const struct firmware *e100_request_firmware(struct nic *nic)
1227{
1228 const char *fw_name;
7e15b0c9 1229 const struct firmware *fw = nic->fw;
9ac32e1b 1230 u8 timer, bundle, min_size;
7e15b0c9 1231 int err = 0;
9ac32e1b 1232
2afecc04
JB		 1233 /* do not load u-code for ICH devices */
1234 if (nic->flags & ich)
9ac32e1b 1235 return NULL;
2afecc04 1236
44c10138 1237 /* Search for ucode match against h/w revision */
9ac32e1b
JSR		 1238 if (nic->mac == mac_82559_D101M)
1239 fw_name = FIRMWARE_D101M;
1240 else if (nic->mac == mac_82559_D101S)
1241 fw_name = FIRMWARE_D101S;
1242 else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10)
1243 fw_name = FIRMWARE_D102E;
1244 else /* No ucode on other devices */
1245 return NULL;
1246
7e15b0c9
DG		 1247 /* If the firmware has not previously been loaded, request a pointer
1248 * to it. If it was previously loaded, we are reinitializing the
1249 * adapter, possibly in a resume from hibernate, in which case
1250 * request_firmware() cannot be used.
1251 */
1252 if (!fw)
1253 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1254
9ac32e1b
JSR		 1255 if (err) {
1256 DPRINTK(PROBE, ERR, "Failed to load firmware \"%s\": %d\n",
1257 fw_name, err);
1258 return ERR_PTR(err);
1259 }
7e15b0c9 1260
9ac32e1b
JSR		 1261 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1262 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1263 if (fw->size != UCODE_SIZE * 4 + 3) {
1264 DPRINTK(PROBE, ERR, "Firmware \"%s\" has wrong size %zu\n",
1265 fw_name, fw->size);
1266 release_firmware(fw);
1267 return ERR_PTR(-EINVAL);
2afecc04
JB		 1268 }
1269
9ac32e1b
JSR		 1270 /* Read timer, bundle and min_size from end of firmware blob */
1271 timer = fw->data[UCODE_SIZE * 4];
1272 bundle = fw->data[UCODE_SIZE * 4 + 1];
1273 min_size = fw->data[UCODE_SIZE * 4 + 2];
1274
1275 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1276 min_size >= UCODE_SIZE) {
1277 DPRINTK(PROBE, ERR,
1278 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1279 fw_name, timer, bundle, min_size);
1280 release_firmware(fw);
1281 return ERR_PTR(-EINVAL);
1282 }
7e15b0c9
DG		 1283
1284 /* OK, firmware is validated and ready to use. Save a pointer
1285 * to it in the nic */
1286 nic->fw = fw;
9ac32e1b 1287 return fw;
24180333
JB		 1288}
1289
9ac32e1b
JSR		 1290static void e100_setup_ucode(struct nic *nic, struct cb *cb,
1291 struct sk_buff *skb)
24180333 1292{
9ac32e1b
JSR		 1293 const struct firmware *fw = (void *)skb;
1294 u8 timer, bundle, min_size;
1295
1296 /* It's not a real skb; we just abused the fact that e100_exec_cb
1297 will pass it through to here... */
1298 cb->skb = NULL;
1299
1300 /* firmware is stored as little endian already */
1301 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1302
1303 /* Read timer, bundle and min_size from end of firmware blob */
1304 timer = fw->data[UCODE_SIZE * 4];
1305 bundle = fw->data[UCODE_SIZE * 4 + 1];
1306 min_size = fw->data[UCODE_SIZE * 4 + 2];
1307
1308 /* Insert user-tunable settings in cb->u.ucode */
1309 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1310 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1311 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1312 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1313 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1314 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1315
1316 cb->command = cpu_to_le16(cb_ucode | cb_el);
1317}
1318
1319static inline int e100_load_ucode_wait(struct nic *nic)
1320{
1321 const struct firmware *fw;
24180333
JB		 1322 int err = 0, counter = 50;
1323 struct cb *cb = nic->cb_to_clean;
1324
9ac32e1b
JSR		 1325 fw = e100_request_firmware(nic);
1326 /* If it's NULL, then no ucode is required */
1327 if (!fw || IS_ERR(fw))
1328 return PTR_ERR(fw);
1329
1330 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
24180333 1331 DPRINTK(PROBE,ERR, "ucode cmd failed with error %d\n", err);
05479938 1332
24180333
JB		 1333 /* must restart cuc */
1334 nic->cuc_cmd = cuc_start;
1335
1336 /* wait for completion */
1337 e100_write_flush(nic);
1338 udelay(10);
1339
1340 /* wait for possibly (ouch) 500ms */
1341 while (!(cb->status & cpu_to_le16(cb_complete))) {
1342 msleep(10);
1343 if (!--counter) break;
1344 }
05479938 1345
3a4fa0a2 1346 /* ack any interrupts, something could have been set */
27345bb6 1347 iowrite8(~0, &nic->csr->scb.stat_ack);
24180333
JB		 1348
1349 /* if the command failed, or is not OK, notify and return */
1350 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1351 DPRINTK(PROBE,ERR, "ucode load failed\n");
1352 err = -EPERM;
1353 }
05479938 1354
24180333 1355 return err;
1da177e4
LT		 1356}
1357
1358static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1359 struct sk_buff *skb)
1360{
1361 cb->command = cpu_to_le16(cb_iaaddr);
1362 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1363}
1364
1365static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1366{
1367 cb->command = cpu_to_le16(cb_dump);
1368 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1369 offsetof(struct mem, dump_buf));
1370}
1371
72001762
AM		 1372static int e100_phy_check_without_mii(struct nic *nic)
1373{
1374 u8 phy_type;
1375 int without_mii;
1376
1377 phy_type = (nic->eeprom[eeprom_phy_iface] >> 8) & 0x0f;
1378
1379 switch (phy_type) {
1380 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */
1381 case I82503: /* Non-MII PHY; UNTESTED! */
1382 case S80C24: /* Non-MII PHY; tested and working */
1383 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24":
1384 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
1385 * doesn't have a programming interface of any sort. The
1386 * media is sensed automatically based on how the link partner
1387 * is configured. This is, in essence, manual configuration.
1388 */
1389 DPRINTK(PROBE, INFO,
1390 "found MII-less i82503 or 80c24 or other PHY\n");
1391
1392 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1393 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */
1394
1395 /* these might be needed for certain MII-less cards...
1396 * nic->flags |= ich;
1397 * nic->flags |= ich_10h_workaround; */
1398
1399 without_mii = 1;
1400 break;
1401 default:
1402 without_mii = 0;
1403 break;
1404 }
1405 return without_mii;
1406}
1407
1da177e4
LT		 1408#define NCONFIG_AUTO_SWITCH 0x0080
1409#define MII_NSC_CONG MII_RESV1
1410#define NSC_CONG_ENABLE 0x0100
1411#define NSC_CONG_TXREADY 0x0400
1412#define ADVERTISE_FC_SUPPORTED 0x0400
1413static int e100_phy_init(struct nic *nic)
1414{
1415 struct net_device *netdev = nic->netdev;
1416 u32 addr;
1417 u16 bmcr, stat, id_lo, id_hi, cong;
1418
1419 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
f26251eb 1420 for (addr = 0; addr < 32; addr++) {
1da177e4
LT		 1421 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1422 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1423 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1424 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
f26251eb 1425 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1da177e4
LT		 1426 break;
1427 }
72001762
AM		 1428 if (addr == 32) {
1429 /* uhoh, no PHY detected: check whether we seem to be some
1430 * weird, rare variant which is *known* to not have any MII.
1431 * But do this AFTER MII checking only, since this does
1432 * lookup of EEPROM values which may easily be unreliable. */
1433 if (e100_phy_check_without_mii(nic))
1434 return 0; /* simply return and hope for the best */
1435 else {
1436 /* for unknown cases log a fatal error */
1437 DPRINTK(HW, ERR,
1438 "Failed to locate any known PHY, aborting.\n");
1439 return -EAGAIN;
1440 }
1441 } else
1442 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1da177e4 1443
1da177e4
LT		 1444 /* Get phy ID */
1445 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1446 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1447 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1448 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1449
8fbd962e
BA		 1450 /* Select the phy and isolate the rest */
1451 for (addr = 0; addr < 32; addr++) {
1452 if (addr != nic->mii.phy_id) {
1453 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1454 } else if (nic->phy != phy_82552_v) {
1455 bmcr = mdio_read(netdev, addr, MII_BMCR);
1456 mdio_write(netdev, addr, MII_BMCR,
1457 bmcr & ~BMCR_ISOLATE);
1458 }
1459 }
1460 /*
1461 * Workaround for 82552:
1462 * Clear the ISOLATE bit on selected phy_id last (mirrored on all
1463 * other phy_id's) using bmcr value from addr discovery loop above.
1464 */
1465 if (nic->phy == phy_82552_v)
1466 mdio_write(netdev, nic->mii.phy_id, MII_BMCR,
1467 bmcr & ~BMCR_ISOLATE);
1468
1da177e4
LT		 1469 /* Handle National tx phys */
1470#define NCS_PHY_MODEL_MASK 0xFFF0FFFF
f26251eb 1471 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1da177e4
LT		 1472 /* Disable congestion control */
1473 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1474 cong |= NSC_CONG_TXREADY;
1475 cong &= ~NSC_CONG_ENABLE;
1476 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1477 }
1478
b55de80e
BA		 1479 if (nic->phy == phy_82552_v) {
1480 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1481
72001762
AM		 1482 /* assign special tweaked mdio_ctrl() function */
1483 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1484
b55de80e
BA		 1485 /* Workaround Si not advertising flow-control during autoneg */
1486 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1487 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1488
1489 /* Reset for the above changes to take effect */
1490 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1491 bmcr |= BMCR_RESET;
1492 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1493 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
60ffa478
JK		 1494 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1495 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1496 /* enable/disable MDI/MDI-X auto-switching. */
1497 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1498 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
64895145 1499 }
1da177e4
LT		 1500
1501 return 0;
1502}
1503
1504static int e100_hw_init(struct nic *nic)
1505{
1506 int err;
1507
1508 e100_hw_reset(nic);
1509
1510 DPRINTK(HW, ERR, "e100_hw_init\n");
f26251eb 1511 if (!in_interrupt() && (err = e100_self_test(nic)))
1da177e4
LT		 1512 return err;
1513
f26251eb 1514 if ((err = e100_phy_init(nic)))
1da177e4 1515 return err;
f26251eb 1516 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1da177e4 1517 return err;
f26251eb 1518 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1da177e4 1519 return err;
9ac32e1b 1520 if ((err = e100_load_ucode_wait(nic)))
1da177e4 1521 return err;
f26251eb 1522 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1da177e4 1523 return err;
f26251eb 1524 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1da177e4 1525 return err;
f26251eb 1526 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1da177e4
LT		 1527 nic->dma_addr + offsetof(struct mem, stats))))
1528 return err;
f26251eb 1529 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1da177e4
LT		 1530 return err;
1531
1532 e100_disable_irq(nic);
1533
1534 return 0;
1535}
1536
1537static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1538{
1539 struct net_device *netdev = nic->netdev;
48e2f183 1540 struct dev_mc_list *list;
4cd24eaf 1541 u16 i, count = min(netdev_mc_count(netdev), E100_MAX_MULTICAST_ADDRS);
1da177e4
LT		 1542
1543 cb->command = cpu_to_le16(cb_multi);
1544 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
48e2f183
JP		 1545 i = 0;
1546 netdev_for_each_mc_addr(list, netdev) {
1547 if (i == count)
1548 break;
1549 memcpy(&cb->u.multi.addr[i++ * ETH_ALEN], &list->dmi_addr,
1da177e4 1550 ETH_ALEN);
48e2f183 1551 }
1da177e4
LT		 1552}
1553
1554static void e100_set_multicast_list(struct net_device *netdev)
1555{
1556 struct nic *nic = netdev_priv(netdev);
1557
1558 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
4cd24eaf 1559 netdev_mc_count(netdev), netdev->flags);
1da177e4 1560
f26251eb 1561 if (netdev->flags & IFF_PROMISC)
1da177e4
LT		 1562 nic->flags |= promiscuous;
1563 else
1564 nic->flags &= ~promiscuous;
1565
f26251eb 1566 if (netdev->flags & IFF_ALLMULTI ||
4cd24eaf 1567 netdev_mc_count(netdev) > E100_MAX_MULTICAST_ADDRS)
1da177e4
LT		 1568 nic->flags |= multicast_all;
1569 else
1570 nic->flags &= ~multicast_all;
1571
1572 e100_exec_cb(nic, NULL, e100_configure);
1573 e100_exec_cb(nic, NULL, e100_multi);
1574}
1575
1576static void e100_update_stats(struct nic *nic)
1577{
09f75cd7
JG		 1578 struct net_device *dev = nic->netdev;
1579 struct net_device_stats *ns = &dev->stats;
1da177e4 1580 struct stats *s = &nic->mem->stats;
aaf918ba
AV		 1581 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1582 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1da177e4
LT		 1583 &s->complete;
1584
1585 /* Device's stats reporting may take several microseconds to
0a0863af 1586 * complete, so we're always waiting for results of the
1da177e4
LT		 1587 * previous command. */
1588
f26251eb 1589 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1da177e4
LT		 1590 *complete = 0;
1591 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1592 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1593 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1594 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1595 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1596 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1597 ns->collisions += nic->tx_collisions;
1598 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1599 le32_to_cpu(s->tx_lost_crs);
1da177e4
LT		 1600 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1601 nic->rx_over_length_errors;
1602 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1603 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1604 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1605 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
ecf7130b 1606 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1da177e4
LT		 1607 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1608 le32_to_cpu(s->rx_alignment_errors) +
1609 le32_to_cpu(s->rx_short_frame_errors) +
1610 le32_to_cpu(s->rx_cdt_errors);
1611 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1612 nic->tx_single_collisions +=
1613 le32_to_cpu(s->tx_single_collisions);
1614 nic->tx_multiple_collisions +=
1615 le32_to_cpu(s->tx_multiple_collisions);
f26251eb 1616 if (nic->mac >= mac_82558_D101_A4) {
1da177e4
LT		 1617 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1618 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1619 nic->rx_fc_unsupported +=
1620 le32_to_cpu(s->fc_rcv_unsupported);
f26251eb 1621 if (nic->mac >= mac_82559_D101M) {
1da177e4
LT		 1622 nic->tx_tco_frames +=
1623 le16_to_cpu(s->xmt_tco_frames);
1624 nic->rx_tco_frames +=
1625 le16_to_cpu(s->rcv_tco_frames);
1626 }
1627 }
1628 }
1629
05479938 1630
f26251eb 1631 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
1f53367d 1632 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1da177e4
LT		 1633}
1634
1635static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1636{
1637 /* Adjust inter-frame-spacing (IFS) between two transmits if
1638 * we're getting collisions on a half-duplex connection. */
1639
f26251eb 1640 if (duplex == DUPLEX_HALF) {
1da177e4
LT		 1641 u32 prev = nic->adaptive_ifs;
1642 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1643
f26251eb 1644 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1da177e4 1645 (nic->tx_frames > min_frames)) {
f26251eb 1646 if (nic->adaptive_ifs < 60)
1da177e4
LT		 1647 nic->adaptive_ifs += 5;
1648 } else if (nic->tx_frames < min_frames) {
f26251eb 1649 if (nic->adaptive_ifs >= 5)
1da177e4
LT		 1650 nic->adaptive_ifs -= 5;
1651 }
f26251eb 1652 if (nic->adaptive_ifs != prev)
1da177e4
LT		 1653 e100_exec_cb(nic, NULL, e100_configure);
1654 }
1655}
1656
1657static void e100_watchdog(unsigned long data)
1658{
1659 struct nic *nic = (struct nic *)data;
1660 struct ethtool_cmd cmd;
1661
1662 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1663
1664 /* mii library handles link maintenance tasks */
1665
1666 mii_ethtool_gset(&nic->mii, &cmd);
1667
f26251eb 1668 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
f4113030
JK		 1669 printk(KERN_INFO "e100: %s NIC Link is Up %s Mbps %s Duplex\n",
1670 nic->netdev->name,
1671 cmd.speed == SPEED_100 ? "100" : "10",
1672 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
f26251eb 1673 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
f4113030
JK		 1674 printk(KERN_INFO "e100: %s NIC Link is Down\n",
1675 nic->netdev->name);
1da177e4
LT		 1676 }
1677
1678 mii_check_link(&nic->mii);
1679
1680 /* Software generated interrupt to recover from (rare) Rx
05479938
JB		 1681 * allocation failure.
1682 * Unfortunately have to use a spinlock to not re-enable interrupts
1683 * accidentally, due to hardware that shares a register between the
1684 * interrupt mask bit and the SW Interrupt generation bit */
1da177e4 1685 spin_lock_irq(&nic->cmd_lock);
27345bb6 1686 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1da177e4 1687 e100_write_flush(nic);
ad8c48ad 1688 spin_unlock_irq(&nic->cmd_lock);
1da177e4
LT		 1689
1690 e100_update_stats(nic);
1691 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1692
f26251eb 1693 if (nic->mac <= mac_82557_D100_C)
1da177e4
LT		 1694 /* Issue a multicast command to workaround a 557 lock up */
1695 e100_set_multicast_list(nic->netdev);
1696
f26251eb 1697 if (nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1da177e4
LT		 1698 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1699 nic->flags |= ich_10h_workaround;
1700 else
1701 nic->flags &= ~ich_10h_workaround;
1702
34c6417b
SH		 1703 mod_timer(&nic->watchdog,
1704 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1da177e4
LT		 1705}
1706
858119e1 1707static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1da177e4
LT		 1708 struct sk_buff *skb)
1709{
1710 cb->command = nic->tx_command;
962082b6 1711 /* interrupt every 16 packets regardless of delay */
f26251eb 1712 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
996ec353 1713 cb->command |= cpu_to_le16(cb_i);
1da177e4
LT		 1714 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1715 cb->u.tcb.tcb_byte_count = 0;
1716 cb->u.tcb.threshold = nic->tx_threshold;
1717 cb->u.tcb.tbd_count = 1;
1718 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1719 skb->data, skb->len, PCI_DMA_TODEVICE));
611494dc 1720 /* check for mapping failure? */
1da177e4
LT		 1721 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1722}
1723
3b29a56d
SH		 1724static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
1725 struct net_device *netdev)
1da177e4
LT		 1726{
1727 struct nic *nic = netdev_priv(netdev);
1728 int err;
1729
f26251eb 1730 if (nic->flags & ich_10h_workaround) {
1da177e4
LT		 1731 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1732 Issue a NOP command followed by a 1us delay before
1733 issuing the Tx command. */
f26251eb 1734 if (e100_exec_cmd(nic, cuc_nop, 0))
1f53367d 1735 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1da177e4
LT		 1736 udelay(1);
1737 }
1738
1739 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1740
f26251eb 1741 switch (err) {
1da177e4
LT		 1742 case -ENOSPC:
1743 /* We queued the skb, but now we're out of space. */
1744 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1745 netif_stop_queue(netdev);
1746 break;
1747 case -ENOMEM:
1748 /* This is a hard error - log it. */
1749 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1750 netif_stop_queue(netdev);
5b548140 1751 return NETDEV_TX_BUSY;
1da177e4
LT		 1752 }
1753
1754 netdev->trans_start = jiffies;
6ed10654 1755 return NETDEV_TX_OK;
1da177e4
LT		 1756}
1757
858119e1 1758static int e100_tx_clean(struct nic *nic)
1da177e4 1759{
09f75cd7 1760 struct net_device *dev = nic->netdev;
1da177e4
LT		 1761 struct cb *cb;
1762 int tx_cleaned = 0;
1763
1764 spin_lock(&nic->cb_lock);
1765
1da177e4 1766 /* Clean CBs marked complete */
f26251eb 1767 for (cb = nic->cb_to_clean;
1da177e4
LT		 1768 cb->status & cpu_to_le16(cb_complete);
1769 cb = nic->cb_to_clean = cb->next) {
dc45010e
JB		 1770 DPRINTK(TX_DONE, DEBUG, "cb[%d]->status = 0x%04X\n",
1771 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1772 cb->status);
1773
f26251eb 1774 if (likely(cb->skb != NULL)) {
09f75cd7
JG		 1775 dev->stats.tx_packets++;
1776 dev->stats.tx_bytes += cb->skb->len;
1da177e4
LT		 1777
1778 pci_unmap_single(nic->pdev,
1779 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1780 le16_to_cpu(cb->u.tcb.tbd.size),
1781 PCI_DMA_TODEVICE);
1782 dev_kfree_skb_any(cb->skb);
1783 cb->skb = NULL;
1784 tx_cleaned = 1;
1785 }
1786 cb->status = 0;
1787 nic->cbs_avail++;
1788 }
1789
1790 spin_unlock(&nic->cb_lock);
1791
1792 /* Recover from running out of Tx resources in xmit_frame */
f26251eb 1793 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1da177e4
LT		 1794 netif_wake_queue(nic->netdev);
1795
1796 return tx_cleaned;
1797}
1798
1799static void e100_clean_cbs(struct nic *nic)
1800{
f26251eb
BA		 1801 if (nic->cbs) {
1802 while (nic->cbs_avail != nic->params.cbs.count) {
1da177e4 1803 struct cb *cb = nic->cb_to_clean;
f26251eb 1804 if (cb->skb) {
1da177e4
LT		 1805 pci_unmap_single(nic->pdev,
1806 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1807 le16_to_cpu(cb->u.tcb.tbd.size),
1808 PCI_DMA_TODEVICE);
1809 dev_kfree_skb(cb->skb);
1810 }
1811 nic->cb_to_clean = nic->cb_to_clean->next;
1812 nic->cbs_avail++;
1813 }
98468efd 1814 pci_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
1da177e4
LT		 1815 nic->cbs = NULL;
1816 nic->cbs_avail = 0;
1817 }
1818 nic->cuc_cmd = cuc_start;
1819 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1820 nic->cbs;
1821}
1822
1823static int e100_alloc_cbs(struct nic *nic)
1824{
1825 struct cb *cb;
1826 unsigned int i, count = nic->params.cbs.count;
1827
1828 nic->cuc_cmd = cuc_start;
1829 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1830 nic->cbs_avail = 0;
1831
98468efd
RO		 1832 nic->cbs = pci_pool_alloc(nic->cbs_pool, GFP_KERNEL,
1833 &nic->cbs_dma_addr);
f26251eb 1834 if (!nic->cbs)
1da177e4 1835 return -ENOMEM;
70abc8cb 1836 memset(nic->cbs, 0, count * sizeof(struct cb));
1da177e4 1837
f26251eb 1838 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1da177e4
LT		 1839 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1840 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1841
1842 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1843 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1844 ((i+1) % count) * sizeof(struct cb));
1da177e4
LT		 1845 }
1846
1847 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1848 nic->cbs_avail = count;
1849
1850 return 0;
1851}
1852
ca93ca42 1853static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1da177e4 1854{
f26251eb
BA		 1855 if (!nic->rxs) return;
1856 if (RU_SUSPENDED != nic->ru_running) return;
ca93ca42
JG		 1857
1858 /* handle init time starts */
f26251eb 1859 if (!rx) rx = nic->rxs;
ca93ca42
JG		 1860
1861 /* (Re)start RU if suspended or idle and RFA is non-NULL */
f26251eb 1862 if (rx->skb) {
ca93ca42
JG		 1863 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1864 nic->ru_running = RU_RUNNING;
1865 }
1da177e4
LT		 1866}
1867
1868#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
858119e1 1869static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1da177e4 1870{
89d71a66 1871 if (!(rx->skb = netdev_alloc_skb_ip_align(nic->netdev, RFD_BUF_LEN)))
1da177e4
LT		 1872 return -ENOMEM;
1873
89d71a66 1874 /* Init, and map the RFD. */
27d7ff46 1875 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1da177e4
LT		 1876 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1877 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1878
8d8bb39b 1879 if (pci_dma_mapping_error(nic->pdev, rx->dma_addr)) {
1f53367d 1880 dev_kfree_skb_any(rx->skb);
097688ef 1881 rx->skb = NULL;
1f53367d
MC		 1882 rx->dma_addr = 0;
1883 return -ENOMEM;
1884 }
1885
1da177e4 1886 /* Link the RFD to end of RFA by linking previous RFD to
7734f6e6
DA		 1887 * this one. We are safe to touch the previous RFD because
1888 * it is protected by the before last buffer's el bit being set */
aaf918ba 1889 if (rx->prev->skb) {
1da177e4 1890 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
6caf52a4 1891 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1923815d 1892 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
773c9c1f 1893 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1da177e4
LT		 1894 }
1895
1896 return 0;
1897}
1898
858119e1 1899static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1da177e4
LT		 1900 unsigned int *work_done, unsigned int work_to_do)
1901{
09f75cd7 1902 struct net_device *dev = nic->netdev;
1da177e4
LT		 1903 struct sk_buff *skb = rx->skb;
1904 struct rfd *rfd = (struct rfd *)skb->data;
1905 u16 rfd_status, actual_size;
1906
f26251eb 1907 if (unlikely(work_done && *work_done >= work_to_do))
1da177e4
LT		 1908 return -EAGAIN;
1909
1910 /* Need to sync before taking a peek at cb_complete bit */
1911 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
773c9c1f 1912 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1da177e4
LT		 1913 rfd_status = le16_to_cpu(rfd->status);
1914
1915 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1916
1917 /* If data isn't ready, nothing to indicate */
7734f6e6
DA		 1918 if (unlikely(!(rfd_status & cb_complete))) {
1919 /* If the next buffer has the el bit, but we think the receiver
1920 * is still running, check to see if it really stopped while
1921 * we had interrupts off.
1922 * This allows for a fast restart without re-enabling
1923 * interrupts */
1924 if ((le16_to_cpu(rfd->command) & cb_el) &&
1925 (RU_RUNNING == nic->ru_running))
1926
17393dd6 1927 if (ioread8(&nic->csr->scb.status) & rus_no_res)
7734f6e6 1928 nic->ru_running = RU_SUSPENDED;
303d67c2
KH		 1929 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1930 sizeof(struct rfd),
6ff9c2e7 1931 PCI_DMA_FROMDEVICE);
1f53367d 1932 return -ENODATA;
7734f6e6 1933 }
1da177e4
LT		 1934
1935 /* Get actual data size */
1936 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
f26251eb 1937 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1da177e4
LT		 1938 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1939
1940 /* Get data */
1941 pci_unmap_single(nic->pdev, rx->dma_addr,
773c9c1f 1942 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1da177e4 1943
7734f6e6
DA		 1944 /* If this buffer has the el bit, but we think the receiver
1945 * is still running, check to see if it really stopped while
1946 * we had interrupts off.
1947 * This allows for a fast restart without re-enabling interrupts.
1948 * This can happen when the RU sees the size change but also sees
1949 * the el bit set. */
1950 if ((le16_to_cpu(rfd->command) & cb_el) &&
1951 (RU_RUNNING == nic->ru_running)) {
1952
17393dd6 1953 if (ioread8(&nic->csr->scb.status) & rus_no_res)
ca93ca42 1954 nic->ru_running = RU_SUSPENDED;
7734f6e6 1955 }
ca93ca42 1956
1da177e4
LT		 1957 /* Pull off the RFD and put the actual data (minus eth hdr) */
1958 skb_reserve(skb, sizeof(struct rfd));
1959 skb_put(skb, actual_size);
1960 skb->protocol = eth_type_trans(skb, nic->netdev);
1961
f26251eb 1962 if (unlikely(!(rfd_status & cb_ok))) {
1da177e4 1963 /* Don't indicate if hardware indicates errors */
1da177e4 1964 dev_kfree_skb_any(skb);
f26251eb 1965 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1da177e4
LT		 1966 /* Don't indicate oversized frames */
1967 nic->rx_over_length_errors++;
1da177e4
LT		 1968 dev_kfree_skb_any(skb);
1969 } else {
09f75cd7
JG		 1970 dev->stats.rx_packets++;
1971 dev->stats.rx_bytes += actual_size;
1da177e4 1972 netif_receive_skb(skb);
f26251eb 1973 if (work_done)
1da177e4
LT		 1974 (*work_done)++;
1975 }
1976
1977 rx->skb = NULL;
1978
1979 return 0;
1980}
1981
858119e1 1982static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1da177e4
LT		 1983 unsigned int work_to_do)
1984{
1985 struct rx *rx;
7734f6e6
DA		 1986 int restart_required = 0, err = 0;
1987 struct rx *old_before_last_rx, *new_before_last_rx;
1988 struct rfd *old_before_last_rfd, *new_before_last_rfd;
1da177e4
LT		 1989
1990 /* Indicate newly arrived packets */
f26251eb 1991 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
7734f6e6
DA		 1992 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1993 /* Hit quota or no more to clean */
1994 if (-EAGAIN == err || -ENODATA == err)
ca93ca42 1995 break;
1da177e4
LT		 1996 }
1997
7734f6e6
DA		 1998
1999 /* On EAGAIN, hit quota so have more work to do, restart once
2000 * cleanup is complete.
2001 * Else, are we already rnr? then pay attention!!! this ensures that
2002 * the state machine progression never allows a start with a
2003 * partially cleaned list, avoiding a race between hardware
2004 * and rx_to_clean when in NAPI mode */
2005 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
2006 restart_required = 1;
2007
2008 old_before_last_rx = nic->rx_to_use->prev->prev;
2009 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
ca93ca42 2010
1da177e4 2011 /* Alloc new skbs to refill list */
f26251eb
BA		 2012 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
2013 if (unlikely(e100_rx_alloc_skb(nic, rx)))
1da177e4
LT		 2014 break; /* Better luck next time (see watchdog) */
2015 }
ca93ca42 2016
7734f6e6
DA		 2017 new_before_last_rx = nic->rx_to_use->prev->prev;
2018 if (new_before_last_rx != old_before_last_rx) {
2019 /* Set the el-bit on the buffer that is before the last buffer.
2020 * This lets us update the next pointer on the last buffer
2021 * without worrying about hardware touching it.
2022 * We set the size to 0 to prevent hardware from touching this
2023 * buffer.
2024 * When the hardware hits the before last buffer with el-bit
2025 * and size of 0, it will RNR interrupt, the RUS will go into
2026 * the No Resources state. It will not complete nor write to
2027 * this buffer. */
2028 new_before_last_rfd =
2029 (struct rfd *)new_before_last_rx->skb->data;
2030 new_before_last_rfd->size = 0;
2031 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2032 pci_dma_sync_single_for_device(nic->pdev,
2033 new_before_last_rx->dma_addr, sizeof(struct rfd),
773c9c1f 2034 PCI_DMA_BIDIRECTIONAL);
7734f6e6
DA		 2035
2036 /* Now that we have a new stopping point, we can clear the old
2037 * stopping point. We must sync twice to get the proper
2038 * ordering on the hardware side of things. */
2039 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2040 pci_dma_sync_single_for_device(nic->pdev,
2041 old_before_last_rx->dma_addr, sizeof(struct rfd),
773c9c1f 2042 PCI_DMA_BIDIRECTIONAL);
7734f6e6
DA		 2043 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
2044 pci_dma_sync_single_for_device(nic->pdev,
2045 old_before_last_rx->dma_addr, sizeof(struct rfd),
773c9c1f 2046 PCI_DMA_BIDIRECTIONAL);
7734f6e6
DA		 2047 }
2048
f26251eb 2049 if (restart_required) {
ca93ca42 2050 // ack the rnr?
915e91d7 2051 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
7734f6e6 2052 e100_start_receiver(nic, nic->rx_to_clean);
f26251eb 2053 if (work_done)
ca93ca42
JG		 2054 (*work_done)++;
2055 }
1da177e4
LT		 2056}
2057
2058static void e100_rx_clean_list(struct nic *nic)
2059{
2060 struct rx *rx;
2061 unsigned int i, count = nic->params.rfds.count;
2062
ca93ca42
JG		 2063 nic->ru_running = RU_UNINITIALIZED;
2064
f26251eb
BA		 2065 if (nic->rxs) {
2066 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2067 if (rx->skb) {
1da177e4 2068 pci_unmap_single(nic->pdev, rx->dma_addr,
773c9c1f 2069 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1da177e4
LT		 2070 dev_kfree_skb(rx->skb);
2071 }
2072 }
2073 kfree(nic->rxs);
2074 nic->rxs = NULL;
2075 }
2076
2077 nic->rx_to_use = nic->rx_to_clean = NULL;
1da177e4
LT		 2078}
2079
2080static int e100_rx_alloc_list(struct nic *nic)
2081{
2082 struct rx *rx;
2083 unsigned int i, count = nic->params.rfds.count;
7734f6e6 2084 struct rfd *before_last;
1da177e4
LT		 2085
2086 nic->rx_to_use = nic->rx_to_clean = NULL;
ca93ca42 2087 nic->ru_running = RU_UNINITIALIZED;
1da177e4 2088
f26251eb 2089 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
1da177e4 2090 return -ENOMEM;
1da177e4 2091
f26251eb 2092 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
1da177e4
LT		 2093 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2094 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
f26251eb 2095 if (e100_rx_alloc_skb(nic, rx)) {
1da177e4
LT		 2096 e100_rx_clean_list(nic);
2097 return -ENOMEM;
2098 }
2099 }
7734f6e6
DA		 2100 /* Set the el-bit on the buffer that is before the last buffer.
2101 * This lets us update the next pointer on the last buffer without
2102 * worrying about hardware touching it.
2103 * We set the size to 0 to prevent hardware from touching this buffer.
2104 * When the hardware hits the before last buffer with el-bit and size
2105 * of 0, it will RNR interrupt, the RU will go into the No Resources
2106 * state. It will not complete nor write to this buffer. */
2107 rx = nic->rxs->prev->prev;
2108 before_last = (struct rfd *)rx->skb->data;
2109 before_last->command |= cpu_to_le16(cb_el);
2110 before_last->size = 0;
2111 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
773c9c1f 2112 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1da177e4
LT		 2113
2114 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
ca93ca42 2115 nic->ru_running = RU_SUSPENDED;
1da177e4
LT		 2116
2117 return 0;
2118}
2119
7d12e780 2120static irqreturn_t e100_intr(int irq, void *dev_id)
1da177e4
LT		 2121{
2122 struct net_device *netdev = dev_id;
2123 struct nic *nic = netdev_priv(netdev);
27345bb6 2124 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
1da177e4
LT		 2125
2126 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
2127
f26251eb 2128 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
1da177e4
LT		 2129 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2130 return IRQ_NONE;
2131
2132 /* Ack interrupt(s) */
27345bb6 2133 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
1da177e4 2134
ca93ca42 2135 /* We hit Receive No Resource (RNR); restart RU after cleaning */
f26251eb 2136 if (stat_ack & stat_ack_rnr)
ca93ca42
JG		 2137 nic->ru_running = RU_SUSPENDED;
2138
288379f0 2139 if (likely(napi_schedule_prep(&nic->napi))) {
0685c31b 2140 e100_disable_irq(nic);
288379f0 2141 __napi_schedule(&nic->napi);
0685c31b 2142 }
1da177e4
LT		 2143
2144 return IRQ_HANDLED;
2145}
2146
bea3348e 2147static int e100_poll(struct napi_struct *napi, int budget)
1da177e4 2148{
bea3348e 2149 struct nic *nic = container_of(napi, struct nic, napi);
ddfce6bb 2150 unsigned int work_done = 0;
1da177e4 2151
bea3348e 2152 e100_rx_clean(nic, &work_done, budget);
53e52c72 2153 e100_tx_clean(nic);
1da177e4 2154
53e52c72
DM		 2155 /* If budget not fully consumed, exit the polling mode */
2156 if (work_done < budget) {
288379f0 2157 napi_complete(napi);
1da177e4 2158 e100_enable_irq(nic);
1da177e4
LT		 2159 }
2160
bea3348e 2161 return work_done;
1da177e4
LT		 2162}
2163
2164#ifdef CONFIG_NET_POLL_CONTROLLER
2165static void e100_netpoll(struct net_device *netdev)
2166{
2167 struct nic *nic = netdev_priv(netdev);
611494dc 2168
1da177e4 2169 e100_disable_irq(nic);
7d12e780 2170 e100_intr(nic->pdev->irq, netdev);
1da177e4
LT		 2171 e100_tx_clean(nic);
2172 e100_enable_irq(nic);
2173}
2174#endif
2175
1da177e4
LT		 2176static int e100_set_mac_address(struct net_device *netdev, void *p)
2177{
2178 struct nic *nic = netdev_priv(netdev);
2179 struct sockaddr *addr = p;
2180
2181 if (!is_valid_ether_addr(addr->sa_data))
2182 return -EADDRNOTAVAIL;
2183
2184 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2185 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2186
2187 return 0;
2188}
2189
2190static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2191{
f26251eb 2192 if (new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
1da177e4
LT		 2193 return -EINVAL;
2194 netdev->mtu = new_mtu;
2195 return 0;
2196}
2197
2198static int e100_asf(struct nic *nic)
2199{
2200 /* ASF can be enabled from eeprom */
2201 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2202 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2203 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2204 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
2205}
2206
2207static int e100_up(struct nic *nic)
2208{
2209 int err;
2210
f26251eb 2211 if ((err = e100_rx_alloc_list(nic)))
1da177e4 2212 return err;
f26251eb 2213 if ((err = e100_alloc_cbs(nic)))
1da177e4 2214 goto err_rx_clean_list;
f26251eb 2215 if ((err = e100_hw_init(nic)))
1da177e4
LT		 2216 goto err_clean_cbs;
2217 e100_set_multicast_list(nic->netdev);
ca93ca42 2218 e100_start_receiver(nic, NULL);
1da177e4 2219 mod_timer(&nic->watchdog, jiffies);
f26251eb 2220 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
1da177e4
LT		 2221 nic->netdev->name, nic->netdev)))
2222 goto err_no_irq;
1da177e4 2223 netif_wake_queue(nic->netdev);
bea3348e 2224 napi_enable(&nic->napi);
0236ebb7
MC		 2225 /* enable ints _after_ enabling poll, preventing a race between
2226 * disable ints+schedule */
2227 e100_enable_irq(nic);
1da177e4
LT		 2228 return 0;
2229
2230err_no_irq:
2231 del_timer_sync(&nic->watchdog);
2232err_clean_cbs:
2233 e100_clean_cbs(nic);
2234err_rx_clean_list:
2235 e100_rx_clean_list(nic);
2236 return err;
2237}
2238
2239static void e100_down(struct nic *nic)
2240{
0236ebb7 2241 /* wait here for poll to complete */
bea3348e 2242 napi_disable(&nic->napi);
0236ebb7 2243 netif_stop_queue(nic->netdev);
1da177e4
LT		 2244 e100_hw_reset(nic);
2245 free_irq(nic->pdev->irq, nic->netdev);
2246 del_timer_sync(&nic->watchdog);
2247 netif_carrier_off(nic->netdev);
1da177e4
LT		 2248 e100_clean_cbs(nic);
2249 e100_rx_clean_list(nic);
2250}
2251
2252static void e100_tx_timeout(struct net_device *netdev)
2253{
2254 struct nic *nic = netdev_priv(netdev);
2255
05479938 2256 /* Reset outside of interrupt context, to avoid request_irq
2acdb1e0
MC		 2257 * in interrupt context */
2258 schedule_work(&nic->tx_timeout_task);
2259}
2260
c4028958 2261static void e100_tx_timeout_task(struct work_struct *work)
2acdb1e0 2262{
c4028958
DH		 2263 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2264 struct net_device *netdev = nic->netdev;
2acdb1e0 2265
1da177e4 2266 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
27345bb6 2267 ioread8(&nic->csr->scb.status));
1da177e4
LT		 2268 e100_down(netdev_priv(netdev));
2269 e100_up(netdev_priv(netdev));
2270}
2271
2272static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2273{
2274 int err;
2275 struct sk_buff *skb;
2276
2277 /* Use driver resources to perform internal MAC or PHY
2278 * loopback test. A single packet is prepared and transmitted
2279 * in loopback mode, and the test passes if the received
2280 * packet compares byte-for-byte to the transmitted packet. */
2281
f26251eb 2282 if ((err = e100_rx_alloc_list(nic)))
1da177e4 2283 return err;
f26251eb 2284 if ((err = e100_alloc_cbs(nic)))
1da177e4
LT		 2285 goto err_clean_rx;
2286
2287 /* ICH PHY loopback is broken so do MAC loopback instead */
f26251eb 2288 if (nic->flags & ich && loopback_mode == lb_phy)
1da177e4
LT		 2289 loopback_mode = lb_mac;
2290
2291 nic->loopback = loopback_mode;
f26251eb 2292 if ((err = e100_hw_init(nic)))
1da177e4
LT		 2293 goto err_loopback_none;
2294
f26251eb 2295 if (loopback_mode == lb_phy)
1da177e4
LT		 2296 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2297 BMCR_LOOPBACK);
2298
ca93ca42 2299 e100_start_receiver(nic, NULL);
1da177e4 2300
f26251eb 2301 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
1da177e4
LT		 2302 err = -ENOMEM;
2303 goto err_loopback_none;
2304 }
2305 skb_put(skb, ETH_DATA_LEN);
2306 memset(skb->data, 0xFF, ETH_DATA_LEN);
2307 e100_xmit_frame(skb, nic->netdev);
2308
2309 msleep(10);
2310
aa49cdd9 2311 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
773c9c1f 2312 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
aa49cdd9 2313
f26251eb 2314 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
1da177e4
LT		 2315 skb->data, ETH_DATA_LEN))
2316 err = -EAGAIN;
2317
2318err_loopback_none:
2319 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2320 nic->loopback = lb_none;
1da177e4 2321 e100_clean_cbs(nic);
aa49cdd9 2322 e100_hw_reset(nic);
1da177e4
LT		 2323err_clean_rx:
2324 e100_rx_clean_list(nic);
2325 return err;
2326}
2327
2328#define MII_LED_CONTROL 0x1B
b55de80e
BA		 2329#define E100_82552_LED_OVERRIDE 0x19
2330#define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2331#define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
1da177e4
LT		 2332static void e100_blink_led(unsigned long data)
2333{
2334 struct nic *nic = (struct nic *)data;
2335 enum led_state {
2336 led_on = 0x01,
2337 led_off = 0x04,
2338 led_on_559 = 0x05,
2339 led_on_557 = 0x07,
2340 };
b55de80e
BA		 2341 u16 led_reg = MII_LED_CONTROL;
2342
2343 if (nic->phy == phy_82552_v) {
2344 led_reg = E100_82552_LED_OVERRIDE;
1da177e4 2345
b55de80e
BA		 2346 nic->leds = (nic->leds == E100_82552_LED_ON) ?
2347 E100_82552_LED_OFF : E100_82552_LED_ON;
2348 } else {
2349 nic->leds = (nic->leds & led_on) ? led_off :
2350 (nic->mac < mac_82559_D101M) ? led_on_557 :
2351 led_on_559;
2352 }
2353 mdio_write(nic->netdev, nic->mii.phy_id, led_reg, nic->leds);
1da177e4
LT		 2354 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2355}
2356
2357static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2358{
2359 struct nic *nic = netdev_priv(netdev);
2360 return mii_ethtool_gset(&nic->mii, cmd);
2361}
2362
2363static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2364{
2365 struct nic *nic = netdev_priv(netdev);
2366 int err;
2367
2368 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2369 err = mii_ethtool_sset(&nic->mii, cmd);
2370 e100_exec_cb(nic, NULL, e100_configure);
2371
2372 return err;
2373}
2374
2375static void e100_get_drvinfo(struct net_device *netdev,
2376 struct ethtool_drvinfo *info)
2377{
2378 struct nic *nic = netdev_priv(netdev);
2379 strcpy(info->driver, DRV_NAME);
2380 strcpy(info->version, DRV_VERSION);
2381 strcpy(info->fw_version, "N/A");
2382 strcpy(info->bus_info, pci_name(nic->pdev));
2383}
2384
abf9b902 2385#define E100_PHY_REGS 0x1C
1da177e4
LT		 2386static int e100_get_regs_len(struct net_device *netdev)
2387{
2388 struct nic *nic = netdev_priv(netdev);
abf9b902 2389 return 1 + E100_PHY_REGS + sizeof(nic->mem->dump_buf);
1da177e4
LT		 2390}
2391
2392static void e100_get_regs(struct net_device *netdev,
2393 struct ethtool_regs *regs, void *p)
2394{
2395 struct nic *nic = netdev_priv(netdev);
2396 u32 *buff = p;
2397 int i;
2398
44c10138 2399 regs->version = (1 << 24) | nic->pdev->revision;
27345bb6
JB		 2400 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2401 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2402 ioread16(&nic->csr->scb.status);
f26251eb 2403 for (i = E100_PHY_REGS; i >= 0; i--)
1da177e4
LT		 2404 buff[1 + E100_PHY_REGS - i] =
2405 mdio_read(netdev, nic->mii.phy_id, i);
2406 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2407 e100_exec_cb(nic, NULL, e100_dump);
2408 msleep(10);
2409 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2410 sizeof(nic->mem->dump_buf));
2411}
2412
2413static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2414{
2415 struct nic *nic = netdev_priv(netdev);
2416 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2417 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2418}
2419
2420static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2421{
2422 struct nic *nic = netdev_priv(netdev);
2423
bc79fc84
RW		 2424 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2425 !device_can_wakeup(&nic->pdev->dev))
1da177e4
LT		 2426 return -EOPNOTSUPP;
2427
f26251eb 2428 if (wol->wolopts)
1da177e4
LT		 2429 nic->flags |= wol_magic;
2430 else
2431 nic->flags &= ~wol_magic;
2432
bc79fc84
RW		 2433 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2434
1da177e4
LT		 2435 e100_exec_cb(nic, NULL, e100_configure);
2436
2437 return 0;
2438}
2439
2440static u32 e100_get_msglevel(struct net_device *netdev)
2441{
2442 struct nic *nic = netdev_priv(netdev);
2443 return nic->msg_enable;
2444}
2445
2446static void e100_set_msglevel(struct net_device *netdev, u32 value)
2447{
2448 struct nic *nic = netdev_priv(netdev);
2449 nic->msg_enable = value;
2450}
2451
2452static int e100_nway_reset(struct net_device *netdev)
2453{
2454 struct nic *nic = netdev_priv(netdev);
2455 return mii_nway_restart(&nic->mii);
2456}
2457
2458static u32 e100_get_link(struct net_device *netdev)
2459{
2460 struct nic *nic = netdev_priv(netdev);
2461 return mii_link_ok(&nic->mii);
2462}
2463
2464static int e100_get_eeprom_len(struct net_device *netdev)
2465{
2466 struct nic *nic = netdev_priv(netdev);
2467 return nic->eeprom_wc << 1;
2468}
2469
2470#define E100_EEPROM_MAGIC 0x1234
2471static int e100_get_eeprom(struct net_device *netdev,
2472 struct ethtool_eeprom *eeprom, u8 *bytes)
2473{
2474 struct nic *nic = netdev_priv(netdev);
2475
2476 eeprom->magic = E100_EEPROM_MAGIC;
2477 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2478
2479 return 0;
2480}
2481
2482static int e100_set_eeprom(struct net_device *netdev,
2483 struct ethtool_eeprom *eeprom, u8 *bytes)
2484{
2485 struct nic *nic = netdev_priv(netdev);
2486
f26251eb 2487 if (eeprom->magic != E100_EEPROM_MAGIC)
1da177e4
LT		 2488 return -EINVAL;
2489
2490 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2491
2492 return e100_eeprom_save(nic, eeprom->offset >> 1,
2493 (eeprom->len >> 1) + 1);
2494}
2495
2496static void e100_get_ringparam(struct net_device *netdev,
2497 struct ethtool_ringparam *ring)
2498{
2499 struct nic *nic = netdev_priv(netdev);
2500 struct param_range *rfds = &nic->params.rfds;
2501 struct param_range *cbs = &nic->params.cbs;
2502
2503 ring->rx_max_pending = rfds->max;
2504 ring->tx_max_pending = cbs->max;
2505 ring->rx_mini_max_pending = 0;
2506 ring->rx_jumbo_max_pending = 0;
2507 ring->rx_pending = rfds->count;
2508 ring->tx_pending = cbs->count;
2509 ring->rx_mini_pending = 0;
2510 ring->rx_jumbo_pending = 0;
2511}
2512
2513static int e100_set_ringparam(struct net_device *netdev,
2514 struct ethtool_ringparam *ring)
2515{
2516 struct nic *nic = netdev_priv(netdev);
2517 struct param_range *rfds = &nic->params.rfds;
2518 struct param_range *cbs = &nic->params.cbs;
2519
05479938 2520 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
1da177e4
LT		 2521 return -EINVAL;
2522
f26251eb 2523 if (netif_running(netdev))
1da177e4
LT		 2524 e100_down(nic);
2525 rfds->count = max(ring->rx_pending, rfds->min);
2526 rfds->count = min(rfds->count, rfds->max);
2527 cbs->count = max(ring->tx_pending, cbs->min);
2528 cbs->count = min(cbs->count, cbs->max);
2529 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2530 rfds->count, cbs->count);
f26251eb 2531 if (netif_running(netdev))
1da177e4
LT		 2532 e100_up(nic);
2533
2534 return 0;
2535}
2536
2537static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2538 "Link test (on/offline)",
2539 "Eeprom test (on/offline)",
2540 "Self test (offline)",
2541 "Mac loopback (offline)",
2542 "Phy loopback (offline)",
2543};
4c3616cd 2544#define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
1da177e4 2545
1da177e4
LT		 2546static void e100_diag_test(struct net_device *netdev,
2547 struct ethtool_test *test, u64 *data)
2548{
2549 struct ethtool_cmd cmd;
2550 struct nic *nic = netdev_priv(netdev);
2551 int i, err;
2552
2553 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2554 data[0] = !mii_link_ok(&nic->mii);
2555 data[1] = e100_eeprom_load(nic);
f26251eb 2556 if (test->flags & ETH_TEST_FL_OFFLINE) {
1da177e4
LT		 2557
2558 /* save speed, duplex & autoneg settings */
2559 err = mii_ethtool_gset(&nic->mii, &cmd);
2560
f26251eb 2561 if (netif_running(netdev))
1da177e4
LT		 2562 e100_down(nic);
2563 data[2] = e100_self_test(nic);
2564 data[3] = e100_loopback_test(nic, lb_mac);
2565 data[4] = e100_loopback_test(nic, lb_phy);
2566
2567 /* restore speed, duplex & autoneg settings */
2568 err = mii_ethtool_sset(&nic->mii, &cmd);
2569
f26251eb 2570 if (netif_running(netdev))
1da177e4
LT		 2571 e100_up(nic);
2572 }
f26251eb 2573 for (i = 0; i < E100_TEST_LEN; i++)
1da177e4 2574 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
a074fb86
MC		 2575
2576 msleep_interruptible(4 * 1000);
1da177e4
LT		 2577}
2578
2579static int e100_phys_id(struct net_device *netdev, u32 data)
2580{
2581 struct nic *nic = netdev_priv(netdev);
b55de80e
BA		 2582 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2583 MII_LED_CONTROL;
1da177e4 2584
f26251eb 2585 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1da177e4
LT		 2586 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2587 mod_timer(&nic->blink_timer, jiffies);
2588 msleep_interruptible(data * 1000);
2589 del_timer_sync(&nic->blink_timer);
b55de80e 2590 mdio_write(netdev, nic->mii.phy_id, led_reg, 0);
1da177e4
LT		 2591
2592 return 0;
2593}
2594
2595static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2596 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2597 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2598 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2599 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2600 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2601 "tx_heartbeat_errors", "tx_window_errors",
2602 /* device-specific stats */
2603 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2604 "tx_flow_control_pause", "rx_flow_control_pause",
2605 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2606};
2607#define E100_NET_STATS_LEN 21
4c3616cd 2608#define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
1da177e4 2609
b9f2c044 2610static int e100_get_sset_count(struct net_device *netdev, int sset)
1da177e4 2611{
b9f2c044
JG		 2612 switch (sset) {
2613 case ETH_SS_TEST:
2614 return E100_TEST_LEN;
2615 case ETH_SS_STATS:
2616 return E100_STATS_LEN;
2617 default:
2618 return -EOPNOTSUPP;
2619 }
1da177e4
LT		 2620}
2621
2622static void e100_get_ethtool_stats(struct net_device *netdev,
2623 struct ethtool_stats *stats, u64 *data)
2624{
2625 struct nic *nic = netdev_priv(netdev);
2626 int i;
2627
f26251eb 2628 for (i = 0; i < E100_NET_STATS_LEN; i++)
09f75cd7 2629 data[i] = ((unsigned long *)&netdev->stats)[i];
1da177e4
LT		 2630
2631 data[i++] = nic->tx_deferred;
2632 data[i++] = nic->tx_single_collisions;
2633 data[i++] = nic->tx_multiple_collisions;
2634 data[i++] = nic->tx_fc_pause;
2635 data[i++] = nic->rx_fc_pause;
2636 data[i++] = nic->rx_fc_unsupported;
2637 data[i++] = nic->tx_tco_frames;
2638 data[i++] = nic->rx_tco_frames;
2639}
2640
2641static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2642{
f26251eb 2643 switch (stringset) {
1da177e4
LT		 2644 case ETH_SS_TEST:
2645 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2646 break;
2647 case ETH_SS_STATS:
2648 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2649 break;
2650 }
2651}
2652
7282d491 2653static const struct ethtool_ops e100_ethtool_ops = {
1da177e4
LT		 2654 .get_settings = e100_get_settings,
2655 .set_settings = e100_set_settings,
2656 .get_drvinfo = e100_get_drvinfo,
2657 .get_regs_len = e100_get_regs_len,
2658 .get_regs = e100_get_regs,
2659 .get_wol = e100_get_wol,
2660 .set_wol = e100_set_wol,
2661 .get_msglevel = e100_get_msglevel,
2662 .set_msglevel = e100_set_msglevel,
2663 .nway_reset = e100_nway_reset,
2664 .get_link = e100_get_link,
2665 .get_eeprom_len = e100_get_eeprom_len,
2666 .get_eeprom = e100_get_eeprom,
2667 .set_eeprom = e100_set_eeprom,
2668 .get_ringparam = e100_get_ringparam,
2669 .set_ringparam = e100_set_ringparam,
1da177e4
LT		 2670 .self_test = e100_diag_test,
2671 .get_strings = e100_get_strings,
2672 .phys_id = e100_phys_id,
1da177e4 2673 .get_ethtool_stats = e100_get_ethtool_stats,
b9f2c044 2674 .get_sset_count = e100_get_sset_count,
1da177e4
LT		 2675};
2676
2677static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2678{
2679 struct nic *nic = netdev_priv(netdev);
2680
2681 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2682}
2683
2684static int e100_alloc(struct nic *nic)
2685{
2686 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2687 &nic->dma_addr);
2688 return nic->mem ? 0 : -ENOMEM;
2689}
2690
2691static void e100_free(struct nic *nic)
2692{
f26251eb 2693 if (nic->mem) {
1da177e4
LT		 2694 pci_free_consistent(nic->pdev, sizeof(struct mem),
2695 nic->mem, nic->dma_addr);
2696 nic->mem = NULL;
2697 }
2698}
2699
2700static int e100_open(struct net_device *netdev)
2701{
2702 struct nic *nic = netdev_priv(netdev);
2703 int err = 0;
2704
2705 netif_carrier_off(netdev);
f26251eb 2706 if ((err = e100_up(nic)))
1da177e4
LT		 2707 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2708 return err;
2709}
2710
2711static int e100_close(struct net_device *netdev)
2712{
2713 e100_down(netdev_priv(netdev));
2714 return 0;
2715}
2716
acc78426
SH		 2717static const struct net_device_ops e100_netdev_ops = {
2718 .ndo_open = e100_open,
2719 .ndo_stop = e100_close,
00829823 2720 .ndo_start_xmit = e100_xmit_frame,
acc78426
SH		 2721 .ndo_validate_addr = eth_validate_addr,
2722 .ndo_set_multicast_list = e100_set_multicast_list,
2723 .ndo_set_mac_address = e100_set_mac_address,
2724 .ndo_change_mtu = e100_change_mtu,
2725 .ndo_do_ioctl = e100_do_ioctl,
2726 .ndo_tx_timeout = e100_tx_timeout,
2727#ifdef CONFIG_NET_POLL_CONTROLLER
2728 .ndo_poll_controller = e100_netpoll,
2729#endif
2730};
2731
1da177e4
LT		 2732static int __devinit e100_probe(struct pci_dev *pdev,
2733 const struct pci_device_id *ent)
2734{
2735 struct net_device *netdev;
2736 struct nic *nic;
2737 int err;
2738
f26251eb
BA		 2739 if (!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2740 if (((1 << debug) - 1) & NETIF_MSG_PROBE)
1da177e4
LT		 2741 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2742 return -ENOMEM;
2743 }
2744
acc78426 2745 netdev->netdev_ops = &e100_netdev_ops;
1da177e4 2746 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
1da177e4 2747 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
0eb5a34c 2748 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1da177e4
LT		 2749
2750 nic = netdev_priv(netdev);
bea3348e 2751 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
1da177e4
LT		 2752 nic->netdev = netdev;
2753 nic->pdev = pdev;
2754 nic->msg_enable = (1 << debug) - 1;
72001762 2755 nic->mdio_ctrl = mdio_ctrl_hw;
1da177e4
LT		 2756 pci_set_drvdata(pdev, netdev);
2757
f26251eb 2758 if ((err = pci_enable_device(pdev))) {
1da177e4
LT		 2759 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2760 goto err_out_free_dev;
2761 }
2762
f26251eb 2763 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1da177e4
LT		 2764 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2765 "base address, aborting.\n");
2766 err = -ENODEV;
2767 goto err_out_disable_pdev;
2768 }
2769
f26251eb 2770 if ((err = pci_request_regions(pdev, DRV_NAME))) {
1da177e4
LT		 2771 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2772 goto err_out_disable_pdev;
2773 }
2774
284901a9 2775 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
1da177e4
LT		 2776 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2777 goto err_out_free_res;
2778 }
2779
1da177e4
LT		 2780 SET_NETDEV_DEV(netdev, &pdev->dev);
2781
27345bb6
JB		 2782 if (use_io)
2783 DPRINTK(PROBE, INFO, "using i/o access mode\n");
2784
2785 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
f26251eb 2786 if (!nic->csr) {
1da177e4
LT		 2787 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2788 err = -ENOMEM;
2789 goto err_out_free_res;
2790 }
2791
f26251eb 2792 if (ent->driver_data)
1da177e4
LT		 2793 nic->flags |= ich;
2794 else
2795 nic->flags &= ~ich;
2796
2797 e100_get_defaults(nic);
2798
1f53367d 2799 /* locks must be initialized before calling hw_reset */
1da177e4
LT		 2800 spin_lock_init(&nic->cb_lock);
2801 spin_lock_init(&nic->cmd_lock);
ac7c6669 2802 spin_lock_init(&nic->mdio_lock);
1da177e4
LT		 2803
2804 /* Reset the device before pci_set_master() in case device is in some
2805 * funky state and has an interrupt pending - hint: we don't have the
2806 * interrupt handler registered yet. */
2807 e100_hw_reset(nic);
2808
2809 pci_set_master(pdev);
2810
2811 init_timer(&nic->watchdog);
2812 nic->watchdog.function = e100_watchdog;
2813 nic->watchdog.data = (unsigned long)nic;
2814 init_timer(&nic->blink_timer);
2815 nic->blink_timer.function = e100_blink_led;
2816 nic->blink_timer.data = (unsigned long)nic;
2817
c4028958 2818 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2acdb1e0 2819
f26251eb 2820 if ((err = e100_alloc(nic))) {
1da177e4
LT		 2821 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2822 goto err_out_iounmap;
2823 }
2824
f26251eb 2825 if ((err = e100_eeprom_load(nic)))
1da177e4
LT		 2826 goto err_out_free;
2827
f92d8728
MC		 2828 e100_phy_init(nic);
2829
1da177e4 2830 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
a92dd923 2831 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
948cd43f
JB		 2832 if (!is_valid_ether_addr(netdev->perm_addr)) {
2833 if (!eeprom_bad_csum_allow) {
2834 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2835 "EEPROM, aborting.\n");
2836 err = -EAGAIN;
2837 goto err_out_free;
2838 } else {
2839 DPRINTK(PROBE, ERR, "Invalid MAC address from EEPROM, "
2840 "you MUST configure one.\n");
2841 }
1da177e4
LT		 2842 }
2843
2844 /* Wol magic packet can be enabled from eeprom */
f26251eb 2845 if ((nic->mac >= mac_82558_D101_A4) &&
bc79fc84 2846 (nic->eeprom[eeprom_id] & eeprom_id_wol)) {
1da177e4 2847 nic->flags |= wol_magic;
bc79fc84
RW		 2848 device_set_wakeup_enable(&pdev->dev, true);
2849 }
1da177e4 2850
6bdacb1a 2851 /* ack any pending wake events, disable PME */
e7272403 2852 pci_pme_active(pdev, false);
1da177e4
LT		 2853
2854 strcpy(netdev->name, "eth%d");
f26251eb 2855 if ((err = register_netdev(netdev))) {
1da177e4
LT		 2856 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2857 goto err_out_free;
2858 }
98468efd
RO		 2859 nic->cbs_pool = pci_pool_create(netdev->name,
2860 nic->pdev,
211a0d94 2861 nic->params.cbs.max * sizeof(struct cb),
98468efd
RO		 2862 sizeof(u32),
2863 0);
e174961c 2864 DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, MAC addr %pM\n",
0795af57 2865 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
e174961c 2866 pdev->irq, netdev->dev_addr);
1da177e4
LT		 2867
2868 return 0;
2869
2870err_out_free:
2871 e100_free(nic);
2872err_out_iounmap:
27345bb6 2873 pci_iounmap(pdev, nic->csr);
1da177e4
LT		 2874err_out_free_res:
2875 pci_release_regions(pdev);
2876err_out_disable_pdev:
2877 pci_disable_device(pdev);
2878err_out_free_dev:
2879 pci_set_drvdata(pdev, NULL);
2880 free_netdev(netdev);
2881 return err;
2882}
2883
2884static void __devexit e100_remove(struct pci_dev *pdev)
2885{
2886 struct net_device *netdev = pci_get_drvdata(pdev);
2887
f26251eb 2888 if (netdev) {
1da177e4
LT		 2889 struct nic *nic = netdev_priv(netdev);
2890 unregister_netdev(netdev);
2891 e100_free(nic);
915e91d7 2892 pci_iounmap(pdev, nic->csr);
98468efd 2893 pci_pool_destroy(nic->cbs_pool);
1da177e4
LT		 2894 free_netdev(netdev);
2895 pci_release_regions(pdev);
2896 pci_disable_device(pdev);
2897 pci_set_drvdata(pdev, NULL);
2898 }
2899}
2900
b55de80e
BA		 2901#define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2902#define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
2903#define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
ac7c992c 2904static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
1da177e4
LT		 2905{
2906 struct net_device *netdev = pci_get_drvdata(pdev);
2907 struct nic *nic = netdev_priv(netdev);
2908
824545e7 2909 if (netif_running(netdev))
f902283b 2910 e100_down(nic);
518d8338 2911 netif_device_detach(netdev);
a53a33da 2912
1da177e4 2913 pci_save_state(pdev);
e8e82b76
AK		 2914
2915 if ((nic->flags & wol_magic) | e100_asf(nic)) {
b55de80e
BA		 2916 /* enable reverse auto-negotiation */
2917 if (nic->phy == phy_82552_v) {
2918 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2919 E100_82552_SMARTSPEED);
2920
2921 mdio_write(netdev, nic->mii.phy_id,
2922 E100_82552_SMARTSPEED, smartspeed |
2923 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
2924 }
ac7c992c 2925 *enable_wake = true;
e8e82b76 2926 } else {
ac7c992c 2927 *enable_wake = false;
e8e82b76 2928 }
975b366a 2929
8543da66 2930 pci_disable_device(pdev);
ac7c992c 2931}
1da177e4 2932
ac7c992c
TLSC		 2933static int __e100_power_off(struct pci_dev *pdev, bool wake)
2934{
6905b1f1 2935 if (wake)
ac7c992c 2936 return pci_prepare_to_sleep(pdev);
6905b1f1
RW		 2937
2938 pci_wake_from_d3(pdev, false);
2939 pci_set_power_state(pdev, PCI_D3hot);
2940
2941 return 0;
1da177e4
LT		 2942}
2943
f902283b 2944#ifdef CONFIG_PM
ac7c992c
TLSC		 2945static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2946{
2947 bool wake;
2948 __e100_shutdown(pdev, &wake);
2949 return __e100_power_off(pdev, wake);
2950}
2951
1da177e4
LT		 2952static int e100_resume(struct pci_dev *pdev)
2953{
2954 struct net_device *netdev = pci_get_drvdata(pdev);
2955 struct nic *nic = netdev_priv(netdev);
2956
975b366a 2957 pci_set_power_state(pdev, PCI_D0);
1da177e4 2958 pci_restore_state(pdev);
6bdacb1a 2959 /* ack any pending wake events, disable PME */
975b366a 2960 pci_enable_wake(pdev, 0, 0);
1da177e4 2961
4b512d26 2962 /* disable reverse auto-negotiation */
b55de80e
BA		 2963 if (nic->phy == phy_82552_v) {
2964 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2965 E100_82552_SMARTSPEED);
2966
2967 mdio_write(netdev, nic->mii.phy_id,
2968 E100_82552_SMARTSPEED,
2969 smartspeed & ~(E100_82552_REV_ANEG));
2970 }
2971
1da177e4 2972 netif_device_attach(netdev);
975b366a 2973 if (netif_running(netdev))
1da177e4
LT		 2974 e100_up(nic);
2975
2976 return 0;
2977}
975b366a 2978#endif /* CONFIG_PM */
1da177e4 2979
d18c3db5 2980static void e100_shutdown(struct pci_dev *pdev)
6bdacb1a 2981{
ac7c992c
TLSC		 2982 bool wake;
2983 __e100_shutdown(pdev, &wake);
2984 if (system_state == SYSTEM_POWER_OFF)
2985 __e100_power_off(pdev, wake);
6bdacb1a
MC		 2986}
2987
2cc30492
AK		 2988/* ------------------ PCI Error Recovery infrastructure -------------- */
2989/**
2990 * e100_io_error_detected - called when PCI error is detected.
2991 * @pdev: Pointer to PCI device
0a0863af 2992 * @state: The current pci connection state
2cc30492
AK		 2993 */
2994static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2995{
2996 struct net_device *netdev = pci_get_drvdata(pdev);
bea3348e 2997 struct nic *nic = netdev_priv(netdev);
2cc30492 2998
2cc30492 2999 netif_device_detach(netdev);
ef681ce1
AD		 3000
3001 if (state == pci_channel_io_perm_failure)
3002 return PCI_ERS_RESULT_DISCONNECT;
3003
3004 if (netif_running(netdev))
3005 e100_down(nic);
b1d26f24 3006 pci_disable_device(pdev);
2cc30492
AK		 3007
3008 /* Request a slot reset. */
3009 return PCI_ERS_RESULT_NEED_RESET;
3010}
3011
3012/**
3013 * e100_io_slot_reset - called after the pci bus has been reset.
3014 * @pdev: Pointer to PCI device
3015 *
3016 * Restart the card from scratch.
3017 */
3018static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
3019{
3020 struct net_device *netdev = pci_get_drvdata(pdev);
3021 struct nic *nic = netdev_priv(netdev);
3022
3023 if (pci_enable_device(pdev)) {
3024 printk(KERN_ERR "e100: Cannot re-enable PCI device after reset.\n");
3025 return PCI_ERS_RESULT_DISCONNECT;
3026 }
3027 pci_set_master(pdev);
3028
3029 /* Only one device per card can do a reset */
3030 if (0 != PCI_FUNC(pdev->devfn))
3031 return PCI_ERS_RESULT_RECOVERED;
3032 e100_hw_reset(nic);
3033 e100_phy_init(nic);
3034
3035 return PCI_ERS_RESULT_RECOVERED;
3036}
3037
3038/**
3039 * e100_io_resume - resume normal operations
3040 * @pdev: Pointer to PCI device
3041 *
3042 * Resume normal operations after an error recovery
3043 * sequence has been completed.
3044 */
3045static void e100_io_resume(struct pci_dev *pdev)
3046{
3047 struct net_device *netdev = pci_get_drvdata(pdev);
3048 struct nic *nic = netdev_priv(netdev);
3049
3050 /* ack any pending wake events, disable PME */
3051 pci_enable_wake(pdev, 0, 0);
3052
3053 netif_device_attach(netdev);
3054 if (netif_running(netdev)) {
3055 e100_open(netdev);
3056 mod_timer(&nic->watchdog, jiffies);
3057 }
3058}
3059
3060static struct pci_error_handlers e100_err_handler = {
3061 .error_detected = e100_io_error_detected,
3062 .slot_reset = e100_io_slot_reset,
3063 .resume = e100_io_resume,
3064};
6bdacb1a 3065
1da177e4
LT		 3066static struct pci_driver e100_driver = {
3067 .name = DRV_NAME,
3068 .id_table = e100_id_table,
3069 .probe = e100_probe,
3070 .remove = __devexit_p(e100_remove),
e8e82b76 3071#ifdef CONFIG_PM
975b366a 3072 /* Power Management hooks */
1da177e4
LT		 3073 .suspend = e100_suspend,
3074 .resume = e100_resume,
3075#endif
05479938 3076 .shutdown = e100_shutdown,
2cc30492 3077 .err_handler = &e100_err_handler,
1da177e4
LT		 3078};
3079
3080static int __init e100_init_module(void)
3081{
f26251eb 3082 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
1da177e4
LT		 3083 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
3084 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
3085 }
29917620 3086 return pci_register_driver(&e100_driver);
1da177e4
LT		 3087}
3088
3089static void __exit e100_cleanup_module(void)
3090{
3091 pci_unregister_driver(&e100_driver);
3092}
3093
3094module_init(e100_init_module);
3095module_exit(e100_cleanup_module);
Linux 6.x block layer and io_uring tree(s)