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Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / net / dsa / qca8k.c
CommitLineData
63a786a3 1// SPDX-License-Identifier: GPL-2.0
6b93fb46
JC		 2/*
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
abb48f80 5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
6b93fb46 6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
6b93fb46
JC		 7 */
8
9#include <linux/module.h>
10#include <linux/phy.h>
11#include <linux/netdevice.h>
12#include <net/dsa.h>
6b93fb46
JC		 13#include <linux/of_net.h>
14#include <linux/of_platform.h>
15#include <linux/if_bridge.h>
16#include <linux/mdio.h>
f32ae8a5 17#include <linux/gpio/consumer.h>
6b93fb46
JC		 18#include <linux/etherdevice.h>
19
20#include "qca8k.h"
21
22#define MIB_DESC(_s, _o, _n) \
23 { \
24 .size = (_s), \
25 .offset = (_o), \
26 .name = (_n), \
27 }
28
29static const struct qca8k_mib_desc ar8327_mib[] = {
30 MIB_DESC(1, 0x00, "RxBroad"),
31 MIB_DESC(1, 0x04, "RxPause"),
32 MIB_DESC(1, 0x08, "RxMulti"),
33 MIB_DESC(1, 0x0c, "RxFcsErr"),
34 MIB_DESC(1, 0x10, "RxAlignErr"),
35 MIB_DESC(1, 0x14, "RxRunt"),
36 MIB_DESC(1, 0x18, "RxFragment"),
37 MIB_DESC(1, 0x1c, "Rx64Byte"),
38 MIB_DESC(1, 0x20, "Rx128Byte"),
39 MIB_DESC(1, 0x24, "Rx256Byte"),
40 MIB_DESC(1, 0x28, "Rx512Byte"),
41 MIB_DESC(1, 0x2c, "Rx1024Byte"),
42 MIB_DESC(1, 0x30, "Rx1518Byte"),
43 MIB_DESC(1, 0x34, "RxMaxByte"),
44 MIB_DESC(1, 0x38, "RxTooLong"),
45 MIB_DESC(2, 0x3c, "RxGoodByte"),
46 MIB_DESC(2, 0x44, "RxBadByte"),
47 MIB_DESC(1, 0x4c, "RxOverFlow"),
48 MIB_DESC(1, 0x50, "Filtered"),
49 MIB_DESC(1, 0x54, "TxBroad"),
50 MIB_DESC(1, 0x58, "TxPause"),
51 MIB_DESC(1, 0x5c, "TxMulti"),
52 MIB_DESC(1, 0x60, "TxUnderRun"),
53 MIB_DESC(1, 0x64, "Tx64Byte"),
54 MIB_DESC(1, 0x68, "Tx128Byte"),
55 MIB_DESC(1, 0x6c, "Tx256Byte"),
56 MIB_DESC(1, 0x70, "Tx512Byte"),
57 MIB_DESC(1, 0x74, "Tx1024Byte"),
58 MIB_DESC(1, 0x78, "Tx1518Byte"),
59 MIB_DESC(1, 0x7c, "TxMaxByte"),
60 MIB_DESC(1, 0x80, "TxOverSize"),
61 MIB_DESC(2, 0x84, "TxByte"),
62 MIB_DESC(1, 0x8c, "TxCollision"),
63 MIB_DESC(1, 0x90, "TxAbortCol"),
64 MIB_DESC(1, 0x94, "TxMultiCol"),
65 MIB_DESC(1, 0x98, "TxSingleCol"),
66 MIB_DESC(1, 0x9c, "TxExcDefer"),
67 MIB_DESC(1, 0xa0, "TxDefer"),
68 MIB_DESC(1, 0xa4, "TxLateCol"),
69};
70
71/* The 32bit switch registers are accessed indirectly. To achieve this we need
72 * to set the page of the register. Track the last page that was set to reduce
73 * mdio writes
74 */
75static u16 qca8k_current_page = 0xffff;
76
77static void
78qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
79{
80 regaddr >>= 1;
81 *r1 = regaddr & 0x1e;
82
83 regaddr >>= 5;
84 *r2 = regaddr & 0x7;
85
86 regaddr >>= 3;
87 *page = regaddr & 0x3ff;
88}
89
90static u32
91qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum)
92{
93 u32 val;
94 int ret;
95
96 ret = bus->read(bus, phy_id, regnum);
97 if (ret >= 0) {
98 val = ret;
99 ret = bus->read(bus, phy_id, regnum + 1);
100 val |= ret << 16;
101 }
102
103 if (ret < 0) {
104 dev_err_ratelimited(&bus->dev,
105 "failed to read qca8k 32bit register\n");
106 return ret;
107 }
108
109 return val;
110}
111
112static void
113qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
114{
115 u16 lo, hi;
116 int ret;
117
118 lo = val & 0xffff;
119 hi = (u16)(val >> 16);
120
121 ret = bus->write(bus, phy_id, regnum, lo);
122 if (ret >= 0)
123 ret = bus->write(bus, phy_id, regnum + 1, hi);
124 if (ret < 0)
125 dev_err_ratelimited(&bus->dev,
126 "failed to write qca8k 32bit register\n");
127}
128
129static void
130qca8k_set_page(struct mii_bus *bus, u16 page)
131{
132 if (page == qca8k_current_page)
133 return;
134
135 if (bus->write(bus, 0x18, 0, page) < 0)
136 dev_err_ratelimited(&bus->dev,
137 "failed to set qca8k page\n");
138 qca8k_current_page = page;
139}
140
141static u32
142qca8k_read(struct qca8k_priv *priv, u32 reg)
143{
144 u16 r1, r2, page;
145 u32 val;
146
147 qca8k_split_addr(reg, &r1, &r2, &page);
148
149 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
150
151 qca8k_set_page(priv->bus, page);
152 val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
153
154 mutex_unlock(&priv->bus->mdio_lock);
155
156 return val;
157}
158
159static void
160qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
161{
162 u16 r1, r2, page;
163
164 qca8k_split_addr(reg, &r1, &r2, &page);
165
166 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
167
168 qca8k_set_page(priv->bus, page);
169 qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);
170
171 mutex_unlock(&priv->bus->mdio_lock);
172}
173
174static u32
175qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
176{
177 u16 r1, r2, page;
178 u32 ret;
179
180 qca8k_split_addr(reg, &r1, &r2, &page);
181
182 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
183
184 qca8k_set_page(priv->bus, page);
185 ret = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
186 ret &= ~mask;
187 ret |= val;
188 qca8k_mii_write32(priv->bus, 0x10 | r2, r1, ret);
189
190 mutex_unlock(&priv->bus->mdio_lock);
191
192 return ret;
193}
194
195static void
196qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
197{
198 qca8k_rmw(priv, reg, 0, val);
199}
200
201static void
202qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
203{
204 qca8k_rmw(priv, reg, val, 0);
205}
206
207static int
208qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
209{
210 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
211
212 *val = qca8k_read(priv, reg);
213
214 return 0;
215}
216
217static int
218qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
219{
220 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
221
222 qca8k_write(priv, reg, val);
223
224 return 0;
225}
226
227static const struct regmap_range qca8k_readable_ranges[] = {
228 regmap_reg_range(0x0000, 0x00e4), /* Global control */
229 regmap_reg_range(0x0100, 0x0168), /* EEE control */
230 regmap_reg_range(0x0200, 0x0270), /* Parser control */
231 regmap_reg_range(0x0400, 0x0454), /* ACL */
232 regmap_reg_range(0x0600, 0x0718), /* Lookup */
233 regmap_reg_range(0x0800, 0x0b70), /* QM */
234 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
235 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
236 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
237 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
238 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
239 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
240 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
241 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
242 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
243
244};
245
7e3108fa 246static const struct regmap_access_table qca8k_readable_table = {
6b93fb46
JC		 247 .yes_ranges = qca8k_readable_ranges,
248 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
249};
250
fcfbfd68 251static struct regmap_config qca8k_regmap_config = {
6b93fb46
JC		 252 .reg_bits = 16,
253 .val_bits = 32,
254 .reg_stride = 4,
255 .max_register = 0x16ac, /* end MIB - Port6 range */
256 .reg_read = qca8k_regmap_read,
257 .reg_write = qca8k_regmap_write,
258 .rd_table = &qca8k_readable_table,
259};
260
261static int
262qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
263{
264 unsigned long timeout;
265
266 timeout = jiffies + msecs_to_jiffies(20);
267
268 /* loop until the busy flag has cleared */
269 do {
270 u32 val = qca8k_read(priv, reg);
271 int busy = val & mask;
272
273 if (!busy)
274 break;
275 cond_resched();
276 } while (!time_after_eq(jiffies, timeout));
277
278 return time_after_eq(jiffies, timeout);
279}
280
281static void
282qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
283{
284 u32 reg[4];
285 int i;
286
287 /* load the ARL table into an array */
288 for (i = 0; i < 4; i++)
289 reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
290
291 /* vid - 83:72 */
292 fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
293 /* aging - 67:64 */
294 fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
295 /* portmask - 54:48 */
296 fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
297 /* mac - 47:0 */
298 fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
299 fdb->mac[1] = reg[1] & 0xff;
300 fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
301 fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
302 fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
303 fdb->mac[5] = reg[0] & 0xff;
304}
305
306static void
307qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
308 u8 aging)
309{
310 u32 reg[3] = { 0 };
311 int i;
312
313 /* vid - 83:72 */
314 reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
315 /* aging - 67:64 */
316 reg[2] |= aging & QCA8K_ATU_STATUS_M;
317 /* portmask - 54:48 */
318 reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
319 /* mac - 47:0 */
320 reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
321 reg[1] |= mac[1];
322 reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
323 reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
324 reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
325 reg[0] |= mac[5];
326
327 /* load the array into the ARL table */
328 for (i = 0; i < 3; i++)
329 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
330}
331
332static int
333qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
334{
335 u32 reg;
336
337 /* Set the command and FDB index */
338 reg = QCA8K_ATU_FUNC_BUSY;
339 reg |= cmd;
340 if (port >= 0) {
341 reg |= QCA8K_ATU_FUNC_PORT_EN;
342 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
343 }
344
345 /* Write the function register triggering the table access */
346 qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
347
348 /* wait for completion */
349 if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))
350 return -1;
351
352 /* Check for table full violation when adding an entry */
353 if (cmd == QCA8K_FDB_LOAD) {
354 reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);
355 if (reg & QCA8K_ATU_FUNC_FULL)
356 return -1;
357 }
358
359 return 0;
360}
361
362static int
363qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
364{
365 int ret;
366
367 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
368 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
369 if (ret >= 0)
370 qca8k_fdb_read(priv, fdb);
371
372 return ret;
373}
374
375static int
376qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
377 u16 vid, u8 aging)
378{
379 int ret;
380
381 mutex_lock(&priv->reg_mutex);
382 qca8k_fdb_write(priv, vid, port_mask, mac, aging);
383 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
384 mutex_unlock(&priv->reg_mutex);
385
386 return ret;
387}
388
389static int
390qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
391{
392 int ret;
393
394 mutex_lock(&priv->reg_mutex);
395 qca8k_fdb_write(priv, vid, port_mask, mac, 0);
396 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
397 mutex_unlock(&priv->reg_mutex);
398
399 return ret;
400}
401
402static void
403qca8k_fdb_flush(struct qca8k_priv *priv)
404{
405 mutex_lock(&priv->reg_mutex);
406 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
407 mutex_unlock(&priv->reg_mutex);
408}
409
410static void
411qca8k_mib_init(struct qca8k_priv *priv)
412{
413 mutex_lock(&priv->reg_mutex);
414 qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
415 qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
416 qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
417 qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
418 mutex_unlock(&priv->reg_mutex);
419}
420
421static int
422qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
423{
5ecdd77c 424 u32 reg, val;
6b93fb46
JC		 425
426 switch (port) {
427 case 0:
428 reg = QCA8K_REG_PORT0_PAD_CTRL;
429 break;
430 case 6:
431 reg = QCA8K_REG_PORT6_PAD_CTRL;
432 break;
433 default:
434 pr_err("Can't set PAD_CTRL on port %d\n", port);
435 return -EINVAL;
436 }
437
438 /* Configure a port to be directly connected to an external
439 * PHY or MAC.
440 */
441 switch (mode) {
442 case PHY_INTERFACE_MODE_RGMII:
5ecdd77c
VK		 443 /* RGMII mode means no delay so don't enable the delay */
444 val = QCA8K_PORT_PAD_RGMII_EN;
445 qca8k_write(priv, reg, val);
6b93fb46 446 break;
a968b5e9
VK		 447 case PHY_INTERFACE_MODE_RGMII_ID:
448 /* RGMII_ID needs internal delay. This is enabled through
449 * PORT5_PAD_CTRL for all ports, rather than individual port
450 * registers
451 */
452 qca8k_write(priv, reg,
453 QCA8K_PORT_PAD_RGMII_EN |
454 QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |
455 QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));
456 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
457 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
458 break;
6b93fb46
JC		 459 case PHY_INTERFACE_MODE_SGMII:
460 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
461 break;
462 default:
463 pr_err("xMII mode %d not supported\n", mode);
464 return -EINVAL;
465 }
466
467 return 0;
468}
469
470static void
471qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
472{
eee1fe64 473 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
6b93fb46
JC		 474
475 /* Port 0 and 6 have no internal PHY */
38222b1a 476 if (port > 0 && port < 6)
6b93fb46
JC		 477 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
478
479 if (enable)
480 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
481 else
482 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
483}
484
db460c54
CL		 485static u32
486qca8k_port_to_phy(int port)
487{
488 /* From Andrew Lunn:
489 * Port 0 has no internal phy.
490 * Port 1 has an internal PHY at MDIO address 0.
491 * Port 2 has an internal PHY at MDIO address 1.
492 * ...
493 * Port 5 has an internal PHY at MDIO address 4.
494 * Port 6 has no internal PHY.
495 */
496
497 return port - 1;
498}
499
500static int
501qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data)
502{
503 u32 phy, val;
504
505 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
506 return -EINVAL;
507
508 /* callee is responsible for not passing bad ports,
509 * but we still would like to make spills impossible.
510 */
511 phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
512 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
513 QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
514 QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
515 QCA8K_MDIO_MASTER_DATA(data);
516
517 qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
518
519 return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
520 QCA8K_MDIO_MASTER_BUSY);
521}
522
523static int
524qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum)
525{
526 u32 phy, val;
527
528 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
529 return -EINVAL;
530
531 /* callee is responsible for not passing bad ports,
532 * but we still would like to make spills impossible.
533 */
534 phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
535 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
536 QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
537 QCA8K_MDIO_MASTER_REG_ADDR(regnum);
538
539 qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
540
541 if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
542 QCA8K_MDIO_MASTER_BUSY))
543 return -ETIMEDOUT;
544
545 val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) &
546 QCA8K_MDIO_MASTER_DATA_MASK);
547
548 return val;
549}
550
551static int
552qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data)
553{
554 struct qca8k_priv *priv = ds->priv;
555
556 return qca8k_mdio_write(priv, port, regnum, data);
557}
558
559static int
560qca8k_phy_read(struct dsa_switch *ds, int port, int regnum)
561{
562 struct qca8k_priv *priv = ds->priv;
563 int ret;
564
565 ret = qca8k_mdio_read(priv, port, regnum);
566
567 if (ret < 0)
568 return 0xffff;
569
570 return ret;
571}
572
573static int
574qca8k_setup_mdio_bus(struct qca8k_priv *priv)
575{
576 u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
577 struct device_node *ports, *port;
578 int err;
579
580 ports = of_get_child_by_name(priv->dev->of_node, "ports");
581 if (!ports)
582 return -EINVAL;
583
584 for_each_available_child_of_node(ports, port) {
585 err = of_property_read_u32(port, "reg", &reg);
f26e0cca
ND		 586 if (err) {
587 of_node_put(port);
588 of_node_put(ports);
db460c54 589 return err;
f26e0cca 590 }
db460c54
CL		 591
592 if (!dsa_is_user_port(priv->ds, reg))
593 continue;
594
595 if (of_property_read_bool(port, "phy-handle"))
596 external_mdio_mask |= BIT(reg);
597 else
598 internal_mdio_mask |= BIT(reg);
599 }
600
f26e0cca 601 of_node_put(ports);
db460c54
CL		 602 if (!external_mdio_mask && !internal_mdio_mask) {
603 dev_err(priv->dev, "no PHYs are defined.\n");
604 return -EINVAL;
605 }
606
607 /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
608 * the MDIO_MASTER register also _disconnects_ the external MDC
609 * passthrough to the internal PHYs. It's not possible to use both
610 * configurations at the same time!
611 *
612 * Because this came up during the review process:
613 * If the external mdio-bus driver is capable magically disabling
614 * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
615 * accessors for the time being, it would be possible to pull this
616 * off.
617 */
618 if (!!external_mdio_mask && !!internal_mdio_mask) {
619 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
620 return -EINVAL;
621 }
622
623 if (external_mdio_mask) {
624 /* Make sure to disable the internal mdio bus in cases
625 * a dt-overlay and driver reload changed the configuration
626 */
627
628 qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
629 QCA8K_MDIO_MASTER_EN);
630 return 0;
631 }
632
633 priv->ops.phy_read = qca8k_phy_read;
634 priv->ops.phy_write = qca8k_phy_write;
635 return 0;
636}
637
6b93fb46
JC		 638static int
639qca8k_setup(struct dsa_switch *ds)
640{
641 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
0c65b2b9
AL		 642 phy_interface_t phy_mode = PHY_INTERFACE_MODE_NA;
643 int ret, i;
79a4ed4f 644 u32 mask;
6b93fb46
JC		 645
646 /* Make sure that port 0 is the cpu port */
647 if (!dsa_is_cpu_port(ds, 0)) {
648 pr_err("port 0 is not the CPU port\n");
649 return -EINVAL;
650 }
651
652 mutex_init(&priv->reg_mutex);
653
654 /* Start by setting up the register mapping */
655 priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
656 &qca8k_regmap_config);
657 if (IS_ERR(priv->regmap))
658 pr_warn("regmap initialization failed");
659
db460c54
CL		 660 ret = qca8k_setup_mdio_bus(priv);
661 if (ret)
662 return ret;
663
6b93fb46 664 /* Initialize CPU port pad mode (xMII type, delays...) */
0c65b2b9
AL		 665 ret = of_get_phy_mode(dsa_to_port(ds, QCA8K_CPU_PORT)->dn, &phy_mode);
666 if (ret) {
6b93fb46 667 pr_err("Can't find phy-mode for master device\n");
0c65b2b9 668 return ret;
6b93fb46
JC		 669 }
670 ret = qca8k_set_pad_ctrl(priv, QCA8K_CPU_PORT, phy_mode);
671 if (ret < 0)
672 return ret;
673
79a4ed4f
MV		 674 /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
675 mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW |
676 QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
677 qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
6b93fb46
JC		 678 qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
679 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
680 qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
681 priv->port_sts[QCA8K_CPU_PORT].enabled = 1;
682
683 /* Enable MIB counters */
684 qca8k_mib_init(priv);
685
686 /* Enable QCA header mode on the cpu port */
687 qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
688 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
689 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
690
691 /* Disable forwarding by default on all ports */
692 for (i = 0; i < QCA8K_NUM_PORTS; i++)
693 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
694 QCA8K_PORT_LOOKUP_MEMBER, 0);
695
696 /* Disable MAC by default on all user ports */
697 for (i = 1; i < QCA8K_NUM_PORTS; i++)
4a5b85ff 698 if (dsa_is_user_port(ds, i))
6b93fb46
JC		 699 qca8k_port_set_status(priv, i, 0);
700
701 /* Forward all unknown frames to CPU port for Linux processing */
702 qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
703 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
704 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
705 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
706 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
707
708 /* Setup connection between CPU port & user ports */
7ae6d93c 709 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
6b93fb46
JC		 710 /* CPU port gets connected to all user ports of the switch */
711 if (dsa_is_cpu_port(ds, i)) {
712 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
02bc6e54 713 QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
6b93fb46
JC		 714 }
715
716 /* Invividual user ports get connected to CPU port only */
4a5b85ff 717 if (dsa_is_user_port(ds, i)) {
6b93fb46
JC		 718 int shift = 16 * (i % 2);
719
720 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
721 QCA8K_PORT_LOOKUP_MEMBER,
722 BIT(QCA8K_CPU_PORT));
723
724 /* Enable ARP Auto-learning by default */
725 qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
726 QCA8K_PORT_LOOKUP_LEARN);
727
728 /* For port based vlans to work we need to set the
729 * default egress vid
730 */
731 qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
732 0xffff << shift, 1 << shift);
733 qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
734 QCA8K_PORT_VLAN_CVID(1) |
735 QCA8K_PORT_VLAN_SVID(1));
736 }
737 }
738
739 /* Flush the FDB table */
740 qca8k_fdb_flush(priv);
741
742 return 0;
743}
744
9bb2289f
MV		 745static void
746qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy)
747{
748 struct qca8k_priv *priv = ds->priv;
749 u32 reg;
750
751 /* Force fixed-link setting for CPU port, skip others. */
752 if (!phy_is_pseudo_fixed_link(phy))
753 return;
754
755 /* Set port speed */
756 switch (phy->speed) {
757 case 10:
758 reg = QCA8K_PORT_STATUS_SPEED_10;
759 break;
760 case 100:
761 reg = QCA8K_PORT_STATUS_SPEED_100;
762 break;
763 case 1000:
764 reg = QCA8K_PORT_STATUS_SPEED_1000;
765 break;
766 default:
767 dev_dbg(priv->dev, "port%d link speed %dMbps not supported.\n",
768 port, phy->speed);
769 return;
770 }
771
772 /* Set duplex mode */
773 if (phy->duplex == DUPLEX_FULL)
774 reg |= QCA8K_PORT_STATUS_DUPLEX;
775
776 /* Force flow control */
777 if (dsa_is_cpu_port(ds, port))
778 reg |= QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_TXFLOW;
779
780 /* Force link down before changing MAC options */
781 qca8k_port_set_status(priv, port, 0);
782 qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
783 qca8k_port_set_status(priv, port, 1);
784}
785
6b93fb46 786static void
89f09048 787qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
6b93fb46
JC		 788{
789 int i;
790
89f09048
FF		 791 if (stringset != ETH_SS_STATS)
792 return;
793
6b93fb46
JC		 794 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
795 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
796 ETH_GSTRING_LEN);
797}
798
799static void
800qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
801 uint64_t *data)
802{
803 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
804 const struct qca8k_mib_desc *mib;
805 u32 reg, i;
806 u64 hi;
807
808 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
809 mib = &ar8327_mib[i];
810 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
811
812 data[i] = qca8k_read(priv, reg);
813 if (mib->size == 2) {
814 hi = qca8k_read(priv, reg + 4);
815 data[i] |= hi << 32;
816 }
817 }
818}
819
820static int
89f09048 821qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
6b93fb46 822{
89f09048
FF		 823 if (sset != ETH_SS_STATS)
824 return 0;
825
6b93fb46
JC		 826 return ARRAY_SIZE(ar8327_mib);
827}
828
46587e4a 829static int
08f50061 830qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
6b93fb46
JC		 831{
832 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
833 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
834 u32 reg;
835
836 mutex_lock(&priv->reg_mutex);
837 reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
46587e4a 838 if (eee->eee_enabled)
6b93fb46
JC		 839 reg |= lpi_en;
840 else
841 reg &= ~lpi_en;
842 qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
843 mutex_unlock(&priv->reg_mutex);
6b93fb46 844
c48f7eb3 845 return 0;
6b93fb46
JC		 846}
847
848static int
08f50061 849qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
6b93fb46 850{
193da90e
VD		 851 /* Nothing to do on the port's MAC */
852 return 0;
6b93fb46
JC		 853}
854
855static void
856qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
857{
858 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
859 u32 stp_state;
860
861 switch (state) {
862 case BR_STATE_DISABLED:
863 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
864 break;
865 case BR_STATE_BLOCKING:
866 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
867 break;
868 case BR_STATE_LISTENING:
869 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
870 break;
871 case BR_STATE_LEARNING:
872 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
873 break;
874 case BR_STATE_FORWARDING:
875 default:
876 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
877 break;
878 }
879
880 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
881 QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
882}
883
884static int
922754a4 885qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
6b93fb46
JC		 886{
887 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
888 int port_mask = BIT(QCA8K_CPU_PORT);
889 int i;
890
6b93fb46 891 for (i = 1; i < QCA8K_NUM_PORTS; i++) {
c8652c83 892 if (dsa_to_port(ds, i)->bridge_dev != br)
6b93fb46
JC		 893 continue;
894 /* Add this port to the portvlan mask of the other ports
895 * in the bridge
896 */
897 qca8k_reg_set(priv,
898 QCA8K_PORT_LOOKUP_CTRL(i),
899 BIT(port));
900 if (i != port)
901 port_mask |= BIT(i);
902 }
903 /* Add all other ports to this ports portvlan mask */
904 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
905 QCA8K_PORT_LOOKUP_MEMBER, port_mask);
906
907 return 0;
908}
909
910static void
f123f2fb 911qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
6b93fb46
JC		 912{
913 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
914 int i;
915
916 for (i = 1; i < QCA8K_NUM_PORTS; i++) {
c8652c83 917 if (dsa_to_port(ds, i)->bridge_dev != br)
6b93fb46
JC		 918 continue;
919 /* Remove this port to the portvlan mask of the other ports
920 * in the bridge
921 */
922 qca8k_reg_clear(priv,
923 QCA8K_PORT_LOOKUP_CTRL(i),
924 BIT(port));
925 }
922754a4 926
6b93fb46
JC		 927 /* Set the cpu port to be the only one in the portvlan mask of
928 * this port
929 */
930 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
931 QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
932}
933
934static int
935qca8k_port_enable(struct dsa_switch *ds, int port,
936 struct phy_device *phy)
937{
938 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
939
2b6fd3ea
AL		 940 if (!dsa_is_user_port(ds, port))
941 return 0;
942
6b93fb46
JC		 943 qca8k_port_set_status(priv, port, 1);
944 priv->port_sts[port].enabled = 1;
945
abb48f80 946 phy_support_asym_pause(phy);
947
6b93fb46
JC		 948 return 0;
949}
950
951static void
75104db0 952qca8k_port_disable(struct dsa_switch *ds, int port)
6b93fb46
JC		 953{
954 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
955
956 qca8k_port_set_status(priv, port, 0);
957 priv->port_sts[port].enabled = 0;
958}
959
960static int
961qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
962 u16 port_mask, u16 vid)
963{
964 /* Set the vid to the port vlan id if no vid is set */
965 if (!vid)
966 vid = 1;
967
968 return qca8k_fdb_add(priv, addr, port_mask, vid,
969 QCA8K_ATU_STATUS_STATIC);
970}
971
972static int
6b93fb46 973qca8k_port_fdb_add(struct dsa_switch *ds, int port,
6c2c1dcb 974 const unsigned char *addr, u16 vid)
6b93fb46
JC		 975{
976 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
977 u16 port_mask = BIT(port);
978
1b6dd556 979 return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
6b93fb46
JC		 980}
981
982static int
983qca8k_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 984 const unsigned char *addr, u16 vid)
6b93fb46
JC		 985{
986 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
987 u16 port_mask = BIT(port);
6b93fb46
JC		 988
989 if (!vid)
990 vid = 1;
991
6c2c1dcb 992 return qca8k_fdb_del(priv, addr, port_mask, vid);
6b93fb46
JC		 993}
994
995static int
996qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 997 dsa_fdb_dump_cb_t *cb, void *data)
6b93fb46
JC		 998{
999 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1000 struct qca8k_fdb _fdb = { 0 };
1001 int cnt = QCA8K_NUM_FDB_RECORDS;
2bedde1a 1002 bool is_static;
6b93fb46
JC		 1003 int ret = 0;
1004
1005 mutex_lock(&priv->reg_mutex);
1006 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
1007 if (!_fdb.aging)
1008 break;
2bedde1a
AS		 1009 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
1010 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
6b93fb46
JC		 1011 if (ret)
1012 break;
1013 }
1014 mutex_unlock(&priv->reg_mutex);
1015
1016 return 0;
1017}
1018
1019static enum dsa_tag_protocol
5ed4e3eb 1020qca8k_get_tag_protocol(struct dsa_switch *ds, int port)
6b93fb46
JC		 1021{
1022 return DSA_TAG_PROTO_QCA;
1023}
1024
a82f67af 1025static const struct dsa_switch_ops qca8k_switch_ops = {
6b93fb46
JC		 1026 .get_tag_protocol = qca8k_get_tag_protocol,
1027 .setup = qca8k_setup,
9bb2289f 1028 .adjust_link = qca8k_adjust_link,
6b93fb46 1029 .get_strings = qca8k_get_strings,
6b93fb46
JC		 1030 .get_ethtool_stats = qca8k_get_ethtool_stats,
1031 .get_sset_count = qca8k_get_sset_count,
08f50061
VD		 1032 .get_mac_eee = qca8k_get_mac_eee,
1033 .set_mac_eee = qca8k_set_mac_eee,
6b93fb46
JC		 1034 .port_enable = qca8k_port_enable,
1035 .port_disable = qca8k_port_disable,
1036 .port_stp_state_set = qca8k_port_stp_state_set,
1037 .port_bridge_join = qca8k_port_bridge_join,
1038 .port_bridge_leave = qca8k_port_bridge_leave,
6b93fb46
JC		 1039 .port_fdb_add = qca8k_port_fdb_add,
1040 .port_fdb_del = qca8k_port_fdb_del,
1041 .port_fdb_dump = qca8k_port_fdb_dump,
1042};
1043
1044static int
1045qca8k_sw_probe(struct mdio_device *mdiodev)
1046{
1047 struct qca8k_priv *priv;
1048 u32 id;
1049
1050 /* allocate the private data struct so that we can probe the switches
1051 * ID register
1052 */
1053 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1054 if (!priv)
1055 return -ENOMEM;
1056
1057 priv->bus = mdiodev->bus;
9bb2289f 1058 priv->dev = &mdiodev->dev;
6b93fb46 1059
a653f2f5
CL		 1060 priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
1061 GPIOD_ASIS);
1062 if (IS_ERR(priv->reset_gpio))
1063 return PTR_ERR(priv->reset_gpio);
1064
1065 if (priv->reset_gpio) {
1066 gpiod_set_value_cansleep(priv->reset_gpio, 1);
1067 /* The active low duration must be greater than 10 ms
1068 * and checkpatch.pl wants 20 ms.
1069 */
1070 msleep(20);
1071 gpiod_set_value_cansleep(priv->reset_gpio, 0);
1072 }
1073
6b93fb46
JC		 1074 /* read the switches ID register */
1075 id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
1076 id >>= QCA8K_MASK_CTRL_ID_S;
1077 id &= QCA8K_MASK_CTRL_ID_M;
1078 if (id != QCA8K_ID_QCA8337)
1079 return -ENODEV;
1080
7e99e347
VD		 1081 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds),
1082 QCA8K_NUM_PORTS);
6b93fb46
JC		 1083 if (!priv->ds)
1084 return -ENOMEM;
1085
7e99e347 1086 priv->ds->dev = &mdiodev->dev;
f0d532c4 1087 priv->ds->num_ports = QCA8K_NUM_PORTS;
6b93fb46 1088 priv->ds->priv = priv;
db460c54
CL		 1089 priv->ops = qca8k_switch_ops;
1090 priv->ds->ops = &priv->ops;
6b93fb46
JC		 1091 mutex_init(&priv->reg_mutex);
1092 dev_set_drvdata(&mdiodev->dev, priv);
1093
23c9ee49 1094 return dsa_register_switch(priv->ds);
6b93fb46
JC		 1095}
1096
1097static void
1098qca8k_sw_remove(struct mdio_device *mdiodev)
1099{
1100 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
1101 int i;
1102
1103 for (i = 0; i < QCA8K_NUM_PORTS; i++)
1104 qca8k_port_set_status(priv, i, 0);
1105
1106 dsa_unregister_switch(priv->ds);
1107}
1108
1109#ifdef CONFIG_PM_SLEEP
1110static void
1111qca8k_set_pm(struct qca8k_priv *priv, int enable)
1112{
1113 int i;
1114
1115 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1116 if (!priv->port_sts[i].enabled)
1117 continue;
1118
1119 qca8k_port_set_status(priv, i, enable);
1120 }
1121}
1122
1123static int qca8k_suspend(struct device *dev)
1124{
717de370 1125 struct qca8k_priv *priv = dev_get_drvdata(dev);
6b93fb46
JC		 1126
1127 qca8k_set_pm(priv, 0);
1128
1129 return dsa_switch_suspend(priv->ds);
1130}
1131
1132static int qca8k_resume(struct device *dev)
1133{
717de370 1134 struct qca8k_priv *priv = dev_get_drvdata(dev);
6b93fb46
JC		 1135
1136 qca8k_set_pm(priv, 1);
1137
1138 return dsa_switch_resume(priv->ds);
1139}
1140#endif /* CONFIG_PM_SLEEP */
1141
1142static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
1143 qca8k_suspend, qca8k_resume);
1144
1145static const struct of_device_id qca8k_of_match[] = {
64cf8167 1146 { .compatible = "qca,qca8334" },
6b93fb46
JC		 1147 { .compatible = "qca,qca8337" },
1148 { /* sentinel */ },
1149};
1150
1151static struct mdio_driver qca8kmdio_driver = {
1152 .probe = qca8k_sw_probe,
1153 .remove = qca8k_sw_remove,
1154 .mdiodrv.driver = {
1155 .name = "qca8k",
1156 .of_match_table = qca8k_of_match,
1157 .pm = &qca8k_pm_ops,
1158 },
1159};
1160
a084ab33 1161mdio_module_driver(qca8kmdio_driver);
6b93fb46
JC		 1162
1163MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1164MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
1165MODULE_LICENSE("GPL v2");
1166MODULE_ALIAS("platform:qca8k");
Linux 6.x block layer and io_uring tree(s)