[linux-2.6-block.git] / drivers / net / dsa / mv88e6xxx / global1.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Marvell 88E6xxx Switch Global (1) Registers support
 *
 * Copyright (c) 2008 Marvell Semiconductor
 *
 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
 *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
 */

#ifndef _MV88E6XXX_GLOBAL1_H
#define _MV88E6XXX_GLOBAL1_H

#include "chip.h"

/* Offset 0x00: Switch Global Status Register */
#define MV88E6XXX_G1_STS				0x00
#define MV88E6352_G1_STS_PPU_STATE			0x8000
#define MV88E6185_G1_STS_PPU_STATE_MASK			0xc000
#define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST		0x0000
#define MV88E6185_G1_STS_PPU_STATE_INITIALIZING		0x4000
#define MV88E6185_G1_STS_PPU_STATE_DISABLED		0x8000
#define MV88E6185_G1_STS_PPU_STATE_POLLING		0xc000
#define MV88E6XXX_G1_STS_INIT_READY			0x0800
#define MV88E6XXX_G1_STS_IRQ_AVB			8
#define MV88E6XXX_G1_STS_IRQ_DEVICE			7
#define MV88E6XXX_G1_STS_IRQ_STATS			6
#define MV88E6XXX_G1_STS_IRQ_VTU_PROB			5
#define MV88E6XXX_G1_STS_IRQ_VTU_DONE			4
#define MV88E6XXX_G1_STS_IRQ_ATU_PROB			3
#define MV88E6XXX_G1_STS_IRQ_ATU_DONE			2
#define MV88E6XXX_G1_STS_IRQ_TCAM_DONE			1
#define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE		0

/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
 */
#define MV88E6XXX_G1_MAC_01		0x01
#define MV88E6XXX_G1_MAC_23		0x02
#define MV88E6XXX_G1_MAC_45		0x03

/* Offset 0x01: ATU FID Register */
#define MV88E6352_G1_ATU_FID		0x01

/* Offset 0x02: VTU FID Register */
#define MV88E6352_G1_VTU_FID		0x02
#define MV88E6352_G1_VTU_FID_MASK	0x0fff

/* Offset 0x03: VTU SID Register */
#define MV88E6352_G1_VTU_SID		0x03
#define MV88E6352_G1_VTU_SID_MASK	0x3f

/* Offset 0x04: Switch Global Control Register */
#define MV88E6XXX_G1_CTL1			0x04
#define MV88E6XXX_G1_CTL1_SW_RESET		0x8000
#define MV88E6XXX_G1_CTL1_PPU_ENABLE		0x4000
#define MV88E6352_G1_CTL1_DISCARD_EXCESS	0x2000
#define MV88E6185_G1_CTL1_SCHED_PRIO		0x0800
#define MV88E6185_G1_CTL1_MAX_FRAME_1632	0x0400
#define MV88E6185_G1_CTL1_RELOAD_EEPROM		0x0200
#define MV88E6XXX_G1_CTL1_DEVICE_EN		0x0080
#define MV88E6XXX_G1_CTL1_STATS_DONE_EN		0x0040
#define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN	0x0020
#define MV88E6XXX_G1_CTL1_VTU_DONE_EN		0x0010
#define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN	0x0008
#define MV88E6XXX_G1_CTL1_ATU_DONE_EN		0x0004
#define MV88E6XXX_G1_CTL1_TCAM_EN		0x0002
#define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN	0x0001

/* Offset 0x05: VTU Operation Register */
#define MV88E6XXX_G1_VTU_OP			0x05
#define MV88E6XXX_G1_VTU_OP_BUSY		0x8000
#define MV88E6XXX_G1_VTU_OP_MASK		0x7000
#define MV88E6XXX_G1_VTU_OP_FLUSH_ALL		0x1000
#define MV88E6XXX_G1_VTU_OP_NOOP		0x2000
#define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE	0x3000
#define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT	0x4000
#define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE	0x5000
#define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT	0x6000
#define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION	0x7000
#define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION	BIT(6)
#define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION	BIT(5)
#define MV88E6XXX_G1_VTU_OP_SPID_MASK		0xf

/* Offset 0x06: VTU VID Register */
#define MV88E6XXX_G1_VTU_VID		0x06
#define MV88E6XXX_G1_VTU_VID_MASK	0x0fff
#define MV88E6390_G1_VTU_VID_PAGE	0x2000
#define MV88E6XXX_G1_VTU_VID_VALID	0x1000

/* Offset 0x07: VTU/STU Data Register 1
 * Offset 0x08: VTU/STU Data Register 2
 * Offset 0x09: VTU/STU Data Register 3
 */
#define MV88E6XXX_G1_VTU_DATA1				0x07
#define MV88E6XXX_G1_VTU_DATA2				0x08
#define MV88E6XXX_G1_VTU_DATA3				0x09
#define MV88E6XXX_G1_VTU_STU_DATA_MASK			0x0003
#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED	0x0000
#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED	0x0001
#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED		0x0002
#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER	0x0003
#define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED	0x0000
#define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING	0x0001
#define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING	0x0002
#define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING	0x0003

/* Offset 0x0A: ATU Control Register */
#define MV88E6XXX_G1_ATU_CTL		0x0a
#define MV88E6XXX_G1_ATU_CTL_LEARN2ALL	0x0008
#define MV88E6161_G1_ATU_CTL_HASH_MASK	0x0003

/* Offset 0x0B: ATU Operation Register */
#define MV88E6XXX_G1_ATU_OP				0x0b
#define MV88E6XXX_G1_ATU_OP_BUSY			0x8000
#define MV88E6XXX_G1_ATU_OP_MASK			0x7000
#define MV88E6XXX_G1_ATU_OP_NOOP			0x0000
#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL		0x1000
#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC	0x2000
#define MV88E6XXX_G1_ATU_OP_LOAD_DB			0x3000
#define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB			0x4000
#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB		0x5000
#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB	0x6000
#define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION		0x7000
#define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION		BIT(7)
#define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION		BIT(6)
#define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION		BIT(5)
#define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION		BIT(4)

/* Offset 0x0C: ATU Data Register */
#define MV88E6XXX_G1_ATU_DATA					0x0c
#define MV88E6XXX_G1_ATU_DATA_TRUNK				0x8000
#define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK			0x00f0
#define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK			0x3ff0
#define MV88E6XXX_G1_ATU_DATA_STATE_MASK			0x000f
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED			0x0000
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST		0x0001
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2			0x0002
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3			0x0003
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4			0x0004
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5			0x0005
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6			0x0006
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST		0x0007
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY		0x0008
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO		0x0009
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL		0x000a
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO	0x000b
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT		0x000c
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO	0x000d
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC			0x000e
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO		0x000f
#define MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED			0x0000
#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY		0x0004
#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL		0x0005
#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT		0x0006
#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC			0x0007
#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO		0x000c
#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO	0x000d
#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO	0x000e
#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO		0x000f

/* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
 * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
 * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
 */
#define MV88E6XXX_G1_ATU_MAC01		0x0d
#define MV88E6XXX_G1_ATU_MAC23		0x0e
#define MV88E6XXX_G1_ATU_MAC45		0x0f

/* Offset 0x10: IP-PRI Mapping Register 0
 * Offset 0x11: IP-PRI Mapping Register 1
 * Offset 0x12: IP-PRI Mapping Register 2
 * Offset 0x13: IP-PRI Mapping Register 3
 * Offset 0x14: IP-PRI Mapping Register 4
 * Offset 0x15: IP-PRI Mapping Register 5
 * Offset 0x16: IP-PRI Mapping Register 6
 * Offset 0x17: IP-PRI Mapping Register 7
 */
#define MV88E6XXX_G1_IP_PRI_0	0x10
#define MV88E6XXX_G1_IP_PRI_1	0x11
#define MV88E6XXX_G1_IP_PRI_2	0x12
#define MV88E6XXX_G1_IP_PRI_3	0x13
#define MV88E6XXX_G1_IP_PRI_4	0x14
#define MV88E6XXX_G1_IP_PRI_5	0x15
#define MV88E6XXX_G1_IP_PRI_6	0x16
#define MV88E6XXX_G1_IP_PRI_7	0x17

/* Offset 0x18: IEEE-PRI Register */
#define MV88E6XXX_G1_IEEE_PRI	0x18

/* Offset 0x19: Core Tag Type */
#define MV88E6185_G1_CORE_TAG_TYPE	0x19

/* Offset 0x1A: Monitor Control */
#define MV88E6185_G1_MONITOR_CTL			0x1a
#define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK	0xf000
#define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK	0x0f00
#define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK	        0x00f0
#define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK	        0x00f0
#define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK	0x000f

/* Offset 0x1A: Monitor & MGMT Control Register */
#define MV88E6390_G1_MONITOR_MGMT_CTL				0x1a
#define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE			0x8000
#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK			0x3f00
#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO	0x0000
#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI	0x0100
#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO	0x0200
#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI	0x0300
#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST		0x2000
#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST		0x2100
#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST		0x3000
#define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK			0x00ff

/* Offset 0x1C: Global Control 2 */
#define MV88E6XXX_G1_CTL2			0x1c
#define MV88E6185_G1_CTL2_CASCADE_PORT_MASK	0xf000
#define MV88E6185_G1_CTL2_CASCADE_PORT_NONE	0xe000
#define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI	0xf000
#define MV88E6352_G1_CTL2_HEADER_TYPE_MASK	0xc000
#define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG	0x0000
#define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT	0x4000
#define MV88E6390_G1_CTL2_HEADER_TYPE_LAG	0x8000
#define MV88E6352_G1_CTL2_RMU_MODE_MASK		0x3000
#define MV88E6352_G1_CTL2_RMU_MODE_DISABLED	0x0000
#define MV88E6352_G1_CTL2_RMU_MODE_PORT_4	0x1000
#define MV88E6352_G1_CTL2_RMU_MODE_PORT_5	0x2000
#define MV88E6352_G1_CTL2_RMU_MODE_PORT_6	0x3000
#define MV88E6085_G1_CTL2_DA_CHECK		0x4000
#define MV88E6085_G1_CTL2_P10RM			0x2000
#define MV88E6085_G1_CTL2_RM_ENABLE		0x1000
#define MV88E6352_G1_CTL2_DA_CHECK		0x0800
#define MV88E6390_G1_CTL2_RMU_MODE_MASK		0x0700
#define MV88E6390_G1_CTL2_RMU_MODE_PORT_0	0x0000
#define MV88E6390_G1_CTL2_RMU_MODE_PORT_1	0x0100
#define MV88E6390_G1_CTL2_RMU_MODE_PORT_9	0x0200
#define MV88E6390_G1_CTL2_RMU_MODE_PORT_10	0x0300
#define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA	0x0600
#define MV88E6390_G1_CTL2_RMU_MODE_DISABLED	0x0700
#define MV88E6390_G1_CTL2_HIST_MODE_MASK	0x00c0
#define MV88E6390_G1_CTL2_HIST_MODE_RX		0x0040
#define MV88E6390_G1_CTL2_HIST_MODE_TX		0x0080
#define MV88E6352_G1_CTL2_CTR_MODE_MASK		0x0060
#define MV88E6390_G1_CTL2_CTR_MODE		0x0020
#define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK	0x001f

/* Offset 0x1D: Stats Operation Register */
#define MV88E6XXX_G1_STATS_OP			0x1d
#define MV88E6XXX_G1_STATS_OP_BUSY		0x8000
#define MV88E6XXX_G1_STATS_OP_NOP		0x0000
#define MV88E6XXX_G1_STATS_OP_FLUSH_ALL		0x1000
#define MV88E6XXX_G1_STATS_OP_FLUSH_PORT	0x2000
#define MV88E6XXX_G1_STATS_OP_READ_CAPTURED	0x4000
#define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT	0x5000
#define MV88E6XXX_G1_STATS_OP_HIST_RX		0x0400
#define MV88E6XXX_G1_STATS_OP_HIST_TX		0x0800
#define MV88E6XXX_G1_STATS_OP_HIST_RX_TX	0x0c00
#define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9	0x0200
#define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10	0x0400

/* Offset 0x1E: Stats Counter Register Bytes 3 & 2
 * Offset 0x1F: Stats Counter Register Bytes 1 & 0
 */
#define MV88E6XXX_G1_STATS_COUNTER_32	0x1e
#define MV88E6XXX_G1_STATS_COUNTER_01	0x1f

int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
			  bit, int val);
int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
			   u16 mask, u16 val);

int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);

int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip);

int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);

int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val);
int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip);
int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
				 enum mv88e6xxx_egress_direction direction,
				 int port);
int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
				 enum mv88e6xxx_egress_direction direction,
				 int port);
int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);

int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip);

int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);

int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);

int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);
int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);
int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);

int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);

int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
				  unsigned int msecs);
int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
			     struct mv88e6xxx_atu_entry *entry);
int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
			       struct mv88e6xxx_atu_entry *entry);
int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all);
int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
			    bool all);
int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip);
void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip);
int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash);
int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash);

int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
			     struct mv88e6xxx_vtu_entry *entry);
int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
			       struct mv88e6xxx_vtu_entry *entry);
int mv88e6250_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
			     struct mv88e6xxx_vtu_entry *entry);
int mv88e6250_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
			       struct mv88e6xxx_vtu_entry *entry);
int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
			     struct mv88e6xxx_vtu_entry *entry);
int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
			       struct mv88e6xxx_vtu_entry *entry);
int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
			     struct mv88e6xxx_vtu_entry *entry);
int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
			       struct mv88e6xxx_vtu_entry *entry);
int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip);
int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip);
void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip);
int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid);

#endif /* _MV88E6XXX_GLOBAL1_H */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
a935c052 VD	2	/*
	3	* Marvell 88E6xxx Switch Global (1) Registers support
	4	*
	5	* Copyright (c) 2008 Marvell Semiconductor
	6	*
4333d619 VD	7	* Copyright (c) 2016-2017 Savoir-faire Linux Inc.
4333d619 VD	8	* Vivien Didelot <vivien.didelot@savoirfairelinux.com>
a935c052 VD	9	*/
	10
	11	#ifndef _MV88E6XXX_GLOBAL1_H
	12	#define _MV88E6XXX_GLOBAL1_H
	13
4d5f2ba7	14	#include "chip.h"
a935c052	15
82466921 VD	16	/* Offset 0x00: Switch Global Status Register */
	17	#define MV88E6XXX_G1_STS 0x00
	18	#define MV88E6352_G1_STS_PPU_STATE 0x8000
	19	#define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
	20	#define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
	21	#define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
	22	#define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
	23	#define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
	24	#define MV88E6XXX_G1_STS_INIT_READY 0x0800
	25	#define MV88E6XXX_G1_STS_IRQ_AVB 8
	26	#define MV88E6XXX_G1_STS_IRQ_DEVICE 7
	27	#define MV88E6XXX_G1_STS_IRQ_STATS 6
62eb1162	28	#define MV88E6XXX_G1_STS_IRQ_VTU_PROB 5
82466921	29	#define MV88E6XXX_G1_STS_IRQ_VTU_DONE 4
0977644c	30	#define MV88E6XXX_G1_STS_IRQ_ATU_PROB 3
82466921 VD	31	#define MV88E6XXX_G1_STS_IRQ_ATU_DONE 2
	32	#define MV88E6XXX_G1_STS_IRQ_TCAM_DONE 1
	33	#define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
	34
4b0c4817 VD	35	/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
	36	* Offset 0x02: Switch MAC Address Register Bytes 2 & 3
	37	* Offset 0x03: Switch MAC Address Register Bytes 4 & 5
	38	*/
	39	#define MV88E6XXX_G1_MAC_01 0x01
	40	#define MV88E6XXX_G1_MAC_23 0x02
	41	#define MV88E6XXX_G1_MAC_45 0x03
	42
27c0e600 VD	43	/* Offset 0x01: ATU FID Register */
	44	#define MV88E6352_G1_ATU_FID 0x01
	45
7ec60d6e VD	46	/* Offset 0x02: VTU FID Register */
	47	#define MV88E6352_G1_VTU_FID 0x02
	48	#define MV88E6352_G1_VTU_FID_MASK 0x0fff
	49
	50	/* Offset 0x03: VTU SID Register */
	51	#define MV88E6352_G1_VTU_SID 0x03
	52	#define MV88E6352_G1_VTU_SID_MASK 0x3f
	53
d77f4321 VD	54	/* Offset 0x04: Switch Global Control Register */
	55	#define MV88E6XXX_G1_CTL1 0x04
	56	#define MV88E6XXX_G1_CTL1_SW_RESET 0x8000
	57	#define MV88E6XXX_G1_CTL1_PPU_ENABLE 0x4000
	58	#define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x2000
	59	#define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800
	60	#define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400
	61	#define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200
	62	#define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080
	63	#define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x0040
	64	#define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x0020
	65	#define MV88E6XXX_G1_CTL1_VTU_DONE_EN 0x0010
	66	#define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN 0x0008
	67	#define MV88E6XXX_G1_CTL1_ATU_DONE_EN 0x0004
	68	#define MV88E6XXX_G1_CTL1_TCAM_EN 0x0002
	69	#define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN 0x0001
7ec60d6e VD	70
	71	/* Offset 0x05: VTU Operation Register */
	72	#define MV88E6XXX_G1_VTU_OP 0x05
	73	#define MV88E6XXX_G1_VTU_OP_BUSY 0x8000
	74	#define MV88E6XXX_G1_VTU_OP_MASK 0x7000
	75	#define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x1000
	76	#define MV88E6XXX_G1_VTU_OP_NOOP 0x2000
	77	#define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE 0x3000
	78	#define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT 0x4000
	79	#define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE 0x5000
	80	#define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT 0x6000
62eb1162 AL	81	#define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION 0x7000
	82	#define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION BIT(6)
	83	#define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION BIT(5)
	84	#define MV88E6XXX_G1_VTU_OP_SPID_MASK 0xf
7ec60d6e VD	85
	86	/* Offset 0x06: VTU VID Register */
	87	#define MV88E6XXX_G1_VTU_VID 0x06
	88	#define MV88E6XXX_G1_VTU_VID_MASK 0x0fff
	89	#define MV88E6390_G1_VTU_VID_PAGE 0x2000
	90	#define MV88E6XXX_G1_VTU_VID_VALID 0x1000
	91
	92	/* Offset 0x07: VTU/STU Data Register 1
	93	* Offset 0x08: VTU/STU Data Register 2
	94	* Offset 0x09: VTU/STU Data Register 3
	95	*/
	96	#define MV88E6XXX_G1_VTU_DATA1 0x07
	97	#define MV88E6XXX_G1_VTU_DATA2 0x08
	98	#define MV88E6XXX_G1_VTU_DATA3 0x09
	99	#define MV88E6XXX_G1_VTU_STU_DATA_MASK 0x0003
	100	#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x0000
	101	#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED 0x0001
	102	#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED 0x0002
	103	#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x0003
	104	#define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED 0x0000
	105	#define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING 0x0001
	106	#define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING 0x0002
	107	#define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING 0x0003
27c0e600 VD	108
	109	/* Offset 0x0A: ATU Control Register */
	110	#define MV88E6XXX_G1_ATU_CTL 0x0a
	111	#define MV88E6XXX_G1_ATU_CTL_LEARN2ALL 0x0008
23e8b470	112	#define MV88E6161_G1_ATU_CTL_HASH_MASK 0x0003
27c0e600 VD	113
	114	/* Offset 0x0B: ATU Operation Register */
	115	#define MV88E6XXX_G1_ATU_OP 0x0b
	116	#define MV88E6XXX_G1_ATU_OP_BUSY 0x8000
	117	#define MV88E6XXX_G1_ATU_OP_MASK 0x7000
	118	#define MV88E6XXX_G1_ATU_OP_NOOP 0x0000
	119	#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL 0x1000
	120	#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC 0x2000
	121	#define MV88E6XXX_G1_ATU_OP_LOAD_DB 0x3000
	122	#define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB 0x4000
	123	#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB 0x5000
	124	#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB 0x6000
	125	#define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION 0x7000
0977644c AL	126	#define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION BIT(7)
0977644c AL	127	#define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION BIT(6)
ddca24df	128	#define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION BIT(5)
0977644c	129	#define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION BIT(4)
27c0e600 VD	130
27c0e600 VD	131	/* Offset 0x0C: ATU Data Register */
d8291a95 VD	132	#define MV88E6XXX_G1_ATU_DATA 0x0c
	133	#define MV88E6XXX_G1_ATU_DATA_TRUNK 0x8000
	134	#define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK 0x00f0
	135	#define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
	136	#define MV88E6XXX_G1_ATU_DATA_STATE_MASK 0x000f
	137	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED 0x0000
	138	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST 0x0001
	139	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2 0x0002
	140	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3 0x0003
	141	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4 0x0004
	142	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5 0x0005
	143	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6 0x0006
	144	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST 0x0007
	145	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY 0x0008
	146	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO 0x0009
	147	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL 0x000a
	148	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO 0x000b
	149	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT 0x000c
	150	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO 0x000d
	151	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC 0x000e
	152	#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO 0x000f
	153	#define MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED 0x0000
	154	#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY 0x0004
	155	#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL 0x0005
	156	#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT 0x0006
	157	#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC 0x0007
	158	#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO 0x000c
	159	#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO 0x000d
	160	#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO 0x000e
	161	#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO 0x000f
27c0e600 VD	162
	163	/* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
	164	* Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
	165	* Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
	166	*/
	167	#define MV88E6XXX_G1_ATU_MAC01 0x0d
	168	#define MV88E6XXX_G1_ATU_MAC23 0x0e
	169	#define MV88E6XXX_G1_ATU_MAC45 0x0f
	170
ccba8f3a VD	171	/* Offset 0x10: IP-PRI Mapping Register 0
	172	* Offset 0x11: IP-PRI Mapping Register 1
	173	* Offset 0x12: IP-PRI Mapping Register 2
	174	* Offset 0x13: IP-PRI Mapping Register 3
	175	* Offset 0x14: IP-PRI Mapping Register 4
	176	* Offset 0x15: IP-PRI Mapping Register 5
	177	* Offset 0x16: IP-PRI Mapping Register 6
	178	* Offset 0x17: IP-PRI Mapping Register 7
	179	*/
	180	#define MV88E6XXX_G1_IP_PRI_0 0x10
	181	#define MV88E6XXX_G1_IP_PRI_1 0x11
	182	#define MV88E6XXX_G1_IP_PRI_2 0x12
	183	#define MV88E6XXX_G1_IP_PRI_3 0x13
	184	#define MV88E6XXX_G1_IP_PRI_4 0x14
	185	#define MV88E6XXX_G1_IP_PRI_5 0x15
	186	#define MV88E6XXX_G1_IP_PRI_6 0x16
	187	#define MV88E6XXX_G1_IP_PRI_7 0x17
	188
	189	/* Offset 0x18: IEEE-PRI Register */
	190	#define MV88E6XXX_G1_IEEE_PRI 0x18
	191
	192	/* Offset 0x19: Core Tag Type */
	193	#define MV88E6185_G1_CORE_TAG_TYPE 0x19
101515c8 VD	194
	195	/* Offset 0x1A: Monitor Control */
	196	#define MV88E6185_G1_MONITOR_CTL 0x1a
	197	#define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK 0xf000
	198	#define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK 0x0f00
	199	#define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK 0x00f0
	200	#define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK 0x00f0
	201	#define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK 0x000f
	202
	203	/* Offset 0x1A: Monitor & MGMT Control Register */
	204	#define MV88E6390_G1_MONITOR_MGMT_CTL 0x1a
	205	#define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE 0x8000
	206	#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK 0x3f00
989f405a RV	207	#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO 0x0000
	208	#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI 0x0100
	209	#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO 0x0200
	210	#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI 0x0300
101515c8 VD	211	#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000
	212	#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100
	213	#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000
	214	#define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff
d77f4321 VD	215
	216	/* Offset 0x1C: Global Control 2 */
	217	#define MV88E6XXX_G1_CTL2 0x1c
02317e68 VD	218	#define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000
	219	#define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000
	220	#define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000
408d2deb VD	221	#define MV88E6352_G1_CTL2_HEADER_TYPE_MASK 0xc000
	222	#define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG 0x0000
	223	#define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT 0x4000
	224	#define MV88E6390_G1_CTL2_HEADER_TYPE_LAG 0x8000
9e5baf9b VD	225	#define MV88E6352_G1_CTL2_RMU_MODE_MASK 0x3000
	226	#define MV88E6352_G1_CTL2_RMU_MODE_DISABLED 0x0000
	227	#define MV88E6352_G1_CTL2_RMU_MODE_PORT_4 0x1000
	228	#define MV88E6352_G1_CTL2_RMU_MODE_PORT_5 0x2000
	229	#define MV88E6352_G1_CTL2_RMU_MODE_PORT_6 0x3000
	230	#define MV88E6085_G1_CTL2_DA_CHECK 0x4000
	231	#define MV88E6085_G1_CTL2_P10RM 0x2000
	232	#define MV88E6085_G1_CTL2_RM_ENABLE 0x1000
	233	#define MV88E6352_G1_CTL2_DA_CHECK 0x0800
	234	#define MV88E6390_G1_CTL2_RMU_MODE_MASK 0x0700
	235	#define MV88E6390_G1_CTL2_RMU_MODE_PORT_0 0x0000
	236	#define MV88E6390_G1_CTL2_RMU_MODE_PORT_1 0x0100
	237	#define MV88E6390_G1_CTL2_RMU_MODE_PORT_9 0x0200
	238	#define MV88E6390_G1_CTL2_RMU_MODE_PORT_10 0x0300
	239	#define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA 0x0600
	240	#define MV88E6390_G1_CTL2_RMU_MODE_DISABLED 0x0700
408d2deb VD	241	#define MV88E6390_G1_CTL2_HIST_MODE_MASK 0x00c0
	242	#define MV88E6390_G1_CTL2_HIST_MODE_RX 0x0040
	243	#define MV88E6390_G1_CTL2_HIST_MODE_TX 0x0080
	244	#define MV88E6352_G1_CTL2_CTR_MODE_MASK 0x0060
	245	#define MV88E6390_G1_CTL2_CTR_MODE 0x0020
23c98919	246	#define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f
d77f4321	247
57d1ef38 VD	248	/* Offset 0x1D: Stats Operation Register */
	249	#define MV88E6XXX_G1_STATS_OP 0x1d
	250	#define MV88E6XXX_G1_STATS_OP_BUSY 0x8000
	251	#define MV88E6XXX_G1_STATS_OP_NOP 0x0000
	252	#define MV88E6XXX_G1_STATS_OP_FLUSH_ALL 0x1000
	253	#define MV88E6XXX_G1_STATS_OP_FLUSH_PORT 0x2000
	254	#define MV88E6XXX_G1_STATS_OP_READ_CAPTURED 0x4000
	255	#define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT 0x5000
	256	#define MV88E6XXX_G1_STATS_OP_HIST_RX 0x0400
	257	#define MV88E6XXX_G1_STATS_OP_HIST_TX 0x0800
	258	#define MV88E6XXX_G1_STATS_OP_HIST_RX_TX 0x0c00
	259	#define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9 0x0200
	260	#define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10 0x0400
	261
	262	/* Offset 0x1E: Stats Counter Register Bytes 3 & 2
	263	* Offset 0x1F: Stats Counter Register Bytes 1 & 0
	264	*/
	265	#define MV88E6XXX_G1_STATS_COUNTER_32 0x1e
	266	#define MV88E6XXX_G1_STATS_COUNTER_01 0x1f
e097097b	267
a935c052 VD	268	int mv88e6xxx_g1_read(struct mv88e6xxx_chip chip, int reg, u16 val);
a935c052 VD	269	int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
19fb7f69 VD	270	int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
19fb7f69 VD	271	bit, int val);
683f2244 VD	272	int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
683f2244 VD	273	u16 mask, u16 val);
17e708ba	274
4b0c4817 VD	275	int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip chip, u8 addr);
4b0c4817 VD	276
17e708ba VD	277	int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
17e708ba VD	278	int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
1f71836f	279	int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip);
17e708ba	280
a199d8b6 VD	281	int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
	282	int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
	283
a605a0fe AL	284	int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
a605a0fe AL	285	int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
79523473	286	int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
40cff8fc	287	int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
de227387	288	int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
7f9ef3af	289	void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip chip, int stat, u32 val);
40cff8fc	290	int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip);
5c74c54c IT	291	int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
	292	enum mv88e6xxx_egress_direction direction,
	293	int port);
	294	int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
	295	enum mv88e6xxx_egress_direction direction,
	296	int port);
33641994 AL	297	int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
33641994 AL	298	int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
6e55f698	299	int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
a935c052	300
93e18d61	301	int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip);
df63b0d9	302
93e18d61	303	int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
df63b0d9	304	int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
93e18d61	305
02317e68 VD	306	int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
02317e68 VD	307
9e5baf9b VD	308	int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);
	309	int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);
	310	int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);
	311
23c98919 VD	312	int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);
23c98919 VD	313
c3a7d4ad	314	int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
720c6343 VD	315	int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
720c6343 VD	316	unsigned int msecs);
dabc1a96 VD	317	int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
dabc1a96 VD	318	struct mv88e6xxx_atu_entry *entry);
9c13c026 VD	319	int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
9c13c026 VD	320	struct mv88e6xxx_atu_entry *entry);
daefc943	321	int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all);
e606ca36 VD	322	int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
e606ca36 VD	323	bool all);
0977644c AL	324	int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip);
0977644c AL	325	void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip);
23e8b470 AL	326	int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip chip, u8 hash);
23e8b470 AL	327	int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash);
720c6343	328
f1394b78 VD	329	int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
f1394b78 VD	330	struct mv88e6xxx_vtu_entry *entry);
0ad5daf6 VD	331	int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
0ad5daf6 VD	332	struct mv88e6xxx_vtu_entry *entry);
bec8e572 RV	333	int mv88e6250_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
	334	struct mv88e6xxx_vtu_entry *entry);
	335	int mv88e6250_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
	336	struct mv88e6xxx_vtu_entry *entry);
f1394b78 VD	337	int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
f1394b78 VD	338	struct mv88e6xxx_vtu_entry *entry);
0ad5daf6 VD	339	int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
0ad5daf6 VD	340	struct mv88e6xxx_vtu_entry *entry);
931d1822 VD	341	int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
	342	struct mv88e6xxx_vtu_entry *entry);
	343	int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
	344	struct mv88e6xxx_vtu_entry *entry);
b486d7c9	345	int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip);
62eb1162 AL	346	int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip);
62eb1162 AL	347	void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip);
c5f299d5	348	int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid);
332aa5cc	349
a935c052	350	#endif /* _MV88E6XXX_GLOBAL1_H */