[linux-2.6-block.git] / drivers / net / dsa / mv88e6060.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
 * Copyright (c) 2008-2009 Marvell Semiconductor
 */

#include <linux/delay.h>
#include <linux/etherdevice.h>
#include <linux/jiffies.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <net/dsa.h>
#include "mv88e6060.h"

static int reg_read(struct mv88e6060_priv *priv, int addr, int reg)
{
	return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg);
}

static int reg_write(struct mv88e6060_priv *priv, int addr, int reg, u16 val)
{
	return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val);
}

static const char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr)
{
	int ret;

	ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
	if (ret >= 0) {
		if (ret == PORT_SWITCH_ID_6060)
			return "Marvell 88E6060 (A0)";
		if (ret == PORT_SWITCH_ID_6060_R1 ||
		    ret == PORT_SWITCH_ID_6060_R2)
			return "Marvell 88E6060 (B0)";
		if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
			return "Marvell 88E6060";
	}

	return NULL;
}

static enum dsa_tag_protocol mv88e6060_get_tag_protocol(struct dsa_switch *ds,
							int port)
{
	return DSA_TAG_PROTO_TRAILER;
}

static int mv88e6060_switch_reset(struct mv88e6060_priv *priv)
{
	int i;
	int ret;
	unsigned long timeout;

	/* Set all ports to the disabled state. */
	for (i = 0; i < MV88E6060_PORTS; i++) {
		ret = reg_read(priv, REG_PORT(i), PORT_CONTROL);
		if (ret < 0)
			return ret;
		ret = reg_write(priv, REG_PORT(i), PORT_CONTROL,
				ret & ~PORT_CONTROL_STATE_MASK);
		if (ret)
			return ret;
	}

	/* Wait for transmit queues to drain. */
	usleep_range(2000, 4000);

	/* Reset the switch. */
	ret = reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL,
			GLOBAL_ATU_CONTROL_SWRESET |
			GLOBAL_ATU_CONTROL_LEARNDIS);
	if (ret)
		return ret;

	/* Wait up to one second for reset to complete. */
	timeout = jiffies + 1 * HZ;
	while (time_before(jiffies, timeout)) {
		ret = reg_read(priv, REG_GLOBAL, GLOBAL_STATUS);
		if (ret < 0)
			return ret;

		if (ret & GLOBAL_STATUS_INIT_READY)
			break;

		usleep_range(1000, 2000);
	}
	if (time_after(jiffies, timeout))
		return -ETIMEDOUT;

	return 0;
}

static int mv88e6060_setup_global(struct mv88e6060_priv *priv)
{
	int ret;

	/* Disable discarding of frames with excessive collisions,
	 * set the maximum frame size to 1536 bytes, and mask all
	 * interrupt sources.
	 */
	ret = reg_write(priv, REG_GLOBAL, GLOBAL_CONTROL,
			GLOBAL_CONTROL_MAX_FRAME_1536);
	if (ret)
		return ret;

	/* Disable automatic address learning.
	 */
	return reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL,
			 GLOBAL_ATU_CONTROL_LEARNDIS);
}

static int mv88e6060_setup_port(struct mv88e6060_priv *priv, int p)
{
	int addr = REG_PORT(p);
	int ret;

	/* Do not force flow control, disable Ingress and Egress
	 * Header tagging, disable VLAN tunneling, and set the port
	 * state to Forwarding.  Additionally, if this is the CPU
	 * port, enable Ingress and Egress Trailer tagging mode.
	 */
	ret = reg_write(priv, addr, PORT_CONTROL,
			dsa_is_cpu_port(priv->ds, p) ?
			PORT_CONTROL_TRAILER |
			PORT_CONTROL_INGRESS_MODE |
			PORT_CONTROL_STATE_FORWARDING :
			PORT_CONTROL_STATE_FORWARDING);
	if (ret)
		return ret;

	/* Port based VLAN map: give each port its own address
	 * database, allow the CPU port to talk to each of the 'real'
	 * ports, and allow each of the 'real' ports to only talk to
	 * the CPU port.
	 */
	ret = reg_write(priv, addr, PORT_VLAN_MAP,
			((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
			(dsa_is_cpu_port(priv->ds, p) ?
			 dsa_user_ports(priv->ds) :
			 BIT(dsa_to_port(priv->ds, p)->cpu_dp->index)));
	if (ret)
		return ret;

	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
	return reg_write(priv, addr, PORT_ASSOC_VECTOR, BIT(p));
}

static int mv88e6060_setup_addr(struct mv88e6060_priv *priv)
{
	u8 addr[ETH_ALEN];
	int ret;
	u16 val;

	eth_random_addr(addr);

	val = addr[0] << 8 | addr[1];

	/* The multicast bit is always transmitted as a zero, so the switch uses
	 * bit 8 for "DiffAddr", where 0 means all ports transmit the same SA.
	 */
	val &= 0xfeff;

	ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_01, val);
	if (ret)
		return ret;

	ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_23,
			(addr[2] << 8) | addr[3]);
	if (ret)
		return ret;

	return reg_write(priv, REG_GLOBAL, GLOBAL_MAC_45,
			 (addr[4] << 8) | addr[5]);
}

static int mv88e6060_setup(struct dsa_switch *ds)
{
	struct mv88e6060_priv *priv = ds->priv;
	int ret;
	int i;

	priv->ds = ds;

	ret = mv88e6060_switch_reset(priv);
	if (ret < 0)
		return ret;

	/* @@@ initialise atu */

	ret = mv88e6060_setup_global(priv);
	if (ret < 0)
		return ret;

	ret = mv88e6060_setup_addr(priv);
	if (ret < 0)
		return ret;

	for (i = 0; i < MV88E6060_PORTS; i++) {
		ret = mv88e6060_setup_port(priv, i);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int mv88e6060_port_to_phy_addr(int port)
{
	if (port >= 0 && port < MV88E6060_PORTS)
		return port;
	return -1;
}

static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
{
	struct mv88e6060_priv *priv = ds->priv;
	int addr;

	addr = mv88e6060_port_to_phy_addr(port);
	if (addr == -1)
		return 0xffff;

	return reg_read(priv, addr, regnum);
}

static int
mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
{
	struct mv88e6060_priv *priv = ds->priv;
	int addr;

	addr = mv88e6060_port_to_phy_addr(port);
	if (addr == -1)
		return 0xffff;

	return reg_write(priv, addr, regnum, val);
}

static const struct dsa_switch_ops mv88e6060_switch_ops = {
	.get_tag_protocol = mv88e6060_get_tag_protocol,
	.setup		= mv88e6060_setup,
	.phy_read	= mv88e6060_phy_read,
	.phy_write	= mv88e6060_phy_write,
};

static int mv88e6060_probe(struct mdio_device *mdiodev)
{
	struct device *dev = &mdiodev->dev;
	struct mv88e6060_priv *priv;
	struct dsa_switch *ds;
	const char *name;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->bus = mdiodev->bus;
	priv->sw_addr = mdiodev->addr;

	name = mv88e6060_get_name(priv->bus, priv->sw_addr);
	if (!name)
		return -ENODEV;

	dev_info(dev, "switch %s detected\n", name);

	ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
	if (!ds)
		return -ENOMEM;

	ds->dev = dev;
	ds->num_ports = MV88E6060_PORTS;
	ds->priv = priv;
	ds->dev = dev;
	ds->ops = &mv88e6060_switch_ops;

	dev_set_drvdata(dev, ds);

	return dsa_register_switch(ds);
}

static void mv88e6060_remove(struct mdio_device *mdiodev)
{
	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);

	dsa_unregister_switch(ds);
}

static const struct of_device_id mv88e6060_of_match[] = {
	{
		.compatible = "marvell,mv88e6060",
	},
	{ /* sentinel */ },
};

static struct mdio_driver mv88e6060_driver = {
	.probe	= mv88e6060_probe,
	.remove = mv88e6060_remove,
	.mdiodrv.driver = {
		.name = "mv88e6060",
		.of_match_table = mv88e6060_of_match,
	},
};

mdio_module_driver(mv88e6060_driver);

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mv88e6060");
Commit	Line	Data
406a4362	1	// SPDX-License-Identifier: GPL-2.0+
2e16a77e LB	2	/*
2e16a77e LB	3	* net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
e84665c9	4	* Copyright (c) 2008-2009 Marvell Semiconductor
2e16a77e LB	5	*/
2e16a77e LB	6
19b2f97e	7	#include <linux/delay.h>
56c3ff9b	8	#include <linux/etherdevice.h>
19b2f97e	9	#include <linux/jiffies.h>
2e16a77e	10	#include <linux/list.h>
2bbba277	11	#include <linux/module.h>
2e16a77e LB	12	#include <linux/netdevice.h>
2e16a77e LB	13	#include <linux/phy.h>
c8f0b869	14	#include <net/dsa.h>
6a4b2980	15	#include "mv88e6060.h"
2e16a77e	16
3e8bc1b8	17	static int reg_read(struct mv88e6060_priv *priv, int addr, int reg)
2e16a77e	18	{
a77d43f1	19	return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg);
2e16a77e LB	20	}
2e16a77e LB	21
3e8bc1b8	22	static int reg_write(struct mv88e6060_priv *priv, int addr, int reg, u16 val)
2e16a77e	23	{
a77d43f1	24	return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val);
2e16a77e LB	25	}
2e16a77e LB	26
0209d144	27	static const char mv88e6060_get_name(struct mii_bus bus, int sw_addr)
2e16a77e LB	28	{
	29	int ret;
	30
6a4b2980	31	ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
2e16a77e	32	if (ret >= 0) {
6a4b2980	33	if (ret == PORT_SWITCH_ID_6060)
3de6aa4c	34	return "Marvell 88E6060 (A0)";
6a4b2980 NA	35	if (ret == PORT_SWITCH_ID_6060_R1 \|\|
6a4b2980 NA	36	ret == PORT_SWITCH_ID_6060_R2)
3de6aa4c	37	return "Marvell 88E6060 (B0)";
6a4b2980	38	if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
2e16a77e LB	39	return "Marvell 88E6060";
	40	}
	41
	42	return NULL;
	43	}
	44
5ed4e3eb FF	45	static enum dsa_tag_protocol mv88e6060_get_tag_protocol(struct dsa_switch *ds,
5ed4e3eb FF	46	int port)
7b314362 AL	47	{
	48	return DSA_TAG_PROTO_TRAILER;
	49	}
	50
3e8bc1b8	51	static int mv88e6060_switch_reset(struct mv88e6060_priv *priv)
2e16a77e LB	52	{
	53	int i;
	54	int ret;
19b2f97e	55	unsigned long timeout;
2e16a77e	56
3675c8d7	57	/* Set all ports to the disabled state. */
6a4b2980	58	for (i = 0; i < MV88E6060_PORTS; i++) {
1ba22bf5 AL	59	ret = reg_read(priv, REG_PORT(i), PORT_CONTROL);
	60	if (ret < 0)
	61	return ret;
c4362c37 AL	62	ret = reg_write(priv, REG_PORT(i), PORT_CONTROL,
	63	ret & ~PORT_CONTROL_STATE_MASK);
	64	if (ret)
	65	return ret;
2e16a77e LB	66	}
2e16a77e LB	67
3675c8d7	68	/* Wait for transmit queues to drain. */
19b2f97e	69	usleep_range(2000, 4000);
2e16a77e	70
3675c8d7	71	/* Reset the switch. */
c4362c37 AL	72	ret = reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL,
	73	GLOBAL_ATU_CONTROL_SWRESET \|
	74	GLOBAL_ATU_CONTROL_LEARNDIS);
	75	if (ret)
	76	return ret;
2e16a77e	77
3675c8d7	78	/* Wait up to one second for reset to complete. */
19b2f97e BG	79	timeout = jiffies + 1 * HZ;
19b2f97e BG	80	while (time_before(jiffies, timeout)) {
1ba22bf5 AL	81	ret = reg_read(priv, REG_GLOBAL, GLOBAL_STATUS);
	82	if (ret < 0)
	83	return ret;
	84
6a4b2980	85	if (ret & GLOBAL_STATUS_INIT_READY)
2e16a77e LB	86	break;
2e16a77e LB	87
19b2f97e	88	usleep_range(1000, 2000);
2e16a77e	89	}
19b2f97e	90	if (time_after(jiffies, timeout))
2e16a77e LB	91	return -ETIMEDOUT;
	92
	93	return 0;
	94	}
	95
3e8bc1b8	96	static int mv88e6060_setup_global(struct mv88e6060_priv *priv)
2e16a77e	97	{
c4362c37 AL	98	int ret;
c4362c37 AL	99
3675c8d7	100	/* Disable discarding of frames with excessive collisions,
2e16a77e LB	101	* set the maximum frame size to 1536 bytes, and mask all
	102	* interrupt sources.
	103	*/
c4362c37 AL	104	ret = reg_write(priv, REG_GLOBAL, GLOBAL_CONTROL,
	105	GLOBAL_CONTROL_MAX_FRAME_1536);
	106	if (ret)
	107	return ret;
2e16a77e	108
a7451560	109	/* Disable automatic address learning.
2e16a77e	110	*/
c4362c37 AL	111	return reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL,
c4362c37 AL	112	GLOBAL_ATU_CONTROL_LEARNDIS);
2e16a77e LB	113	}
2e16a77e LB	114
3e8bc1b8	115	static int mv88e6060_setup_port(struct mv88e6060_priv *priv, int p)
2e16a77e LB	116	{
2e16a77e LB	117	int addr = REG_PORT(p);
c4362c37	118	int ret;
2e16a77e	119
3675c8d7	120	/* Do not force flow control, disable Ingress and Egress
2e16a77e LB	121	* Header tagging, disable VLAN tunneling, and set the port
	122	* state to Forwarding. Additionally, if this is the CPU
	123	* port, enable Ingress and Egress Trailer tagging mode.
	124	*/
c4362c37 AL	125	ret = reg_write(priv, addr, PORT_CONTROL,
c4362c37 AL	126	dsa_is_cpu_port(priv->ds, p) ?
6a4b2980 NA	127	PORT_CONTROL_TRAILER \|
	128	PORT_CONTROL_INGRESS_MODE \|
	129	PORT_CONTROL_STATE_FORWARDING :
	130	PORT_CONTROL_STATE_FORWARDING);
c4362c37 AL	131	if (ret)
c4362c37 AL	132	return ret;
2e16a77e	133
3675c8d7	134	/* Port based VLAN map: give each port its own address
2e16a77e LB	135	* database, allow the CPU port to talk to each of the 'real'
	136	* ports, and allow each of the 'real' ports to only talk to
	137	* the CPU port.
	138	*/
c4362c37 AL	139	ret = reg_write(priv, addr, PORT_VLAN_MAP,
	140	((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) \|
	141	(dsa_is_cpu_port(priv->ds, p) ?
	142	dsa_user_ports(priv->ds) :
	143	BIT(dsa_to_port(priv->ds, p)->cpu_dp->index)));
	144	if (ret)
	145	return ret;
2e16a77e	146
3675c8d7	147	/* Port Association Vector: when learning source addresses
2e16a77e LB	148	* of packets, add the address to the address database using
	149	* a port bitmap that has only the bit for this port set and
	150	* the other bits clear.
	151	*/
c4362c37	152	return reg_write(priv, addr, PORT_ASSOC_VECTOR, BIT(p));
2e16a77e LB	153	}
2e16a77e LB	154
3e8bc1b8	155	static int mv88e6060_setup_addr(struct mv88e6060_priv *priv)
56c3ff9b VD	156	{
56c3ff9b VD	157	u8 addr[ETH_ALEN];
c4362c37	158	int ret;
56c3ff9b VD	159	u16 val;
	160
	161	eth_random_addr(addr);
	162
	163	val = addr[0] << 8 \| addr[1];
	164
	165	/* The multicast bit is always transmitted as a zero, so the switch uses
	166	* bit 8 for "DiffAddr", where 0 means all ports transmit the same SA.
	167	*/
	168	val &= 0xfeff;
	169
c4362c37 AL	170	ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_01, val);
	171	if (ret)
	172	return ret;
	173
	174	ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_23,
	175	(addr[2] << 8) \| addr[3]);
	176	if (ret)
	177	return ret;
56c3ff9b	178
c4362c37 AL	179	return reg_write(priv, REG_GLOBAL, GLOBAL_MAC_45,
c4362c37 AL	180	(addr[4] << 8) \| addr[5]);
56c3ff9b VD	181	}
56c3ff9b VD	182
2e16a77e LB	183	static int mv88e6060_setup(struct dsa_switch *ds)
2e16a77e LB	184	{
3e8bc1b8	185	struct mv88e6060_priv *priv = ds->priv;
2e16a77e	186	int ret;
a77d43f1	187	int i;
2e16a77e	188
3e8bc1b8 AL	189	priv->ds = ds;
	190
	191	ret = mv88e6060_switch_reset(priv);
2e16a77e LB	192	if (ret < 0)
	193	return ret;
	194
	195	/* @@@ initialise atu */
	196
3e8bc1b8	197	ret = mv88e6060_setup_global(priv);
2e16a77e LB	198	if (ret < 0)
	199	return ret;
	200
3e8bc1b8	201	ret = mv88e6060_setup_addr(priv);
56c3ff9b VD	202	if (ret < 0)
	203	return ret;
	204
6a4b2980	205	for (i = 0; i < MV88E6060_PORTS; i++) {
3e8bc1b8	206	ret = mv88e6060_setup_port(priv, i);
2e16a77e LB	207	if (ret < 0)
	208	return ret;
	209	}
	210
	211	return 0;
	212	}
	213
2e16a77e LB	214	static int mv88e6060_port_to_phy_addr(int port)
2e16a77e LB	215	{
6a4b2980	216	if (port >= 0 && port < MV88E6060_PORTS)
2e16a77e LB	217	return port;
	218	return -1;
	219	}
	220
	221	static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
	222	{
3e8bc1b8	223	struct mv88e6060_priv *priv = ds->priv;
2e16a77e LB	224	int addr;
	225
	226	addr = mv88e6060_port_to_phy_addr(port);
	227	if (addr == -1)
	228	return 0xffff;
	229
3e8bc1b8	230	return reg_read(priv, addr, regnum);
2e16a77e LB	231	}
	232
	233	static int
	234	mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
	235	{
3e8bc1b8	236	struct mv88e6060_priv *priv = ds->priv;
2e16a77e LB	237	int addr;
	238
	239	addr = mv88e6060_port_to_phy_addr(port);
	240	if (addr == -1)
	241	return 0xffff;
	242
3e8bc1b8	243	return reg_write(priv, addr, regnum, val);
2e16a77e LB	244	}
2e16a77e LB	245
a82f67af	246	static const struct dsa_switch_ops mv88e6060_switch_ops = {
7b314362	247	.get_tag_protocol = mv88e6060_get_tag_protocol,
2e16a77e	248	.setup = mv88e6060_setup,
2e16a77e LB	249	.phy_read = mv88e6060_phy_read,
2e16a77e LB	250	.phy_write = mv88e6060_phy_write,
2e16a77e LB	251	};
2e16a77e LB	252
27761760 AL	253	static int mv88e6060_probe(struct mdio_device *mdiodev)
	254	{
	255	struct device *dev = &mdiodev->dev;
	256	struct mv88e6060_priv *priv;
	257	struct dsa_switch *ds;
	258	const char *name;
	259
	260	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	261	if (!priv)
	262	return -ENOMEM;
	263
	264	priv->bus = mdiodev->bus;
	265	priv->sw_addr = mdiodev->addr;
	266
	267	name = mv88e6060_get_name(priv->bus, priv->sw_addr);
	268	if (!name)
	269	return -ENODEV;
	270
	271	dev_info(dev, "switch %s detected\n", name);
	272
7e99e347	273	ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
27761760 AL	274	if (!ds)
	275	return -ENOMEM;
	276
7e99e347 VD	277	ds->dev = dev;
7e99e347 VD	278	ds->num_ports = MV88E6060_PORTS;
27761760 AL	279	ds->priv = priv;
	280	ds->dev = dev;
	281	ds->ops = &mv88e6060_switch_ops;
	282
	283	dev_set_drvdata(dev, ds);
	284
	285	return dsa_register_switch(ds);
	286	}
	287
	288	static void mv88e6060_remove(struct mdio_device *mdiodev)
	289	{
	290	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
	291
	292	dsa_unregister_switch(ds);
	293	}
	294
	295	static const struct of_device_id mv88e6060_of_match[] = {
	296	{
	297	.compatible = "marvell,mv88e6060",
	298	},
	299	{ /* sentinel */ },
	300	};
	301
	302	static struct mdio_driver mv88e6060_driver = {
	303	.probe = mv88e6060_probe,
	304	.remove = mv88e6060_remove,
	305	.mdiodrv.driver = {
	306	.name = "mv88e6060",
	307	.of_match_table = mv88e6060_of_match,
	308	},
	309	};
	310
2f8e7ece	311	mdio_module_driver(mv88e6060_driver);
3d825ede BH	312
	313	MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
	314	MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
	315	MODULE_LICENSE("GPL");
	316	MODULE_ALIAS("platform:mv88e6060");