projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: macvlan: convert to hw_features
[linux-2.6-block.git] / drivers / net / cxgb3 / cxgb3_main.c
CommitLineData
4d22de3e 1/*
a02d44a0 2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
4d22de3e 3 *
1d68e93d
DLR		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
4d22de3e 9 *
1d68e93d
DLR		 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
4d22de3e 31 */
4d22de3e
DLR		 32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/dma-mapping.h>
37#include <linux/netdevice.h>
38#include <linux/etherdevice.h>
39#include <linux/if_vlan.h>
0f07c4ee 40#include <linux/mdio.h>
4d22de3e
DLR		 41#include <linux/sockios.h>
42#include <linux/workqueue.h>
43#include <linux/proc_fs.h>
44#include <linux/rtnetlink.h>
2e283962 45#include <linux/firmware.h>
d9da466a 46#include <linux/log2.h>
34336ec0 47#include <linux/stringify.h>
e998f245 48#include <linux/sched.h>
5a0e3ad6 49#include <linux/slab.h>
4d22de3e
DLR		 50#include <asm/uaccess.h>
51
52#include "common.h"
53#include "cxgb3_ioctl.h"
54#include "regs.h"
55#include "cxgb3_offload.h"
56#include "version.h"
57
58#include "cxgb3_ctl_defs.h"
59#include "t3_cpl.h"
60#include "firmware_exports.h"
61
62enum {
63 MAX_TXQ_ENTRIES = 16384,
64 MAX_CTRL_TXQ_ENTRIES = 1024,
65 MAX_RSPQ_ENTRIES = 16384,
66 MAX_RX_BUFFERS = 16384,
67 MAX_RX_JUMBO_BUFFERS = 16384,
68 MIN_TXQ_ENTRIES = 4,
69 MIN_CTRL_TXQ_ENTRIES = 4,
70 MIN_RSPQ_ENTRIES = 32,
71 MIN_FL_ENTRIES = 32
72};
73
74#define PORT_MASK ((1 << MAX_NPORTS) - 1)
75
76#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
78 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
79
80#define EEPROM_MAGIC 0x38E2F10C
81
678771d6
DLR		 82#define CH_DEVICE(devid, idx) \
83 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, PCI_ANY_ID, 0, 0, idx }
4d22de3e 84
a3aa1884 85static DEFINE_PCI_DEVICE_TABLE(cxgb3_pci_tbl) = {
678771d6
DLR		 86 CH_DEVICE(0x20, 0), /* PE9000 */
87 CH_DEVICE(0x21, 1), /* T302E */
88 CH_DEVICE(0x22, 2), /* T310E */
89 CH_DEVICE(0x23, 3), /* T320X */
90 CH_DEVICE(0x24, 1), /* T302X */
91 CH_DEVICE(0x25, 3), /* T320E */
92 CH_DEVICE(0x26, 2), /* T310X */
93 CH_DEVICE(0x30, 2), /* T3B10 */
94 CH_DEVICE(0x31, 3), /* T3B20 */
95 CH_DEVICE(0x32, 1), /* T3B02 */
ce03aadd 96 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
74451424
DLR		 97 CH_DEVICE(0x36, 3), /* S320E-CR */
98 CH_DEVICE(0x37, 7), /* N320E-G2 */
4d22de3e
DLR		 99 {0,}
100};
101
102MODULE_DESCRIPTION(DRV_DESC);
103MODULE_AUTHOR("Chelsio Communications");
1d68e93d 104MODULE_LICENSE("Dual BSD/GPL");
4d22de3e
DLR		 105MODULE_VERSION(DRV_VERSION);
106MODULE_DEVICE_TABLE(pci, cxgb3_pci_tbl);
107
108static int dflt_msg_enable = DFLT_MSG_ENABLE;
109
110module_param(dflt_msg_enable, int, 0644);
111MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T3 default message enable bitmap");
112
113/*
114 * The driver uses the best interrupt scheme available on a platform in the
115 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
116 * of these schemes the driver may consider as follows:
117 *
118 * msi = 2: choose from among all three options
119 * msi = 1: only consider MSI and pin interrupts
120 * msi = 0: force pin interrupts
121 */
122static int msi = 2;
123
124module_param(msi, int, 0644);
125MODULE_PARM_DESC(msi, "whether to use MSI or MSI-X");
126
127/*
128 * The driver enables offload as a default.
129 * To disable it, use ofld_disable = 1.
130 */
131
132static int ofld_disable = 0;
133
134module_param(ofld_disable, int, 0644);
135MODULE_PARM_DESC(ofld_disable, "whether to enable offload at init time or not");
136
137/*
138 * We have work elements that we need to cancel when an interface is taken
139 * down. Normally the work elements would be executed by keventd but that
140 * can deadlock because of linkwatch. If our close method takes the rtnl
141 * lock and linkwatch is ahead of our work elements in keventd, linkwatch
142 * will block keventd as it needs the rtnl lock, and we'll deadlock waiting
143 * for our work to complete. Get our own work queue to solve this.
144 */
e998f245 145struct workqueue_struct *cxgb3_wq;
4d22de3e
DLR		 146
147/**
148 * link_report - show link status and link speed/duplex
149 * @p: the port whose settings are to be reported
150 *
151 * Shows the link status, speed, and duplex of a port.
152 */
153static void link_report(struct net_device *dev)
154{
155 if (!netif_carrier_ok(dev))
156 printk(KERN_INFO "%s: link down\n", dev->name);
157 else {
158 const char *s = "10Mbps";
159 const struct port_info *p = netdev_priv(dev);
160
161 switch (p->link_config.speed) {
162 case SPEED_10000:
163 s = "10Gbps";
164 break;
165 case SPEED_1000:
166 s = "1000Mbps";
167 break;
168 case SPEED_100:
169 s = "100Mbps";
170 break;
171 }
172
173 printk(KERN_INFO "%s: link up, %s, %s-duplex\n", dev->name, s,
174 p->link_config.duplex == DUPLEX_FULL ? "full" : "half");
175 }
176}
177
34701fde
DLR		 178static void enable_tx_fifo_drain(struct adapter *adapter,
179 struct port_info *pi)
180{
181 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, 0,
182 F_ENDROPPKT);
183 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, 0);
184 t3_write_reg(adapter, A_XGM_TX_CTRL + pi->mac.offset, F_TXEN);
185 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, F_RXEN);
186}
187
188static void disable_tx_fifo_drain(struct adapter *adapter,
189 struct port_info *pi)
190{
191 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset,
192 F_ENDROPPKT, 0);
193}
194
bf792094
DLR		 195void t3_os_link_fault(struct adapter *adap, int port_id, int state)
196{
197 struct net_device *dev = adap->port[port_id];
198 struct port_info *pi = netdev_priv(dev);
199
200 if (state == netif_carrier_ok(dev))
201 return;
202
203 if (state) {
204 struct cmac *mac = &pi->mac;
205
206 netif_carrier_on(dev);
207
34701fde
DLR		 208 disable_tx_fifo_drain(adap, pi);
209
bf792094
DLR		 210 /* Clear local faults */
211 t3_xgm_intr_disable(adap, pi->port_id);
212 t3_read_reg(adap, A_XGM_INT_STATUS +
213 pi->mac.offset);
214 t3_write_reg(adap,
215 A_XGM_INT_CAUSE + pi->mac.offset,
216 F_XGM_INT);
217
218 t3_set_reg_field(adap,
219 A_XGM_INT_ENABLE +
220 pi->mac.offset,
221 F_XGM_INT, F_XGM_INT);
222 t3_xgm_intr_enable(adap, pi->port_id);
223
224 t3_mac_enable(mac, MAC_DIRECTION_TX);
34701fde 225 } else {
bf792094
DLR		 226 netif_carrier_off(dev);
227
34701fde
DLR		 228 /* Flush TX FIFO */
229 enable_tx_fifo_drain(adap, pi);
230 }
bf792094
DLR		 231 link_report(dev);
232}
233
4d22de3e
DLR		 234/**
235 * t3_os_link_changed - handle link status changes
236 * @adapter: the adapter associated with the link change
237 * @port_id: the port index whose limk status has changed
238 * @link_stat: the new status of the link
239 * @speed: the new speed setting
240 * @duplex: the new duplex setting
241 * @pause: the new flow-control setting
242 *
243 * This is the OS-dependent handler for link status changes. The OS
244 * neutral handler takes care of most of the processing for these events,
245 * then calls this handler for any OS-specific processing.
246 */
247void t3_os_link_changed(struct adapter *adapter, int port_id, int link_stat,
248 int speed, int duplex, int pause)
249{
250 struct net_device *dev = adapter->port[port_id];
6d6dabac
DLR		 251 struct port_info *pi = netdev_priv(dev);
252 struct cmac *mac = &pi->mac;
4d22de3e
DLR		 253
254 /* Skip changes from disabled ports. */
255 if (!netif_running(dev))
256 return;
257
258 if (link_stat != netif_carrier_ok(dev)) {
6d6dabac 259 if (link_stat) {
34701fde
DLR		 260 disable_tx_fifo_drain(adapter, pi);
261
59cf8107 262 t3_mac_enable(mac, MAC_DIRECTION_RX);
bf792094
DLR		 263
264 /* Clear local faults */
265 t3_xgm_intr_disable(adapter, pi->port_id);
266 t3_read_reg(adapter, A_XGM_INT_STATUS +
267 pi->mac.offset);
268 t3_write_reg(adapter,
269 A_XGM_INT_CAUSE + pi->mac.offset,
270 F_XGM_INT);
271
272 t3_set_reg_field(adapter,
273 A_XGM_INT_ENABLE + pi->mac.offset,
274 F_XGM_INT, F_XGM_INT);
275 t3_xgm_intr_enable(adapter, pi->port_id);
276
4d22de3e 277 netif_carrier_on(dev);
6d6dabac 278 } else {
4d22de3e 279 netif_carrier_off(dev);
bf792094
DLR		 280
281 t3_xgm_intr_disable(adapter, pi->port_id);
282 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
283 t3_set_reg_field(adapter,
284 A_XGM_INT_ENABLE + pi->mac.offset,
285 F_XGM_INT, 0);
286
287 if (is_10G(adapter))
288 pi->phy.ops->power_down(&pi->phy, 1);
289
290 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
59cf8107
DLR		 291 t3_mac_disable(mac, MAC_DIRECTION_RX);
292 t3_link_start(&pi->phy, mac, &pi->link_config);
34701fde
DLR		 293
294 /* Flush TX FIFO */
295 enable_tx_fifo_drain(adapter, pi);
6d6dabac
DLR		 296 }
297
4d22de3e
DLR		 298 link_report(dev);
299 }
300}
301
1e882025
DLR		 302/**
303 * t3_os_phymod_changed - handle PHY module changes
304 * @phy: the PHY reporting the module change
305 * @mod_type: new module type
306 *
307 * This is the OS-dependent handler for PHY module changes. It is
308 * invoked when a PHY module is removed or inserted for any OS-specific
309 * processing.
310 */
311void t3_os_phymod_changed(struct adapter *adap, int port_id)
312{
313 static const char *mod_str[] = {
314 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown"
315 };
316
317 const struct net_device *dev = adap->port[port_id];
318 const struct port_info *pi = netdev_priv(dev);
319
320 if (pi->phy.modtype == phy_modtype_none)
321 printk(KERN_INFO "%s: PHY module unplugged\n", dev->name);
322 else
323 printk(KERN_INFO "%s: %s PHY module inserted\n", dev->name,
324 mod_str[pi->phy.modtype]);
325}
326
4d22de3e
DLR		 327static void cxgb_set_rxmode(struct net_device *dev)
328{
4d22de3e
DLR		 329 struct port_info *pi = netdev_priv(dev);
330
0988d269 331 t3_mac_set_rx_mode(&pi->mac, dev);
4d22de3e
DLR		 332}
333
334/**
335 * link_start - enable a port
336 * @dev: the device to enable
337 *
338 * Performs the MAC and PHY actions needed to enable a port.
339 */
340static void link_start(struct net_device *dev)
341{
4d22de3e
DLR		 342 struct port_info *pi = netdev_priv(dev);
343 struct cmac *mac = &pi->mac;
344
4d22de3e 345 t3_mac_reset(mac);
f14d42f3 346 t3_mac_set_num_ucast(mac, MAX_MAC_IDX);
4d22de3e 347 t3_mac_set_mtu(mac, dev->mtu);
f14d42f3
KX		 348 t3_mac_set_address(mac, LAN_MAC_IDX, dev->dev_addr);
349 t3_mac_set_address(mac, SAN_MAC_IDX, pi->iscsic.mac_addr);
0988d269 350 t3_mac_set_rx_mode(mac, dev);
4d22de3e
DLR		 351 t3_link_start(&pi->phy, mac, &pi->link_config);
352 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
353}
354
355static inline void cxgb_disable_msi(struct adapter *adapter)
356{
357 if (adapter->flags & USING_MSIX) {
358 pci_disable_msix(adapter->pdev);
359 adapter->flags &= ~USING_MSIX;
360 } else if (adapter->flags & USING_MSI) {
361 pci_disable_msi(adapter->pdev);
362 adapter->flags &= ~USING_MSI;
363 }
364}
365
366/*
367 * Interrupt handler for asynchronous events used with MSI-X.
368 */
369static irqreturn_t t3_async_intr_handler(int irq, void *cookie)
370{
371 t3_slow_intr_handler(cookie);
372 return IRQ_HANDLED;
373}
374
375/*
376 * Name the MSI-X interrupts.
377 */
378static void name_msix_vecs(struct adapter *adap)
379{
380 int i, j, msi_idx = 1, n = sizeof(adap->msix_info[0].desc) - 1;
381
382 snprintf(adap->msix_info[0].desc, n, "%s", adap->name);
383 adap->msix_info[0].desc[n] = 0;
384
385 for_each_port(adap, j) {
386 struct net_device *d = adap->port[j];
387 const struct port_info *pi = netdev_priv(d);
388
389 for (i = 0; i < pi->nqsets; i++, msi_idx++) {
390 snprintf(adap->msix_info[msi_idx].desc, n,
8c263761 391 "%s-%d", d->name, pi->first_qset + i);
4d22de3e
DLR		 392 adap->msix_info[msi_idx].desc[n] = 0;
393 }
8c263761 394 }
4d22de3e
DLR		 395}
396
397static int request_msix_data_irqs(struct adapter *adap)
398{
399 int i, j, err, qidx = 0;
400
401 for_each_port(adap, i) {
402 int nqsets = adap2pinfo(adap, i)->nqsets;
403
404 for (j = 0; j < nqsets; ++j) {
405 err = request_irq(adap->msix_info[qidx + 1].vec,
406 t3_intr_handler(adap,
407 adap->sge.qs[qidx].
408 rspq.polling), 0,
409 adap->msix_info[qidx + 1].desc,
410 &adap->sge.qs[qidx]);
411 if (err) {
412 while (--qidx >= 0)
413 free_irq(adap->msix_info[qidx + 1].vec,
414 &adap->sge.qs[qidx]);
415 return err;
416 }
417 qidx++;
418 }
419 }
420 return 0;
421}
422
8c263761
DLR		 423static void free_irq_resources(struct adapter *adapter)
424{
425 if (adapter->flags & USING_MSIX) {
426 int i, n = 0;
427
428 free_irq(adapter->msix_info[0].vec, adapter);
429 for_each_port(adapter, i)
5cda9364 430 n += adap2pinfo(adapter, i)->nqsets;
8c263761
DLR		 431
432 for (i = 0; i < n; ++i)
433 free_irq(adapter->msix_info[i + 1].vec,
434 &adapter->sge.qs[i]);
435 } else
436 free_irq(adapter->pdev->irq, adapter);
437}
438
b881955b
DLR		 439static int await_mgmt_replies(struct adapter *adap, unsigned long init_cnt,
440 unsigned long n)
441{
e95ef5d3 442 int attempts = 10;
b881955b
DLR		 443
444 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) {
445 if (!--attempts)
446 return -ETIMEDOUT;
447 msleep(10);
448 }
449 return 0;
450}
451
452static int init_tp_parity(struct adapter *adap)
453{
454 int i;
455 struct sk_buff *skb;
456 struct cpl_set_tcb_field *greq;
457 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts;
458
459 t3_tp_set_offload_mode(adap, 1);
460
461 for (i = 0; i < 16; i++) {
462 struct cpl_smt_write_req *req;
463
74b793e1
DLR		 464 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
465 if (!skb)
466 skb = adap->nofail_skb;
467 if (!skb)
468 goto alloc_skb_fail;
469
b881955b
DLR		 470 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
471 memset(req, 0, sizeof(*req));
472 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
473 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i));
dce7d1d0 474 req->mtu_idx = NMTUS - 1;
b881955b
DLR		 475 req->iff = i;
476 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 477 if (skb == adap->nofail_skb) {
478 await_mgmt_replies(adap, cnt, i + 1);
479 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
480 if (!adap->nofail_skb)
481 goto alloc_skb_fail;
482 }
b881955b
DLR		 483 }
484
485 for (i = 0; i < 2048; i++) {
486 struct cpl_l2t_write_req *req;
487
74b793e1
DLR		 488 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
489 if (!skb)
490 skb = adap->nofail_skb;
491 if (!skb)
492 goto alloc_skb_fail;
493
b881955b
DLR		 494 req = (struct cpl_l2t_write_req *)__skb_put(skb, sizeof(*req));
495 memset(req, 0, sizeof(*req));
496 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
497 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i));
498 req->params = htonl(V_L2T_W_IDX(i));
499 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 500 if (skb == adap->nofail_skb) {
501 await_mgmt_replies(adap, cnt, 16 + i + 1);
502 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
503 if (!adap->nofail_skb)
504 goto alloc_skb_fail;
505 }
b881955b
DLR		 506 }
507
508 for (i = 0; i < 2048; i++) {
509 struct cpl_rte_write_req *req;
510
74b793e1
DLR		 511 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
512 if (!skb)
513 skb = adap->nofail_skb;
514 if (!skb)
515 goto alloc_skb_fail;
516
b881955b
DLR		 517 req = (struct cpl_rte_write_req *)__skb_put(skb, sizeof(*req));
518 memset(req, 0, sizeof(*req));
519 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
520 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i));
521 req->l2t_idx = htonl(V_L2T_W_IDX(i));
522 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 523 if (skb == adap->nofail_skb) {
524 await_mgmt_replies(adap, cnt, 16 + 2048 + i + 1);
525 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
526 if (!adap->nofail_skb)
527 goto alloc_skb_fail;
528 }
b881955b
DLR		 529 }
530
74b793e1
DLR		 531 skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
532 if (!skb)
533 skb = adap->nofail_skb;
534 if (!skb)
535 goto alloc_skb_fail;
536
b881955b
DLR		 537 greq = (struct cpl_set_tcb_field *)__skb_put(skb, sizeof(*greq));
538 memset(greq, 0, sizeof(*greq));
539 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
540 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0));
541 greq->mask = cpu_to_be64(1);
542 t3_mgmt_tx(adap, skb);
543
544 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
74b793e1
DLR		 545 if (skb == adap->nofail_skb) {
546 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
547 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
548 }
549
b881955b
DLR		 550 t3_tp_set_offload_mode(adap, 0);
551 return i;
74b793e1
DLR		 552
553alloc_skb_fail:
554 t3_tp_set_offload_mode(adap, 0);
555 return -ENOMEM;
b881955b
DLR		 556}
557
4d22de3e
DLR		 558/**
559 * setup_rss - configure RSS
560 * @adap: the adapter
561 *
562 * Sets up RSS to distribute packets to multiple receive queues. We
563 * configure the RSS CPU lookup table to distribute to the number of HW
564 * receive queues, and the response queue lookup table to narrow that
565 * down to the response queues actually configured for each port.
566 * We always configure the RSS mapping for two ports since the mapping
567 * table has plenty of entries.
568 */
569static void setup_rss(struct adapter *adap)
570{
571 int i;
572 unsigned int nq0 = adap2pinfo(adap, 0)->nqsets;
573 unsigned int nq1 = adap->port[1] ? adap2pinfo(adap, 1)->nqsets : 1;
574 u8 cpus[SGE_QSETS + 1];
575 u16 rspq_map[RSS_TABLE_SIZE];
576
577 for (i = 0; i < SGE_QSETS; ++i)
578 cpus[i] = i;
579 cpus[SGE_QSETS] = 0xff; /* terminator */
580
581 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
582 rspq_map[i] = i % nq0;
583 rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq1) + nq0;
584 }
585
586 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
587 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN |
a2604be5 588 V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, cpus, rspq_map);
4d22de3e
DLR		 589}
590
e998f245
SW		 591static void ring_dbs(struct adapter *adap)
592{
593 int i, j;
594
595 for (i = 0; i < SGE_QSETS; i++) {
596 struct sge_qset *qs = &adap->sge.qs[i];
597
598 if (qs->adap)
599 for (j = 0; j < SGE_TXQ_PER_SET; j++)
600 t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX | V_EGRCNTX(qs->txq[j].cntxt_id));
601 }
602}
603
bea3348e 604static void init_napi(struct adapter *adap)
4d22de3e 605{
bea3348e 606 int i;
4d22de3e 607
bea3348e
SH		 608 for (i = 0; i < SGE_QSETS; i++) {
609 struct sge_qset *qs = &adap->sge.qs[i];
4d22de3e 610
bea3348e
SH		 611 if (qs->adap)
612 netif_napi_add(qs->netdev, &qs->napi, qs->napi.poll,
613 64);
4d22de3e 614 }
48c4b6db
DLR		 615
616 /*
617 * netif_napi_add() can be called only once per napi_struct because it
618 * adds each new napi_struct to a list. Be careful not to call it a
619 * second time, e.g., during EEH recovery, by making a note of it.
620 */
621 adap->flags |= NAPI_INIT;
4d22de3e
DLR		 622}
623
624/*
625 * Wait until all NAPI handlers are descheduled. This includes the handlers of
626 * both netdevices representing interfaces and the dummy ones for the extra
627 * queues.
628 */
629static void quiesce_rx(struct adapter *adap)
630{
631 int i;
4d22de3e 632
bea3348e
SH		 633 for (i = 0; i < SGE_QSETS; i++)
634 if (adap->sge.qs[i].adap)
635 napi_disable(&adap->sge.qs[i].napi);
636}
4d22de3e 637
bea3348e
SH		 638static void enable_all_napi(struct adapter *adap)
639{
640 int i;
641 for (i = 0; i < SGE_QSETS; i++)
642 if (adap->sge.qs[i].adap)
643 napi_enable(&adap->sge.qs[i].napi);
4d22de3e
DLR		 644}
645
04ecb072
DLR		 646/**
647 * set_qset_lro - Turn a queue set's LRO capability on and off
648 * @dev: the device the qset is attached to
649 * @qset_idx: the queue set index
650 * @val: the LRO switch
651 *
652 * Sets LRO on or off for a particular queue set.
653 * the device's features flag is updated to reflect the LRO
654 * capability when all queues belonging to the device are
655 * in the same state.
656 */
657static void set_qset_lro(struct net_device *dev, int qset_idx, int val)
658{
659 struct port_info *pi = netdev_priv(dev);
660 struct adapter *adapter = pi->adapter;
04ecb072
DLR		 661
662 adapter->params.sge.qset[qset_idx].lro = !!val;
663 adapter->sge.qs[qset_idx].lro_enabled = !!val;
04ecb072
DLR		 664}
665
4d22de3e
DLR		 666/**
667 * setup_sge_qsets - configure SGE Tx/Rx/response queues
668 * @adap: the adapter
669 *
670 * Determines how many sets of SGE queues to use and initializes them.
671 * We support multiple queue sets per port if we have MSI-X, otherwise
672 * just one queue set per port.
673 */
674static int setup_sge_qsets(struct adapter *adap)
675{
bea3348e 676 int i, j, err, irq_idx = 0, qset_idx = 0;
8ac3ba68 677 unsigned int ntxq = SGE_TXQ_PER_SET;
4d22de3e
DLR		 678
679 if (adap->params.rev > 0 && !(adap->flags & USING_MSI))
680 irq_idx = -1;
681
682 for_each_port(adap, i) {
683 struct net_device *dev = adap->port[i];
bea3348e 684 struct port_info *pi = netdev_priv(dev);
4d22de3e 685
bea3348e 686 pi->qs = &adap->sge.qs[pi->first_qset];
e594e96e 687 for (j = 0; j < pi->nqsets; ++j, ++qset_idx) {
47fd23fe 688 set_qset_lro(dev, qset_idx, pi->rx_offload & T3_LRO);
4d22de3e
DLR		 689 err = t3_sge_alloc_qset(adap, qset_idx, 1,
690 (adap->flags & USING_MSIX) ? qset_idx + 1 :
691 irq_idx,
82ad3329
DLR		 692 &adap->params.sge.qset[qset_idx], ntxq, dev,
693 netdev_get_tx_queue(dev, j));
4d22de3e
DLR		 694 if (err) {
695 t3_free_sge_resources(adap);
696 return err;
697 }
698 }
699 }
700
701 return 0;
702}
703
3e5192ee 704static ssize_t attr_show(struct device *d, char *buf,
896392ef 705 ssize_t(*format) (struct net_device *, char *))
4d22de3e
DLR		 706{
707 ssize_t len;
4d22de3e
DLR		 708
709 /* Synchronize with ioctls that may shut down the device */
710 rtnl_lock();
896392ef 711 len = (*format) (to_net_dev(d), buf);
4d22de3e
DLR		 712 rtnl_unlock();
713 return len;
714}
715
3e5192ee 716static ssize_t attr_store(struct device *d,
0ee8d33c 717 const char *buf, size_t len,
896392ef 718 ssize_t(*set) (struct net_device *, unsigned int),
4d22de3e
DLR		 719 unsigned int min_val, unsigned int max_val)
720{
721 char *endp;
722 ssize_t ret;
723 unsigned int val;
4d22de3e
DLR		 724
725 if (!capable(CAP_NET_ADMIN))
726 return -EPERM;
727
728 val = simple_strtoul(buf, &endp, 0);
729 if (endp == buf || val < min_val || val > max_val)
730 return -EINVAL;
731
732 rtnl_lock();
896392ef 733 ret = (*set) (to_net_dev(d), val);
4d22de3e
DLR		 734 if (!ret)
735 ret = len;
736 rtnl_unlock();
737 return ret;
738}
739
740#define CXGB3_SHOW(name, val_expr) \
896392ef 741static ssize_t format_##name(struct net_device *dev, char *buf) \
4d22de3e 742{ \
5fbf816f
DLR		 743 struct port_info *pi = netdev_priv(dev); \
744 struct adapter *adap = pi->adapter; \
4d22de3e
DLR		 745 return sprintf(buf, "%u\n", val_expr); \
746} \
0ee8d33c
DLR		 747static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
748 char *buf) \
4d22de3e 749{ \
3e5192ee 750 return attr_show(d, buf, format_##name); \
4d22de3e
DLR		 751}
752
896392ef 753static ssize_t set_nfilters(struct net_device *dev, unsigned int val)
4d22de3e 754{
5fbf816f
DLR		 755 struct port_info *pi = netdev_priv(dev);
756 struct adapter *adap = pi->adapter;
9f238486 757 int min_tids = is_offload(adap) ? MC5_MIN_TIDS : 0;
896392ef 758
4d22de3e
DLR		 759 if (adap->flags & FULL_INIT_DONE)
760 return -EBUSY;
761 if (val && adap->params.rev == 0)
762 return -EINVAL;
9f238486
DLR		 763 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
764 min_tids)
4d22de3e
DLR		 765 return -EINVAL;
766 adap->params.mc5.nfilters = val;
767 return 0;
768}
769
0ee8d33c
DLR		 770static ssize_t store_nfilters(struct device *d, struct device_attribute *attr,
771 const char *buf, size_t len)
4d22de3e 772{
3e5192ee 773 return attr_store(d, buf, len, set_nfilters, 0, ~0);
4d22de3e
DLR		 774}
775
896392ef 776static ssize_t set_nservers(struct net_device *dev, unsigned int val)
4d22de3e 777{
5fbf816f
DLR		 778 struct port_info *pi = netdev_priv(dev);
779 struct adapter *adap = pi->adapter;
896392ef 780
4d22de3e
DLR		 781 if (adap->flags & FULL_INIT_DONE)
782 return -EBUSY;
9f238486
DLR		 783 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nfilters -
784 MC5_MIN_TIDS)
4d22de3e
DLR		 785 return -EINVAL;
786 adap->params.mc5.nservers = val;
787 return 0;
788}
789
0ee8d33c
DLR		 790static ssize_t store_nservers(struct device *d, struct device_attribute *attr,
791 const char *buf, size_t len)
4d22de3e 792{
3e5192ee 793 return attr_store(d, buf, len, set_nservers, 0, ~0);
4d22de3e
DLR		 794}
795
796#define CXGB3_ATTR_R(name, val_expr) \
797CXGB3_SHOW(name, val_expr) \
0ee8d33c 798static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
4d22de3e
DLR		 799
800#define CXGB3_ATTR_RW(name, val_expr, store_method) \
801CXGB3_SHOW(name, val_expr) \
0ee8d33c 802static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_method)
4d22de3e
DLR		 803
804CXGB3_ATTR_R(cam_size, t3_mc5_size(&adap->mc5));
805CXGB3_ATTR_RW(nfilters, adap->params.mc5.nfilters, store_nfilters);
806CXGB3_ATTR_RW(nservers, adap->params.mc5.nservers, store_nservers);
807
808static struct attribute *cxgb3_attrs[] = {
0ee8d33c
DLR		 809 &dev_attr_cam_size.attr,
810 &dev_attr_nfilters.attr,
811 &dev_attr_nservers.attr,
4d22de3e
DLR		 812 NULL
813};
814
815static struct attribute_group cxgb3_attr_group = {.attrs = cxgb3_attrs };
816
3e5192ee 817static ssize_t tm_attr_show(struct device *d,
0ee8d33c 818 char *buf, int sched)
4d22de3e 819{
5fbf816f
DLR		 820 struct port_info *pi = netdev_priv(to_net_dev(d));
821 struct adapter *adap = pi->adapter;
4d22de3e 822 unsigned int v, addr, bpt, cpt;
5fbf816f 823 ssize_t len;
4d22de3e
DLR		 824
825 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
826 rtnl_lock();
827 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
828 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
829 if (sched & 1)
830 v >>= 16;
831 bpt = (v >> 8) & 0xff;
832 cpt = v & 0xff;
833 if (!cpt)
834 len = sprintf(buf, "disabled\n");
835 else {
836 v = (adap->params.vpd.cclk * 1000) / cpt;
837 len = sprintf(buf, "%u Kbps\n", (v * bpt) / 125);
838 }
839 rtnl_unlock();
840 return len;
841}
842
3e5192ee 843static ssize_t tm_attr_store(struct device *d,
0ee8d33c 844 const char *buf, size_t len, int sched)
4d22de3e 845{
5fbf816f
DLR		 846 struct port_info *pi = netdev_priv(to_net_dev(d));
847 struct adapter *adap = pi->adapter;
848 unsigned int val;
4d22de3e
DLR		 849 char *endp;
850 ssize_t ret;
4d22de3e
DLR		 851
852 if (!capable(CAP_NET_ADMIN))
853 return -EPERM;
854
855 val = simple_strtoul(buf, &endp, 0);
856 if (endp == buf || val > 10000000)
857 return -EINVAL;
858
859 rtnl_lock();
860 ret = t3_config_sched(adap, val, sched);
861 if (!ret)
862 ret = len;
863 rtnl_unlock();
864 return ret;
865}
866
867#define TM_ATTR(name, sched) \
0ee8d33c
DLR		 868static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
869 char *buf) \
4d22de3e 870{ \
3e5192ee 871 return tm_attr_show(d, buf, sched); \
4d22de3e 872} \
0ee8d33c
DLR		 873static ssize_t store_##name(struct device *d, struct device_attribute *attr, \
874 const char *buf, size_t len) \
4d22de3e 875{ \
3e5192ee 876 return tm_attr_store(d, buf, len, sched); \
4d22de3e 877} \
0ee8d33c 878static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name)
4d22de3e
DLR		 879
880TM_ATTR(sched0, 0);
881TM_ATTR(sched1, 1);
882TM_ATTR(sched2, 2);
883TM_ATTR(sched3, 3);
884TM_ATTR(sched4, 4);
885TM_ATTR(sched5, 5);
886TM_ATTR(sched6, 6);
887TM_ATTR(sched7, 7);
888
889static struct attribute *offload_attrs[] = {
0ee8d33c
DLR		 890 &dev_attr_sched0.attr,
891 &dev_attr_sched1.attr,
892 &dev_attr_sched2.attr,
893 &dev_attr_sched3.attr,
894 &dev_attr_sched4.attr,
895 &dev_attr_sched5.attr,
896 &dev_attr_sched6.attr,
897 &dev_attr_sched7.attr,
4d22de3e
DLR		 898 NULL
899};
900
901static struct attribute_group offload_attr_group = {.attrs = offload_attrs };
902
903/*
904 * Sends an sk_buff to an offload queue driver
905 * after dealing with any active network taps.
906 */
907static inline int offload_tx(struct t3cdev *tdev, struct sk_buff *skb)
908{
909 int ret;
910
911 local_bh_disable();
912 ret = t3_offload_tx(tdev, skb);
913 local_bh_enable();
914 return ret;
915}
916
917static int write_smt_entry(struct adapter *adapter, int idx)
918{
919 struct cpl_smt_write_req *req;
f14d42f3 920 struct port_info *pi = netdev_priv(adapter->port[idx]);
4d22de3e
DLR		 921 struct sk_buff *skb = alloc_skb(sizeof(*req), GFP_KERNEL);
922
923 if (!skb)
924 return -ENOMEM;
925
926 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
927 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
928 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx));
929 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */
930 req->iff = idx;
4d22de3e 931 memcpy(req->src_mac0, adapter->port[idx]->dev_addr, ETH_ALEN);
f14d42f3 932 memcpy(req->src_mac1, pi->iscsic.mac_addr, ETH_ALEN);
4d22de3e
DLR		 933 skb->priority = 1;
934 offload_tx(&adapter->tdev, skb);
935 return 0;
936}
937
938static int init_smt(struct adapter *adapter)
939{
940 int i;
941
942 for_each_port(adapter, i)
943 write_smt_entry(adapter, i);
944 return 0;
945}
946
947static void init_port_mtus(struct adapter *adapter)
948{
949 unsigned int mtus = adapter->port[0]->mtu;
950
951 if (adapter->port[1])
952 mtus |= adapter->port[1]->mtu << 16;
953 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus);
954}
955
8c263761 956static int send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo,
14ab9892
DLR		 957 int hi, int port)
958{
959 struct sk_buff *skb;
960 struct mngt_pktsched_wr *req;
8c263761 961 int ret;
14ab9892 962
74b793e1
DLR		 963 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
964 if (!skb)
965 skb = adap->nofail_skb;
966 if (!skb)
967 return -ENOMEM;
968
14ab9892
DLR		 969 req = (struct mngt_pktsched_wr *)skb_put(skb, sizeof(*req));
970 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT));
971 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET;
972 req->sched = sched;
973 req->idx = qidx;
974 req->min = lo;
975 req->max = hi;
976 req->binding = port;
8c263761 977 ret = t3_mgmt_tx(adap, skb);
74b793e1
DLR		 978 if (skb == adap->nofail_skb) {
979 adap->nofail_skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
980 GFP_KERNEL);
981 if (!adap->nofail_skb)
982 ret = -ENOMEM;
983 }
8c263761
DLR		 984
985 return ret;
14ab9892
DLR		 986}
987
8c263761 988static int bind_qsets(struct adapter *adap)
14ab9892 989{
8c263761 990 int i, j, err = 0;
14ab9892
DLR		 991
992 for_each_port(adap, i) {
993 const struct port_info *pi = adap2pinfo(adap, i);
994
8c263761
DLR		 995 for (j = 0; j < pi->nqsets; ++j) {
996 int ret = send_pktsched_cmd(adap, 1,
997 pi->first_qset + j, -1,
998 -1, i);
999 if (ret)
1000 err = ret;
1001 }
14ab9892 1002 }
8c263761
DLR		 1003
1004 return err;
14ab9892
DLR		 1005}
1006
34336ec0
BH		 1007#define FW_VERSION __stringify(FW_VERSION_MAJOR) "." \
1008 __stringify(FW_VERSION_MINOR) "." __stringify(FW_VERSION_MICRO)
1009#define FW_FNAME "cxgb3/t3fw-" FW_VERSION ".bin"
1010#define TPSRAM_VERSION __stringify(TP_VERSION_MAJOR) "." \
1011 __stringify(TP_VERSION_MINOR) "." __stringify(TP_VERSION_MICRO)
1012#define TPSRAM_NAME "cxgb3/t3%c_psram-" TPSRAM_VERSION ".bin"
2e8c07c3
DLR		 1013#define AEL2005_OPT_EDC_NAME "cxgb3/ael2005_opt_edc.bin"
1014#define AEL2005_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"
9450526a 1015#define AEL2020_TWX_EDC_NAME "cxgb3/ael2020_twx_edc.bin"
34336ec0
BH		 1016MODULE_FIRMWARE(FW_FNAME);
1017MODULE_FIRMWARE("cxgb3/t3b_psram-" TPSRAM_VERSION ".bin");
1018MODULE_FIRMWARE("cxgb3/t3c_psram-" TPSRAM_VERSION ".bin");
1019MODULE_FIRMWARE(AEL2005_OPT_EDC_NAME);
1020MODULE_FIRMWARE(AEL2005_TWX_EDC_NAME);
1021MODULE_FIRMWARE(AEL2020_TWX_EDC_NAME);
2e8c07c3
DLR		 1022
1023static inline const char *get_edc_fw_name(int edc_idx)
1024{
1025 const char *fw_name = NULL;
1026
1027 switch (edc_idx) {
1028 case EDC_OPT_AEL2005:
1029 fw_name = AEL2005_OPT_EDC_NAME;
1030 break;
1031 case EDC_TWX_AEL2005:
1032 fw_name = AEL2005_TWX_EDC_NAME;
1033 break;
1034 case EDC_TWX_AEL2020:
1035 fw_name = AEL2020_TWX_EDC_NAME;
1036 break;
1037 }
1038 return fw_name;
1039}
1040
1041int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size)
1042{
1043 struct adapter *adapter = phy->adapter;
1044 const struct firmware *fw;
1045 char buf[64];
1046 u32 csum;
1047 const __be32 *p;
1048 u16 *cache = phy->phy_cache;
1049 int i, ret;
1050
1051 snprintf(buf, sizeof(buf), get_edc_fw_name(edc_idx));
1052
1053 ret = request_firmware(&fw, buf, &adapter->pdev->dev);
1054 if (ret < 0) {
1055 dev_err(&adapter->pdev->dev,
1056 "could not upgrade firmware: unable to load %s\n",
1057 buf);
1058 return ret;
1059 }
1060
1061 /* check size, take checksum in account */
1062 if (fw->size > size + 4) {
1063 CH_ERR(adapter, "firmware image too large %u, expected %d\n",
1064 (unsigned int)fw->size, size + 4);
1065 ret = -EINVAL;
1066 }
1067
1068 /* compute checksum */
1069 p = (const __be32 *)fw->data;
1070 for (csum = 0, i = 0; i < fw->size / sizeof(csum); i++)
1071 csum += ntohl(p[i]);
1072
1073 if (csum != 0xffffffff) {
1074 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1075 csum);
1076 ret = -EINVAL;
1077 }
1078
1079 for (i = 0; i < size / 4 ; i++) {
1080 *cache++ = (be32_to_cpu(p[i]) & 0xffff0000) >> 16;
1081 *cache++ = be32_to_cpu(p[i]) & 0xffff;
1082 }
1083
1084 release_firmware(fw);
1085
1086 return ret;
1087}
2e283962
DLR		 1088
1089static int upgrade_fw(struct adapter *adap)
1090{
1091 int ret;
2e283962
DLR		 1092 const struct firmware *fw;
1093 struct device *dev = &adap->pdev->dev;
1094
34336ec0 1095 ret = request_firmware(&fw, FW_FNAME, dev);
2e283962
DLR		 1096 if (ret < 0) {
1097 dev_err(dev, "could not upgrade firmware: unable to load %s\n",
34336ec0 1098 FW_FNAME);
2e283962
DLR		 1099 return ret;
1100 }
1101 ret = t3_load_fw(adap, fw->data, fw->size);
1102 release_firmware(fw);
47330077
DLR		 1103
1104 if (ret == 0)
1105 dev_info(dev, "successful upgrade to firmware %d.%d.%d\n",
1106 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
1107 else
1108 dev_err(dev, "failed to upgrade to firmware %d.%d.%d\n",
1109 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
2eab17ab 1110
47330077
DLR		 1111 return ret;
1112}
1113
1114static inline char t3rev2char(struct adapter *adapter)
1115{
1116 char rev = 0;
1117
1118 switch(adapter->params.rev) {
1119 case T3_REV_B:
1120 case T3_REV_B2:
1121 rev = 'b';
1122 break;
1aafee26
DLR		 1123 case T3_REV_C:
1124 rev = 'c';
1125 break;
47330077
DLR		 1126 }
1127 return rev;
1128}
1129
9265fabf 1130static int update_tpsram(struct adapter *adap)
47330077
DLR		 1131{
1132 const struct firmware *tpsram;
1133 char buf[64];
1134 struct device *dev = &adap->pdev->dev;
1135 int ret;
1136 char rev;
2eab17ab 1137
47330077
DLR		 1138 rev = t3rev2char(adap);
1139 if (!rev)
1140 return 0;
1141
34336ec0 1142 snprintf(buf, sizeof(buf), TPSRAM_NAME, rev);
47330077
DLR		 1143
1144 ret = request_firmware(&tpsram, buf, dev);
1145 if (ret < 0) {
1146 dev_err(dev, "could not load TP SRAM: unable to load %s\n",
1147 buf);
1148 return ret;
1149 }
2eab17ab 1150
47330077
DLR		 1151 ret = t3_check_tpsram(adap, tpsram->data, tpsram->size);
1152 if (ret)
2eab17ab 1153 goto release_tpsram;
47330077
DLR		 1154
1155 ret = t3_set_proto_sram(adap, tpsram->data);
1156 if (ret == 0)
1157 dev_info(dev,
1158 "successful update of protocol engine "
1159 "to %d.%d.%d\n",
1160 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1161 else
1162 dev_err(dev, "failed to update of protocol engine %d.%d.%d\n",
1163 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1164 if (ret)
1165 dev_err(dev, "loading protocol SRAM failed\n");
1166
1167release_tpsram:
1168 release_firmware(tpsram);
2eab17ab 1169
2e283962
DLR		 1170 return ret;
1171}
1172
4d22de3e
DLR		 1173/**
1174 * cxgb_up - enable the adapter
1175 * @adapter: adapter being enabled
1176 *
1177 * Called when the first port is enabled, this function performs the
1178 * actions necessary to make an adapter operational, such as completing
1179 * the initialization of HW modules, and enabling interrupts.
1180 *
1181 * Must be called with the rtnl lock held.
1182 */
1183static int cxgb_up(struct adapter *adap)
1184{
c54f5c24 1185 int err;
4d22de3e
DLR		 1186
1187 if (!(adap->flags & FULL_INIT_DONE)) {
8207befa 1188 err = t3_check_fw_version(adap);
a5a3b460 1189 if (err == -EINVAL) {
2e283962 1190 err = upgrade_fw(adap);
8207befa
DLR		 1191 CH_WARN(adap, "FW upgrade to %d.%d.%d %s\n",
1192 FW_VERSION_MAJOR, FW_VERSION_MINOR,
1193 FW_VERSION_MICRO, err ? "failed" : "succeeded");
a5a3b460 1194 }
4d22de3e 1195
8207befa 1196 err = t3_check_tpsram_version(adap);
47330077
DLR		 1197 if (err == -EINVAL) {
1198 err = update_tpsram(adap);
8207befa
DLR		 1199 CH_WARN(adap, "TP upgrade to %d.%d.%d %s\n",
1200 TP_VERSION_MAJOR, TP_VERSION_MINOR,
1201 TP_VERSION_MICRO, err ? "failed" : "succeeded");
47330077
DLR		 1202 }
1203
20d3fc11
DLR		 1204 /*
1205 * Clear interrupts now to catch errors if t3_init_hw fails.
1206 * We clear them again later as initialization may trigger
1207 * conditions that can interrupt.
1208 */
1209 t3_intr_clear(adap);
1210
4d22de3e
DLR		 1211 err = t3_init_hw(adap, 0);
1212 if (err)
1213 goto out;
1214
b881955b 1215 t3_set_reg_field(adap, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT);
6cdbd77e 1216 t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
bea3348e 1217
4d22de3e
DLR		 1218 err = setup_sge_qsets(adap);
1219 if (err)
1220 goto out;
1221
1222 setup_rss(adap);
48c4b6db
DLR		 1223 if (!(adap->flags & NAPI_INIT))
1224 init_napi(adap);
31563789
DLR		 1225
1226 t3_start_sge_timers(adap);
4d22de3e
DLR		 1227 adap->flags |= FULL_INIT_DONE;
1228 }
1229
1230 t3_intr_clear(adap);
1231
1232 if (adap->flags & USING_MSIX) {
1233 name_msix_vecs(adap);
1234 err = request_irq(adap->msix_info[0].vec,
1235 t3_async_intr_handler, 0,
1236 adap->msix_info[0].desc, adap);
1237 if (err)
1238 goto irq_err;
1239
42256f57
DLR		 1240 err = request_msix_data_irqs(adap);
1241 if (err) {
4d22de3e
DLR		 1242 free_irq(adap->msix_info[0].vec, adap);
1243 goto irq_err;
1244 }
1245 } else if ((err = request_irq(adap->pdev->irq,
1246 t3_intr_handler(adap,
1247 adap->sge.qs[0].rspq.
1248 polling),
2db6346f
TG		 1249 (adap->flags & USING_MSI) ?
1250 0 : IRQF_SHARED,
4d22de3e
DLR		 1251 adap->name, adap)))
1252 goto irq_err;
1253
bea3348e 1254 enable_all_napi(adap);
4d22de3e
DLR		 1255 t3_sge_start(adap);
1256 t3_intr_enable(adap);
14ab9892 1257
b881955b
DLR		 1258 if (adap->params.rev >= T3_REV_C && !(adap->flags & TP_PARITY_INIT) &&
1259 is_offload(adap) && init_tp_parity(adap) == 0)
1260 adap->flags |= TP_PARITY_INIT;
1261
1262 if (adap->flags & TP_PARITY_INIT) {
1263 t3_write_reg(adap, A_TP_INT_CAUSE,
1264 F_CMCACHEPERR | F_ARPLUTPERR);
1265 t3_write_reg(adap, A_TP_INT_ENABLE, 0x7fbfffff);
1266 }
1267
8c263761 1268 if (!(adap->flags & QUEUES_BOUND)) {
18edc84c
DLR		 1269 int ret = bind_qsets(adap);
1270
1271 if (ret < 0) {
1272 CH_ERR(adap, "failed to bind qsets, err %d\n", ret);
8c263761
DLR		 1273 t3_intr_disable(adap);
1274 free_irq_resources(adap);
18edc84c 1275 err = ret;
8c263761
DLR		 1276 goto out;
1277 }
1278 adap->flags |= QUEUES_BOUND;
1279 }
14ab9892 1280
4d22de3e
DLR		 1281out:
1282 return err;
1283irq_err:
1284 CH_ERR(adap, "request_irq failed, err %d\n", err);
1285 goto out;
1286}
1287
1288/*
1289 * Release resources when all the ports and offloading have been stopped.
1290 */
55bc3228 1291static void cxgb_down(struct adapter *adapter, int on_wq)
4d22de3e
DLR		 1292{
1293 t3_sge_stop(adapter);
1294 spin_lock_irq(&adapter->work_lock); /* sync with PHY intr task */
1295 t3_intr_disable(adapter);
1296 spin_unlock_irq(&adapter->work_lock);
1297
8c263761 1298 free_irq_resources(adapter);
4d22de3e 1299 quiesce_rx(adapter);
a6f018e3 1300 t3_sge_stop(adapter);
55bc3228
CL		 1301 if (!on_wq)
1302 flush_workqueue(cxgb3_wq);/* wait for external IRQ handler */
4d22de3e
DLR		 1303}
1304
1305static void schedule_chk_task(struct adapter *adap)
1306{
1307 unsigned int timeo;
1308
1309 timeo = adap->params.linkpoll_period ?
1310 (HZ * adap->params.linkpoll_period) / 10 :
1311 adap->params.stats_update_period * HZ;
1312 if (timeo)
1313 queue_delayed_work(cxgb3_wq, &adap->adap_check_task, timeo);
1314}
1315
1316static int offload_open(struct net_device *dev)
1317{
5fbf816f
DLR		 1318 struct port_info *pi = netdev_priv(dev);
1319 struct adapter *adapter = pi->adapter;
1320 struct t3cdev *tdev = dev2t3cdev(dev);
4d22de3e 1321 int adap_up = adapter->open_device_map & PORT_MASK;
c54f5c24 1322 int err;
4d22de3e
DLR		 1323
1324 if (test_and_set_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1325 return 0;
1326
1327 if (!adap_up && (err = cxgb_up(adapter)) < 0)
48c4b6db 1328 goto out;
4d22de3e
DLR		 1329
1330 t3_tp_set_offload_mode(adapter, 1);
1331 tdev->lldev = adapter->port[0];
1332 err = cxgb3_offload_activate(adapter);
1333 if (err)
1334 goto out;
1335
1336 init_port_mtus(adapter);
1337 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd,
1338 adapter->params.b_wnd,
1339 adapter->params.rev == 0 ?
1340 adapter->port[0]->mtu : 0xffff);
1341 init_smt(adapter);
1342
d96a51f6
DN		 1343 if (sysfs_create_group(&tdev->lldev->dev.kobj, &offload_attr_group))
1344 dev_dbg(&dev->dev, "cannot create sysfs group\n");
4d22de3e
DLR		 1345
1346 /* Call back all registered clients */
1347 cxgb3_add_clients(tdev);
1348
1349out:
1350 /* restore them in case the offload module has changed them */
1351 if (err) {
1352 t3_tp_set_offload_mode(adapter, 0);
1353 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1354 cxgb3_set_dummy_ops(tdev);
1355 }
1356 return err;
1357}
1358
1359static int offload_close(struct t3cdev *tdev)
1360{
1361 struct adapter *adapter = tdev2adap(tdev);
23f333a2 1362 struct t3c_data *td = T3C_DATA(tdev);
4d22de3e
DLR		 1363
1364 if (!test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1365 return 0;
1366
1367 /* Call back all registered clients */
1368 cxgb3_remove_clients(tdev);
1369
0ee8d33c 1370 sysfs_remove_group(&tdev->lldev->dev.kobj, &offload_attr_group);
4d22de3e 1371
c80b0c28 1372 /* Flush work scheduled while releasing TIDs */
23f333a2 1373 flush_work_sync(&td->tid_release_task);
c80b0c28 1374
4d22de3e
DLR		 1375 tdev->lldev = NULL;
1376 cxgb3_set_dummy_ops(tdev);
1377 t3_tp_set_offload_mode(adapter, 0);
1378 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1379
1380 if (!adapter->open_device_map)
55bc3228 1381 cxgb_down(adapter, 0);
4d22de3e
DLR		 1382
1383 cxgb3_offload_deactivate(adapter);
1384 return 0;
1385}
1386
1387static int cxgb_open(struct net_device *dev)
1388{
4d22de3e 1389 struct port_info *pi = netdev_priv(dev);
5fbf816f 1390 struct adapter *adapter = pi->adapter;
4d22de3e 1391 int other_ports = adapter->open_device_map & PORT_MASK;
5fbf816f 1392 int err;
4d22de3e 1393
48c4b6db 1394 if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0)
4d22de3e
DLR		 1395 return err;
1396
1397 set_bit(pi->port_id, &adapter->open_device_map);
8ac3ba68 1398 if (is_offload(adapter) && !ofld_disable) {
4d22de3e
DLR		 1399 err = offload_open(dev);
1400 if (err)
1401 printk(KERN_WARNING
1402 "Could not initialize offload capabilities\n");
1403 }
1404
19221e75
BH		 1405 netif_set_real_num_tx_queues(dev, pi->nqsets);
1406 err = netif_set_real_num_rx_queues(dev, pi->nqsets);
1407 if (err)
1408 return err;
4d22de3e
DLR		 1409 link_start(dev);
1410 t3_port_intr_enable(adapter, pi->port_id);
82ad3329 1411 netif_tx_start_all_queues(dev);
4d22de3e
DLR		 1412 if (!other_ports)
1413 schedule_chk_task(adapter);
1414
fa0d4c11 1415 cxgb3_event_notify(&adapter->tdev, OFFLOAD_PORT_UP, pi->port_id);
4d22de3e
DLR		 1416 return 0;
1417}
1418
55bc3228 1419static int __cxgb_close(struct net_device *dev, int on_wq)
4d22de3e 1420{
5fbf816f
DLR		 1421 struct port_info *pi = netdev_priv(dev);
1422 struct adapter *adapter = pi->adapter;
4d22de3e 1423
e8d19370
DLR		 1424
1425 if (!adapter->open_device_map)
1426 return 0;
1427
bf792094
DLR		 1428 /* Stop link fault interrupts */
1429 t3_xgm_intr_disable(adapter, pi->port_id);
1430 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
1431
5fbf816f 1432 t3_port_intr_disable(adapter, pi->port_id);
82ad3329 1433 netif_tx_stop_all_queues(dev);
5fbf816f 1434 pi->phy.ops->power_down(&pi->phy, 1);
4d22de3e 1435 netif_carrier_off(dev);
5fbf816f 1436 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX);
4d22de3e 1437
20d3fc11 1438 spin_lock_irq(&adapter->work_lock); /* sync with update task */
5fbf816f 1439 clear_bit(pi->port_id, &adapter->open_device_map);
20d3fc11 1440 spin_unlock_irq(&adapter->work_lock);
4d22de3e
DLR		 1441
1442 if (!(adapter->open_device_map & PORT_MASK))
c80b0c28 1443 cancel_delayed_work_sync(&adapter->adap_check_task);
4d22de3e
DLR		 1444
1445 if (!adapter->open_device_map)
55bc3228 1446 cxgb_down(adapter, on_wq);
4d22de3e 1447
fa0d4c11 1448 cxgb3_event_notify(&adapter->tdev, OFFLOAD_PORT_DOWN, pi->port_id);
4d22de3e
DLR		 1449 return 0;
1450}
1451
55bc3228
CL		 1452static int cxgb_close(struct net_device *dev)
1453{
1454 return __cxgb_close(dev, 0);
1455}
1456
4d22de3e
DLR		 1457static struct net_device_stats *cxgb_get_stats(struct net_device *dev)
1458{
5fbf816f
DLR		 1459 struct port_info *pi = netdev_priv(dev);
1460 struct adapter *adapter = pi->adapter;
1461 struct net_device_stats *ns = &pi->netstats;
4d22de3e
DLR		 1462 const struct mac_stats *pstats;
1463
1464 spin_lock(&adapter->stats_lock);
5fbf816f 1465 pstats = t3_mac_update_stats(&pi->mac);
4d22de3e
DLR		 1466 spin_unlock(&adapter->stats_lock);
1467
1468 ns->tx_bytes = pstats->tx_octets;
1469 ns->tx_packets = pstats->tx_frames;
1470 ns->rx_bytes = pstats->rx_octets;
1471 ns->rx_packets = pstats->rx_frames;
1472 ns->multicast = pstats->rx_mcast_frames;
1473
1474 ns->tx_errors = pstats->tx_underrun;
1475 ns->rx_errors = pstats->rx_symbol_errs + pstats->rx_fcs_errs +
1476 pstats->rx_too_long + pstats->rx_jabber + pstats->rx_short +
1477 pstats->rx_fifo_ovfl;
1478
1479 /* detailed rx_errors */
1480 ns->rx_length_errors = pstats->rx_jabber + pstats->rx_too_long;
1481 ns->rx_over_errors = 0;
1482 ns->rx_crc_errors = pstats->rx_fcs_errs;
1483 ns->rx_frame_errors = pstats->rx_symbol_errs;
1484 ns->rx_fifo_errors = pstats->rx_fifo_ovfl;
1485 ns->rx_missed_errors = pstats->rx_cong_drops;
1486
1487 /* detailed tx_errors */
1488 ns->tx_aborted_errors = 0;
1489 ns->tx_carrier_errors = 0;
1490 ns->tx_fifo_errors = pstats->tx_underrun;
1491 ns->tx_heartbeat_errors = 0;
1492 ns->tx_window_errors = 0;
1493 return ns;
1494}
1495
1496static u32 get_msglevel(struct net_device *dev)
1497{
5fbf816f
DLR		 1498 struct port_info *pi = netdev_priv(dev);
1499 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1500
1501 return adapter->msg_enable;
1502}
1503
1504static void set_msglevel(struct net_device *dev, u32 val)
1505{
5fbf816f
DLR		 1506 struct port_info *pi = netdev_priv(dev);
1507 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1508
1509 adapter->msg_enable = val;
1510}
1511
1512static char stats_strings[][ETH_GSTRING_LEN] = {
1513 "TxOctetsOK ",
1514 "TxFramesOK ",
1515 "TxMulticastFramesOK",
1516 "TxBroadcastFramesOK",
1517 "TxPauseFrames ",
1518 "TxUnderrun ",
1519 "TxExtUnderrun ",
1520
1521 "TxFrames64 ",
1522 "TxFrames65To127 ",
1523 "TxFrames128To255 ",
1524 "TxFrames256To511 ",
1525 "TxFrames512To1023 ",
1526 "TxFrames1024To1518 ",
1527 "TxFrames1519ToMax ",
1528
1529 "RxOctetsOK ",
1530 "RxFramesOK ",
1531 "RxMulticastFramesOK",
1532 "RxBroadcastFramesOK",
1533 "RxPauseFrames ",
1534 "RxFCSErrors ",
1535 "RxSymbolErrors ",
1536 "RxShortErrors ",
1537 "RxJabberErrors ",
1538 "RxLengthErrors ",
1539 "RxFIFOoverflow ",
1540
1541 "RxFrames64 ",
1542 "RxFrames65To127 ",
1543 "RxFrames128To255 ",
1544 "RxFrames256To511 ",
1545 "RxFrames512To1023 ",
1546 "RxFrames1024To1518 ",
1547 "RxFrames1519ToMax ",
1548
1549 "PhyFIFOErrors ",
1550 "TSO ",
1551 "VLANextractions ",
1552 "VLANinsertions ",
1553 "TxCsumOffload ",
1554 "RxCsumGood ",
b47385bd
DLR		 1555 "LroAggregated ",
1556 "LroFlushed ",
1557 "LroNoDesc ",
fc90664e
DLR		 1558 "RxDrops ",
1559
1560 "CheckTXEnToggled ",
1561 "CheckResets ",
1562
bf792094 1563 "LinkFaults ",
4d22de3e
DLR		 1564};
1565
b9f2c044 1566static int get_sset_count(struct net_device *dev, int sset)
4d22de3e 1567{
b9f2c044
JG		 1568 switch (sset) {
1569 case ETH_SS_STATS:
1570 return ARRAY_SIZE(stats_strings);
1571 default:
1572 return -EOPNOTSUPP;
1573 }
4d22de3e
DLR		 1574}
1575
1576#define T3_REGMAP_SIZE (3 * 1024)
1577
1578static int get_regs_len(struct net_device *dev)
1579{
1580 return T3_REGMAP_SIZE;
1581}
1582
1583static int get_eeprom_len(struct net_device *dev)
1584{
1585 return EEPROMSIZE;
1586}
1587
1588static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1589{
5fbf816f
DLR		 1590 struct port_info *pi = netdev_priv(dev);
1591 struct adapter *adapter = pi->adapter;
4d22de3e 1592 u32 fw_vers = 0;
47330077 1593 u32 tp_vers = 0;
4d22de3e 1594
cf3760da 1595 spin_lock(&adapter->stats_lock);
4d22de3e 1596 t3_get_fw_version(adapter, &fw_vers);
47330077 1597 t3_get_tp_version(adapter, &tp_vers);
cf3760da 1598 spin_unlock(&adapter->stats_lock);
4d22de3e
DLR		 1599
1600 strcpy(info->driver, DRV_NAME);
1601 strcpy(info->version, DRV_VERSION);
1602 strcpy(info->bus_info, pci_name(adapter->pdev));
1603 if (!fw_vers)
1604 strcpy(info->fw_version, "N/A");
4aac3899 1605 else {
4d22de3e 1606 snprintf(info->fw_version, sizeof(info->fw_version),
47330077 1607 "%s %u.%u.%u TP %u.%u.%u",
4aac3899
DLR		 1608 G_FW_VERSION_TYPE(fw_vers) ? "T" : "N",
1609 G_FW_VERSION_MAJOR(fw_vers),
1610 G_FW_VERSION_MINOR(fw_vers),
47330077
DLR		 1611 G_FW_VERSION_MICRO(fw_vers),
1612 G_TP_VERSION_MAJOR(tp_vers),
1613 G_TP_VERSION_MINOR(tp_vers),
1614 G_TP_VERSION_MICRO(tp_vers));
4aac3899 1615 }
4d22de3e
DLR		 1616}
1617
1618static void get_strings(struct net_device *dev, u32 stringset, u8 * data)
1619{
1620 if (stringset == ETH_SS_STATS)
1621 memcpy(data, stats_strings, sizeof(stats_strings));
1622}
1623
1624static unsigned long collect_sge_port_stats(struct adapter *adapter,
1625 struct port_info *p, int idx)
1626{
1627 int i;
1628 unsigned long tot = 0;
1629
8c263761
DLR		 1630 for (i = p->first_qset; i < p->first_qset + p->nqsets; ++i)
1631 tot += adapter->sge.qs[i].port_stats[idx];
4d22de3e
DLR		 1632 return tot;
1633}
1634
1635static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1636 u64 *data)
1637{
4d22de3e 1638 struct port_info *pi = netdev_priv(dev);
5fbf816f 1639 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1640 const struct mac_stats *s;
1641
1642 spin_lock(&adapter->stats_lock);
1643 s = t3_mac_update_stats(&pi->mac);
1644 spin_unlock(&adapter->stats_lock);
1645
1646 *data++ = s->tx_octets;
1647 *data++ = s->tx_frames;
1648 *data++ = s->tx_mcast_frames;
1649 *data++ = s->tx_bcast_frames;
1650 *data++ = s->tx_pause;
1651 *data++ = s->tx_underrun;
1652 *data++ = s->tx_fifo_urun;
1653
1654 *data++ = s->tx_frames_64;
1655 *data++ = s->tx_frames_65_127;
1656 *data++ = s->tx_frames_128_255;
1657 *data++ = s->tx_frames_256_511;
1658 *data++ = s->tx_frames_512_1023;
1659 *data++ = s->tx_frames_1024_1518;
1660 *data++ = s->tx_frames_1519_max;
1661
1662 *data++ = s->rx_octets;
1663 *data++ = s->rx_frames;
1664 *data++ = s->rx_mcast_frames;
1665 *data++ = s->rx_bcast_frames;
1666 *data++ = s->rx_pause;
1667 *data++ = s->rx_fcs_errs;
1668 *data++ = s->rx_symbol_errs;
1669 *data++ = s->rx_short;
1670 *data++ = s->rx_jabber;
1671 *data++ = s->rx_too_long;
1672 *data++ = s->rx_fifo_ovfl;
1673
1674 *data++ = s->rx_frames_64;
1675 *data++ = s->rx_frames_65_127;
1676 *data++ = s->rx_frames_128_255;
1677 *data++ = s->rx_frames_256_511;
1678 *data++ = s->rx_frames_512_1023;
1679 *data++ = s->rx_frames_1024_1518;
1680 *data++ = s->rx_frames_1519_max;
1681
1682 *data++ = pi->phy.fifo_errors;
1683
1684 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TSO);
1685 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANEX);
1686 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANINS);
1687 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM);
1688 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD);
7be2df45
HX		 1689 *data++ = 0;
1690 *data++ = 0;
1691 *data++ = 0;
4d22de3e 1692 *data++ = s->rx_cong_drops;
fc90664e
DLR		 1693
1694 *data++ = s->num_toggled;
1695 *data++ = s->num_resets;
bf792094
DLR		 1696
1697 *data++ = s->link_faults;
4d22de3e
DLR		 1698}
1699
1700static inline void reg_block_dump(struct adapter *ap, void *buf,
1701 unsigned int start, unsigned int end)
1702{
1703 u32 *p = buf + start;
1704
1705 for (; start <= end; start += sizeof(u32))
1706 *p++ = t3_read_reg(ap, start);
1707}
1708
1709static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1710 void *buf)
1711{
5fbf816f
DLR		 1712 struct port_info *pi = netdev_priv(dev);
1713 struct adapter *ap = pi->adapter;
4d22de3e
DLR		 1714
1715 /*
1716 * Version scheme:
1717 * bits 0..9: chip version
1718 * bits 10..15: chip revision
1719 * bit 31: set for PCIe cards
1720 */
1721 regs->version = 3 | (ap->params.rev << 10) | (is_pcie(ap) << 31);
1722
1723 /*
1724 * We skip the MAC statistics registers because they are clear-on-read.
1725 * Also reading multi-register stats would need to synchronize with the
1726 * periodic mac stats accumulation. Hard to justify the complexity.
1727 */
1728 memset(buf, 0, T3_REGMAP_SIZE);
1729 reg_block_dump(ap, buf, 0, A_SG_RSPQ_CREDIT_RETURN);
1730 reg_block_dump(ap, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT);
1731 reg_block_dump(ap, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE);
1732 reg_block_dump(ap, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA);
1733 reg_block_dump(ap, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3);
1734 reg_block_dump(ap, buf, A_XGM_SERDES_STATUS0,
1735 XGM_REG(A_XGM_SERDES_STAT3, 1));
1736 reg_block_dump(ap, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1),
1737 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1));
1738}
1739
1740static int restart_autoneg(struct net_device *dev)
1741{
1742 struct port_info *p = netdev_priv(dev);
1743
1744 if (!netif_running(dev))
1745 return -EAGAIN;
1746 if (p->link_config.autoneg != AUTONEG_ENABLE)
1747 return -EINVAL;
1748 p->phy.ops->autoneg_restart(&p->phy);
1749 return 0;
1750}
1751
12fcf941 1752static int set_phys_id(struct net_device *dev,
1753 enum ethtool_phys_id_state state)
4d22de3e 1754{
5fbf816f
DLR		 1755 struct port_info *pi = netdev_priv(dev);
1756 struct adapter *adapter = pi->adapter;
4d22de3e 1757
12fcf941 1758 switch (state) {
1759 case ETHTOOL_ID_ACTIVE:
fce55922 1760 return 1; /* cycle on/off once per second */
12fcf941 1761
1762 case ETHTOOL_ID_OFF:
1763 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL, 0);
1764 break;
4d22de3e 1765
12fcf941 1766 case ETHTOOL_ID_ON:
1767 case ETHTOOL_ID_INACTIVE:
4d22de3e 1768 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
4d22de3e 1769 F_GPIO0_OUT_VAL);
12fcf941 1770 }
1771
4d22de3e
DLR		 1772 return 0;
1773}
1774
1775static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1776{
1777 struct port_info *p = netdev_priv(dev);
1778
1779 cmd->supported = p->link_config.supported;
1780 cmd->advertising = p->link_config.advertising;
1781
1782 if (netif_carrier_ok(dev)) {
1783 cmd->speed = p->link_config.speed;
1784 cmd->duplex = p->link_config.duplex;
1785 } else {
1786 cmd->speed = -1;
1787 cmd->duplex = -1;
1788 }
1789
1790 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
0f07c4ee 1791 cmd->phy_address = p->phy.mdio.prtad;
4d22de3e
DLR		 1792 cmd->transceiver = XCVR_EXTERNAL;
1793 cmd->autoneg = p->link_config.autoneg;
1794 cmd->maxtxpkt = 0;
1795 cmd->maxrxpkt = 0;
1796 return 0;
1797}
1798
1799static int speed_duplex_to_caps(int speed, int duplex)
1800{
1801 int cap = 0;
1802
1803 switch (speed) {
1804 case SPEED_10:
1805 if (duplex == DUPLEX_FULL)
1806 cap = SUPPORTED_10baseT_Full;
1807 else
1808 cap = SUPPORTED_10baseT_Half;
1809 break;
1810 case SPEED_100:
1811 if (duplex == DUPLEX_FULL)
1812 cap = SUPPORTED_100baseT_Full;
1813 else
1814 cap = SUPPORTED_100baseT_Half;
1815 break;
1816 case SPEED_1000:
1817 if (duplex == DUPLEX_FULL)
1818 cap = SUPPORTED_1000baseT_Full;
1819 else
1820 cap = SUPPORTED_1000baseT_Half;
1821 break;
1822 case SPEED_10000:
1823 if (duplex == DUPLEX_FULL)
1824 cap = SUPPORTED_10000baseT_Full;
1825 }
1826 return cap;
1827}
1828
1829#define ADVERTISED_MASK (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1830 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1831 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | \
1832 ADVERTISED_10000baseT_Full)
1833
1834static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1835{
1836 struct port_info *p = netdev_priv(dev);
1837 struct link_config *lc = &p->link_config;
1838
9b1e3656
DLR		 1839 if (!(lc->supported & SUPPORTED_Autoneg)) {
1840 /*
1841 * PHY offers a single speed/duplex. See if that's what's
1842 * being requested.
1843 */
1844 if (cmd->autoneg == AUTONEG_DISABLE) {
97915b5b 1845 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
9b1e3656
DLR		 1846 if (lc->supported & cap)
1847 return 0;
1848 }
1849 return -EINVAL;
1850 }
4d22de3e
DLR		 1851
1852 if (cmd->autoneg == AUTONEG_DISABLE) {
1853 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
1854
1855 if (!(lc->supported & cap) || cmd->speed == SPEED_1000)
1856 return -EINVAL;
1857 lc->requested_speed = cmd->speed;
1858 lc->requested_duplex = cmd->duplex;
1859 lc->advertising = 0;
1860 } else {
1861 cmd->advertising &= ADVERTISED_MASK;
1862 cmd->advertising &= lc->supported;
1863 if (!cmd->advertising)
1864 return -EINVAL;
1865 lc->requested_speed = SPEED_INVALID;
1866 lc->requested_duplex = DUPLEX_INVALID;
1867 lc->advertising = cmd->advertising | ADVERTISED_Autoneg;
1868 }
1869 lc->autoneg = cmd->autoneg;
1870 if (netif_running(dev))
1871 t3_link_start(&p->phy, &p->mac, lc);
1872 return 0;
1873}
1874
1875static void get_pauseparam(struct net_device *dev,
1876 struct ethtool_pauseparam *epause)
1877{
1878 struct port_info *p = netdev_priv(dev);
1879
1880 epause->autoneg = (p->link_config.requested_fc & PAUSE_AUTONEG) != 0;
1881 epause->rx_pause = (p->link_config.fc & PAUSE_RX) != 0;
1882 epause->tx_pause = (p->link_config.fc & PAUSE_TX) != 0;
1883}
1884
1885static int set_pauseparam(struct net_device *dev,
1886 struct ethtool_pauseparam *epause)
1887{
1888 struct port_info *p = netdev_priv(dev);
1889 struct link_config *lc = &p->link_config;
1890
1891 if (epause->autoneg == AUTONEG_DISABLE)
1892 lc->requested_fc = 0;
1893 else if (lc->supported & SUPPORTED_Autoneg)
1894 lc->requested_fc = PAUSE_AUTONEG;
1895 else
1896 return -EINVAL;
1897
1898 if (epause->rx_pause)
1899 lc->requested_fc |= PAUSE_RX;
1900 if (epause->tx_pause)
1901 lc->requested_fc |= PAUSE_TX;
1902 if (lc->autoneg == AUTONEG_ENABLE) {
1903 if (netif_running(dev))
1904 t3_link_start(&p->phy, &p->mac, lc);
1905 } else {
1906 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1907 if (netif_running(dev))
1908 t3_mac_set_speed_duplex_fc(&p->mac, -1, -1, lc->fc);
1909 }
1910 return 0;
1911}
1912
1913static u32 get_rx_csum(struct net_device *dev)
1914{
1915 struct port_info *p = netdev_priv(dev);
1916
47fd23fe 1917 return p->rx_offload & T3_RX_CSUM;
4d22de3e
DLR		 1918}
1919
1920static int set_rx_csum(struct net_device *dev, u32 data)
1921{
1922 struct port_info *p = netdev_priv(dev);
1923
47fd23fe
RD		 1924 if (data) {
1925 p->rx_offload |= T3_RX_CSUM;
1926 } else {
b47385bd
DLR		 1927 int i;
1928
47fd23fe 1929 p->rx_offload &= ~(T3_RX_CSUM | T3_LRO);
04ecb072
DLR		 1930 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++)
1931 set_qset_lro(dev, i, 0);
b47385bd 1932 }
4d22de3e
DLR		 1933 return 0;
1934}
1935
1936static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1937{
5fbf816f
DLR		 1938 struct port_info *pi = netdev_priv(dev);
1939 struct adapter *adapter = pi->adapter;
05b97b30 1940 const struct qset_params *q = &adapter->params.sge.qset[pi->first_qset];
4d22de3e
DLR		 1941
1942 e->rx_max_pending = MAX_RX_BUFFERS;
1943 e->rx_mini_max_pending = 0;
1944 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS;
1945 e->tx_max_pending = MAX_TXQ_ENTRIES;
1946
05b97b30
DLR		 1947 e->rx_pending = q->fl_size;
1948 e->rx_mini_pending = q->rspq_size;
1949 e->rx_jumbo_pending = q->jumbo_size;
1950 e->tx_pending = q->txq_size[0];
4d22de3e
DLR		 1951}
1952
1953static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1954{
5fbf816f
DLR		 1955 struct port_info *pi = netdev_priv(dev);
1956 struct adapter *adapter = pi->adapter;
05b97b30 1957 struct qset_params *q;
5fbf816f 1958 int i;
4d22de3e
DLR		 1959
1960 if (e->rx_pending > MAX_RX_BUFFERS ||
1961 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS ||
1962 e->tx_pending > MAX_TXQ_ENTRIES ||
1963 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1964 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1965 e->rx_pending < MIN_FL_ENTRIES ||
1966 e->rx_jumbo_pending < MIN_FL_ENTRIES ||
1967 e->tx_pending < adapter->params.nports * MIN_TXQ_ENTRIES)
1968 return -EINVAL;
1969
1970 if (adapter->flags & FULL_INIT_DONE)
1971 return -EBUSY;
1972
05b97b30
DLR		 1973 q = &adapter->params.sge.qset[pi->first_qset];
1974 for (i = 0; i < pi->nqsets; ++i, ++q) {
4d22de3e
DLR		 1975 q->rspq_size = e->rx_mini_pending;
1976 q->fl_size = e->rx_pending;
1977 q->jumbo_size = e->rx_jumbo_pending;
1978 q->txq_size[0] = e->tx_pending;
1979 q->txq_size[1] = e->tx_pending;
1980 q->txq_size[2] = e->tx_pending;
1981 }
1982 return 0;
1983}
1984
1985static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1986{
5fbf816f
DLR		 1987 struct port_info *pi = netdev_priv(dev);
1988 struct adapter *adapter = pi->adapter;
c211c969
AB		 1989 struct qset_params *qsp;
1990 struct sge_qset *qs;
1991 int i;
4d22de3e
DLR		 1992
1993 if (c->rx_coalesce_usecs * 10 > M_NEWTIMER)
1994 return -EINVAL;
1995
c211c969
AB		 1996 for (i = 0; i < pi->nqsets; i++) {
1997 qsp = &adapter->params.sge.qset[i];
1998 qs = &adapter->sge.qs[i];
1999 qsp->coalesce_usecs = c->rx_coalesce_usecs;
2000 t3_update_qset_coalesce(qs, qsp);
2001 }
2002
4d22de3e
DLR		 2003 return 0;
2004}
2005
2006static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2007{
5fbf816f
DLR		 2008 struct port_info *pi = netdev_priv(dev);
2009 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2010 struct qset_params *q = adapter->params.sge.qset;
2011
2012 c->rx_coalesce_usecs = q->coalesce_usecs;
2013 return 0;
2014}
2015
2016static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2017 u8 * data)
2018{
5fbf816f
DLR		 2019 struct port_info *pi = netdev_priv(dev);
2020 struct adapter *adapter = pi->adapter;
4d22de3e 2021 int i, err = 0;
4d22de3e
DLR		 2022
2023 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2024 if (!buf)
2025 return -ENOMEM;
2026
2027 e->magic = EEPROM_MAGIC;
2028 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
05e5c116 2029 err = t3_seeprom_read(adapter, i, (__le32 *) & buf[i]);
4d22de3e
DLR		 2030
2031 if (!err)
2032 memcpy(data, buf + e->offset, e->len);
2033 kfree(buf);
2034 return err;
2035}
2036
2037static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2038 u8 * data)
2039{
5fbf816f
DLR		 2040 struct port_info *pi = netdev_priv(dev);
2041 struct adapter *adapter = pi->adapter;
05e5c116
AV		 2042 u32 aligned_offset, aligned_len;
2043 __le32 *p;
4d22de3e 2044 u8 *buf;
c54f5c24 2045 int err;
4d22de3e
DLR		 2046
2047 if (eeprom->magic != EEPROM_MAGIC)
2048 return -EINVAL;
2049
2050 aligned_offset = eeprom->offset & ~3;
2051 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2052
2053 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2054 buf = kmalloc(aligned_len, GFP_KERNEL);
2055 if (!buf)
2056 return -ENOMEM;
05e5c116 2057 err = t3_seeprom_read(adapter, aligned_offset, (__le32 *) buf);
4d22de3e
DLR		 2058 if (!err && aligned_len > 4)
2059 err = t3_seeprom_read(adapter,
2060 aligned_offset + aligned_len - 4,
05e5c116 2061 (__le32 *) & buf[aligned_len - 4]);
4d22de3e
DLR		 2062 if (err)
2063 goto out;
2064 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2065 } else
2066 buf = data;
2067
2068 err = t3_seeprom_wp(adapter, 0);
2069 if (err)
2070 goto out;
2071
05e5c116 2072 for (p = (__le32 *) buf; !err && aligned_len; aligned_len -= 4, p++) {
4d22de3e
DLR		 2073 err = t3_seeprom_write(adapter, aligned_offset, *p);
2074 aligned_offset += 4;
2075 }
2076
2077 if (!err)
2078 err = t3_seeprom_wp(adapter, 1);
2079out:
2080 if (buf != data)
2081 kfree(buf);
2082 return err;
2083}
2084
2085static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2086{
2087 wol->supported = 0;
2088 wol->wolopts = 0;
2089 memset(&wol->sopass, 0, sizeof(wol->sopass));
2090}
2091
2092static const struct ethtool_ops cxgb_ethtool_ops = {
2093 .get_settings = get_settings,
2094 .set_settings = set_settings,
2095 .get_drvinfo = get_drvinfo,
2096 .get_msglevel = get_msglevel,
2097 .set_msglevel = set_msglevel,
2098 .get_ringparam = get_sge_param,
2099 .set_ringparam = set_sge_param,
2100 .get_coalesce = get_coalesce,
2101 .set_coalesce = set_coalesce,
2102 .get_eeprom_len = get_eeprom_len,
2103 .get_eeprom = get_eeprom,
2104 .set_eeprom = set_eeprom,
2105 .get_pauseparam = get_pauseparam,
2106 .set_pauseparam = set_pauseparam,
2107 .get_rx_csum = get_rx_csum,
2108 .set_rx_csum = set_rx_csum,
4d22de3e 2109 .set_tx_csum = ethtool_op_set_tx_csum,
4d22de3e
DLR		 2110 .set_sg = ethtool_op_set_sg,
2111 .get_link = ethtool_op_get_link,
2112 .get_strings = get_strings,
12fcf941 2113 .set_phys_id = set_phys_id,
4d22de3e 2114 .nway_reset = restart_autoneg,
b9f2c044 2115 .get_sset_count = get_sset_count,
4d22de3e
DLR		 2116 .get_ethtool_stats = get_stats,
2117 .get_regs_len = get_regs_len,
2118 .get_regs = get_regs,
2119 .get_wol = get_wol,
4d22de3e 2120 .set_tso = ethtool_op_set_tso,
4d22de3e
DLR		 2121};
2122
2123static int in_range(int val, int lo, int hi)
2124{
2125 return val < 0 || (val <= hi && val >= lo);
2126}
2127
2128static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr)
2129{
5fbf816f
DLR		 2130 struct port_info *pi = netdev_priv(dev);
2131 struct adapter *adapter = pi->adapter;
4d22de3e 2132 u32 cmd;
5fbf816f 2133 int ret;
4d22de3e
DLR		 2134
2135 if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
2136 return -EFAULT;
2137
2138 switch (cmd) {
4d22de3e
DLR		 2139 case CHELSIO_SET_QSET_PARAMS:{
2140 int i;
2141 struct qset_params *q;
2142 struct ch_qset_params t;
8c263761
DLR		 2143 int q1 = pi->first_qset;
2144 int nqsets = pi->nqsets;
4d22de3e
DLR		 2145
2146 if (!capable(CAP_NET_ADMIN))
2147 return -EPERM;
2148 if (copy_from_user(&t, useraddr, sizeof(t)))
2149 return -EFAULT;
2150 if (t.qset_idx >= SGE_QSETS)
2151 return -EINVAL;
2152 if (!in_range(t.intr_lat, 0, M_NEWTIMER) ||
8e95a202
JP		 2153 !in_range(t.cong_thres, 0, 255) ||
2154 !in_range(t.txq_size[0], MIN_TXQ_ENTRIES,
2155 MAX_TXQ_ENTRIES) ||
2156 !in_range(t.txq_size[1], MIN_TXQ_ENTRIES,
2157 MAX_TXQ_ENTRIES) ||
2158 !in_range(t.txq_size[2], MIN_CTRL_TXQ_ENTRIES,
2159 MAX_CTRL_TXQ_ENTRIES) ||
2160 !in_range(t.fl_size[0], MIN_FL_ENTRIES,
2161 MAX_RX_BUFFERS) ||
2162 !in_range(t.fl_size[1], MIN_FL_ENTRIES,
2163 MAX_RX_JUMBO_BUFFERS) ||
2164 !in_range(t.rspq_size, MIN_RSPQ_ENTRIES,
2165 MAX_RSPQ_ENTRIES))
4d22de3e 2166 return -EINVAL;
8c263761
DLR		 2167
2168 if ((adapter->flags & FULL_INIT_DONE) && t.lro > 0)
2169 for_each_port(adapter, i) {
2170 pi = adap2pinfo(adapter, i);
2171 if (t.qset_idx >= pi->first_qset &&
2172 t.qset_idx < pi->first_qset + pi->nqsets &&
47fd23fe 2173 !(pi->rx_offload & T3_RX_CSUM))
8c263761
DLR		 2174 return -EINVAL;
2175 }
2176
4d22de3e
DLR		 2177 if ((adapter->flags & FULL_INIT_DONE) &&
2178 (t.rspq_size >= 0 || t.fl_size[0] >= 0 ||
2179 t.fl_size[1] >= 0 || t.txq_size[0] >= 0 ||
2180 t.txq_size[1] >= 0 || t.txq_size[2] >= 0 ||
2181 t.polling >= 0 || t.cong_thres >= 0))
2182 return -EBUSY;
2183
8c263761
DLR		 2184 /* Allow setting of any available qset when offload enabled */
2185 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2186 q1 = 0;
2187 for_each_port(adapter, i) {
2188 pi = adap2pinfo(adapter, i);
2189 nqsets += pi->first_qset + pi->nqsets;
2190 }
2191 }
2192
2193 if (t.qset_idx < q1)
2194 return -EINVAL;
2195 if (t.qset_idx > q1 + nqsets - 1)
2196 return -EINVAL;
2197
4d22de3e
DLR		 2198 q = &adapter->params.sge.qset[t.qset_idx];
2199
2200 if (t.rspq_size >= 0)
2201 q->rspq_size = t.rspq_size;
2202 if (t.fl_size[0] >= 0)
2203 q->fl_size = t.fl_size[0];
2204 if (t.fl_size[1] >= 0)
2205 q->jumbo_size = t.fl_size[1];
2206 if (t.txq_size[0] >= 0)
2207 q->txq_size[0] = t.txq_size[0];
2208 if (t.txq_size[1] >= 0)
2209 q->txq_size[1] = t.txq_size[1];
2210 if (t.txq_size[2] >= 0)
2211 q->txq_size[2] = t.txq_size[2];
2212 if (t.cong_thres >= 0)
2213 q->cong_thres = t.cong_thres;
2214 if (t.intr_lat >= 0) {
2215 struct sge_qset *qs =
2216 &adapter->sge.qs[t.qset_idx];
2217
2218 q->coalesce_usecs = t.intr_lat;
2219 t3_update_qset_coalesce(qs, q);
2220 }
2221 if (t.polling >= 0) {
2222 if (adapter->flags & USING_MSIX)
2223 q->polling = t.polling;
2224 else {
2225 /* No polling with INTx for T3A */
2226 if (adapter->params.rev == 0 &&
2227 !(adapter->flags & USING_MSI))
2228 t.polling = 0;
2229
2230 for (i = 0; i < SGE_QSETS; i++) {
2231 q = &adapter->params.sge.
2232 qset[i];
2233 q->polling = t.polling;
2234 }
2235 }
2236 }
04ecb072
DLR		 2237 if (t.lro >= 0)
2238 set_qset_lro(dev, t.qset_idx, t.lro);
2239
4d22de3e
DLR		 2240 break;
2241 }
2242 case CHELSIO_GET_QSET_PARAMS:{
2243 struct qset_params *q;
2244 struct ch_qset_params t;
8c263761
DLR		 2245 int q1 = pi->first_qset;
2246 int nqsets = pi->nqsets;
2247 int i;
4d22de3e
DLR		 2248
2249 if (copy_from_user(&t, useraddr, sizeof(t)))
2250 return -EFAULT;
8c263761
DLR		 2251
2252 /* Display qsets for all ports when offload enabled */
2253 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2254 q1 = 0;
2255 for_each_port(adapter, i) {
2256 pi = adap2pinfo(adapter, i);
2257 nqsets = pi->first_qset + pi->nqsets;
2258 }
2259 }
2260
2261 if (t.qset_idx >= nqsets)
4d22de3e
DLR		 2262 return -EINVAL;
2263
8c263761 2264 q = &adapter->params.sge.qset[q1 + t.qset_idx];
4d22de3e
DLR		 2265 t.rspq_size = q->rspq_size;
2266 t.txq_size[0] = q->txq_size[0];
2267 t.txq_size[1] = q->txq_size[1];
2268 t.txq_size[2] = q->txq_size[2];
2269 t.fl_size[0] = q->fl_size;
2270 t.fl_size[1] = q->jumbo_size;
2271 t.polling = q->polling;
b47385bd 2272 t.lro = q->lro;
4d22de3e
DLR		 2273 t.intr_lat = q->coalesce_usecs;
2274 t.cong_thres = q->cong_thres;
8c263761
DLR		 2275 t.qnum = q1;
2276
2277 if (adapter->flags & USING_MSIX)
2278 t.vector = adapter->msix_info[q1 + t.qset_idx + 1].vec;
2279 else
2280 t.vector = adapter->pdev->irq;
4d22de3e
DLR		 2281
2282 if (copy_to_user(useraddr, &t, sizeof(t)))
2283 return -EFAULT;
2284 break;
2285 }
2286 case CHELSIO_SET_QSET_NUM:{
2287 struct ch_reg edata;
4d22de3e
DLR		 2288 unsigned int i, first_qset = 0, other_qsets = 0;
2289
2290 if (!capable(CAP_NET_ADMIN))
2291 return -EPERM;
2292 if (adapter->flags & FULL_INIT_DONE)
2293 return -EBUSY;
2294 if (copy_from_user(&edata, useraddr, sizeof(edata)))
2295 return -EFAULT;
2296 if (edata.val < 1 ||
2297 (edata.val > 1 && !(adapter->flags & USING_MSIX)))
2298 return -EINVAL;
2299
2300 for_each_port(adapter, i)
2301 if (adapter->port[i] && adapter->port[i] != dev)
2302 other_qsets += adap2pinfo(adapter, i)->nqsets;
2303
2304 if (edata.val + other_qsets > SGE_QSETS)
2305 return -EINVAL;
2306
2307 pi->nqsets = edata.val;
2308
2309 for_each_port(adapter, i)
2310 if (adapter->port[i]) {
2311 pi = adap2pinfo(adapter, i);
2312 pi->first_qset = first_qset;
2313 first_qset += pi->nqsets;
2314 }
2315 break;
2316 }
2317 case CHELSIO_GET_QSET_NUM:{
2318 struct ch_reg edata;
4d22de3e 2319
49c37c03
DR		 2320 memset(&edata, 0, sizeof(struct ch_reg));
2321
4d22de3e
DLR		 2322 edata.cmd = CHELSIO_GET_QSET_NUM;
2323 edata.val = pi->nqsets;
2324 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2325 return -EFAULT;
2326 break;
2327 }
2328 case CHELSIO_LOAD_FW:{
2329 u8 *fw_data;
2330 struct ch_mem_range t;
2331
1b3aa7af 2332 if (!capable(CAP_SYS_RAWIO))
4d22de3e
DLR		 2333 return -EPERM;
2334 if (copy_from_user(&t, useraddr, sizeof(t)))
2335 return -EFAULT;
1b3aa7af 2336 /* Check t.len sanity ? */
c5dc9a35
JL		 2337 fw_data = memdup_user(useraddr + sizeof(t), t.len);
2338 if (IS_ERR(fw_data))
2339 return PTR_ERR(fw_data);
4d22de3e
DLR		 2340
2341 ret = t3_load_fw(adapter, fw_data, t.len);
2342 kfree(fw_data);
2343 if (ret)
2344 return ret;
2345 break;
2346 }
2347 case CHELSIO_SETMTUTAB:{
2348 struct ch_mtus m;
2349 int i;
2350
2351 if (!is_offload(adapter))
2352 return -EOPNOTSUPP;
2353 if (!capable(CAP_NET_ADMIN))
2354 return -EPERM;
2355 if (offload_running(adapter))
2356 return -EBUSY;
2357 if (copy_from_user(&m, useraddr, sizeof(m)))
2358 return -EFAULT;
2359 if (m.nmtus != NMTUS)
2360 return -EINVAL;
2361 if (m.mtus[0] < 81) /* accommodate SACK */
2362 return -EINVAL;
2363
2364 /* MTUs must be in ascending order */
2365 for (i = 1; i < NMTUS; ++i)
2366 if (m.mtus[i] < m.mtus[i - 1])
2367 return -EINVAL;
2368
2369 memcpy(adapter->params.mtus, m.mtus,
2370 sizeof(adapter->params.mtus));
2371 break;
2372 }
2373 case CHELSIO_GET_PM:{
2374 struct tp_params *p = &adapter->params.tp;
2375 struct ch_pm m = {.cmd = CHELSIO_GET_PM };
2376
2377 if (!is_offload(adapter))
2378 return -EOPNOTSUPP;
2379 m.tx_pg_sz = p->tx_pg_size;
2380 m.tx_num_pg = p->tx_num_pgs;
2381 m.rx_pg_sz = p->rx_pg_size;
2382 m.rx_num_pg = p->rx_num_pgs;
2383 m.pm_total = p->pmtx_size + p->chan_rx_size * p->nchan;
2384 if (copy_to_user(useraddr, &m, sizeof(m)))
2385 return -EFAULT;
2386 break;
2387 }
2388 case CHELSIO_SET_PM:{
2389 struct ch_pm m;
2390 struct tp_params *p = &adapter->params.tp;
2391
2392 if (!is_offload(adapter))
2393 return -EOPNOTSUPP;
2394 if (!capable(CAP_NET_ADMIN))
2395 return -EPERM;
2396 if (adapter->flags & FULL_INIT_DONE)
2397 return -EBUSY;
2398 if (copy_from_user(&m, useraddr, sizeof(m)))
2399 return -EFAULT;
d9da466a 2400 if (!is_power_of_2(m.rx_pg_sz) ||
2401 !is_power_of_2(m.tx_pg_sz))
4d22de3e
DLR		 2402 return -EINVAL; /* not power of 2 */
2403 if (!(m.rx_pg_sz & 0x14000))
2404 return -EINVAL; /* not 16KB or 64KB */
2405 if (!(m.tx_pg_sz & 0x1554000))
2406 return -EINVAL;
2407 if (m.tx_num_pg == -1)
2408 m.tx_num_pg = p->tx_num_pgs;
2409 if (m.rx_num_pg == -1)
2410 m.rx_num_pg = p->rx_num_pgs;
2411 if (m.tx_num_pg % 24 || m.rx_num_pg % 24)
2412 return -EINVAL;
2413 if (m.rx_num_pg * m.rx_pg_sz > p->chan_rx_size ||
2414 m.tx_num_pg * m.tx_pg_sz > p->chan_tx_size)
2415 return -EINVAL;
2416 p->rx_pg_size = m.rx_pg_sz;
2417 p->tx_pg_size = m.tx_pg_sz;
2418 p->rx_num_pgs = m.rx_num_pg;
2419 p->tx_num_pgs = m.tx_num_pg;
2420 break;
2421 }
2422 case CHELSIO_GET_MEM:{
2423 struct ch_mem_range t;
2424 struct mc7 *mem;
2425 u64 buf[32];
2426
2427 if (!is_offload(adapter))
2428 return -EOPNOTSUPP;
2429 if (!(adapter->flags & FULL_INIT_DONE))
2430 return -EIO; /* need the memory controllers */
2431 if (copy_from_user(&t, useraddr, sizeof(t)))
2432 return -EFAULT;
2433 if ((t.addr & 7) || (t.len & 7))
2434 return -EINVAL;
2435 if (t.mem_id == MEM_CM)
2436 mem = &adapter->cm;
2437 else if (t.mem_id == MEM_PMRX)
2438 mem = &adapter->pmrx;
2439 else if (t.mem_id == MEM_PMTX)
2440 mem = &adapter->pmtx;
2441 else
2442 return -EINVAL;
2443
2444 /*
1825494a
DLR		 2445 * Version scheme:
2446 * bits 0..9: chip version
2447 * bits 10..15: chip revision
2448 */
4d22de3e
DLR		 2449 t.version = 3 | (adapter->params.rev << 10);
2450 if (copy_to_user(useraddr, &t, sizeof(t)))
2451 return -EFAULT;
2452
2453 /*
2454 * Read 256 bytes at a time as len can be large and we don't
2455 * want to use huge intermediate buffers.
2456 */
2457 useraddr += sizeof(t); /* advance to start of buffer */
2458 while (t.len) {
2459 unsigned int chunk =
2460 min_t(unsigned int, t.len, sizeof(buf));
2461
2462 ret =
2463 t3_mc7_bd_read(mem, t.addr / 8, chunk / 8,
2464 buf);
2465 if (ret)
2466 return ret;
2467 if (copy_to_user(useraddr, buf, chunk))
2468 return -EFAULT;
2469 useraddr += chunk;
2470 t.addr += chunk;
2471 t.len -= chunk;
2472 }
2473 break;
2474 }
2475 case CHELSIO_SET_TRACE_FILTER:{
2476 struct ch_trace t;
2477 const struct trace_params *tp;
2478
2479 if (!capable(CAP_NET_ADMIN))
2480 return -EPERM;
2481 if (!offload_running(adapter))
2482 return -EAGAIN;
2483 if (copy_from_user(&t, useraddr, sizeof(t)))
2484 return -EFAULT;
2485
2486 tp = (const struct trace_params *)&t.sip;
2487 if (t.config_tx)
2488 t3_config_trace_filter(adapter, tp, 0,
2489 t.invert_match,
2490 t.trace_tx);
2491 if (t.config_rx)
2492 t3_config_trace_filter(adapter, tp, 1,
2493 t.invert_match,
2494 t.trace_rx);
2495 break;
2496 }
4d22de3e
DLR		 2497 default:
2498 return -EOPNOTSUPP;
2499 }
2500 return 0;
2501}
2502
2503static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2504{
4d22de3e 2505 struct mii_ioctl_data *data = if_mii(req);
5fbf816f
DLR		 2506 struct port_info *pi = netdev_priv(dev);
2507 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2508
2509 switch (cmd) {
0f07c4ee
BH		 2510 case SIOCGMIIREG:
2511 case SIOCSMIIREG:
2512 /* Convert phy_id from older PRTAD/DEVAD format */
2513 if (is_10G(adapter) &&
2514 !mdio_phy_id_is_c45(data->phy_id) &&
2515 (data->phy_id & 0x1f00) &&
2516 !(data->phy_id & 0xe0e0))
2517 data->phy_id = mdio_phy_id_c45(data->phy_id >> 8,
2518 data->phy_id & 0x1f);
4d22de3e 2519 /* FALLTHRU */
0f07c4ee
BH		 2520 case SIOCGMIIPHY:
2521 return mdio_mii_ioctl(&pi->phy.mdio, data, cmd);
4d22de3e
DLR		 2522 case SIOCCHIOCTL:
2523 return cxgb_extension_ioctl(dev, req->ifr_data);
2524 default:
2525 return -EOPNOTSUPP;
2526 }
4d22de3e
DLR		 2527}
2528
2529static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2530{
4d22de3e 2531 struct port_info *pi = netdev_priv(dev);
5fbf816f
DLR		 2532 struct adapter *adapter = pi->adapter;
2533 int ret;
4d22de3e
DLR		 2534
2535 if (new_mtu < 81) /* accommodate SACK */
2536 return -EINVAL;
2537 if ((ret = t3_mac_set_mtu(&pi->mac, new_mtu)))
2538 return ret;
2539 dev->mtu = new_mtu;
2540 init_port_mtus(adapter);
2541 if (adapter->params.rev == 0 && offload_running(adapter))
2542 t3_load_mtus(adapter, adapter->params.mtus,
2543 adapter->params.a_wnd, adapter->params.b_wnd,
2544 adapter->port[0]->mtu);
2545 return 0;
2546}
2547
2548static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2549{
4d22de3e 2550 struct port_info *pi = netdev_priv(dev);
5fbf816f 2551 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2552 struct sockaddr *addr = p;
2553
2554 if (!is_valid_ether_addr(addr->sa_data))
2555 return -EINVAL;
2556
2557 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
f14d42f3 2558 t3_mac_set_address(&pi->mac, LAN_MAC_IDX, dev->dev_addr);
4d22de3e
DLR		 2559 if (offload_running(adapter))
2560 write_smt_entry(adapter, pi->port_id);
2561 return 0;
2562}
2563
2564/**
2565 * t3_synchronize_rx - wait for current Rx processing on a port to complete
2566 * @adap: the adapter
2567 * @p: the port
2568 *
2569 * Ensures that current Rx processing on any of the queues associated with
2570 * the given port completes before returning. We do this by acquiring and
2571 * releasing the locks of the response queues associated with the port.
2572 */
2573static void t3_synchronize_rx(struct adapter *adap, const struct port_info *p)
2574{
2575 int i;
2576
8c263761
DLR		 2577 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
2578 struct sge_rspq *q = &adap->sge.qs[i].rspq;
4d22de3e
DLR		 2579
2580 spin_lock_irq(&q->lock);
2581 spin_unlock_irq(&q->lock);
2582 }
2583}
2584
2585static void vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2586{
4d22de3e 2587 struct port_info *pi = netdev_priv(dev);
5fbf816f 2588 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2589
2590 pi->vlan_grp = grp;
2591 if (adapter->params.rev > 0)
2592 t3_set_vlan_accel(adapter, 1 << pi->port_id, grp != NULL);
2593 else {
2594 /* single control for all ports */
2595 unsigned int i, have_vlans = 0;
2596 for_each_port(adapter, i)
2597 have_vlans |= adap2pinfo(adapter, i)->vlan_grp != NULL;
2598
2599 t3_set_vlan_accel(adapter, 1, have_vlans);
2600 }
2601 t3_synchronize_rx(adapter, pi);
2602}
2603
4d22de3e
DLR		 2604#ifdef CONFIG_NET_POLL_CONTROLLER
2605static void cxgb_netpoll(struct net_device *dev)
2606{
890de332 2607 struct port_info *pi = netdev_priv(dev);
5fbf816f 2608 struct adapter *adapter = pi->adapter;
890de332 2609 int qidx;
4d22de3e 2610
890de332
DLR		 2611 for (qidx = pi->first_qset; qidx < pi->first_qset + pi->nqsets; qidx++) {
2612 struct sge_qset *qs = &adapter->sge.qs[qidx];
2613 void *source;
2eab17ab 2614
890de332
DLR		 2615 if (adapter->flags & USING_MSIX)
2616 source = qs;
2617 else
2618 source = adapter;
2619
2620 t3_intr_handler(adapter, qs->rspq.polling) (0, source);
2621 }
4d22de3e
DLR		 2622}
2623#endif
2624
2625/*
2626 * Periodic accumulation of MAC statistics.
2627 */
2628static void mac_stats_update(struct adapter *adapter)
2629{
2630 int i;
2631
2632 for_each_port(adapter, i) {
2633 struct net_device *dev = adapter->port[i];
2634 struct port_info *p = netdev_priv(dev);
2635
2636 if (netif_running(dev)) {
2637 spin_lock(&adapter->stats_lock);
2638 t3_mac_update_stats(&p->mac);
2639 spin_unlock(&adapter->stats_lock);
2640 }
2641 }
2642}
2643
2644static void check_link_status(struct adapter *adapter)
2645{
2646 int i;
2647
2648 for_each_port(adapter, i) {
2649 struct net_device *dev = adapter->port[i];
2650 struct port_info *p = netdev_priv(dev);
c22c8149 2651 int link_fault;
4d22de3e 2652
bf792094 2653 spin_lock_irq(&adapter->work_lock);
c22c8149
DLR		 2654 link_fault = p->link_fault;
2655 spin_unlock_irq(&adapter->work_lock);
2656
2657 if (link_fault) {
3851c66c 2658 t3_link_fault(adapter, i);
bf792094
DLR		 2659 continue;
2660 }
bf792094
DLR		 2661
2662 if (!(p->phy.caps & SUPPORTED_IRQ) && netif_running(dev)) {
2663 t3_xgm_intr_disable(adapter, i);
2664 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2665
4d22de3e 2666 t3_link_changed(adapter, i);
bf792094
DLR		 2667 t3_xgm_intr_enable(adapter, i);
2668 }
4d22de3e
DLR		 2669 }
2670}
2671
fc90664e
DLR		 2672static void check_t3b2_mac(struct adapter *adapter)
2673{
2674 int i;
2675
f2d961c9
DLR		 2676 if (!rtnl_trylock()) /* synchronize with ifdown */
2677 return;
2678
fc90664e
DLR		 2679 for_each_port(adapter, i) {
2680 struct net_device *dev = adapter->port[i];
2681 struct port_info *p = netdev_priv(dev);
2682 int status;
2683
2684 if (!netif_running(dev))
2685 continue;
2686
2687 status = 0;
6d6dabac 2688 if (netif_running(dev) && netif_carrier_ok(dev))
fc90664e
DLR		 2689 status = t3b2_mac_watchdog_task(&p->mac);
2690 if (status == 1)
2691 p->mac.stats.num_toggled++;
2692 else if (status == 2) {
2693 struct cmac *mac = &p->mac;
2694
2695 t3_mac_set_mtu(mac, dev->mtu);
f14d42f3 2696 t3_mac_set_address(mac, LAN_MAC_IDX, dev->dev_addr);
fc90664e
DLR		 2697 cxgb_set_rxmode(dev);
2698 t3_link_start(&p->phy, mac, &p->link_config);
2699 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
2700 t3_port_intr_enable(adapter, p->port_id);
2701 p->mac.stats.num_resets++;
2702 }
2703 }
2704 rtnl_unlock();
2705}
2706
2707
4d22de3e
DLR		 2708static void t3_adap_check_task(struct work_struct *work)
2709{
2710 struct adapter *adapter = container_of(work, struct adapter,
2711 adap_check_task.work);
2712 const struct adapter_params *p = &adapter->params;
fc882196
DLR		 2713 int port;
2714 unsigned int v, status, reset;
4d22de3e
DLR		 2715
2716 adapter->check_task_cnt++;
2717
3851c66c 2718 check_link_status(adapter);
4d22de3e
DLR		 2719
2720 /* Accumulate MAC stats if needed */
2721 if (!p->linkpoll_period ||
2722 (adapter->check_task_cnt * p->linkpoll_period) / 10 >=
2723 p->stats_update_period) {
2724 mac_stats_update(adapter);
2725 adapter->check_task_cnt = 0;
2726 }
2727
fc90664e
DLR		 2728 if (p->rev == T3_REV_B2)
2729 check_t3b2_mac(adapter);
2730
fc882196
DLR		 2731 /*
2732 * Scan the XGMAC's to check for various conditions which we want to
2733 * monitor in a periodic polling manner rather than via an interrupt
2734 * condition. This is used for conditions which would otherwise flood
2735 * the system with interrupts and we only really need to know that the
2736 * conditions are "happening" ... For each condition we count the
2737 * detection of the condition and reset it for the next polling loop.
2738 */
2739 for_each_port(adapter, port) {
2740 struct cmac *mac = &adap2pinfo(adapter, port)->mac;
2741 u32 cause;
2742
2743 cause = t3_read_reg(adapter, A_XGM_INT_CAUSE + mac->offset);
2744 reset = 0;
2745 if (cause & F_RXFIFO_OVERFLOW) {
2746 mac->stats.rx_fifo_ovfl++;
2747 reset |= F_RXFIFO_OVERFLOW;
2748 }
2749
2750 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, reset);
2751 }
2752
2753 /*
2754 * We do the same as above for FL_EMPTY interrupts.
2755 */
2756 status = t3_read_reg(adapter, A_SG_INT_CAUSE);
2757 reset = 0;
2758
2759 if (status & F_FLEMPTY) {
2760 struct sge_qset *qs = &adapter->sge.qs[0];
2761 int i = 0;
2762
2763 reset |= F_FLEMPTY;
2764
2765 v = (t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS) >> S_FL0EMPTY) &
2766 0xffff;
2767
2768 while (v) {
2769 qs->fl[i].empty += (v & 1);
2770 if (i)
2771 qs++;
2772 i ^= 1;
2773 v >>= 1;
2774 }
2775 }
2776
2777 t3_write_reg(adapter, A_SG_INT_CAUSE, reset);
2778
4d22de3e 2779 /* Schedule the next check update if any port is active. */
20d3fc11 2780 spin_lock_irq(&adapter->work_lock);
4d22de3e
DLR		 2781 if (adapter->open_device_map & PORT_MASK)
2782 schedule_chk_task(adapter);
20d3fc11 2783 spin_unlock_irq(&adapter->work_lock);
4d22de3e
DLR		 2784}
2785
e998f245
SW		 2786static void db_full_task(struct work_struct *work)
2787{
2788 struct adapter *adapter = container_of(work, struct adapter,
2789 db_full_task);
2790
2791 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_FULL, 0);
2792}
2793
2794static void db_empty_task(struct work_struct *work)
2795{
2796 struct adapter *adapter = container_of(work, struct adapter,
2797 db_empty_task);
2798
2799 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_EMPTY, 0);
2800}
2801
2802static void db_drop_task(struct work_struct *work)
2803{
2804 struct adapter *adapter = container_of(work, struct adapter,
2805 db_drop_task);
2806 unsigned long delay = 1000;
2807 unsigned short r;
2808
2809 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_DROP, 0);
2810
2811 /*
2812 * Sleep a while before ringing the driver qset dbs.
2813 * The delay is between 1000-2023 usecs.
2814 */
2815 get_random_bytes(&r, 2);
2816 delay += r & 1023;
2817 set_current_state(TASK_UNINTERRUPTIBLE);
2818 schedule_timeout(usecs_to_jiffies(delay));
2819 ring_dbs(adapter);
2820}
2821
4d22de3e
DLR		 2822/*
2823 * Processes external (PHY) interrupts in process context.
2824 */
2825static void ext_intr_task(struct work_struct *work)
2826{
2827 struct adapter *adapter = container_of(work, struct adapter,
2828 ext_intr_handler_task);
bf792094
DLR		 2829 int i;
2830
2831 /* Disable link fault interrupts */
2832 for_each_port(adapter, i) {
2833 struct net_device *dev = adapter->port[i];
2834 struct port_info *p = netdev_priv(dev);
2835
2836 t3_xgm_intr_disable(adapter, i);
2837 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2838 }
4d22de3e 2839
bf792094 2840 /* Re-enable link fault interrupts */
4d22de3e
DLR		 2841 t3_phy_intr_handler(adapter);
2842
bf792094
DLR		 2843 for_each_port(adapter, i)
2844 t3_xgm_intr_enable(adapter, i);
2845
4d22de3e
DLR		 2846 /* Now reenable external interrupts */
2847 spin_lock_irq(&adapter->work_lock);
2848 if (adapter->slow_intr_mask) {
2849 adapter->slow_intr_mask |= F_T3DBG;
2850 t3_write_reg(adapter, A_PL_INT_CAUSE0, F_T3DBG);
2851 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2852 adapter->slow_intr_mask);
2853 }
2854 spin_unlock_irq(&adapter->work_lock);
2855}
2856
2857/*
2858 * Interrupt-context handler for external (PHY) interrupts.
2859 */
2860void t3_os_ext_intr_handler(struct adapter *adapter)
2861{
2862 /*
2863 * Schedule a task to handle external interrupts as they may be slow
2864 * and we use a mutex to protect MDIO registers. We disable PHY
2865 * interrupts in the meantime and let the task reenable them when
2866 * it's done.
2867 */
2868 spin_lock(&adapter->work_lock);
2869 if (adapter->slow_intr_mask) {
2870 adapter->slow_intr_mask &= ~F_T3DBG;
2871 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2872 adapter->slow_intr_mask);
2873 queue_work(cxgb3_wq, &adapter->ext_intr_handler_task);
2874 }
2875 spin_unlock(&adapter->work_lock);
2876}
2877
bf792094
DLR		 2878void t3_os_link_fault_handler(struct adapter *adapter, int port_id)
2879{
2880 struct net_device *netdev = adapter->port[port_id];
2881 struct port_info *pi = netdev_priv(netdev);
2882
2883 spin_lock(&adapter->work_lock);
2884 pi->link_fault = 1;
bf792094
DLR		 2885 spin_unlock(&adapter->work_lock);
2886}
2887
55bc3228 2888static int t3_adapter_error(struct adapter *adapter, int reset, int on_wq)
20d3fc11
DLR		 2889{
2890 int i, ret = 0;
2891
cb0bc205
DLR		 2892 if (is_offload(adapter) &&
2893 test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
fa0d4c11 2894 cxgb3_event_notify(&adapter->tdev, OFFLOAD_STATUS_DOWN, 0);
cb0bc205
DLR		 2895 offload_close(&adapter->tdev);
2896 }
2897
20d3fc11
DLR		 2898 /* Stop all ports */
2899 for_each_port(adapter, i) {
2900 struct net_device *netdev = adapter->port[i];
2901
2902 if (netif_running(netdev))
55bc3228 2903 __cxgb_close(netdev, on_wq);
20d3fc11
DLR		 2904 }
2905
20d3fc11
DLR		 2906 /* Stop SGE timers */
2907 t3_stop_sge_timers(adapter);
2908
2909 adapter->flags &= ~FULL_INIT_DONE;
2910
2911 if (reset)
2912 ret = t3_reset_adapter(adapter);
2913
2914 pci_disable_device(adapter->pdev);
2915
2916 return ret;
2917}
2918
2919static int t3_reenable_adapter(struct adapter *adapter)
2920{
2921 if (pci_enable_device(adapter->pdev)) {
2922 dev_err(&adapter->pdev->dev,
2923 "Cannot re-enable PCI device after reset.\n");
2924 goto err;
2925 }
2926 pci_set_master(adapter->pdev);
2927 pci_restore_state(adapter->pdev);
ccdddf50 2928 pci_save_state(adapter->pdev);
20d3fc11
DLR		 2929
2930 /* Free sge resources */
2931 t3_free_sge_resources(adapter);
2932
2933 if (t3_replay_prep_adapter(adapter))
2934 goto err;
2935
2936 return 0;
2937err:
2938 return -1;
2939}
2940
2941static void t3_resume_ports(struct adapter *adapter)
2942{
2943 int i;
2944
2945 /* Restart the ports */
2946 for_each_port(adapter, i) {
2947 struct net_device *netdev = adapter->port[i];
2948
2949 if (netif_running(netdev)) {
2950 if (cxgb_open(netdev)) {
2951 dev_err(&adapter->pdev->dev,
2952 "can't bring device back up"
2953 " after reset\n");
2954 continue;
2955 }
2956 }
2957 }
cb0bc205
DLR		 2958
2959 if (is_offload(adapter) && !ofld_disable)
fa0d4c11 2960 cxgb3_event_notify(&adapter->tdev, OFFLOAD_STATUS_UP, 0);
20d3fc11
DLR		 2961}
2962
2963/*
2964 * processes a fatal error.
2965 * Bring the ports down, reset the chip, bring the ports back up.
2966 */
2967static void fatal_error_task(struct work_struct *work)
2968{
2969 struct adapter *adapter = container_of(work, struct adapter,
2970 fatal_error_handler_task);
2971 int err = 0;
2972
2973 rtnl_lock();
55bc3228 2974 err = t3_adapter_error(adapter, 1, 1);
20d3fc11
DLR		 2975 if (!err)
2976 err = t3_reenable_adapter(adapter);
2977 if (!err)
2978 t3_resume_ports(adapter);
2979
2980 CH_ALERT(adapter, "adapter reset %s\n", err ? "failed" : "succeeded");
2981 rtnl_unlock();
2982}
2983
4d22de3e
DLR		 2984void t3_fatal_err(struct adapter *adapter)
2985{
2986 unsigned int fw_status[4];
2987
2988 if (adapter->flags & FULL_INIT_DONE) {
2989 t3_sge_stop(adapter);
c64c2eae
DLR		 2990 t3_write_reg(adapter, A_XGM_TX_CTRL, 0);
2991 t3_write_reg(adapter, A_XGM_RX_CTRL, 0);
2992 t3_write_reg(adapter, XGM_REG(A_XGM_TX_CTRL, 1), 0);
2993 t3_write_reg(adapter, XGM_REG(A_XGM_RX_CTRL, 1), 0);
20d3fc11
DLR		 2994
2995 spin_lock(&adapter->work_lock);
4d22de3e 2996 t3_intr_disable(adapter);
20d3fc11
DLR		 2997 queue_work(cxgb3_wq, &adapter->fatal_error_handler_task);
2998 spin_unlock(&adapter->work_lock);
4d22de3e
DLR		 2999 }
3000 CH_ALERT(adapter, "encountered fatal error, operation suspended\n");
3001 if (!t3_cim_ctl_blk_read(adapter, 0xa0, 4, fw_status))
3002 CH_ALERT(adapter, "FW status: 0x%x, 0x%x, 0x%x, 0x%x\n",
3003 fw_status[0], fw_status[1],
3004 fw_status[2], fw_status[3]);
4d22de3e
DLR		 3005}
3006
91a6b50c
DLR		 3007/**
3008 * t3_io_error_detected - called when PCI error is detected
3009 * @pdev: Pointer to PCI device
3010 * @state: The current pci connection state
3011 *
3012 * This function is called after a PCI bus error affecting
3013 * this device has been detected.
3014 */
3015static pci_ers_result_t t3_io_error_detected(struct pci_dev *pdev,
3016 pci_channel_state_t state)
3017{
bc4b6b52 3018 struct adapter *adapter = pci_get_drvdata(pdev);
91a6b50c 3019
e8d19370
DLR		 3020 if (state == pci_channel_io_perm_failure)
3021 return PCI_ERS_RESULT_DISCONNECT;
3022
c661c4a2 3023 t3_adapter_error(adapter, 0, 0);
91a6b50c 3024
48c4b6db 3025 /* Request a slot reset. */
91a6b50c
DLR		 3026 return PCI_ERS_RESULT_NEED_RESET;
3027}
3028
3029/**
3030 * t3_io_slot_reset - called after the pci bus has been reset.
3031 * @pdev: Pointer to PCI device
3032 *
3033 * Restart the card from scratch, as if from a cold-boot.
3034 */
3035static pci_ers_result_t t3_io_slot_reset(struct pci_dev *pdev)
3036{
bc4b6b52 3037 struct adapter *adapter = pci_get_drvdata(pdev);
91a6b50c 3038
20d3fc11
DLR		 3039 if (!t3_reenable_adapter(adapter))
3040 return PCI_ERS_RESULT_RECOVERED;
91a6b50c 3041
48c4b6db 3042 return PCI_ERS_RESULT_DISCONNECT;
91a6b50c
DLR		 3043}
3044
3045/**
3046 * t3_io_resume - called when traffic can start flowing again.
3047 * @pdev: Pointer to PCI device
3048 *
3049 * This callback is called when the error recovery driver tells us that
3050 * its OK to resume normal operation.
3051 */
3052static void t3_io_resume(struct pci_dev *pdev)
3053{
bc4b6b52 3054 struct adapter *adapter = pci_get_drvdata(pdev);
91a6b50c 3055
68f40c10
DLR		 3056 CH_ALERT(adapter, "adapter recovering, PEX ERR 0x%x\n",
3057 t3_read_reg(adapter, A_PCIE_PEX_ERR));
3058
20d3fc11 3059 t3_resume_ports(adapter);
91a6b50c
DLR		 3060}
3061
3062static struct pci_error_handlers t3_err_handler = {
3063 .error_detected = t3_io_error_detected,
3064 .slot_reset = t3_io_slot_reset,
3065 .resume = t3_io_resume,
3066};
3067
8c263761
DLR		 3068/*
3069 * Set the number of qsets based on the number of CPUs and the number of ports,
3070 * not to exceed the number of available qsets, assuming there are enough qsets
3071 * per port in HW.
3072 */
3073static void set_nqsets(struct adapter *adap)
3074{
3075 int i, j = 0;
3076 int num_cpus = num_online_cpus();
3077 int hwports = adap->params.nports;
5cda9364 3078 int nqsets = adap->msix_nvectors - 1;
8c263761 3079
f9ee3882 3080 if (adap->params.rev > 0 && adap->flags & USING_MSIX) {
8c263761
DLR		 3081 if (hwports == 2 &&
3082 (hwports * nqsets > SGE_QSETS ||
3083 num_cpus >= nqsets / hwports))
3084 nqsets /= hwports;
3085 if (nqsets > num_cpus)
3086 nqsets = num_cpus;
3087 if (nqsets < 1 || hwports == 4)
3088 nqsets = 1;
3089 } else
3090 nqsets = 1;
3091
3092 for_each_port(adap, i) {
3093 struct port_info *pi = adap2pinfo(adap, i);
3094
3095 pi->first_qset = j;
3096 pi->nqsets = nqsets;
3097 j = pi->first_qset + nqsets;
3098
3099 dev_info(&adap->pdev->dev,
3100 "Port %d using %d queue sets.\n", i, nqsets);
3101 }
3102}
3103
4d22de3e
DLR		 3104static int __devinit cxgb_enable_msix(struct adapter *adap)
3105{
3106 struct msix_entry entries[SGE_QSETS + 1];
5cda9364 3107 int vectors;
4d22de3e
DLR		 3108 int i, err;
3109
5cda9364
DLR		 3110 vectors = ARRAY_SIZE(entries);
3111 for (i = 0; i < vectors; ++i)
4d22de3e
DLR		 3112 entries[i].entry = i;
3113
5cda9364
DLR		 3114 while ((err = pci_enable_msix(adap->pdev, entries, vectors)) > 0)
3115 vectors = err;
3116
2c2f409f
DLR		 3117 if (err < 0)
3118 pci_disable_msix(adap->pdev);
3119
3120 if (!err && vectors < (adap->params.nports + 1)) {
3121 pci_disable_msix(adap->pdev);
5cda9364 3122 err = -1;
2c2f409f 3123 }
5cda9364 3124
4d22de3e 3125 if (!err) {
5cda9364 3126 for (i = 0; i < vectors; ++i)
4d22de3e 3127 adap->msix_info[i].vec = entries[i].vector;
5cda9364
DLR		 3128 adap->msix_nvectors = vectors;
3129 }
3130
4d22de3e
DLR		 3131 return err;
3132}
3133
3134static void __devinit print_port_info(struct adapter *adap,
3135 const struct adapter_info *ai)
3136{
3137 static const char *pci_variant[] = {
3138 "PCI", "PCI-X", "PCI-X ECC", "PCI-X 266", "PCI Express"
3139 };
3140
3141 int i;
3142 char buf[80];
3143
3144 if (is_pcie(adap))
3145 snprintf(buf, sizeof(buf), "%s x%d",
3146 pci_variant[adap->params.pci.variant],
3147 adap->params.pci.width);
3148 else
3149 snprintf(buf, sizeof(buf), "%s %dMHz/%d-bit",
3150 pci_variant[adap->params.pci.variant],
3151 adap->params.pci.speed, adap->params.pci.width);
3152
3153 for_each_port(adap, i) {
3154 struct net_device *dev = adap->port[i];
3155 const struct port_info *pi = netdev_priv(dev);
3156
3157 if (!test_bit(i, &adap->registered_device_map))
3158 continue;
8ac3ba68 3159 printk(KERN_INFO "%s: %s %s %sNIC (rev %d) %s%s\n",
04497982 3160 dev->name, ai->desc, pi->phy.desc,
8ac3ba68 3161 is_offload(adap) ? "R" : "", adap->params.rev, buf,
4d22de3e
DLR		 3162 (adap->flags & USING_MSIX) ? " MSI-X" :
3163 (adap->flags & USING_MSI) ? " MSI" : "");
3164 if (adap->name == dev->name && adap->params.vpd.mclk)
167cdf5f
DLR		 3165 printk(KERN_INFO
3166 "%s: %uMB CM, %uMB PMTX, %uMB PMRX, S/N: %s\n",
4d22de3e
DLR		 3167 adap->name, t3_mc7_size(&adap->cm) >> 20,
3168 t3_mc7_size(&adap->pmtx) >> 20,
167cdf5f
DLR		 3169 t3_mc7_size(&adap->pmrx) >> 20,
3170 adap->params.vpd.sn);
4d22de3e
DLR		 3171 }
3172}
3173
dd752696
SH		 3174static const struct net_device_ops cxgb_netdev_ops = {
3175 .ndo_open = cxgb_open,
3176 .ndo_stop = cxgb_close,
43a944f3 3177 .ndo_start_xmit = t3_eth_xmit,
dd752696
SH		 3178 .ndo_get_stats = cxgb_get_stats,
3179 .ndo_validate_addr = eth_validate_addr,
3180 .ndo_set_multicast_list = cxgb_set_rxmode,
3181 .ndo_do_ioctl = cxgb_ioctl,
3182 .ndo_change_mtu = cxgb_change_mtu,
3183 .ndo_set_mac_address = cxgb_set_mac_addr,
3184 .ndo_vlan_rx_register = vlan_rx_register,
3185#ifdef CONFIG_NET_POLL_CONTROLLER
3186 .ndo_poll_controller = cxgb_netpoll,
3187#endif
3188};
3189
f14d42f3
KX		 3190static void __devinit cxgb3_init_iscsi_mac(struct net_device *dev)
3191{
3192 struct port_info *pi = netdev_priv(dev);
3193
3194 memcpy(pi->iscsic.mac_addr, dev->dev_addr, ETH_ALEN);
3195 pi->iscsic.mac_addr[3] |= 0x80;
3196}
3197
4d22de3e
DLR		 3198static int __devinit init_one(struct pci_dev *pdev,
3199 const struct pci_device_id *ent)
3200{
3201 static int version_printed;
3202
3203 int i, err, pci_using_dac = 0;
68f40c10 3204 resource_size_t mmio_start, mmio_len;
4d22de3e
DLR		 3205 const struct adapter_info *ai;
3206 struct adapter *adapter = NULL;
3207 struct port_info *pi;
3208
3209 if (!version_printed) {
3210 printk(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
3211 ++version_printed;
3212 }
3213
3214 if (!cxgb3_wq) {
3215 cxgb3_wq = create_singlethread_workqueue(DRV_NAME);
3216 if (!cxgb3_wq) {
3217 printk(KERN_ERR DRV_NAME
3218 ": cannot initialize work queue\n");
3219 return -ENOMEM;
3220 }
3221 }
3222
7aaaaa1e 3223 err = pci_enable_device(pdev);
4d22de3e 3224 if (err) {
7aaaaa1e
KV		 3225 dev_err(&pdev->dev, "cannot enable PCI device\n");
3226 goto out;
4d22de3e
DLR		 3227 }
3228
7aaaaa1e 3229 err = pci_request_regions(pdev, DRV_NAME);
4d22de3e 3230 if (err) {
7aaaaa1e
KV		 3231 /* Just info, some other driver may have claimed the device. */
3232 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
3233 goto out_disable_device;
4d22de3e
DLR		 3234 }
3235
6a35528a 3236 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4d22de3e 3237 pci_using_dac = 1;
6a35528a 3238 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4d22de3e
DLR		 3239 if (err) {
3240 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
3241 "coherent allocations\n");
7aaaaa1e 3242 goto out_release_regions;
4d22de3e 3243 }
284901a9 3244 } else if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
4d22de3e 3245 dev_err(&pdev->dev, "no usable DMA configuration\n");
7aaaaa1e 3246 goto out_release_regions;
4d22de3e
DLR		 3247 }
3248
3249 pci_set_master(pdev);
204e2f98 3250 pci_save_state(pdev);
4d22de3e
DLR		 3251
3252 mmio_start = pci_resource_start(pdev, 0);
3253 mmio_len = pci_resource_len(pdev, 0);
3254 ai = t3_get_adapter_info(ent->driver_data);
3255
3256 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
3257 if (!adapter) {
3258 err = -ENOMEM;
7aaaaa1e 3259 goto out_release_regions;
4d22de3e
DLR		 3260 }
3261
74b793e1
DLR		 3262 adapter->nofail_skb =
3263 alloc_skb(sizeof(struct cpl_set_tcb_field), GFP_KERNEL);
3264 if (!adapter->nofail_skb) {
3265 dev_err(&pdev->dev, "cannot allocate nofail buffer\n");
3266 err = -ENOMEM;
3267 goto out_free_adapter;
3268 }
3269
4d22de3e
DLR		 3270 adapter->regs = ioremap_nocache(mmio_start, mmio_len);
3271 if (!adapter->regs) {
3272 dev_err(&pdev->dev, "cannot map device registers\n");
3273 err = -ENOMEM;
3274 goto out_free_adapter;
3275 }
3276
3277 adapter->pdev = pdev;
3278 adapter->name = pci_name(pdev);
3279 adapter->msg_enable = dflt_msg_enable;
3280 adapter->mmio_len = mmio_len;
3281
3282 mutex_init(&adapter->mdio_lock);
3283 spin_lock_init(&adapter->work_lock);
3284 spin_lock_init(&adapter->stats_lock);
3285
3286 INIT_LIST_HEAD(&adapter->adapter_list);
3287 INIT_WORK(&adapter->ext_intr_handler_task, ext_intr_task);
20d3fc11 3288 INIT_WORK(&adapter->fatal_error_handler_task, fatal_error_task);
e998f245
SW		 3289
3290 INIT_WORK(&adapter->db_full_task, db_full_task);
3291 INIT_WORK(&adapter->db_empty_task, db_empty_task);
3292 INIT_WORK(&adapter->db_drop_task, db_drop_task);
3293
4d22de3e
DLR		 3294 INIT_DELAYED_WORK(&adapter->adap_check_task, t3_adap_check_task);
3295
952cdf33 3296 for (i = 0; i < ai->nports0 + ai->nports1; ++i) {
4d22de3e
DLR		 3297 struct net_device *netdev;
3298
82ad3329 3299 netdev = alloc_etherdev_mq(sizeof(struct port_info), SGE_QSETS);
4d22de3e
DLR		 3300 if (!netdev) {
3301 err = -ENOMEM;
3302 goto out_free_dev;
3303 }
3304
4d22de3e
DLR		 3305 SET_NETDEV_DEV(netdev, &pdev->dev);
3306
3307 adapter->port[i] = netdev;
3308 pi = netdev_priv(netdev);
5fbf816f 3309 pi->adapter = adapter;
47fd23fe 3310 pi->rx_offload = T3_RX_CSUM | T3_LRO;
4d22de3e
DLR		 3311 pi->port_id = i;
3312 netif_carrier_off(netdev);
3313 netdev->irq = pdev->irq;
3314 netdev->mem_start = mmio_start;
3315 netdev->mem_end = mmio_start + mmio_len - 1;
4d22de3e 3316 netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
7be2df45 3317 netdev->features |= NETIF_F_GRO;
4d22de3e
DLR		 3318 if (pci_using_dac)
3319 netdev->features |= NETIF_F_HIGHDMA;
3320
3321 netdev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
dd752696 3322 netdev->netdev_ops = &cxgb_netdev_ops;
4d22de3e
DLR		 3323 SET_ETHTOOL_OPS(netdev, &cxgb_ethtool_ops);
3324 }
3325
5fbf816f 3326 pci_set_drvdata(pdev, adapter);
4d22de3e
DLR		 3327 if (t3_prep_adapter(adapter, ai, 1) < 0) {
3328 err = -ENODEV;
3329 goto out_free_dev;
3330 }
2eab17ab 3331
4d22de3e
DLR		 3332 /*
3333 * The card is now ready to go. If any errors occur during device
3334 * registration we do not fail the whole card but rather proceed only
3335 * with the ports we manage to register successfully. However we must
3336 * register at least one net device.
3337 */
3338 for_each_port(adapter, i) {
3339 err = register_netdev(adapter->port[i]);
3340 if (err)
3341 dev_warn(&pdev->dev,
3342 "cannot register net device %s, skipping\n",
3343 adapter->port[i]->name);
3344 else {
3345 /*
3346 * Change the name we use for messages to the name of
3347 * the first successfully registered interface.
3348 */
3349 if (!adapter->registered_device_map)
3350 adapter->name = adapter->port[i]->name;
3351
3352 __set_bit(i, &adapter->registered_device_map);
3353 }
3354 }
3355 if (!adapter->registered_device_map) {
3356 dev_err(&pdev->dev, "could not register any net devices\n");
3357 goto out_free_dev;
3358 }
3359
f14d42f3
KX		 3360 for_each_port(adapter, i)
3361 cxgb3_init_iscsi_mac(adapter->port[i]);
3362
4d22de3e
DLR		 3363 /* Driver's ready. Reflect it on LEDs */
3364 t3_led_ready(adapter);
3365
3366 if (is_offload(adapter)) {
3367 __set_bit(OFFLOAD_DEVMAP_BIT, &adapter->registered_device_map);
3368 cxgb3_adapter_ofld(adapter);
3369 }
3370
3371 /* See what interrupts we'll be using */
3372 if (msi > 1 && cxgb_enable_msix(adapter) == 0)
3373 adapter->flags |= USING_MSIX;
3374 else if (msi > 0 && pci_enable_msi(pdev) == 0)
3375 adapter->flags |= USING_MSI;
3376
8c263761
DLR		 3377 set_nqsets(adapter);
3378
0ee8d33c 3379 err = sysfs_create_group(&adapter->port[0]->dev.kobj,
4d22de3e
DLR		 3380 &cxgb3_attr_group);
3381
3382 print_port_info(adapter, ai);
3383 return 0;
3384
3385out_free_dev:
3386 iounmap(adapter->regs);
952cdf33 3387 for (i = ai->nports0 + ai->nports1 - 1; i >= 0; --i)
4d22de3e
DLR		 3388 if (adapter->port[i])
3389 free_netdev(adapter->port[i]);
3390
3391out_free_adapter:
3392 kfree(adapter);
3393
4d22de3e
DLR		 3394out_release_regions:
3395 pci_release_regions(pdev);
7aaaaa1e
KV		 3396out_disable_device:
3397 pci_disable_device(pdev);
4d22de3e 3398 pci_set_drvdata(pdev, NULL);
7aaaaa1e 3399out:
4d22de3e
DLR		 3400 return err;
3401}
3402
3403static void __devexit remove_one(struct pci_dev *pdev)
3404{
5fbf816f 3405 struct adapter *adapter = pci_get_drvdata(pdev);
4d22de3e 3406
5fbf816f 3407 if (adapter) {
4d22de3e 3408 int i;
4d22de3e
DLR		 3409
3410 t3_sge_stop(adapter);
0ee8d33c 3411 sysfs_remove_group(&adapter->port[0]->dev.kobj,
4d22de3e
DLR		 3412 &cxgb3_attr_group);
3413
4d22de3e
DLR		 3414 if (is_offload(adapter)) {
3415 cxgb3_adapter_unofld(adapter);
3416 if (test_bit(OFFLOAD_DEVMAP_BIT,
3417 &adapter->open_device_map))
3418 offload_close(&adapter->tdev);
3419 }
3420
67d92ab7
DLR		 3421 for_each_port(adapter, i)
3422 if (test_bit(i, &adapter->registered_device_map))
3423 unregister_netdev(adapter->port[i]);
3424
0ca41c04 3425 t3_stop_sge_timers(adapter);
4d22de3e
DLR		 3426 t3_free_sge_resources(adapter);
3427 cxgb_disable_msi(adapter);
3428
4d22de3e
DLR		 3429 for_each_port(adapter, i)
3430 if (adapter->port[i])
3431 free_netdev(adapter->port[i]);
3432
3433 iounmap(adapter->regs);
74b793e1
DLR		 3434 if (adapter->nofail_skb)
3435 kfree_skb(adapter->nofail_skb);
4d22de3e
DLR		 3436 kfree(adapter);
3437 pci_release_regions(pdev);
3438 pci_disable_device(pdev);
3439 pci_set_drvdata(pdev, NULL);
3440 }
3441}
3442
3443static struct pci_driver driver = {
3444 .name = DRV_NAME,
3445 .id_table = cxgb3_pci_tbl,
3446 .probe = init_one,
3447 .remove = __devexit_p(remove_one),
91a6b50c 3448 .err_handler = &t3_err_handler,
4d22de3e
DLR		 3449};
3450
3451static int __init cxgb3_init_module(void)
3452{
3453 int ret;
3454
3455 cxgb3_offload_init();
3456
3457 ret = pci_register_driver(&driver);
3458 return ret;
3459}
3460
3461static void __exit cxgb3_cleanup_module(void)
3462{
3463 pci_unregister_driver(&driver);
3464 if (cxgb3_wq)
3465 destroy_workqueue(cxgb3_wq);
3466}
3467
3468module_init(cxgb3_init_module);
3469module_exit(cxgb3_cleanup_module);
Linux 6.x block layer and io_uring tree(s)