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RDMA/cxgb3: Remove BUG_ON() on CQ rearm failure
[linux-2.6-block.git] / drivers / net / cxgb3 / cxgb3_main.c
CommitLineData
4d22de3e 1/*
a02d44a0 2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
4d22de3e 3 *
1d68e93d
DLR		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
4d22de3e 9 *
1d68e93d
DLR		 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
4d22de3e 31 */
4d22de3e
DLR		 32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/dma-mapping.h>
37#include <linux/netdevice.h>
38#include <linux/etherdevice.h>
39#include <linux/if_vlan.h>
0f07c4ee 40#include <linux/mdio.h>
4d22de3e
DLR		 41#include <linux/sockios.h>
42#include <linux/workqueue.h>
43#include <linux/proc_fs.h>
44#include <linux/rtnetlink.h>
2e283962 45#include <linux/firmware.h>
d9da466a 46#include <linux/log2.h>
34336ec0 47#include <linux/stringify.h>
4d22de3e
DLR		 48#include <asm/uaccess.h>
49
50#include "common.h"
51#include "cxgb3_ioctl.h"
52#include "regs.h"
53#include "cxgb3_offload.h"
54#include "version.h"
55
56#include "cxgb3_ctl_defs.h"
57#include "t3_cpl.h"
58#include "firmware_exports.h"
59
60enum {
61 MAX_TXQ_ENTRIES = 16384,
62 MAX_CTRL_TXQ_ENTRIES = 1024,
63 MAX_RSPQ_ENTRIES = 16384,
64 MAX_RX_BUFFERS = 16384,
65 MAX_RX_JUMBO_BUFFERS = 16384,
66 MIN_TXQ_ENTRIES = 4,
67 MIN_CTRL_TXQ_ENTRIES = 4,
68 MIN_RSPQ_ENTRIES = 32,
69 MIN_FL_ENTRIES = 32
70};
71
72#define PORT_MASK ((1 << MAX_NPORTS) - 1)
73
74#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
75 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
76 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
77
78#define EEPROM_MAGIC 0x38E2F10C
79
678771d6
DLR		 80#define CH_DEVICE(devid, idx) \
81 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, PCI_ANY_ID, 0, 0, idx }
4d22de3e
DLR		 82
83static const struct pci_device_id cxgb3_pci_tbl[] = {
678771d6
DLR		 84 CH_DEVICE(0x20, 0), /* PE9000 */
85 CH_DEVICE(0x21, 1), /* T302E */
86 CH_DEVICE(0x22, 2), /* T310E */
87 CH_DEVICE(0x23, 3), /* T320X */
88 CH_DEVICE(0x24, 1), /* T302X */
89 CH_DEVICE(0x25, 3), /* T320E */
90 CH_DEVICE(0x26, 2), /* T310X */
91 CH_DEVICE(0x30, 2), /* T3B10 */
92 CH_DEVICE(0x31, 3), /* T3B20 */
93 CH_DEVICE(0x32, 1), /* T3B02 */
ce03aadd 94 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
74451424
DLR		 95 CH_DEVICE(0x36, 3), /* S320E-CR */
96 CH_DEVICE(0x37, 7), /* N320E-G2 */
4d22de3e
DLR		 97 {0,}
98};
99
100MODULE_DESCRIPTION(DRV_DESC);
101MODULE_AUTHOR("Chelsio Communications");
1d68e93d 102MODULE_LICENSE("Dual BSD/GPL");
4d22de3e
DLR		 103MODULE_VERSION(DRV_VERSION);
104MODULE_DEVICE_TABLE(pci, cxgb3_pci_tbl);
105
106static int dflt_msg_enable = DFLT_MSG_ENABLE;
107
108module_param(dflt_msg_enable, int, 0644);
109MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T3 default message enable bitmap");
110
111/*
112 * The driver uses the best interrupt scheme available on a platform in the
113 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
114 * of these schemes the driver may consider as follows:
115 *
116 * msi = 2: choose from among all three options
117 * msi = 1: only consider MSI and pin interrupts
118 * msi = 0: force pin interrupts
119 */
120static int msi = 2;
121
122module_param(msi, int, 0644);
123MODULE_PARM_DESC(msi, "whether to use MSI or MSI-X");
124
125/*
126 * The driver enables offload as a default.
127 * To disable it, use ofld_disable = 1.
128 */
129
130static int ofld_disable = 0;
131
132module_param(ofld_disable, int, 0644);
133MODULE_PARM_DESC(ofld_disable, "whether to enable offload at init time or not");
134
135/*
136 * We have work elements that we need to cancel when an interface is taken
137 * down. Normally the work elements would be executed by keventd but that
138 * can deadlock because of linkwatch. If our close method takes the rtnl
139 * lock and linkwatch is ahead of our work elements in keventd, linkwatch
140 * will block keventd as it needs the rtnl lock, and we'll deadlock waiting
141 * for our work to complete. Get our own work queue to solve this.
142 */
143static struct workqueue_struct *cxgb3_wq;
144
145/**
146 * link_report - show link status and link speed/duplex
147 * @p: the port whose settings are to be reported
148 *
149 * Shows the link status, speed, and duplex of a port.
150 */
151static void link_report(struct net_device *dev)
152{
153 if (!netif_carrier_ok(dev))
154 printk(KERN_INFO "%s: link down\n", dev->name);
155 else {
156 const char *s = "10Mbps";
157 const struct port_info *p = netdev_priv(dev);
158
159 switch (p->link_config.speed) {
160 case SPEED_10000:
161 s = "10Gbps";
162 break;
163 case SPEED_1000:
164 s = "1000Mbps";
165 break;
166 case SPEED_100:
167 s = "100Mbps";
168 break;
169 }
170
171 printk(KERN_INFO "%s: link up, %s, %s-duplex\n", dev->name, s,
172 p->link_config.duplex == DUPLEX_FULL ? "full" : "half");
173 }
174}
175
34701fde
DLR		 176static void enable_tx_fifo_drain(struct adapter *adapter,
177 struct port_info *pi)
178{
179 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, 0,
180 F_ENDROPPKT);
181 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, 0);
182 t3_write_reg(adapter, A_XGM_TX_CTRL + pi->mac.offset, F_TXEN);
183 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, F_RXEN);
184}
185
186static void disable_tx_fifo_drain(struct adapter *adapter,
187 struct port_info *pi)
188{
189 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset,
190 F_ENDROPPKT, 0);
191}
192
bf792094
DLR		 193void t3_os_link_fault(struct adapter *adap, int port_id, int state)
194{
195 struct net_device *dev = adap->port[port_id];
196 struct port_info *pi = netdev_priv(dev);
197
198 if (state == netif_carrier_ok(dev))
199 return;
200
201 if (state) {
202 struct cmac *mac = &pi->mac;
203
204 netif_carrier_on(dev);
205
34701fde
DLR		 206 disable_tx_fifo_drain(adap, pi);
207
bf792094
DLR		 208 /* Clear local faults */
209 t3_xgm_intr_disable(adap, pi->port_id);
210 t3_read_reg(adap, A_XGM_INT_STATUS +
211 pi->mac.offset);
212 t3_write_reg(adap,
213 A_XGM_INT_CAUSE + pi->mac.offset,
214 F_XGM_INT);
215
216 t3_set_reg_field(adap,
217 A_XGM_INT_ENABLE +
218 pi->mac.offset,
219 F_XGM_INT, F_XGM_INT);
220 t3_xgm_intr_enable(adap, pi->port_id);
221
222 t3_mac_enable(mac, MAC_DIRECTION_TX);
34701fde 223 } else {
bf792094
DLR		 224 netif_carrier_off(dev);
225
34701fde
DLR		 226 /* Flush TX FIFO */
227 enable_tx_fifo_drain(adap, pi);
228 }
bf792094
DLR		 229 link_report(dev);
230}
231
4d22de3e
DLR		 232/**
233 * t3_os_link_changed - handle link status changes
234 * @adapter: the adapter associated with the link change
235 * @port_id: the port index whose limk status has changed
236 * @link_stat: the new status of the link
237 * @speed: the new speed setting
238 * @duplex: the new duplex setting
239 * @pause: the new flow-control setting
240 *
241 * This is the OS-dependent handler for link status changes. The OS
242 * neutral handler takes care of most of the processing for these events,
243 * then calls this handler for any OS-specific processing.
244 */
245void t3_os_link_changed(struct adapter *adapter, int port_id, int link_stat,
246 int speed, int duplex, int pause)
247{
248 struct net_device *dev = adapter->port[port_id];
6d6dabac
DLR		 249 struct port_info *pi = netdev_priv(dev);
250 struct cmac *mac = &pi->mac;
4d22de3e
DLR		 251
252 /* Skip changes from disabled ports. */
253 if (!netif_running(dev))
254 return;
255
256 if (link_stat != netif_carrier_ok(dev)) {
6d6dabac 257 if (link_stat) {
34701fde
DLR		 258 disable_tx_fifo_drain(adapter, pi);
259
59cf8107 260 t3_mac_enable(mac, MAC_DIRECTION_RX);
bf792094
DLR		 261
262 /* Clear local faults */
263 t3_xgm_intr_disable(adapter, pi->port_id);
264 t3_read_reg(adapter, A_XGM_INT_STATUS +
265 pi->mac.offset);
266 t3_write_reg(adapter,
267 A_XGM_INT_CAUSE + pi->mac.offset,
268 F_XGM_INT);
269
270 t3_set_reg_field(adapter,
271 A_XGM_INT_ENABLE + pi->mac.offset,
272 F_XGM_INT, F_XGM_INT);
273 t3_xgm_intr_enable(adapter, pi->port_id);
274
4d22de3e 275 netif_carrier_on(dev);
6d6dabac 276 } else {
4d22de3e 277 netif_carrier_off(dev);
bf792094
DLR		 278
279 t3_xgm_intr_disable(adapter, pi->port_id);
280 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
281 t3_set_reg_field(adapter,
282 A_XGM_INT_ENABLE + pi->mac.offset,
283 F_XGM_INT, 0);
284
285 if (is_10G(adapter))
286 pi->phy.ops->power_down(&pi->phy, 1);
287
288 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
59cf8107
DLR		 289 t3_mac_disable(mac, MAC_DIRECTION_RX);
290 t3_link_start(&pi->phy, mac, &pi->link_config);
34701fde
DLR		 291
292 /* Flush TX FIFO */
293 enable_tx_fifo_drain(adapter, pi);
6d6dabac
DLR		 294 }
295
4d22de3e
DLR		 296 link_report(dev);
297 }
298}
299
1e882025
DLR		 300/**
301 * t3_os_phymod_changed - handle PHY module changes
302 * @phy: the PHY reporting the module change
303 * @mod_type: new module type
304 *
305 * This is the OS-dependent handler for PHY module changes. It is
306 * invoked when a PHY module is removed or inserted for any OS-specific
307 * processing.
308 */
309void t3_os_phymod_changed(struct adapter *adap, int port_id)
310{
311 static const char *mod_str[] = {
312 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown"
313 };
314
315 const struct net_device *dev = adap->port[port_id];
316 const struct port_info *pi = netdev_priv(dev);
317
318 if (pi->phy.modtype == phy_modtype_none)
319 printk(KERN_INFO "%s: PHY module unplugged\n", dev->name);
320 else
321 printk(KERN_INFO "%s: %s PHY module inserted\n", dev->name,
322 mod_str[pi->phy.modtype]);
323}
324
4d22de3e
DLR		 325static void cxgb_set_rxmode(struct net_device *dev)
326{
327 struct t3_rx_mode rm;
328 struct port_info *pi = netdev_priv(dev);
329
330 init_rx_mode(&rm, dev, dev->mc_list);
331 t3_mac_set_rx_mode(&pi->mac, &rm);
332}
333
334/**
335 * link_start - enable a port
336 * @dev: the device to enable
337 *
338 * Performs the MAC and PHY actions needed to enable a port.
339 */
340static void link_start(struct net_device *dev)
341{
342 struct t3_rx_mode rm;
343 struct port_info *pi = netdev_priv(dev);
344 struct cmac *mac = &pi->mac;
345
346 init_rx_mode(&rm, dev, dev->mc_list);
347 t3_mac_reset(mac);
f14d42f3 348 t3_mac_set_num_ucast(mac, MAX_MAC_IDX);
4d22de3e 349 t3_mac_set_mtu(mac, dev->mtu);
f14d42f3
KX		 350 t3_mac_set_address(mac, LAN_MAC_IDX, dev->dev_addr);
351 t3_mac_set_address(mac, SAN_MAC_IDX, pi->iscsic.mac_addr);
4d22de3e
DLR		 352 t3_mac_set_rx_mode(mac, &rm);
353 t3_link_start(&pi->phy, mac, &pi->link_config);
354 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
355}
356
357static inline void cxgb_disable_msi(struct adapter *adapter)
358{
359 if (adapter->flags & USING_MSIX) {
360 pci_disable_msix(adapter->pdev);
361 adapter->flags &= ~USING_MSIX;
362 } else if (adapter->flags & USING_MSI) {
363 pci_disable_msi(adapter->pdev);
364 adapter->flags &= ~USING_MSI;
365 }
366}
367
368/*
369 * Interrupt handler for asynchronous events used with MSI-X.
370 */
371static irqreturn_t t3_async_intr_handler(int irq, void *cookie)
372{
373 t3_slow_intr_handler(cookie);
374 return IRQ_HANDLED;
375}
376
377/*
378 * Name the MSI-X interrupts.
379 */
380static void name_msix_vecs(struct adapter *adap)
381{
382 int i, j, msi_idx = 1, n = sizeof(adap->msix_info[0].desc) - 1;
383
384 snprintf(adap->msix_info[0].desc, n, "%s", adap->name);
385 adap->msix_info[0].desc[n] = 0;
386
387 for_each_port(adap, j) {
388 struct net_device *d = adap->port[j];
389 const struct port_info *pi = netdev_priv(d);
390
391 for (i = 0; i < pi->nqsets; i++, msi_idx++) {
392 snprintf(adap->msix_info[msi_idx].desc, n,
8c263761 393 "%s-%d", d->name, pi->first_qset + i);
4d22de3e
DLR		 394 adap->msix_info[msi_idx].desc[n] = 0;
395 }
8c263761 396 }
4d22de3e
DLR		 397}
398
399static int request_msix_data_irqs(struct adapter *adap)
400{
401 int i, j, err, qidx = 0;
402
403 for_each_port(adap, i) {
404 int nqsets = adap2pinfo(adap, i)->nqsets;
405
406 for (j = 0; j < nqsets; ++j) {
407 err = request_irq(adap->msix_info[qidx + 1].vec,
408 t3_intr_handler(adap,
409 adap->sge.qs[qidx].
410 rspq.polling), 0,
411 adap->msix_info[qidx + 1].desc,
412 &adap->sge.qs[qidx]);
413 if (err) {
414 while (--qidx >= 0)
415 free_irq(adap->msix_info[qidx + 1].vec,
416 &adap->sge.qs[qidx]);
417 return err;
418 }
419 qidx++;
420 }
421 }
422 return 0;
423}
424
8c263761
DLR		 425static void free_irq_resources(struct adapter *adapter)
426{
427 if (adapter->flags & USING_MSIX) {
428 int i, n = 0;
429
430 free_irq(adapter->msix_info[0].vec, adapter);
431 for_each_port(adapter, i)
5cda9364 432 n += adap2pinfo(adapter, i)->nqsets;
8c263761
DLR		 433
434 for (i = 0; i < n; ++i)
435 free_irq(adapter->msix_info[i + 1].vec,
436 &adapter->sge.qs[i]);
437 } else
438 free_irq(adapter->pdev->irq, adapter);
439}
440
b881955b
DLR		 441static int await_mgmt_replies(struct adapter *adap, unsigned long init_cnt,
442 unsigned long n)
443{
444 int attempts = 5;
445
446 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) {
447 if (!--attempts)
448 return -ETIMEDOUT;
449 msleep(10);
450 }
451 return 0;
452}
453
454static int init_tp_parity(struct adapter *adap)
455{
456 int i;
457 struct sk_buff *skb;
458 struct cpl_set_tcb_field *greq;
459 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts;
460
461 t3_tp_set_offload_mode(adap, 1);
462
463 for (i = 0; i < 16; i++) {
464 struct cpl_smt_write_req *req;
465
74b793e1
DLR		 466 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
467 if (!skb)
468 skb = adap->nofail_skb;
469 if (!skb)
470 goto alloc_skb_fail;
471
b881955b
DLR		 472 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
473 memset(req, 0, sizeof(*req));
474 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
475 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i));
dce7d1d0 476 req->mtu_idx = NMTUS - 1;
b881955b
DLR		 477 req->iff = i;
478 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 479 if (skb == adap->nofail_skb) {
480 await_mgmt_replies(adap, cnt, i + 1);
481 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
482 if (!adap->nofail_skb)
483 goto alloc_skb_fail;
484 }
b881955b
DLR		 485 }
486
487 for (i = 0; i < 2048; i++) {
488 struct cpl_l2t_write_req *req;
489
74b793e1
DLR		 490 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
491 if (!skb)
492 skb = adap->nofail_skb;
493 if (!skb)
494 goto alloc_skb_fail;
495
b881955b
DLR		 496 req = (struct cpl_l2t_write_req *)__skb_put(skb, sizeof(*req));
497 memset(req, 0, sizeof(*req));
498 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
499 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i));
500 req->params = htonl(V_L2T_W_IDX(i));
501 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 502 if (skb == adap->nofail_skb) {
503 await_mgmt_replies(adap, cnt, 16 + i + 1);
504 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
505 if (!adap->nofail_skb)
506 goto alloc_skb_fail;
507 }
b881955b
DLR		 508 }
509
510 for (i = 0; i < 2048; i++) {
511 struct cpl_rte_write_req *req;
512
74b793e1
DLR		 513 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
514 if (!skb)
515 skb = adap->nofail_skb;
516 if (!skb)
517 goto alloc_skb_fail;
518
b881955b
DLR		 519 req = (struct cpl_rte_write_req *)__skb_put(skb, sizeof(*req));
520 memset(req, 0, sizeof(*req));
521 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
522 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i));
523 req->l2t_idx = htonl(V_L2T_W_IDX(i));
524 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 525 if (skb == adap->nofail_skb) {
526 await_mgmt_replies(adap, cnt, 16 + 2048 + i + 1);
527 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
528 if (!adap->nofail_skb)
529 goto alloc_skb_fail;
530 }
b881955b
DLR		 531 }
532
74b793e1
DLR		 533 skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
534 if (!skb)
535 skb = adap->nofail_skb;
536 if (!skb)
537 goto alloc_skb_fail;
538
b881955b
DLR		 539 greq = (struct cpl_set_tcb_field *)__skb_put(skb, sizeof(*greq));
540 memset(greq, 0, sizeof(*greq));
541 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
542 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0));
543 greq->mask = cpu_to_be64(1);
544 t3_mgmt_tx(adap, skb);
545
546 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
74b793e1
DLR		 547 if (skb == adap->nofail_skb) {
548 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
549 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
550 }
551
b881955b
DLR		 552 t3_tp_set_offload_mode(adap, 0);
553 return i;
74b793e1
DLR		 554
555alloc_skb_fail:
556 t3_tp_set_offload_mode(adap, 0);
557 return -ENOMEM;
b881955b
DLR		 558}
559
4d22de3e
DLR		 560/**
561 * setup_rss - configure RSS
562 * @adap: the adapter
563 *
564 * Sets up RSS to distribute packets to multiple receive queues. We
565 * configure the RSS CPU lookup table to distribute to the number of HW
566 * receive queues, and the response queue lookup table to narrow that
567 * down to the response queues actually configured for each port.
568 * We always configure the RSS mapping for two ports since the mapping
569 * table has plenty of entries.
570 */
571static void setup_rss(struct adapter *adap)
572{
573 int i;
574 unsigned int nq0 = adap2pinfo(adap, 0)->nqsets;
575 unsigned int nq1 = adap->port[1] ? adap2pinfo(adap, 1)->nqsets : 1;
576 u8 cpus[SGE_QSETS + 1];
577 u16 rspq_map[RSS_TABLE_SIZE];
578
579 for (i = 0; i < SGE_QSETS; ++i)
580 cpus[i] = i;
581 cpus[SGE_QSETS] = 0xff; /* terminator */
582
583 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
584 rspq_map[i] = i % nq0;
585 rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq1) + nq0;
586 }
587
588 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
589 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN |
a2604be5 590 V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, cpus, rspq_map);
4d22de3e
DLR		 591}
592
bea3348e 593static void init_napi(struct adapter *adap)
4d22de3e 594{
bea3348e 595 int i;
4d22de3e 596
bea3348e
SH		 597 for (i = 0; i < SGE_QSETS; i++) {
598 struct sge_qset *qs = &adap->sge.qs[i];
4d22de3e 599
bea3348e
SH		 600 if (qs->adap)
601 netif_napi_add(qs->netdev, &qs->napi, qs->napi.poll,
602 64);
4d22de3e 603 }
48c4b6db
DLR		 604
605 /*
606 * netif_napi_add() can be called only once per napi_struct because it
607 * adds each new napi_struct to a list. Be careful not to call it a
608 * second time, e.g., during EEH recovery, by making a note of it.
609 */
610 adap->flags |= NAPI_INIT;
4d22de3e
DLR		 611}
612
613/*
614 * Wait until all NAPI handlers are descheduled. This includes the handlers of
615 * both netdevices representing interfaces and the dummy ones for the extra
616 * queues.
617 */
618static void quiesce_rx(struct adapter *adap)
619{
620 int i;
4d22de3e 621
bea3348e
SH		 622 for (i = 0; i < SGE_QSETS; i++)
623 if (adap->sge.qs[i].adap)
624 napi_disable(&adap->sge.qs[i].napi);
625}
4d22de3e 626
bea3348e
SH		 627static void enable_all_napi(struct adapter *adap)
628{
629 int i;
630 for (i = 0; i < SGE_QSETS; i++)
631 if (adap->sge.qs[i].adap)
632 napi_enable(&adap->sge.qs[i].napi);
4d22de3e
DLR		 633}
634
04ecb072
DLR		 635/**
636 * set_qset_lro - Turn a queue set's LRO capability on and off
637 * @dev: the device the qset is attached to
638 * @qset_idx: the queue set index
639 * @val: the LRO switch
640 *
641 * Sets LRO on or off for a particular queue set.
642 * the device's features flag is updated to reflect the LRO
643 * capability when all queues belonging to the device are
644 * in the same state.
645 */
646static void set_qset_lro(struct net_device *dev, int qset_idx, int val)
647{
648 struct port_info *pi = netdev_priv(dev);
649 struct adapter *adapter = pi->adapter;
04ecb072
DLR		 650
651 adapter->params.sge.qset[qset_idx].lro = !!val;
652 adapter->sge.qs[qset_idx].lro_enabled = !!val;
04ecb072
DLR		 653}
654
4d22de3e
DLR		 655/**
656 * setup_sge_qsets - configure SGE Tx/Rx/response queues
657 * @adap: the adapter
658 *
659 * Determines how many sets of SGE queues to use and initializes them.
660 * We support multiple queue sets per port if we have MSI-X, otherwise
661 * just one queue set per port.
662 */
663static int setup_sge_qsets(struct adapter *adap)
664{
bea3348e 665 int i, j, err, irq_idx = 0, qset_idx = 0;
8ac3ba68 666 unsigned int ntxq = SGE_TXQ_PER_SET;
4d22de3e
DLR		 667
668 if (adap->params.rev > 0 && !(adap->flags & USING_MSI))
669 irq_idx = -1;
670
671 for_each_port(adap, i) {
672 struct net_device *dev = adap->port[i];
bea3348e 673 struct port_info *pi = netdev_priv(dev);
4d22de3e 674
bea3348e 675 pi->qs = &adap->sge.qs[pi->first_qset];
e594e96e 676 for (j = 0; j < pi->nqsets; ++j, ++qset_idx) {
47fd23fe 677 set_qset_lro(dev, qset_idx, pi->rx_offload & T3_LRO);
4d22de3e
DLR		 678 err = t3_sge_alloc_qset(adap, qset_idx, 1,
679 (adap->flags & USING_MSIX) ? qset_idx + 1 :
680 irq_idx,
82ad3329
DLR		 681 &adap->params.sge.qset[qset_idx], ntxq, dev,
682 netdev_get_tx_queue(dev, j));
4d22de3e
DLR		 683 if (err) {
684 t3_free_sge_resources(adap);
685 return err;
686 }
687 }
688 }
689
690 return 0;
691}
692
3e5192ee 693static ssize_t attr_show(struct device *d, char *buf,
896392ef 694 ssize_t(*format) (struct net_device *, char *))
4d22de3e
DLR		 695{
696 ssize_t len;
4d22de3e
DLR		 697
698 /* Synchronize with ioctls that may shut down the device */
699 rtnl_lock();
896392ef 700 len = (*format) (to_net_dev(d), buf);
4d22de3e
DLR		 701 rtnl_unlock();
702 return len;
703}
704
3e5192ee 705static ssize_t attr_store(struct device *d,
0ee8d33c 706 const char *buf, size_t len,
896392ef 707 ssize_t(*set) (struct net_device *, unsigned int),
4d22de3e
DLR		 708 unsigned int min_val, unsigned int max_val)
709{
710 char *endp;
711 ssize_t ret;
712 unsigned int val;
4d22de3e
DLR		 713
714 if (!capable(CAP_NET_ADMIN))
715 return -EPERM;
716
717 val = simple_strtoul(buf, &endp, 0);
718 if (endp == buf || val < min_val || val > max_val)
719 return -EINVAL;
720
721 rtnl_lock();
896392ef 722 ret = (*set) (to_net_dev(d), val);
4d22de3e
DLR		 723 if (!ret)
724 ret = len;
725 rtnl_unlock();
726 return ret;
727}
728
729#define CXGB3_SHOW(name, val_expr) \
896392ef 730static ssize_t format_##name(struct net_device *dev, char *buf) \
4d22de3e 731{ \
5fbf816f
DLR		 732 struct port_info *pi = netdev_priv(dev); \
733 struct adapter *adap = pi->adapter; \
4d22de3e
DLR		 734 return sprintf(buf, "%u\n", val_expr); \
735} \
0ee8d33c
DLR		 736static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
737 char *buf) \
4d22de3e 738{ \
3e5192ee 739 return attr_show(d, buf, format_##name); \
4d22de3e
DLR		 740}
741
896392ef 742static ssize_t set_nfilters(struct net_device *dev, unsigned int val)
4d22de3e 743{
5fbf816f
DLR		 744 struct port_info *pi = netdev_priv(dev);
745 struct adapter *adap = pi->adapter;
9f238486 746 int min_tids = is_offload(adap) ? MC5_MIN_TIDS : 0;
896392ef 747
4d22de3e
DLR		 748 if (adap->flags & FULL_INIT_DONE)
749 return -EBUSY;
750 if (val && adap->params.rev == 0)
751 return -EINVAL;
9f238486
DLR		 752 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
753 min_tids)
4d22de3e
DLR		 754 return -EINVAL;
755 adap->params.mc5.nfilters = val;
756 return 0;
757}
758
0ee8d33c
DLR		 759static ssize_t store_nfilters(struct device *d, struct device_attribute *attr,
760 const char *buf, size_t len)
4d22de3e 761{
3e5192ee 762 return attr_store(d, buf, len, set_nfilters, 0, ~0);
4d22de3e
DLR		 763}
764
896392ef 765static ssize_t set_nservers(struct net_device *dev, unsigned int val)
4d22de3e 766{
5fbf816f
DLR		 767 struct port_info *pi = netdev_priv(dev);
768 struct adapter *adap = pi->adapter;
896392ef 769
4d22de3e
DLR		 770 if (adap->flags & FULL_INIT_DONE)
771 return -EBUSY;
9f238486
DLR		 772 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nfilters -
773 MC5_MIN_TIDS)
4d22de3e
DLR		 774 return -EINVAL;
775 adap->params.mc5.nservers = val;
776 return 0;
777}
778
0ee8d33c
DLR		 779static ssize_t store_nservers(struct device *d, struct device_attribute *attr,
780 const char *buf, size_t len)
4d22de3e 781{
3e5192ee 782 return attr_store(d, buf, len, set_nservers, 0, ~0);
4d22de3e
DLR		 783}
784
785#define CXGB3_ATTR_R(name, val_expr) \
786CXGB3_SHOW(name, val_expr) \
0ee8d33c 787static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
4d22de3e
DLR		 788
789#define CXGB3_ATTR_RW(name, val_expr, store_method) \
790CXGB3_SHOW(name, val_expr) \
0ee8d33c 791static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_method)
4d22de3e
DLR		 792
793CXGB3_ATTR_R(cam_size, t3_mc5_size(&adap->mc5));
794CXGB3_ATTR_RW(nfilters, adap->params.mc5.nfilters, store_nfilters);
795CXGB3_ATTR_RW(nservers, adap->params.mc5.nservers, store_nservers);
796
797static struct attribute *cxgb3_attrs[] = {
0ee8d33c
DLR		 798 &dev_attr_cam_size.attr,
799 &dev_attr_nfilters.attr,
800 &dev_attr_nservers.attr,
4d22de3e
DLR		 801 NULL
802};
803
804static struct attribute_group cxgb3_attr_group = {.attrs = cxgb3_attrs };
805
3e5192ee 806static ssize_t tm_attr_show(struct device *d,
0ee8d33c 807 char *buf, int sched)
4d22de3e 808{
5fbf816f
DLR		 809 struct port_info *pi = netdev_priv(to_net_dev(d));
810 struct adapter *adap = pi->adapter;
4d22de3e 811 unsigned int v, addr, bpt, cpt;
5fbf816f 812 ssize_t len;
4d22de3e
DLR		 813
814 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
815 rtnl_lock();
816 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
817 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
818 if (sched & 1)
819 v >>= 16;
820 bpt = (v >> 8) & 0xff;
821 cpt = v & 0xff;
822 if (!cpt)
823 len = sprintf(buf, "disabled\n");
824 else {
825 v = (adap->params.vpd.cclk * 1000) / cpt;
826 len = sprintf(buf, "%u Kbps\n", (v * bpt) / 125);
827 }
828 rtnl_unlock();
829 return len;
830}
831
3e5192ee 832static ssize_t tm_attr_store(struct device *d,
0ee8d33c 833 const char *buf, size_t len, int sched)
4d22de3e 834{
5fbf816f
DLR		 835 struct port_info *pi = netdev_priv(to_net_dev(d));
836 struct adapter *adap = pi->adapter;
837 unsigned int val;
4d22de3e
DLR		 838 char *endp;
839 ssize_t ret;
4d22de3e
DLR		 840
841 if (!capable(CAP_NET_ADMIN))
842 return -EPERM;
843
844 val = simple_strtoul(buf, &endp, 0);
845 if (endp == buf || val > 10000000)
846 return -EINVAL;
847
848 rtnl_lock();
849 ret = t3_config_sched(adap, val, sched);
850 if (!ret)
851 ret = len;
852 rtnl_unlock();
853 return ret;
854}
855
856#define TM_ATTR(name, sched) \
0ee8d33c
DLR		 857static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
858 char *buf) \
4d22de3e 859{ \
3e5192ee 860 return tm_attr_show(d, buf, sched); \
4d22de3e 861} \
0ee8d33c
DLR		 862static ssize_t store_##name(struct device *d, struct device_attribute *attr, \
863 const char *buf, size_t len) \
4d22de3e 864{ \
3e5192ee 865 return tm_attr_store(d, buf, len, sched); \
4d22de3e 866} \
0ee8d33c 867static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name)
4d22de3e
DLR		 868
869TM_ATTR(sched0, 0);
870TM_ATTR(sched1, 1);
871TM_ATTR(sched2, 2);
872TM_ATTR(sched3, 3);
873TM_ATTR(sched4, 4);
874TM_ATTR(sched5, 5);
875TM_ATTR(sched6, 6);
876TM_ATTR(sched7, 7);
877
878static struct attribute *offload_attrs[] = {
0ee8d33c
DLR		 879 &dev_attr_sched0.attr,
880 &dev_attr_sched1.attr,
881 &dev_attr_sched2.attr,
882 &dev_attr_sched3.attr,
883 &dev_attr_sched4.attr,
884 &dev_attr_sched5.attr,
885 &dev_attr_sched6.attr,
886 &dev_attr_sched7.attr,
4d22de3e
DLR		 887 NULL
888};
889
890static struct attribute_group offload_attr_group = {.attrs = offload_attrs };
891
892/*
893 * Sends an sk_buff to an offload queue driver
894 * after dealing with any active network taps.
895 */
896static inline int offload_tx(struct t3cdev *tdev, struct sk_buff *skb)
897{
898 int ret;
899
900 local_bh_disable();
901 ret = t3_offload_tx(tdev, skb);
902 local_bh_enable();
903 return ret;
904}
905
906static int write_smt_entry(struct adapter *adapter, int idx)
907{
908 struct cpl_smt_write_req *req;
f14d42f3 909 struct port_info *pi = netdev_priv(adapter->port[idx]);
4d22de3e
DLR		 910 struct sk_buff *skb = alloc_skb(sizeof(*req), GFP_KERNEL);
911
912 if (!skb)
913 return -ENOMEM;
914
915 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
916 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
917 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx));
918 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */
919 req->iff = idx;
4d22de3e 920 memcpy(req->src_mac0, adapter->port[idx]->dev_addr, ETH_ALEN);
f14d42f3 921 memcpy(req->src_mac1, pi->iscsic.mac_addr, ETH_ALEN);
4d22de3e
DLR		 922 skb->priority = 1;
923 offload_tx(&adapter->tdev, skb);
924 return 0;
925}
926
927static int init_smt(struct adapter *adapter)
928{
929 int i;
930
931 for_each_port(adapter, i)
932 write_smt_entry(adapter, i);
933 return 0;
934}
935
936static void init_port_mtus(struct adapter *adapter)
937{
938 unsigned int mtus = adapter->port[0]->mtu;
939
940 if (adapter->port[1])
941 mtus |= adapter->port[1]->mtu << 16;
942 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus);
943}
944
8c263761 945static int send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo,
14ab9892
DLR		 946 int hi, int port)
947{
948 struct sk_buff *skb;
949 struct mngt_pktsched_wr *req;
8c263761 950 int ret;
14ab9892 951
74b793e1
DLR		 952 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
953 if (!skb)
954 skb = adap->nofail_skb;
955 if (!skb)
956 return -ENOMEM;
957
14ab9892
DLR		 958 req = (struct mngt_pktsched_wr *)skb_put(skb, sizeof(*req));
959 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT));
960 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET;
961 req->sched = sched;
962 req->idx = qidx;
963 req->min = lo;
964 req->max = hi;
965 req->binding = port;
8c263761 966 ret = t3_mgmt_tx(adap, skb);
74b793e1
DLR		 967 if (skb == adap->nofail_skb) {
968 adap->nofail_skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
969 GFP_KERNEL);
970 if (!adap->nofail_skb)
971 ret = -ENOMEM;
972 }
8c263761
DLR		 973
974 return ret;
14ab9892
DLR		 975}
976
8c263761 977static int bind_qsets(struct adapter *adap)
14ab9892 978{
8c263761 979 int i, j, err = 0;
14ab9892
DLR		 980
981 for_each_port(adap, i) {
982 const struct port_info *pi = adap2pinfo(adap, i);
983
8c263761
DLR		 984 for (j = 0; j < pi->nqsets; ++j) {
985 int ret = send_pktsched_cmd(adap, 1,
986 pi->first_qset + j, -1,
987 -1, i);
988 if (ret)
989 err = ret;
990 }
14ab9892 991 }
8c263761
DLR		 992
993 return err;
14ab9892
DLR		 994}
995
34336ec0
BH		 996#define FW_VERSION __stringify(FW_VERSION_MAJOR) "." \
997 __stringify(FW_VERSION_MINOR) "." __stringify(FW_VERSION_MICRO)
998#define FW_FNAME "cxgb3/t3fw-" FW_VERSION ".bin"
999#define TPSRAM_VERSION __stringify(TP_VERSION_MAJOR) "." \
1000 __stringify(TP_VERSION_MINOR) "." __stringify(TP_VERSION_MICRO)
1001#define TPSRAM_NAME "cxgb3/t3%c_psram-" TPSRAM_VERSION ".bin"
2e8c07c3
DLR		 1002#define AEL2005_OPT_EDC_NAME "cxgb3/ael2005_opt_edc.bin"
1003#define AEL2005_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"
9450526a 1004#define AEL2020_TWX_EDC_NAME "cxgb3/ael2020_twx_edc.bin"
34336ec0
BH		 1005MODULE_FIRMWARE(FW_FNAME);
1006MODULE_FIRMWARE("cxgb3/t3b_psram-" TPSRAM_VERSION ".bin");
1007MODULE_FIRMWARE("cxgb3/t3c_psram-" TPSRAM_VERSION ".bin");
1008MODULE_FIRMWARE(AEL2005_OPT_EDC_NAME);
1009MODULE_FIRMWARE(AEL2005_TWX_EDC_NAME);
1010MODULE_FIRMWARE(AEL2020_TWX_EDC_NAME);
2e8c07c3
DLR		 1011
1012static inline const char *get_edc_fw_name(int edc_idx)
1013{
1014 const char *fw_name = NULL;
1015
1016 switch (edc_idx) {
1017 case EDC_OPT_AEL2005:
1018 fw_name = AEL2005_OPT_EDC_NAME;
1019 break;
1020 case EDC_TWX_AEL2005:
1021 fw_name = AEL2005_TWX_EDC_NAME;
1022 break;
1023 case EDC_TWX_AEL2020:
1024 fw_name = AEL2020_TWX_EDC_NAME;
1025 break;
1026 }
1027 return fw_name;
1028}
1029
1030int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size)
1031{
1032 struct adapter *adapter = phy->adapter;
1033 const struct firmware *fw;
1034 char buf[64];
1035 u32 csum;
1036 const __be32 *p;
1037 u16 *cache = phy->phy_cache;
1038 int i, ret;
1039
1040 snprintf(buf, sizeof(buf), get_edc_fw_name(edc_idx));
1041
1042 ret = request_firmware(&fw, buf, &adapter->pdev->dev);
1043 if (ret < 0) {
1044 dev_err(&adapter->pdev->dev,
1045 "could not upgrade firmware: unable to load %s\n",
1046 buf);
1047 return ret;
1048 }
1049
1050 /* check size, take checksum in account */
1051 if (fw->size > size + 4) {
1052 CH_ERR(adapter, "firmware image too large %u, expected %d\n",
1053 (unsigned int)fw->size, size + 4);
1054 ret = -EINVAL;
1055 }
1056
1057 /* compute checksum */
1058 p = (const __be32 *)fw->data;
1059 for (csum = 0, i = 0; i < fw->size / sizeof(csum); i++)
1060 csum += ntohl(p[i]);
1061
1062 if (csum != 0xffffffff) {
1063 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1064 csum);
1065 ret = -EINVAL;
1066 }
1067
1068 for (i = 0; i < size / 4 ; i++) {
1069 *cache++ = (be32_to_cpu(p[i]) & 0xffff0000) >> 16;
1070 *cache++ = be32_to_cpu(p[i]) & 0xffff;
1071 }
1072
1073 release_firmware(fw);
1074
1075 return ret;
1076}
2e283962
DLR		 1077
1078static int upgrade_fw(struct adapter *adap)
1079{
1080 int ret;
2e283962
DLR		 1081 const struct firmware *fw;
1082 struct device *dev = &adap->pdev->dev;
1083
34336ec0 1084 ret = request_firmware(&fw, FW_FNAME, dev);
2e283962
DLR		 1085 if (ret < 0) {
1086 dev_err(dev, "could not upgrade firmware: unable to load %s\n",
34336ec0 1087 FW_FNAME);
2e283962
DLR		 1088 return ret;
1089 }
1090 ret = t3_load_fw(adap, fw->data, fw->size);
1091 release_firmware(fw);
47330077
DLR		 1092
1093 if (ret == 0)
1094 dev_info(dev, "successful upgrade to firmware %d.%d.%d\n",
1095 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
1096 else
1097 dev_err(dev, "failed to upgrade to firmware %d.%d.%d\n",
1098 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
2eab17ab 1099
47330077
DLR		 1100 return ret;
1101}
1102
1103static inline char t3rev2char(struct adapter *adapter)
1104{
1105 char rev = 0;
1106
1107 switch(adapter->params.rev) {
1108 case T3_REV_B:
1109 case T3_REV_B2:
1110 rev = 'b';
1111 break;
1aafee26
DLR		 1112 case T3_REV_C:
1113 rev = 'c';
1114 break;
47330077
DLR		 1115 }
1116 return rev;
1117}
1118
9265fabf 1119static int update_tpsram(struct adapter *adap)
47330077
DLR		 1120{
1121 const struct firmware *tpsram;
1122 char buf[64];
1123 struct device *dev = &adap->pdev->dev;
1124 int ret;
1125 char rev;
2eab17ab 1126
47330077
DLR		 1127 rev = t3rev2char(adap);
1128 if (!rev)
1129 return 0;
1130
34336ec0 1131 snprintf(buf, sizeof(buf), TPSRAM_NAME, rev);
47330077
DLR		 1132
1133 ret = request_firmware(&tpsram, buf, dev);
1134 if (ret < 0) {
1135 dev_err(dev, "could not load TP SRAM: unable to load %s\n",
1136 buf);
1137 return ret;
1138 }
2eab17ab 1139
47330077
DLR		 1140 ret = t3_check_tpsram(adap, tpsram->data, tpsram->size);
1141 if (ret)
2eab17ab 1142 goto release_tpsram;
47330077
DLR		 1143
1144 ret = t3_set_proto_sram(adap, tpsram->data);
1145 if (ret == 0)
1146 dev_info(dev,
1147 "successful update of protocol engine "
1148 "to %d.%d.%d\n",
1149 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1150 else
1151 dev_err(dev, "failed to update of protocol engine %d.%d.%d\n",
1152 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1153 if (ret)
1154 dev_err(dev, "loading protocol SRAM failed\n");
1155
1156release_tpsram:
1157 release_firmware(tpsram);
2eab17ab 1158
2e283962
DLR		 1159 return ret;
1160}
1161
4d22de3e
DLR		 1162/**
1163 * cxgb_up - enable the adapter
1164 * @adapter: adapter being enabled
1165 *
1166 * Called when the first port is enabled, this function performs the
1167 * actions necessary to make an adapter operational, such as completing
1168 * the initialization of HW modules, and enabling interrupts.
1169 *
1170 * Must be called with the rtnl lock held.
1171 */
1172static int cxgb_up(struct adapter *adap)
1173{
c54f5c24 1174 int err;
4d22de3e
DLR		 1175
1176 if (!(adap->flags & FULL_INIT_DONE)) {
8207befa 1177 err = t3_check_fw_version(adap);
a5a3b460 1178 if (err == -EINVAL) {
2e283962 1179 err = upgrade_fw(adap);
8207befa
DLR		 1180 CH_WARN(adap, "FW upgrade to %d.%d.%d %s\n",
1181 FW_VERSION_MAJOR, FW_VERSION_MINOR,
1182 FW_VERSION_MICRO, err ? "failed" : "succeeded");
a5a3b460 1183 }
4d22de3e 1184
8207befa 1185 err = t3_check_tpsram_version(adap);
47330077
DLR		 1186 if (err == -EINVAL) {
1187 err = update_tpsram(adap);
8207befa
DLR		 1188 CH_WARN(adap, "TP upgrade to %d.%d.%d %s\n",
1189 TP_VERSION_MAJOR, TP_VERSION_MINOR,
1190 TP_VERSION_MICRO, err ? "failed" : "succeeded");
47330077
DLR		 1191 }
1192
20d3fc11
DLR		 1193 /*
1194 * Clear interrupts now to catch errors if t3_init_hw fails.
1195 * We clear them again later as initialization may trigger
1196 * conditions that can interrupt.
1197 */
1198 t3_intr_clear(adap);
1199
4d22de3e
DLR		 1200 err = t3_init_hw(adap, 0);
1201 if (err)
1202 goto out;
1203
b881955b 1204 t3_set_reg_field(adap, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT);
6cdbd77e 1205 t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
bea3348e 1206
4d22de3e
DLR		 1207 err = setup_sge_qsets(adap);
1208 if (err)
1209 goto out;
1210
1211 setup_rss(adap);
48c4b6db
DLR		 1212 if (!(adap->flags & NAPI_INIT))
1213 init_napi(adap);
31563789
DLR		 1214
1215 t3_start_sge_timers(adap);
4d22de3e
DLR		 1216 adap->flags |= FULL_INIT_DONE;
1217 }
1218
1219 t3_intr_clear(adap);
1220
1221 if (adap->flags & USING_MSIX) {
1222 name_msix_vecs(adap);
1223 err = request_irq(adap->msix_info[0].vec,
1224 t3_async_intr_handler, 0,
1225 adap->msix_info[0].desc, adap);
1226 if (err)
1227 goto irq_err;
1228
42256f57
DLR		 1229 err = request_msix_data_irqs(adap);
1230 if (err) {
4d22de3e
DLR		 1231 free_irq(adap->msix_info[0].vec, adap);
1232 goto irq_err;
1233 }
1234 } else if ((err = request_irq(adap->pdev->irq,
1235 t3_intr_handler(adap,
1236 adap->sge.qs[0].rspq.
1237 polling),
2db6346f
TG		 1238 (adap->flags & USING_MSI) ?
1239 0 : IRQF_SHARED,
4d22de3e
DLR		 1240 adap->name, adap)))
1241 goto irq_err;
1242
bea3348e 1243 enable_all_napi(adap);
4d22de3e
DLR		 1244 t3_sge_start(adap);
1245 t3_intr_enable(adap);
14ab9892 1246
b881955b
DLR		 1247 if (adap->params.rev >= T3_REV_C && !(adap->flags & TP_PARITY_INIT) &&
1248 is_offload(adap) && init_tp_parity(adap) == 0)
1249 adap->flags |= TP_PARITY_INIT;
1250
1251 if (adap->flags & TP_PARITY_INIT) {
1252 t3_write_reg(adap, A_TP_INT_CAUSE,
1253 F_CMCACHEPERR | F_ARPLUTPERR);
1254 t3_write_reg(adap, A_TP_INT_ENABLE, 0x7fbfffff);
1255 }
1256
8c263761
DLR		 1257 if (!(adap->flags & QUEUES_BOUND)) {
1258 err = bind_qsets(adap);
1259 if (err) {
1260 CH_ERR(adap, "failed to bind qsets, err %d\n", err);
1261 t3_intr_disable(adap);
1262 free_irq_resources(adap);
1263 goto out;
1264 }
1265 adap->flags |= QUEUES_BOUND;
1266 }
14ab9892 1267
4d22de3e
DLR		 1268out:
1269 return err;
1270irq_err:
1271 CH_ERR(adap, "request_irq failed, err %d\n", err);
1272 goto out;
1273}
1274
1275/*
1276 * Release resources when all the ports and offloading have been stopped.
1277 */
1278static void cxgb_down(struct adapter *adapter)
1279{
1280 t3_sge_stop(adapter);
1281 spin_lock_irq(&adapter->work_lock); /* sync with PHY intr task */
1282 t3_intr_disable(adapter);
1283 spin_unlock_irq(&adapter->work_lock);
1284
8c263761 1285 free_irq_resources(adapter);
4d22de3e 1286 quiesce_rx(adapter);
c80b0c28 1287 flush_workqueue(cxgb3_wq); /* wait for external IRQ handler */
4d22de3e
DLR		 1288}
1289
1290static void schedule_chk_task(struct adapter *adap)
1291{
1292 unsigned int timeo;
1293
1294 timeo = adap->params.linkpoll_period ?
1295 (HZ * adap->params.linkpoll_period) / 10 :
1296 adap->params.stats_update_period * HZ;
1297 if (timeo)
1298 queue_delayed_work(cxgb3_wq, &adap->adap_check_task, timeo);
1299}
1300
1301static int offload_open(struct net_device *dev)
1302{
5fbf816f
DLR		 1303 struct port_info *pi = netdev_priv(dev);
1304 struct adapter *adapter = pi->adapter;
1305 struct t3cdev *tdev = dev2t3cdev(dev);
4d22de3e 1306 int adap_up = adapter->open_device_map & PORT_MASK;
c54f5c24 1307 int err;
4d22de3e
DLR		 1308
1309 if (test_and_set_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1310 return 0;
1311
1312 if (!adap_up && (err = cxgb_up(adapter)) < 0)
48c4b6db 1313 goto out;
4d22de3e
DLR		 1314
1315 t3_tp_set_offload_mode(adapter, 1);
1316 tdev->lldev = adapter->port[0];
1317 err = cxgb3_offload_activate(adapter);
1318 if (err)
1319 goto out;
1320
1321 init_port_mtus(adapter);
1322 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd,
1323 adapter->params.b_wnd,
1324 adapter->params.rev == 0 ?
1325 adapter->port[0]->mtu : 0xffff);
1326 init_smt(adapter);
1327
d96a51f6
DN		 1328 if (sysfs_create_group(&tdev->lldev->dev.kobj, &offload_attr_group))
1329 dev_dbg(&dev->dev, "cannot create sysfs group\n");
4d22de3e
DLR		 1330
1331 /* Call back all registered clients */
1332 cxgb3_add_clients(tdev);
1333
1334out:
1335 /* restore them in case the offload module has changed them */
1336 if (err) {
1337 t3_tp_set_offload_mode(adapter, 0);
1338 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1339 cxgb3_set_dummy_ops(tdev);
1340 }
1341 return err;
1342}
1343
1344static int offload_close(struct t3cdev *tdev)
1345{
1346 struct adapter *adapter = tdev2adap(tdev);
1347
1348 if (!test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1349 return 0;
1350
1351 /* Call back all registered clients */
1352 cxgb3_remove_clients(tdev);
1353
0ee8d33c 1354 sysfs_remove_group(&tdev->lldev->dev.kobj, &offload_attr_group);
4d22de3e 1355
c80b0c28
DLR		 1356 /* Flush work scheduled while releasing TIDs */
1357 flush_scheduled_work();
1358
4d22de3e
DLR		 1359 tdev->lldev = NULL;
1360 cxgb3_set_dummy_ops(tdev);
1361 t3_tp_set_offload_mode(adapter, 0);
1362 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1363
1364 if (!adapter->open_device_map)
1365 cxgb_down(adapter);
1366
1367 cxgb3_offload_deactivate(adapter);
1368 return 0;
1369}
1370
1371static int cxgb_open(struct net_device *dev)
1372{
4d22de3e 1373 struct port_info *pi = netdev_priv(dev);
5fbf816f 1374 struct adapter *adapter = pi->adapter;
4d22de3e 1375 int other_ports = adapter->open_device_map & PORT_MASK;
5fbf816f 1376 int err;
4d22de3e 1377
48c4b6db 1378 if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0)
4d22de3e
DLR		 1379 return err;
1380
1381 set_bit(pi->port_id, &adapter->open_device_map);
8ac3ba68 1382 if (is_offload(adapter) && !ofld_disable) {
4d22de3e
DLR		 1383 err = offload_open(dev);
1384 if (err)
1385 printk(KERN_WARNING
1386 "Could not initialize offload capabilities\n");
1387 }
1388
82ad3329 1389 dev->real_num_tx_queues = pi->nqsets;
4d22de3e
DLR		 1390 link_start(dev);
1391 t3_port_intr_enable(adapter, pi->port_id);
82ad3329 1392 netif_tx_start_all_queues(dev);
4d22de3e
DLR		 1393 if (!other_ports)
1394 schedule_chk_task(adapter);
1395
fa0d4c11 1396 cxgb3_event_notify(&adapter->tdev, OFFLOAD_PORT_UP, pi->port_id);
4d22de3e
DLR		 1397 return 0;
1398}
1399
1400static int cxgb_close(struct net_device *dev)
1401{
5fbf816f
DLR		 1402 struct port_info *pi = netdev_priv(dev);
1403 struct adapter *adapter = pi->adapter;
4d22de3e 1404
e8d19370
DLR		 1405
1406 if (!adapter->open_device_map)
1407 return 0;
1408
bf792094
DLR		 1409 /* Stop link fault interrupts */
1410 t3_xgm_intr_disable(adapter, pi->port_id);
1411 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
1412
5fbf816f 1413 t3_port_intr_disable(adapter, pi->port_id);
82ad3329 1414 netif_tx_stop_all_queues(dev);
5fbf816f 1415 pi->phy.ops->power_down(&pi->phy, 1);
4d22de3e 1416 netif_carrier_off(dev);
5fbf816f 1417 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX);
4d22de3e 1418
20d3fc11 1419 spin_lock_irq(&adapter->work_lock); /* sync with update task */
5fbf816f 1420 clear_bit(pi->port_id, &adapter->open_device_map);
20d3fc11 1421 spin_unlock_irq(&adapter->work_lock);
4d22de3e
DLR		 1422
1423 if (!(adapter->open_device_map & PORT_MASK))
c80b0c28 1424 cancel_delayed_work_sync(&adapter->adap_check_task);
4d22de3e
DLR		 1425
1426 if (!adapter->open_device_map)
1427 cxgb_down(adapter);
1428
fa0d4c11 1429 cxgb3_event_notify(&adapter->tdev, OFFLOAD_PORT_DOWN, pi->port_id);
4d22de3e
DLR		 1430 return 0;
1431}
1432
1433static struct net_device_stats *cxgb_get_stats(struct net_device *dev)
1434{
5fbf816f
DLR		 1435 struct port_info *pi = netdev_priv(dev);
1436 struct adapter *adapter = pi->adapter;
1437 struct net_device_stats *ns = &pi->netstats;
4d22de3e
DLR		 1438 const struct mac_stats *pstats;
1439
1440 spin_lock(&adapter->stats_lock);
5fbf816f 1441 pstats = t3_mac_update_stats(&pi->mac);
4d22de3e
DLR		 1442 spin_unlock(&adapter->stats_lock);
1443
1444 ns->tx_bytes = pstats->tx_octets;
1445 ns->tx_packets = pstats->tx_frames;
1446 ns->rx_bytes = pstats->rx_octets;
1447 ns->rx_packets = pstats->rx_frames;
1448 ns->multicast = pstats->rx_mcast_frames;
1449
1450 ns->tx_errors = pstats->tx_underrun;
1451 ns->rx_errors = pstats->rx_symbol_errs + pstats->rx_fcs_errs +
1452 pstats->rx_too_long + pstats->rx_jabber + pstats->rx_short +
1453 pstats->rx_fifo_ovfl;
1454
1455 /* detailed rx_errors */
1456 ns->rx_length_errors = pstats->rx_jabber + pstats->rx_too_long;
1457 ns->rx_over_errors = 0;
1458 ns->rx_crc_errors = pstats->rx_fcs_errs;
1459 ns->rx_frame_errors = pstats->rx_symbol_errs;
1460 ns->rx_fifo_errors = pstats->rx_fifo_ovfl;
1461 ns->rx_missed_errors = pstats->rx_cong_drops;
1462
1463 /* detailed tx_errors */
1464 ns->tx_aborted_errors = 0;
1465 ns->tx_carrier_errors = 0;
1466 ns->tx_fifo_errors = pstats->tx_underrun;
1467 ns->tx_heartbeat_errors = 0;
1468 ns->tx_window_errors = 0;
1469 return ns;
1470}
1471
1472static u32 get_msglevel(struct net_device *dev)
1473{
5fbf816f
DLR		 1474 struct port_info *pi = netdev_priv(dev);
1475 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1476
1477 return adapter->msg_enable;
1478}
1479
1480static void set_msglevel(struct net_device *dev, u32 val)
1481{
5fbf816f
DLR		 1482 struct port_info *pi = netdev_priv(dev);
1483 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1484
1485 adapter->msg_enable = val;
1486}
1487
1488static char stats_strings[][ETH_GSTRING_LEN] = {
1489 "TxOctetsOK ",
1490 "TxFramesOK ",
1491 "TxMulticastFramesOK",
1492 "TxBroadcastFramesOK",
1493 "TxPauseFrames ",
1494 "TxUnderrun ",
1495 "TxExtUnderrun ",
1496
1497 "TxFrames64 ",
1498 "TxFrames65To127 ",
1499 "TxFrames128To255 ",
1500 "TxFrames256To511 ",
1501 "TxFrames512To1023 ",
1502 "TxFrames1024To1518 ",
1503 "TxFrames1519ToMax ",
1504
1505 "RxOctetsOK ",
1506 "RxFramesOK ",
1507 "RxMulticastFramesOK",
1508 "RxBroadcastFramesOK",
1509 "RxPauseFrames ",
1510 "RxFCSErrors ",
1511 "RxSymbolErrors ",
1512 "RxShortErrors ",
1513 "RxJabberErrors ",
1514 "RxLengthErrors ",
1515 "RxFIFOoverflow ",
1516
1517 "RxFrames64 ",
1518 "RxFrames65To127 ",
1519 "RxFrames128To255 ",
1520 "RxFrames256To511 ",
1521 "RxFrames512To1023 ",
1522 "RxFrames1024To1518 ",
1523 "RxFrames1519ToMax ",
1524
1525 "PhyFIFOErrors ",
1526 "TSO ",
1527 "VLANextractions ",
1528 "VLANinsertions ",
1529 "TxCsumOffload ",
1530 "RxCsumGood ",
b47385bd
DLR		 1531 "LroAggregated ",
1532 "LroFlushed ",
1533 "LroNoDesc ",
fc90664e
DLR		 1534 "RxDrops ",
1535
1536 "CheckTXEnToggled ",
1537 "CheckResets ",
1538
bf792094 1539 "LinkFaults ",
4d22de3e
DLR		 1540};
1541
b9f2c044 1542static int get_sset_count(struct net_device *dev, int sset)
4d22de3e 1543{
b9f2c044
JG		 1544 switch (sset) {
1545 case ETH_SS_STATS:
1546 return ARRAY_SIZE(stats_strings);
1547 default:
1548 return -EOPNOTSUPP;
1549 }
4d22de3e
DLR		 1550}
1551
1552#define T3_REGMAP_SIZE (3 * 1024)
1553
1554static int get_regs_len(struct net_device *dev)
1555{
1556 return T3_REGMAP_SIZE;
1557}
1558
1559static int get_eeprom_len(struct net_device *dev)
1560{
1561 return EEPROMSIZE;
1562}
1563
1564static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1565{
5fbf816f
DLR		 1566 struct port_info *pi = netdev_priv(dev);
1567 struct adapter *adapter = pi->adapter;
4d22de3e 1568 u32 fw_vers = 0;
47330077 1569 u32 tp_vers = 0;
4d22de3e 1570
cf3760da 1571 spin_lock(&adapter->stats_lock);
4d22de3e 1572 t3_get_fw_version(adapter, &fw_vers);
47330077 1573 t3_get_tp_version(adapter, &tp_vers);
cf3760da 1574 spin_unlock(&adapter->stats_lock);
4d22de3e
DLR		 1575
1576 strcpy(info->driver, DRV_NAME);
1577 strcpy(info->version, DRV_VERSION);
1578 strcpy(info->bus_info, pci_name(adapter->pdev));
1579 if (!fw_vers)
1580 strcpy(info->fw_version, "N/A");
4aac3899 1581 else {
4d22de3e 1582 snprintf(info->fw_version, sizeof(info->fw_version),
47330077 1583 "%s %u.%u.%u TP %u.%u.%u",
4aac3899
DLR		 1584 G_FW_VERSION_TYPE(fw_vers) ? "T" : "N",
1585 G_FW_VERSION_MAJOR(fw_vers),
1586 G_FW_VERSION_MINOR(fw_vers),
47330077
DLR		 1587 G_FW_VERSION_MICRO(fw_vers),
1588 G_TP_VERSION_MAJOR(tp_vers),
1589 G_TP_VERSION_MINOR(tp_vers),
1590 G_TP_VERSION_MICRO(tp_vers));
4aac3899 1591 }
4d22de3e
DLR		 1592}
1593
1594static void get_strings(struct net_device *dev, u32 stringset, u8 * data)
1595{
1596 if (stringset == ETH_SS_STATS)
1597 memcpy(data, stats_strings, sizeof(stats_strings));
1598}
1599
1600static unsigned long collect_sge_port_stats(struct adapter *adapter,
1601 struct port_info *p, int idx)
1602{
1603 int i;
1604 unsigned long tot = 0;
1605
8c263761
DLR		 1606 for (i = p->first_qset; i < p->first_qset + p->nqsets; ++i)
1607 tot += adapter->sge.qs[i].port_stats[idx];
4d22de3e
DLR		 1608 return tot;
1609}
1610
1611static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1612 u64 *data)
1613{
4d22de3e 1614 struct port_info *pi = netdev_priv(dev);
5fbf816f 1615 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1616 const struct mac_stats *s;
1617
1618 spin_lock(&adapter->stats_lock);
1619 s = t3_mac_update_stats(&pi->mac);
1620 spin_unlock(&adapter->stats_lock);
1621
1622 *data++ = s->tx_octets;
1623 *data++ = s->tx_frames;
1624 *data++ = s->tx_mcast_frames;
1625 *data++ = s->tx_bcast_frames;
1626 *data++ = s->tx_pause;
1627 *data++ = s->tx_underrun;
1628 *data++ = s->tx_fifo_urun;
1629
1630 *data++ = s->tx_frames_64;
1631 *data++ = s->tx_frames_65_127;
1632 *data++ = s->tx_frames_128_255;
1633 *data++ = s->tx_frames_256_511;
1634 *data++ = s->tx_frames_512_1023;
1635 *data++ = s->tx_frames_1024_1518;
1636 *data++ = s->tx_frames_1519_max;
1637
1638 *data++ = s->rx_octets;
1639 *data++ = s->rx_frames;
1640 *data++ = s->rx_mcast_frames;
1641 *data++ = s->rx_bcast_frames;
1642 *data++ = s->rx_pause;
1643 *data++ = s->rx_fcs_errs;
1644 *data++ = s->rx_symbol_errs;
1645 *data++ = s->rx_short;
1646 *data++ = s->rx_jabber;
1647 *data++ = s->rx_too_long;
1648 *data++ = s->rx_fifo_ovfl;
1649
1650 *data++ = s->rx_frames_64;
1651 *data++ = s->rx_frames_65_127;
1652 *data++ = s->rx_frames_128_255;
1653 *data++ = s->rx_frames_256_511;
1654 *data++ = s->rx_frames_512_1023;
1655 *data++ = s->rx_frames_1024_1518;
1656 *data++ = s->rx_frames_1519_max;
1657
1658 *data++ = pi->phy.fifo_errors;
1659
1660 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TSO);
1661 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANEX);
1662 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANINS);
1663 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM);
1664 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD);
7be2df45
HX		 1665 *data++ = 0;
1666 *data++ = 0;
1667 *data++ = 0;
4d22de3e 1668 *data++ = s->rx_cong_drops;
fc90664e
DLR		 1669
1670 *data++ = s->num_toggled;
1671 *data++ = s->num_resets;
bf792094
DLR		 1672
1673 *data++ = s->link_faults;
4d22de3e
DLR		 1674}
1675
1676static inline void reg_block_dump(struct adapter *ap, void *buf,
1677 unsigned int start, unsigned int end)
1678{
1679 u32 *p = buf + start;
1680
1681 for (; start <= end; start += sizeof(u32))
1682 *p++ = t3_read_reg(ap, start);
1683}
1684
1685static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1686 void *buf)
1687{
5fbf816f
DLR		 1688 struct port_info *pi = netdev_priv(dev);
1689 struct adapter *ap = pi->adapter;
4d22de3e
DLR		 1690
1691 /*
1692 * Version scheme:
1693 * bits 0..9: chip version
1694 * bits 10..15: chip revision
1695 * bit 31: set for PCIe cards
1696 */
1697 regs->version = 3 | (ap->params.rev << 10) | (is_pcie(ap) << 31);
1698
1699 /*
1700 * We skip the MAC statistics registers because they are clear-on-read.
1701 * Also reading multi-register stats would need to synchronize with the
1702 * periodic mac stats accumulation. Hard to justify the complexity.
1703 */
1704 memset(buf, 0, T3_REGMAP_SIZE);
1705 reg_block_dump(ap, buf, 0, A_SG_RSPQ_CREDIT_RETURN);
1706 reg_block_dump(ap, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT);
1707 reg_block_dump(ap, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE);
1708 reg_block_dump(ap, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA);
1709 reg_block_dump(ap, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3);
1710 reg_block_dump(ap, buf, A_XGM_SERDES_STATUS0,
1711 XGM_REG(A_XGM_SERDES_STAT3, 1));
1712 reg_block_dump(ap, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1),
1713 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1));
1714}
1715
1716static int restart_autoneg(struct net_device *dev)
1717{
1718 struct port_info *p = netdev_priv(dev);
1719
1720 if (!netif_running(dev))
1721 return -EAGAIN;
1722 if (p->link_config.autoneg != AUTONEG_ENABLE)
1723 return -EINVAL;
1724 p->phy.ops->autoneg_restart(&p->phy);
1725 return 0;
1726}
1727
1728static int cxgb3_phys_id(struct net_device *dev, u32 data)
1729{
5fbf816f
DLR		 1730 struct port_info *pi = netdev_priv(dev);
1731 struct adapter *adapter = pi->adapter;
4d22de3e 1732 int i;
4d22de3e
DLR		 1733
1734 if (data == 0)
1735 data = 2;
1736
1737 for (i = 0; i < data * 2; i++) {
1738 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1739 (i & 1) ? F_GPIO0_OUT_VAL : 0);
1740 if (msleep_interruptible(500))
1741 break;
1742 }
1743 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1744 F_GPIO0_OUT_VAL);
1745 return 0;
1746}
1747
1748static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1749{
1750 struct port_info *p = netdev_priv(dev);
1751
1752 cmd->supported = p->link_config.supported;
1753 cmd->advertising = p->link_config.advertising;
1754
1755 if (netif_carrier_ok(dev)) {
1756 cmd->speed = p->link_config.speed;
1757 cmd->duplex = p->link_config.duplex;
1758 } else {
1759 cmd->speed = -1;
1760 cmd->duplex = -1;
1761 }
1762
1763 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
0f07c4ee 1764 cmd->phy_address = p->phy.mdio.prtad;
4d22de3e
DLR		 1765 cmd->transceiver = XCVR_EXTERNAL;
1766 cmd->autoneg = p->link_config.autoneg;
1767 cmd->maxtxpkt = 0;
1768 cmd->maxrxpkt = 0;
1769 return 0;
1770}
1771
1772static int speed_duplex_to_caps(int speed, int duplex)
1773{
1774 int cap = 0;
1775
1776 switch (speed) {
1777 case SPEED_10:
1778 if (duplex == DUPLEX_FULL)
1779 cap = SUPPORTED_10baseT_Full;
1780 else
1781 cap = SUPPORTED_10baseT_Half;
1782 break;
1783 case SPEED_100:
1784 if (duplex == DUPLEX_FULL)
1785 cap = SUPPORTED_100baseT_Full;
1786 else
1787 cap = SUPPORTED_100baseT_Half;
1788 break;
1789 case SPEED_1000:
1790 if (duplex == DUPLEX_FULL)
1791 cap = SUPPORTED_1000baseT_Full;
1792 else
1793 cap = SUPPORTED_1000baseT_Half;
1794 break;
1795 case SPEED_10000:
1796 if (duplex == DUPLEX_FULL)
1797 cap = SUPPORTED_10000baseT_Full;
1798 }
1799 return cap;
1800}
1801
1802#define ADVERTISED_MASK (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1803 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1804 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | \
1805 ADVERTISED_10000baseT_Full)
1806
1807static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1808{
1809 struct port_info *p = netdev_priv(dev);
1810 struct link_config *lc = &p->link_config;
1811
9b1e3656
DLR		 1812 if (!(lc->supported & SUPPORTED_Autoneg)) {
1813 /*
1814 * PHY offers a single speed/duplex. See if that's what's
1815 * being requested.
1816 */
1817 if (cmd->autoneg == AUTONEG_DISABLE) {
97915b5b 1818 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
9b1e3656
DLR		 1819 if (lc->supported & cap)
1820 return 0;
1821 }
1822 return -EINVAL;
1823 }
4d22de3e
DLR		 1824
1825 if (cmd->autoneg == AUTONEG_DISABLE) {
1826 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
1827
1828 if (!(lc->supported & cap) || cmd->speed == SPEED_1000)
1829 return -EINVAL;
1830 lc->requested_speed = cmd->speed;
1831 lc->requested_duplex = cmd->duplex;
1832 lc->advertising = 0;
1833 } else {
1834 cmd->advertising &= ADVERTISED_MASK;
1835 cmd->advertising &= lc->supported;
1836 if (!cmd->advertising)
1837 return -EINVAL;
1838 lc->requested_speed = SPEED_INVALID;
1839 lc->requested_duplex = DUPLEX_INVALID;
1840 lc->advertising = cmd->advertising | ADVERTISED_Autoneg;
1841 }
1842 lc->autoneg = cmd->autoneg;
1843 if (netif_running(dev))
1844 t3_link_start(&p->phy, &p->mac, lc);
1845 return 0;
1846}
1847
1848static void get_pauseparam(struct net_device *dev,
1849 struct ethtool_pauseparam *epause)
1850{
1851 struct port_info *p = netdev_priv(dev);
1852
1853 epause->autoneg = (p->link_config.requested_fc & PAUSE_AUTONEG) != 0;
1854 epause->rx_pause = (p->link_config.fc & PAUSE_RX) != 0;
1855 epause->tx_pause = (p->link_config.fc & PAUSE_TX) != 0;
1856}
1857
1858static int set_pauseparam(struct net_device *dev,
1859 struct ethtool_pauseparam *epause)
1860{
1861 struct port_info *p = netdev_priv(dev);
1862 struct link_config *lc = &p->link_config;
1863
1864 if (epause->autoneg == AUTONEG_DISABLE)
1865 lc->requested_fc = 0;
1866 else if (lc->supported & SUPPORTED_Autoneg)
1867 lc->requested_fc = PAUSE_AUTONEG;
1868 else
1869 return -EINVAL;
1870
1871 if (epause->rx_pause)
1872 lc->requested_fc |= PAUSE_RX;
1873 if (epause->tx_pause)
1874 lc->requested_fc |= PAUSE_TX;
1875 if (lc->autoneg == AUTONEG_ENABLE) {
1876 if (netif_running(dev))
1877 t3_link_start(&p->phy, &p->mac, lc);
1878 } else {
1879 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1880 if (netif_running(dev))
1881 t3_mac_set_speed_duplex_fc(&p->mac, -1, -1, lc->fc);
1882 }
1883 return 0;
1884}
1885
1886static u32 get_rx_csum(struct net_device *dev)
1887{
1888 struct port_info *p = netdev_priv(dev);
1889
47fd23fe 1890 return p->rx_offload & T3_RX_CSUM;
4d22de3e
DLR		 1891}
1892
1893static int set_rx_csum(struct net_device *dev, u32 data)
1894{
1895 struct port_info *p = netdev_priv(dev);
1896
47fd23fe
RD		 1897 if (data) {
1898 p->rx_offload |= T3_RX_CSUM;
1899 } else {
b47385bd
DLR		 1900 int i;
1901
47fd23fe 1902 p->rx_offload &= ~(T3_RX_CSUM | T3_LRO);
04ecb072
DLR		 1903 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++)
1904 set_qset_lro(dev, i, 0);
b47385bd 1905 }
4d22de3e
DLR		 1906 return 0;
1907}
1908
1909static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1910{
5fbf816f
DLR		 1911 struct port_info *pi = netdev_priv(dev);
1912 struct adapter *adapter = pi->adapter;
05b97b30 1913 const struct qset_params *q = &adapter->params.sge.qset[pi->first_qset];
4d22de3e
DLR		 1914
1915 e->rx_max_pending = MAX_RX_BUFFERS;
1916 e->rx_mini_max_pending = 0;
1917 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS;
1918 e->tx_max_pending = MAX_TXQ_ENTRIES;
1919
05b97b30
DLR		 1920 e->rx_pending = q->fl_size;
1921 e->rx_mini_pending = q->rspq_size;
1922 e->rx_jumbo_pending = q->jumbo_size;
1923 e->tx_pending = q->txq_size[0];
4d22de3e
DLR		 1924}
1925
1926static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1927{
5fbf816f
DLR		 1928 struct port_info *pi = netdev_priv(dev);
1929 struct adapter *adapter = pi->adapter;
05b97b30 1930 struct qset_params *q;
5fbf816f 1931 int i;
4d22de3e
DLR		 1932
1933 if (e->rx_pending > MAX_RX_BUFFERS ||
1934 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS ||
1935 e->tx_pending > MAX_TXQ_ENTRIES ||
1936 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1937 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1938 e->rx_pending < MIN_FL_ENTRIES ||
1939 e->rx_jumbo_pending < MIN_FL_ENTRIES ||
1940 e->tx_pending < adapter->params.nports * MIN_TXQ_ENTRIES)
1941 return -EINVAL;
1942
1943 if (adapter->flags & FULL_INIT_DONE)
1944 return -EBUSY;
1945
05b97b30
DLR		 1946 q = &adapter->params.sge.qset[pi->first_qset];
1947 for (i = 0; i < pi->nqsets; ++i, ++q) {
4d22de3e
DLR		 1948 q->rspq_size = e->rx_mini_pending;
1949 q->fl_size = e->rx_pending;
1950 q->jumbo_size = e->rx_jumbo_pending;
1951 q->txq_size[0] = e->tx_pending;
1952 q->txq_size[1] = e->tx_pending;
1953 q->txq_size[2] = e->tx_pending;
1954 }
1955 return 0;
1956}
1957
1958static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1959{
5fbf816f
DLR		 1960 struct port_info *pi = netdev_priv(dev);
1961 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1962 struct qset_params *qsp = &adapter->params.sge.qset[0];
1963 struct sge_qset *qs = &adapter->sge.qs[0];
1964
1965 if (c->rx_coalesce_usecs * 10 > M_NEWTIMER)
1966 return -EINVAL;
1967
1968 qsp->coalesce_usecs = c->rx_coalesce_usecs;
1969 t3_update_qset_coalesce(qs, qsp);
1970 return 0;
1971}
1972
1973static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1974{
5fbf816f
DLR		 1975 struct port_info *pi = netdev_priv(dev);
1976 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1977 struct qset_params *q = adapter->params.sge.qset;
1978
1979 c->rx_coalesce_usecs = q->coalesce_usecs;
1980 return 0;
1981}
1982
1983static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
1984 u8 * data)
1985{
5fbf816f
DLR		 1986 struct port_info *pi = netdev_priv(dev);
1987 struct adapter *adapter = pi->adapter;
4d22de3e 1988 int i, err = 0;
4d22de3e
DLR		 1989
1990 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
1991 if (!buf)
1992 return -ENOMEM;
1993
1994 e->magic = EEPROM_MAGIC;
1995 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
05e5c116 1996 err = t3_seeprom_read(adapter, i, (__le32 *) & buf[i]);
4d22de3e
DLR		 1997
1998 if (!err)
1999 memcpy(data, buf + e->offset, e->len);
2000 kfree(buf);
2001 return err;
2002}
2003
2004static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2005 u8 * data)
2006{
5fbf816f
DLR		 2007 struct port_info *pi = netdev_priv(dev);
2008 struct adapter *adapter = pi->adapter;
05e5c116
AV		 2009 u32 aligned_offset, aligned_len;
2010 __le32 *p;
4d22de3e 2011 u8 *buf;
c54f5c24 2012 int err;
4d22de3e
DLR		 2013
2014 if (eeprom->magic != EEPROM_MAGIC)
2015 return -EINVAL;
2016
2017 aligned_offset = eeprom->offset & ~3;
2018 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2019
2020 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2021 buf = kmalloc(aligned_len, GFP_KERNEL);
2022 if (!buf)
2023 return -ENOMEM;
05e5c116 2024 err = t3_seeprom_read(adapter, aligned_offset, (__le32 *) buf);
4d22de3e
DLR		 2025 if (!err && aligned_len > 4)
2026 err = t3_seeprom_read(adapter,
2027 aligned_offset + aligned_len - 4,
05e5c116 2028 (__le32 *) & buf[aligned_len - 4]);
4d22de3e
DLR		 2029 if (err)
2030 goto out;
2031 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2032 } else
2033 buf = data;
2034
2035 err = t3_seeprom_wp(adapter, 0);
2036 if (err)
2037 goto out;
2038
05e5c116 2039 for (p = (__le32 *) buf; !err && aligned_len; aligned_len -= 4, p++) {
4d22de3e
DLR		 2040 err = t3_seeprom_write(adapter, aligned_offset, *p);
2041 aligned_offset += 4;
2042 }
2043
2044 if (!err)
2045 err = t3_seeprom_wp(adapter, 1);
2046out:
2047 if (buf != data)
2048 kfree(buf);
2049 return err;
2050}
2051
2052static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2053{
2054 wol->supported = 0;
2055 wol->wolopts = 0;
2056 memset(&wol->sopass, 0, sizeof(wol->sopass));
2057}
2058
2059static const struct ethtool_ops cxgb_ethtool_ops = {
2060 .get_settings = get_settings,
2061 .set_settings = set_settings,
2062 .get_drvinfo = get_drvinfo,
2063 .get_msglevel = get_msglevel,
2064 .set_msglevel = set_msglevel,
2065 .get_ringparam = get_sge_param,
2066 .set_ringparam = set_sge_param,
2067 .get_coalesce = get_coalesce,
2068 .set_coalesce = set_coalesce,
2069 .get_eeprom_len = get_eeprom_len,
2070 .get_eeprom = get_eeprom,
2071 .set_eeprom = set_eeprom,
2072 .get_pauseparam = get_pauseparam,
2073 .set_pauseparam = set_pauseparam,
2074 .get_rx_csum = get_rx_csum,
2075 .set_rx_csum = set_rx_csum,
4d22de3e 2076 .set_tx_csum = ethtool_op_set_tx_csum,
4d22de3e
DLR		 2077 .set_sg = ethtool_op_set_sg,
2078 .get_link = ethtool_op_get_link,
2079 .get_strings = get_strings,
2080 .phys_id = cxgb3_phys_id,
2081 .nway_reset = restart_autoneg,
b9f2c044 2082 .get_sset_count = get_sset_count,
4d22de3e
DLR		 2083 .get_ethtool_stats = get_stats,
2084 .get_regs_len = get_regs_len,
2085 .get_regs = get_regs,
2086 .get_wol = get_wol,
4d22de3e 2087 .set_tso = ethtool_op_set_tso,
4d22de3e
DLR		 2088};
2089
2090static int in_range(int val, int lo, int hi)
2091{
2092 return val < 0 || (val <= hi && val >= lo);
2093}
2094
2095static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr)
2096{
5fbf816f
DLR		 2097 struct port_info *pi = netdev_priv(dev);
2098 struct adapter *adapter = pi->adapter;
4d22de3e 2099 u32 cmd;
5fbf816f 2100 int ret;
4d22de3e
DLR		 2101
2102 if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
2103 return -EFAULT;
2104
2105 switch (cmd) {
4d22de3e
DLR		 2106 case CHELSIO_SET_QSET_PARAMS:{
2107 int i;
2108 struct qset_params *q;
2109 struct ch_qset_params t;
8c263761
DLR		 2110 int q1 = pi->first_qset;
2111 int nqsets = pi->nqsets;
4d22de3e
DLR		 2112
2113 if (!capable(CAP_NET_ADMIN))
2114 return -EPERM;
2115 if (copy_from_user(&t, useraddr, sizeof(t)))
2116 return -EFAULT;
2117 if (t.qset_idx >= SGE_QSETS)
2118 return -EINVAL;
2119 if (!in_range(t.intr_lat, 0, M_NEWTIMER) ||
8e95a202
JP		 2120 !in_range(t.cong_thres, 0, 255) ||
2121 !in_range(t.txq_size[0], MIN_TXQ_ENTRIES,
2122 MAX_TXQ_ENTRIES) ||
2123 !in_range(t.txq_size[1], MIN_TXQ_ENTRIES,
2124 MAX_TXQ_ENTRIES) ||
2125 !in_range(t.txq_size[2], MIN_CTRL_TXQ_ENTRIES,
2126 MAX_CTRL_TXQ_ENTRIES) ||
2127 !in_range(t.fl_size[0], MIN_FL_ENTRIES,
2128 MAX_RX_BUFFERS) ||
2129 !in_range(t.fl_size[1], MIN_FL_ENTRIES,
2130 MAX_RX_JUMBO_BUFFERS) ||
2131 !in_range(t.rspq_size, MIN_RSPQ_ENTRIES,
2132 MAX_RSPQ_ENTRIES))
4d22de3e 2133 return -EINVAL;
8c263761
DLR		 2134
2135 if ((adapter->flags & FULL_INIT_DONE) && t.lro > 0)
2136 for_each_port(adapter, i) {
2137 pi = adap2pinfo(adapter, i);
2138 if (t.qset_idx >= pi->first_qset &&
2139 t.qset_idx < pi->first_qset + pi->nqsets &&
47fd23fe 2140 !(pi->rx_offload & T3_RX_CSUM))
8c263761
DLR		 2141 return -EINVAL;
2142 }
2143
4d22de3e
DLR		 2144 if ((adapter->flags & FULL_INIT_DONE) &&
2145 (t.rspq_size >= 0 || t.fl_size[0] >= 0 ||
2146 t.fl_size[1] >= 0 || t.txq_size[0] >= 0 ||
2147 t.txq_size[1] >= 0 || t.txq_size[2] >= 0 ||
2148 t.polling >= 0 || t.cong_thres >= 0))
2149 return -EBUSY;
2150
8c263761
DLR		 2151 /* Allow setting of any available qset when offload enabled */
2152 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2153 q1 = 0;
2154 for_each_port(adapter, i) {
2155 pi = adap2pinfo(adapter, i);
2156 nqsets += pi->first_qset + pi->nqsets;
2157 }
2158 }
2159
2160 if (t.qset_idx < q1)
2161 return -EINVAL;
2162 if (t.qset_idx > q1 + nqsets - 1)
2163 return -EINVAL;
2164
4d22de3e
DLR		 2165 q = &adapter->params.sge.qset[t.qset_idx];
2166
2167 if (t.rspq_size >= 0)
2168 q->rspq_size = t.rspq_size;
2169 if (t.fl_size[0] >= 0)
2170 q->fl_size = t.fl_size[0];
2171 if (t.fl_size[1] >= 0)
2172 q->jumbo_size = t.fl_size[1];
2173 if (t.txq_size[0] >= 0)
2174 q->txq_size[0] = t.txq_size[0];
2175 if (t.txq_size[1] >= 0)
2176 q->txq_size[1] = t.txq_size[1];
2177 if (t.txq_size[2] >= 0)
2178 q->txq_size[2] = t.txq_size[2];
2179 if (t.cong_thres >= 0)
2180 q->cong_thres = t.cong_thres;
2181 if (t.intr_lat >= 0) {
2182 struct sge_qset *qs =
2183 &adapter->sge.qs[t.qset_idx];
2184
2185 q->coalesce_usecs = t.intr_lat;
2186 t3_update_qset_coalesce(qs, q);
2187 }
2188 if (t.polling >= 0) {
2189 if (adapter->flags & USING_MSIX)
2190 q->polling = t.polling;
2191 else {
2192 /* No polling with INTx for T3A */
2193 if (adapter->params.rev == 0 &&
2194 !(adapter->flags & USING_MSI))
2195 t.polling = 0;
2196
2197 for (i = 0; i < SGE_QSETS; i++) {
2198 q = &adapter->params.sge.
2199 qset[i];
2200 q->polling = t.polling;
2201 }
2202 }
2203 }
04ecb072
DLR		 2204 if (t.lro >= 0)
2205 set_qset_lro(dev, t.qset_idx, t.lro);
2206
4d22de3e
DLR		 2207 break;
2208 }
2209 case CHELSIO_GET_QSET_PARAMS:{
2210 struct qset_params *q;
2211 struct ch_qset_params t;
8c263761
DLR		 2212 int q1 = pi->first_qset;
2213 int nqsets = pi->nqsets;
2214 int i;
4d22de3e
DLR		 2215
2216 if (copy_from_user(&t, useraddr, sizeof(t)))
2217 return -EFAULT;
8c263761
DLR		 2218
2219 /* Display qsets for all ports when offload enabled */
2220 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2221 q1 = 0;
2222 for_each_port(adapter, i) {
2223 pi = adap2pinfo(adapter, i);
2224 nqsets = pi->first_qset + pi->nqsets;
2225 }
2226 }
2227
2228 if (t.qset_idx >= nqsets)
4d22de3e
DLR		 2229 return -EINVAL;
2230
8c263761 2231 q = &adapter->params.sge.qset[q1 + t.qset_idx];
4d22de3e
DLR		 2232 t.rspq_size = q->rspq_size;
2233 t.txq_size[0] = q->txq_size[0];
2234 t.txq_size[1] = q->txq_size[1];
2235 t.txq_size[2] = q->txq_size[2];
2236 t.fl_size[0] = q->fl_size;
2237 t.fl_size[1] = q->jumbo_size;
2238 t.polling = q->polling;
b47385bd 2239 t.lro = q->lro;
4d22de3e
DLR		 2240 t.intr_lat = q->coalesce_usecs;
2241 t.cong_thres = q->cong_thres;
8c263761
DLR		 2242 t.qnum = q1;
2243
2244 if (adapter->flags & USING_MSIX)
2245 t.vector = adapter->msix_info[q1 + t.qset_idx + 1].vec;
2246 else
2247 t.vector = adapter->pdev->irq;
4d22de3e
DLR		 2248
2249 if (copy_to_user(useraddr, &t, sizeof(t)))
2250 return -EFAULT;
2251 break;
2252 }
2253 case CHELSIO_SET_QSET_NUM:{
2254 struct ch_reg edata;
4d22de3e
DLR		 2255 unsigned int i, first_qset = 0, other_qsets = 0;
2256
2257 if (!capable(CAP_NET_ADMIN))
2258 return -EPERM;
2259 if (adapter->flags & FULL_INIT_DONE)
2260 return -EBUSY;
2261 if (copy_from_user(&edata, useraddr, sizeof(edata)))
2262 return -EFAULT;
2263 if (edata.val < 1 ||
2264 (edata.val > 1 && !(adapter->flags & USING_MSIX)))
2265 return -EINVAL;
2266
2267 for_each_port(adapter, i)
2268 if (adapter->port[i] && adapter->port[i] != dev)
2269 other_qsets += adap2pinfo(adapter, i)->nqsets;
2270
2271 if (edata.val + other_qsets > SGE_QSETS)
2272 return -EINVAL;
2273
2274 pi->nqsets = edata.val;
2275
2276 for_each_port(adapter, i)
2277 if (adapter->port[i]) {
2278 pi = adap2pinfo(adapter, i);
2279 pi->first_qset = first_qset;
2280 first_qset += pi->nqsets;
2281 }
2282 break;
2283 }
2284 case CHELSIO_GET_QSET_NUM:{
2285 struct ch_reg edata;
4d22de3e
DLR		 2286
2287 edata.cmd = CHELSIO_GET_QSET_NUM;
2288 edata.val = pi->nqsets;
2289 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2290 return -EFAULT;
2291 break;
2292 }
2293 case CHELSIO_LOAD_FW:{
2294 u8 *fw_data;
2295 struct ch_mem_range t;
2296
1b3aa7af 2297 if (!capable(CAP_SYS_RAWIO))
4d22de3e
DLR		 2298 return -EPERM;
2299 if (copy_from_user(&t, useraddr, sizeof(t)))
2300 return -EFAULT;
1b3aa7af 2301 /* Check t.len sanity ? */
4d22de3e
DLR		 2302 fw_data = kmalloc(t.len, GFP_KERNEL);
2303 if (!fw_data)
2304 return -ENOMEM;
2305
2306 if (copy_from_user
2307 (fw_data, useraddr + sizeof(t), t.len)) {
2308 kfree(fw_data);
2309 return -EFAULT;
2310 }
2311
2312 ret = t3_load_fw(adapter, fw_data, t.len);
2313 kfree(fw_data);
2314 if (ret)
2315 return ret;
2316 break;
2317 }
2318 case CHELSIO_SETMTUTAB:{
2319 struct ch_mtus m;
2320 int i;
2321
2322 if (!is_offload(adapter))
2323 return -EOPNOTSUPP;
2324 if (!capable(CAP_NET_ADMIN))
2325 return -EPERM;
2326 if (offload_running(adapter))
2327 return -EBUSY;
2328 if (copy_from_user(&m, useraddr, sizeof(m)))
2329 return -EFAULT;
2330 if (m.nmtus != NMTUS)
2331 return -EINVAL;
2332 if (m.mtus[0] < 81) /* accommodate SACK */
2333 return -EINVAL;
2334
2335 /* MTUs must be in ascending order */
2336 for (i = 1; i < NMTUS; ++i)
2337 if (m.mtus[i] < m.mtus[i - 1])
2338 return -EINVAL;
2339
2340 memcpy(adapter->params.mtus, m.mtus,
2341 sizeof(adapter->params.mtus));
2342 break;
2343 }
2344 case CHELSIO_GET_PM:{
2345 struct tp_params *p = &adapter->params.tp;
2346 struct ch_pm m = {.cmd = CHELSIO_GET_PM };
2347
2348 if (!is_offload(adapter))
2349 return -EOPNOTSUPP;
2350 m.tx_pg_sz = p->tx_pg_size;
2351 m.tx_num_pg = p->tx_num_pgs;
2352 m.rx_pg_sz = p->rx_pg_size;
2353 m.rx_num_pg = p->rx_num_pgs;
2354 m.pm_total = p->pmtx_size + p->chan_rx_size * p->nchan;
2355 if (copy_to_user(useraddr, &m, sizeof(m)))
2356 return -EFAULT;
2357 break;
2358 }
2359 case CHELSIO_SET_PM:{
2360 struct ch_pm m;
2361 struct tp_params *p = &adapter->params.tp;
2362
2363 if (!is_offload(adapter))
2364 return -EOPNOTSUPP;
2365 if (!capable(CAP_NET_ADMIN))
2366 return -EPERM;
2367 if (adapter->flags & FULL_INIT_DONE)
2368 return -EBUSY;
2369 if (copy_from_user(&m, useraddr, sizeof(m)))
2370 return -EFAULT;
d9da466a 2371 if (!is_power_of_2(m.rx_pg_sz) ||
2372 !is_power_of_2(m.tx_pg_sz))
4d22de3e
DLR		 2373 return -EINVAL; /* not power of 2 */
2374 if (!(m.rx_pg_sz & 0x14000))
2375 return -EINVAL; /* not 16KB or 64KB */
2376 if (!(m.tx_pg_sz & 0x1554000))
2377 return -EINVAL;
2378 if (m.tx_num_pg == -1)
2379 m.tx_num_pg = p->tx_num_pgs;
2380 if (m.rx_num_pg == -1)
2381 m.rx_num_pg = p->rx_num_pgs;
2382 if (m.tx_num_pg % 24 || m.rx_num_pg % 24)
2383 return -EINVAL;
2384 if (m.rx_num_pg * m.rx_pg_sz > p->chan_rx_size ||
2385 m.tx_num_pg * m.tx_pg_sz > p->chan_tx_size)
2386 return -EINVAL;
2387 p->rx_pg_size = m.rx_pg_sz;
2388 p->tx_pg_size = m.tx_pg_sz;
2389 p->rx_num_pgs = m.rx_num_pg;
2390 p->tx_num_pgs = m.tx_num_pg;
2391 break;
2392 }
2393 case CHELSIO_GET_MEM:{
2394 struct ch_mem_range t;
2395 struct mc7 *mem;
2396 u64 buf[32];
2397
2398 if (!is_offload(adapter))
2399 return -EOPNOTSUPP;
2400 if (!(adapter->flags & FULL_INIT_DONE))
2401 return -EIO; /* need the memory controllers */
2402 if (copy_from_user(&t, useraddr, sizeof(t)))
2403 return -EFAULT;
2404 if ((t.addr & 7) || (t.len & 7))
2405 return -EINVAL;
2406 if (t.mem_id == MEM_CM)
2407 mem = &adapter->cm;
2408 else if (t.mem_id == MEM_PMRX)
2409 mem = &adapter->pmrx;
2410 else if (t.mem_id == MEM_PMTX)
2411 mem = &adapter->pmtx;
2412 else
2413 return -EINVAL;
2414
2415 /*
1825494a
DLR		 2416 * Version scheme:
2417 * bits 0..9: chip version
2418 * bits 10..15: chip revision
2419 */
4d22de3e
DLR		 2420 t.version = 3 | (adapter->params.rev << 10);
2421 if (copy_to_user(useraddr, &t, sizeof(t)))
2422 return -EFAULT;
2423
2424 /*
2425 * Read 256 bytes at a time as len can be large and we don't
2426 * want to use huge intermediate buffers.
2427 */
2428 useraddr += sizeof(t); /* advance to start of buffer */
2429 while (t.len) {
2430 unsigned int chunk =
2431 min_t(unsigned int, t.len, sizeof(buf));
2432
2433 ret =
2434 t3_mc7_bd_read(mem, t.addr / 8, chunk / 8,
2435 buf);
2436 if (ret)
2437 return ret;
2438 if (copy_to_user(useraddr, buf, chunk))
2439 return -EFAULT;
2440 useraddr += chunk;
2441 t.addr += chunk;
2442 t.len -= chunk;
2443 }
2444 break;
2445 }
2446 case CHELSIO_SET_TRACE_FILTER:{
2447 struct ch_trace t;
2448 const struct trace_params *tp;
2449
2450 if (!capable(CAP_NET_ADMIN))
2451 return -EPERM;
2452 if (!offload_running(adapter))
2453 return -EAGAIN;
2454 if (copy_from_user(&t, useraddr, sizeof(t)))
2455 return -EFAULT;
2456
2457 tp = (const struct trace_params *)&t.sip;
2458 if (t.config_tx)
2459 t3_config_trace_filter(adapter, tp, 0,
2460 t.invert_match,
2461 t.trace_tx);
2462 if (t.config_rx)
2463 t3_config_trace_filter(adapter, tp, 1,
2464 t.invert_match,
2465 t.trace_rx);
2466 break;
2467 }
4d22de3e
DLR		 2468 default:
2469 return -EOPNOTSUPP;
2470 }
2471 return 0;
2472}
2473
2474static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2475{
4d22de3e 2476 struct mii_ioctl_data *data = if_mii(req);
5fbf816f
DLR		 2477 struct port_info *pi = netdev_priv(dev);
2478 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2479
2480 switch (cmd) {
0f07c4ee
BH		 2481 case SIOCGMIIREG:
2482 case SIOCSMIIREG:
2483 /* Convert phy_id from older PRTAD/DEVAD format */
2484 if (is_10G(adapter) &&
2485 !mdio_phy_id_is_c45(data->phy_id) &&
2486 (data->phy_id & 0x1f00) &&
2487 !(data->phy_id & 0xe0e0))
2488 data->phy_id = mdio_phy_id_c45(data->phy_id >> 8,
2489 data->phy_id & 0x1f);
4d22de3e 2490 /* FALLTHRU */
0f07c4ee
BH		 2491 case SIOCGMIIPHY:
2492 return mdio_mii_ioctl(&pi->phy.mdio, data, cmd);
4d22de3e
DLR		 2493 case SIOCCHIOCTL:
2494 return cxgb_extension_ioctl(dev, req->ifr_data);
2495 default:
2496 return -EOPNOTSUPP;
2497 }
4d22de3e
DLR		 2498}
2499
2500static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2501{
4d22de3e 2502 struct port_info *pi = netdev_priv(dev);
5fbf816f
DLR		 2503 struct adapter *adapter = pi->adapter;
2504 int ret;
4d22de3e
DLR		 2505
2506 if (new_mtu < 81) /* accommodate SACK */
2507 return -EINVAL;
2508 if ((ret = t3_mac_set_mtu(&pi->mac, new_mtu)))
2509 return ret;
2510 dev->mtu = new_mtu;
2511 init_port_mtus(adapter);
2512 if (adapter->params.rev == 0 && offload_running(adapter))
2513 t3_load_mtus(adapter, adapter->params.mtus,
2514 adapter->params.a_wnd, adapter->params.b_wnd,
2515 adapter->port[0]->mtu);
2516 return 0;
2517}
2518
2519static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2520{
4d22de3e 2521 struct port_info *pi = netdev_priv(dev);
5fbf816f 2522 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2523 struct sockaddr *addr = p;
2524
2525 if (!is_valid_ether_addr(addr->sa_data))
2526 return -EINVAL;
2527
2528 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
f14d42f3 2529 t3_mac_set_address(&pi->mac, LAN_MAC_IDX, dev->dev_addr);
4d22de3e
DLR		 2530 if (offload_running(adapter))
2531 write_smt_entry(adapter, pi->port_id);
2532 return 0;
2533}
2534
2535/**
2536 * t3_synchronize_rx - wait for current Rx processing on a port to complete
2537 * @adap: the adapter
2538 * @p: the port
2539 *
2540 * Ensures that current Rx processing on any of the queues associated with
2541 * the given port completes before returning. We do this by acquiring and
2542 * releasing the locks of the response queues associated with the port.
2543 */
2544static void t3_synchronize_rx(struct adapter *adap, const struct port_info *p)
2545{
2546 int i;
2547
8c263761
DLR		 2548 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
2549 struct sge_rspq *q = &adap->sge.qs[i].rspq;
4d22de3e
DLR		 2550
2551 spin_lock_irq(&q->lock);
2552 spin_unlock_irq(&q->lock);
2553 }
2554}
2555
2556static void vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2557{
4d22de3e 2558 struct port_info *pi = netdev_priv(dev);
5fbf816f 2559 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2560
2561 pi->vlan_grp = grp;
2562 if (adapter->params.rev > 0)
2563 t3_set_vlan_accel(adapter, 1 << pi->port_id, grp != NULL);
2564 else {
2565 /* single control for all ports */
2566 unsigned int i, have_vlans = 0;
2567 for_each_port(adapter, i)
2568 have_vlans |= adap2pinfo(adapter, i)->vlan_grp != NULL;
2569
2570 t3_set_vlan_accel(adapter, 1, have_vlans);
2571 }
2572 t3_synchronize_rx(adapter, pi);
2573}
2574
4d22de3e
DLR		 2575#ifdef CONFIG_NET_POLL_CONTROLLER
2576static void cxgb_netpoll(struct net_device *dev)
2577{
890de332 2578 struct port_info *pi = netdev_priv(dev);
5fbf816f 2579 struct adapter *adapter = pi->adapter;
890de332 2580 int qidx;
4d22de3e 2581
890de332
DLR		 2582 for (qidx = pi->first_qset; qidx < pi->first_qset + pi->nqsets; qidx++) {
2583 struct sge_qset *qs = &adapter->sge.qs[qidx];
2584 void *source;
2eab17ab 2585
890de332
DLR		 2586 if (adapter->flags & USING_MSIX)
2587 source = qs;
2588 else
2589 source = adapter;
2590
2591 t3_intr_handler(adapter, qs->rspq.polling) (0, source);
2592 }
4d22de3e
DLR		 2593}
2594#endif
2595
2596/*
2597 * Periodic accumulation of MAC statistics.
2598 */
2599static void mac_stats_update(struct adapter *adapter)
2600{
2601 int i;
2602
2603 for_each_port(adapter, i) {
2604 struct net_device *dev = adapter->port[i];
2605 struct port_info *p = netdev_priv(dev);
2606
2607 if (netif_running(dev)) {
2608 spin_lock(&adapter->stats_lock);
2609 t3_mac_update_stats(&p->mac);
2610 spin_unlock(&adapter->stats_lock);
2611 }
2612 }
2613}
2614
2615static void check_link_status(struct adapter *adapter)
2616{
2617 int i;
2618
2619 for_each_port(adapter, i) {
2620 struct net_device *dev = adapter->port[i];
2621 struct port_info *p = netdev_priv(dev);
c22c8149 2622 int link_fault;
4d22de3e 2623
bf792094 2624 spin_lock_irq(&adapter->work_lock);
c22c8149
DLR		 2625 link_fault = p->link_fault;
2626 spin_unlock_irq(&adapter->work_lock);
2627
2628 if (link_fault) {
3851c66c 2629 t3_link_fault(adapter, i);
bf792094
DLR		 2630 continue;
2631 }
bf792094
DLR		 2632
2633 if (!(p->phy.caps & SUPPORTED_IRQ) && netif_running(dev)) {
2634 t3_xgm_intr_disable(adapter, i);
2635 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2636
4d22de3e 2637 t3_link_changed(adapter, i);
bf792094
DLR		 2638 t3_xgm_intr_enable(adapter, i);
2639 }
4d22de3e
DLR		 2640 }
2641}
2642
fc90664e
DLR		 2643static void check_t3b2_mac(struct adapter *adapter)
2644{
2645 int i;
2646
f2d961c9
DLR		 2647 if (!rtnl_trylock()) /* synchronize with ifdown */
2648 return;
2649
fc90664e
DLR		 2650 for_each_port(adapter, i) {
2651 struct net_device *dev = adapter->port[i];
2652 struct port_info *p = netdev_priv(dev);
2653 int status;
2654
2655 if (!netif_running(dev))
2656 continue;
2657
2658 status = 0;
6d6dabac 2659 if (netif_running(dev) && netif_carrier_ok(dev))
fc90664e
DLR		 2660 status = t3b2_mac_watchdog_task(&p->mac);
2661 if (status == 1)
2662 p->mac.stats.num_toggled++;
2663 else if (status == 2) {
2664 struct cmac *mac = &p->mac;
2665
2666 t3_mac_set_mtu(mac, dev->mtu);
f14d42f3 2667 t3_mac_set_address(mac, LAN_MAC_IDX, dev->dev_addr);
fc90664e
DLR		 2668 cxgb_set_rxmode(dev);
2669 t3_link_start(&p->phy, mac, &p->link_config);
2670 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
2671 t3_port_intr_enable(adapter, p->port_id);
2672 p->mac.stats.num_resets++;
2673 }
2674 }
2675 rtnl_unlock();
2676}
2677
2678
4d22de3e
DLR		 2679static void t3_adap_check_task(struct work_struct *work)
2680{
2681 struct adapter *adapter = container_of(work, struct adapter,
2682 adap_check_task.work);
2683 const struct adapter_params *p = &adapter->params;
fc882196
DLR		 2684 int port;
2685 unsigned int v, status, reset;
4d22de3e
DLR		 2686
2687 adapter->check_task_cnt++;
2688
3851c66c 2689 check_link_status(adapter);
4d22de3e
DLR		 2690
2691 /* Accumulate MAC stats if needed */
2692 if (!p->linkpoll_period ||
2693 (adapter->check_task_cnt * p->linkpoll_period) / 10 >=
2694 p->stats_update_period) {
2695 mac_stats_update(adapter);
2696 adapter->check_task_cnt = 0;
2697 }
2698
fc90664e
DLR		 2699 if (p->rev == T3_REV_B2)
2700 check_t3b2_mac(adapter);
2701
fc882196
DLR		 2702 /*
2703 * Scan the XGMAC's to check for various conditions which we want to
2704 * monitor in a periodic polling manner rather than via an interrupt
2705 * condition. This is used for conditions which would otherwise flood
2706 * the system with interrupts and we only really need to know that the
2707 * conditions are "happening" ... For each condition we count the
2708 * detection of the condition and reset it for the next polling loop.
2709 */
2710 for_each_port(adapter, port) {
2711 struct cmac *mac = &adap2pinfo(adapter, port)->mac;
2712 u32 cause;
2713
2714 cause = t3_read_reg(adapter, A_XGM_INT_CAUSE + mac->offset);
2715 reset = 0;
2716 if (cause & F_RXFIFO_OVERFLOW) {
2717 mac->stats.rx_fifo_ovfl++;
2718 reset |= F_RXFIFO_OVERFLOW;
2719 }
2720
2721 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, reset);
2722 }
2723
2724 /*
2725 * We do the same as above for FL_EMPTY interrupts.
2726 */
2727 status = t3_read_reg(adapter, A_SG_INT_CAUSE);
2728 reset = 0;
2729
2730 if (status & F_FLEMPTY) {
2731 struct sge_qset *qs = &adapter->sge.qs[0];
2732 int i = 0;
2733
2734 reset |= F_FLEMPTY;
2735
2736 v = (t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS) >> S_FL0EMPTY) &
2737 0xffff;
2738
2739 while (v) {
2740 qs->fl[i].empty += (v & 1);
2741 if (i)
2742 qs++;
2743 i ^= 1;
2744 v >>= 1;
2745 }
2746 }
2747
2748 t3_write_reg(adapter, A_SG_INT_CAUSE, reset);
2749
4d22de3e 2750 /* Schedule the next check update if any port is active. */
20d3fc11 2751 spin_lock_irq(&adapter->work_lock);
4d22de3e
DLR		 2752 if (adapter->open_device_map & PORT_MASK)
2753 schedule_chk_task(adapter);
20d3fc11 2754 spin_unlock_irq(&adapter->work_lock);
4d22de3e
DLR		 2755}
2756
2757/*
2758 * Processes external (PHY) interrupts in process context.
2759 */
2760static void ext_intr_task(struct work_struct *work)
2761{
2762 struct adapter *adapter = container_of(work, struct adapter,
2763 ext_intr_handler_task);
bf792094
DLR		 2764 int i;
2765
2766 /* Disable link fault interrupts */
2767 for_each_port(adapter, i) {
2768 struct net_device *dev = adapter->port[i];
2769 struct port_info *p = netdev_priv(dev);
2770
2771 t3_xgm_intr_disable(adapter, i);
2772 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2773 }
4d22de3e 2774
bf792094 2775 /* Re-enable link fault interrupts */
4d22de3e
DLR		 2776 t3_phy_intr_handler(adapter);
2777
bf792094
DLR		 2778 for_each_port(adapter, i)
2779 t3_xgm_intr_enable(adapter, i);
2780
4d22de3e
DLR		 2781 /* Now reenable external interrupts */
2782 spin_lock_irq(&adapter->work_lock);
2783 if (adapter->slow_intr_mask) {
2784 adapter->slow_intr_mask |= F_T3DBG;
2785 t3_write_reg(adapter, A_PL_INT_CAUSE0, F_T3DBG);
2786 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2787 adapter->slow_intr_mask);
2788 }
2789 spin_unlock_irq(&adapter->work_lock);
2790}
2791
2792/*
2793 * Interrupt-context handler for external (PHY) interrupts.
2794 */
2795void t3_os_ext_intr_handler(struct adapter *adapter)
2796{
2797 /*
2798 * Schedule a task to handle external interrupts as they may be slow
2799 * and we use a mutex to protect MDIO registers. We disable PHY
2800 * interrupts in the meantime and let the task reenable them when
2801 * it's done.
2802 */
2803 spin_lock(&adapter->work_lock);
2804 if (adapter->slow_intr_mask) {
2805 adapter->slow_intr_mask &= ~F_T3DBG;
2806 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2807 adapter->slow_intr_mask);
2808 queue_work(cxgb3_wq, &adapter->ext_intr_handler_task);
2809 }
2810 spin_unlock(&adapter->work_lock);
2811}
2812
bf792094
DLR		 2813void t3_os_link_fault_handler(struct adapter *adapter, int port_id)
2814{
2815 struct net_device *netdev = adapter->port[port_id];
2816 struct port_info *pi = netdev_priv(netdev);
2817
2818 spin_lock(&adapter->work_lock);
2819 pi->link_fault = 1;
bf792094
DLR		 2820 spin_unlock(&adapter->work_lock);
2821}
2822
20d3fc11
DLR		 2823static int t3_adapter_error(struct adapter *adapter, int reset)
2824{
2825 int i, ret = 0;
2826
cb0bc205
DLR		 2827 if (is_offload(adapter) &&
2828 test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
fa0d4c11 2829 cxgb3_event_notify(&adapter->tdev, OFFLOAD_STATUS_DOWN, 0);
cb0bc205
DLR		 2830 offload_close(&adapter->tdev);
2831 }
2832
20d3fc11
DLR		 2833 /* Stop all ports */
2834 for_each_port(adapter, i) {
2835 struct net_device *netdev = adapter->port[i];
2836
2837 if (netif_running(netdev))
2838 cxgb_close(netdev);
2839 }
2840
20d3fc11
DLR		 2841 /* Stop SGE timers */
2842 t3_stop_sge_timers(adapter);
2843
2844 adapter->flags &= ~FULL_INIT_DONE;
2845
2846 if (reset)
2847 ret = t3_reset_adapter(adapter);
2848
2849 pci_disable_device(adapter->pdev);
2850
2851 return ret;
2852}
2853
2854static int t3_reenable_adapter(struct adapter *adapter)
2855{
2856 if (pci_enable_device(adapter->pdev)) {
2857 dev_err(&adapter->pdev->dev,
2858 "Cannot re-enable PCI device after reset.\n");
2859 goto err;
2860 }
2861 pci_set_master(adapter->pdev);
2862 pci_restore_state(adapter->pdev);
ccdddf50 2863 pci_save_state(adapter->pdev);
20d3fc11
DLR		 2864
2865 /* Free sge resources */
2866 t3_free_sge_resources(adapter);
2867
2868 if (t3_replay_prep_adapter(adapter))
2869 goto err;
2870
2871 return 0;
2872err:
2873 return -1;
2874}
2875
2876static void t3_resume_ports(struct adapter *adapter)
2877{
2878 int i;
2879
2880 /* Restart the ports */
2881 for_each_port(adapter, i) {
2882 struct net_device *netdev = adapter->port[i];
2883
2884 if (netif_running(netdev)) {
2885 if (cxgb_open(netdev)) {
2886 dev_err(&adapter->pdev->dev,
2887 "can't bring device back up"
2888 " after reset\n");
2889 continue;
2890 }
2891 }
2892 }
cb0bc205
DLR		 2893
2894 if (is_offload(adapter) && !ofld_disable)
fa0d4c11 2895 cxgb3_event_notify(&adapter->tdev, OFFLOAD_STATUS_UP, 0);
20d3fc11
DLR		 2896}
2897
2898/*
2899 * processes a fatal error.
2900 * Bring the ports down, reset the chip, bring the ports back up.
2901 */
2902static void fatal_error_task(struct work_struct *work)
2903{
2904 struct adapter *adapter = container_of(work, struct adapter,
2905 fatal_error_handler_task);
2906 int err = 0;
2907
2908 rtnl_lock();
2909 err = t3_adapter_error(adapter, 1);
2910 if (!err)
2911 err = t3_reenable_adapter(adapter);
2912 if (!err)
2913 t3_resume_ports(adapter);
2914
2915 CH_ALERT(adapter, "adapter reset %s\n", err ? "failed" : "succeeded");
2916 rtnl_unlock();
2917}
2918
4d22de3e
DLR		 2919void t3_fatal_err(struct adapter *adapter)
2920{
2921 unsigned int fw_status[4];
2922
2923 if (adapter->flags & FULL_INIT_DONE) {
2924 t3_sge_stop(adapter);
c64c2eae
DLR		 2925 t3_write_reg(adapter, A_XGM_TX_CTRL, 0);
2926 t3_write_reg(adapter, A_XGM_RX_CTRL, 0);
2927 t3_write_reg(adapter, XGM_REG(A_XGM_TX_CTRL, 1), 0);
2928 t3_write_reg(adapter, XGM_REG(A_XGM_RX_CTRL, 1), 0);
20d3fc11
DLR		 2929
2930 spin_lock(&adapter->work_lock);
4d22de3e 2931 t3_intr_disable(adapter);
20d3fc11
DLR		 2932 queue_work(cxgb3_wq, &adapter->fatal_error_handler_task);
2933 spin_unlock(&adapter->work_lock);
4d22de3e
DLR		 2934 }
2935 CH_ALERT(adapter, "encountered fatal error, operation suspended\n");
2936 if (!t3_cim_ctl_blk_read(adapter, 0xa0, 4, fw_status))
2937 CH_ALERT(adapter, "FW status: 0x%x, 0x%x, 0x%x, 0x%x\n",
2938 fw_status[0], fw_status[1],
2939 fw_status[2], fw_status[3]);
4d22de3e
DLR		 2940}
2941
91a6b50c
DLR		 2942/**
2943 * t3_io_error_detected - called when PCI error is detected
2944 * @pdev: Pointer to PCI device
2945 * @state: The current pci connection state
2946 *
2947 * This function is called after a PCI bus error affecting
2948 * this device has been detected.
2949 */
2950static pci_ers_result_t t3_io_error_detected(struct pci_dev *pdev,
2951 pci_channel_state_t state)
2952{
bc4b6b52 2953 struct adapter *adapter = pci_get_drvdata(pdev);
20d3fc11 2954 int ret;
91a6b50c 2955
e8d19370
DLR		 2956 if (state == pci_channel_io_perm_failure)
2957 return PCI_ERS_RESULT_DISCONNECT;
2958
20d3fc11 2959 ret = t3_adapter_error(adapter, 0);
91a6b50c 2960
48c4b6db 2961 /* Request a slot reset. */
91a6b50c
DLR		 2962 return PCI_ERS_RESULT_NEED_RESET;
2963}
2964
2965/**
2966 * t3_io_slot_reset - called after the pci bus has been reset.
2967 * @pdev: Pointer to PCI device
2968 *
2969 * Restart the card from scratch, as if from a cold-boot.
2970 */
2971static pci_ers_result_t t3_io_slot_reset(struct pci_dev *pdev)
2972{
bc4b6b52 2973 struct adapter *adapter = pci_get_drvdata(pdev);
91a6b50c 2974
20d3fc11
DLR		 2975 if (!t3_reenable_adapter(adapter))
2976 return PCI_ERS_RESULT_RECOVERED;
91a6b50c 2977
48c4b6db 2978 return PCI_ERS_RESULT_DISCONNECT;
91a6b50c
DLR		 2979}
2980
2981/**
2982 * t3_io_resume - called when traffic can start flowing again.
2983 * @pdev: Pointer to PCI device
2984 *
2985 * This callback is called when the error recovery driver tells us that
2986 * its OK to resume normal operation.
2987 */
2988static void t3_io_resume(struct pci_dev *pdev)
2989{
bc4b6b52 2990 struct adapter *adapter = pci_get_drvdata(pdev);
91a6b50c 2991
68f40c10
DLR		 2992 CH_ALERT(adapter, "adapter recovering, PEX ERR 0x%x\n",
2993 t3_read_reg(adapter, A_PCIE_PEX_ERR));
2994
20d3fc11 2995 t3_resume_ports(adapter);
91a6b50c
DLR		 2996}
2997
2998static struct pci_error_handlers t3_err_handler = {
2999 .error_detected = t3_io_error_detected,
3000 .slot_reset = t3_io_slot_reset,
3001 .resume = t3_io_resume,
3002};
3003
8c263761
DLR		 3004/*
3005 * Set the number of qsets based on the number of CPUs and the number of ports,
3006 * not to exceed the number of available qsets, assuming there are enough qsets
3007 * per port in HW.
3008 */
3009static void set_nqsets(struct adapter *adap)
3010{
3011 int i, j = 0;
3012 int num_cpus = num_online_cpus();
3013 int hwports = adap->params.nports;
5cda9364 3014 int nqsets = adap->msix_nvectors - 1;
8c263761 3015
f9ee3882 3016 if (adap->params.rev > 0 && adap->flags & USING_MSIX) {
8c263761
DLR		 3017 if (hwports == 2 &&
3018 (hwports * nqsets > SGE_QSETS ||
3019 num_cpus >= nqsets / hwports))
3020 nqsets /= hwports;
3021 if (nqsets > num_cpus)
3022 nqsets = num_cpus;
3023 if (nqsets < 1 || hwports == 4)
3024 nqsets = 1;
3025 } else
3026 nqsets = 1;
3027
3028 for_each_port(adap, i) {
3029 struct port_info *pi = adap2pinfo(adap, i);
3030
3031 pi->first_qset = j;
3032 pi->nqsets = nqsets;
3033 j = pi->first_qset + nqsets;
3034
3035 dev_info(&adap->pdev->dev,
3036 "Port %d using %d queue sets.\n", i, nqsets);
3037 }
3038}
3039
4d22de3e
DLR		 3040static int __devinit cxgb_enable_msix(struct adapter *adap)
3041{
3042 struct msix_entry entries[SGE_QSETS + 1];
5cda9364 3043 int vectors;
4d22de3e
DLR		 3044 int i, err;
3045
5cda9364
DLR		 3046 vectors = ARRAY_SIZE(entries);
3047 for (i = 0; i < vectors; ++i)
4d22de3e
DLR		 3048 entries[i].entry = i;
3049
5cda9364
DLR		 3050 while ((err = pci_enable_msix(adap->pdev, entries, vectors)) > 0)
3051 vectors = err;
3052
2c2f409f
DLR		 3053 if (err < 0)
3054 pci_disable_msix(adap->pdev);
3055
3056 if (!err && vectors < (adap->params.nports + 1)) {
3057 pci_disable_msix(adap->pdev);
5cda9364 3058 err = -1;
2c2f409f 3059 }
5cda9364 3060
4d22de3e 3061 if (!err) {
5cda9364 3062 for (i = 0; i < vectors; ++i)
4d22de3e 3063 adap->msix_info[i].vec = entries[i].vector;
5cda9364
DLR		 3064 adap->msix_nvectors = vectors;
3065 }
3066
4d22de3e
DLR		 3067 return err;
3068}
3069
3070static void __devinit print_port_info(struct adapter *adap,
3071 const struct adapter_info *ai)
3072{
3073 static const char *pci_variant[] = {
3074 "PCI", "PCI-X", "PCI-X ECC", "PCI-X 266", "PCI Express"
3075 };
3076
3077 int i;
3078 char buf[80];
3079
3080 if (is_pcie(adap))
3081 snprintf(buf, sizeof(buf), "%s x%d",
3082 pci_variant[adap->params.pci.variant],
3083 adap->params.pci.width);
3084 else
3085 snprintf(buf, sizeof(buf), "%s %dMHz/%d-bit",
3086 pci_variant[adap->params.pci.variant],
3087 adap->params.pci.speed, adap->params.pci.width);
3088
3089 for_each_port(adap, i) {
3090 struct net_device *dev = adap->port[i];
3091 const struct port_info *pi = netdev_priv(dev);
3092
3093 if (!test_bit(i, &adap->registered_device_map))
3094 continue;
8ac3ba68 3095 printk(KERN_INFO "%s: %s %s %sNIC (rev %d) %s%s\n",
04497982 3096 dev->name, ai->desc, pi->phy.desc,
8ac3ba68 3097 is_offload(adap) ? "R" : "", adap->params.rev, buf,
4d22de3e
DLR		 3098 (adap->flags & USING_MSIX) ? " MSI-X" :
3099 (adap->flags & USING_MSI) ? " MSI" : "");
3100 if (adap->name == dev->name && adap->params.vpd.mclk)
167cdf5f
DLR		 3101 printk(KERN_INFO
3102 "%s: %uMB CM, %uMB PMTX, %uMB PMRX, S/N: %s\n",
4d22de3e
DLR		 3103 adap->name, t3_mc7_size(&adap->cm) >> 20,
3104 t3_mc7_size(&adap->pmtx) >> 20,
167cdf5f
DLR		 3105 t3_mc7_size(&adap->pmrx) >> 20,
3106 adap->params.vpd.sn);
4d22de3e
DLR		 3107 }
3108}
3109
dd752696
SH		 3110static const struct net_device_ops cxgb_netdev_ops = {
3111 .ndo_open = cxgb_open,
3112 .ndo_stop = cxgb_close,
43a944f3 3113 .ndo_start_xmit = t3_eth_xmit,
dd752696
SH		 3114 .ndo_get_stats = cxgb_get_stats,
3115 .ndo_validate_addr = eth_validate_addr,
3116 .ndo_set_multicast_list = cxgb_set_rxmode,
3117 .ndo_do_ioctl = cxgb_ioctl,
3118 .ndo_change_mtu = cxgb_change_mtu,
3119 .ndo_set_mac_address = cxgb_set_mac_addr,
3120 .ndo_vlan_rx_register = vlan_rx_register,
3121#ifdef CONFIG_NET_POLL_CONTROLLER
3122 .ndo_poll_controller = cxgb_netpoll,
3123#endif
3124};
3125
f14d42f3
KX		 3126static void __devinit cxgb3_init_iscsi_mac(struct net_device *dev)
3127{
3128 struct port_info *pi = netdev_priv(dev);
3129
3130 memcpy(pi->iscsic.mac_addr, dev->dev_addr, ETH_ALEN);
3131 pi->iscsic.mac_addr[3] |= 0x80;
3132}
3133
4d22de3e
DLR		 3134static int __devinit init_one(struct pci_dev *pdev,
3135 const struct pci_device_id *ent)
3136{
3137 static int version_printed;
3138
3139 int i, err, pci_using_dac = 0;
68f40c10 3140 resource_size_t mmio_start, mmio_len;
4d22de3e
DLR		 3141 const struct adapter_info *ai;
3142 struct adapter *adapter = NULL;
3143 struct port_info *pi;
3144
3145 if (!version_printed) {
3146 printk(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
3147 ++version_printed;
3148 }
3149
3150 if (!cxgb3_wq) {
3151 cxgb3_wq = create_singlethread_workqueue(DRV_NAME);
3152 if (!cxgb3_wq) {
3153 printk(KERN_ERR DRV_NAME
3154 ": cannot initialize work queue\n");
3155 return -ENOMEM;
3156 }
3157 }
3158
3159 err = pci_request_regions(pdev, DRV_NAME);
3160 if (err) {
3161 /* Just info, some other driver may have claimed the device. */
3162 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
3163 return err;
3164 }
3165
3166 err = pci_enable_device(pdev);
3167 if (err) {
3168 dev_err(&pdev->dev, "cannot enable PCI device\n");
3169 goto out_release_regions;
3170 }
3171
6a35528a 3172 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4d22de3e 3173 pci_using_dac = 1;
6a35528a 3174 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4d22de3e
DLR		 3175 if (err) {
3176 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
3177 "coherent allocations\n");
3178 goto out_disable_device;
3179 }
284901a9 3180 } else if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
4d22de3e
DLR		 3181 dev_err(&pdev->dev, "no usable DMA configuration\n");
3182 goto out_disable_device;
3183 }
3184
3185 pci_set_master(pdev);
204e2f98 3186 pci_save_state(pdev);
4d22de3e
DLR		 3187
3188 mmio_start = pci_resource_start(pdev, 0);
3189 mmio_len = pci_resource_len(pdev, 0);
3190 ai = t3_get_adapter_info(ent->driver_data);
3191
3192 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
3193 if (!adapter) {
3194 err = -ENOMEM;
3195 goto out_disable_device;
3196 }
3197
74b793e1
DLR		 3198 adapter->nofail_skb =
3199 alloc_skb(sizeof(struct cpl_set_tcb_field), GFP_KERNEL);
3200 if (!adapter->nofail_skb) {
3201 dev_err(&pdev->dev, "cannot allocate nofail buffer\n");
3202 err = -ENOMEM;
3203 goto out_free_adapter;
3204 }
3205
4d22de3e
DLR		 3206 adapter->regs = ioremap_nocache(mmio_start, mmio_len);
3207 if (!adapter->regs) {
3208 dev_err(&pdev->dev, "cannot map device registers\n");
3209 err = -ENOMEM;
3210 goto out_free_adapter;
3211 }
3212
3213 adapter->pdev = pdev;
3214 adapter->name = pci_name(pdev);
3215 adapter->msg_enable = dflt_msg_enable;
3216 adapter->mmio_len = mmio_len;
3217
3218 mutex_init(&adapter->mdio_lock);
3219 spin_lock_init(&adapter->work_lock);
3220 spin_lock_init(&adapter->stats_lock);
3221
3222 INIT_LIST_HEAD(&adapter->adapter_list);
3223 INIT_WORK(&adapter->ext_intr_handler_task, ext_intr_task);
20d3fc11 3224 INIT_WORK(&adapter->fatal_error_handler_task, fatal_error_task);
4d22de3e
DLR		 3225 INIT_DELAYED_WORK(&adapter->adap_check_task, t3_adap_check_task);
3226
952cdf33 3227 for (i = 0; i < ai->nports0 + ai->nports1; ++i) {
4d22de3e
DLR		 3228 struct net_device *netdev;
3229
82ad3329 3230 netdev = alloc_etherdev_mq(sizeof(struct port_info), SGE_QSETS);
4d22de3e
DLR		 3231 if (!netdev) {
3232 err = -ENOMEM;
3233 goto out_free_dev;
3234 }
3235
4d22de3e
DLR		 3236 SET_NETDEV_DEV(netdev, &pdev->dev);
3237
3238 adapter->port[i] = netdev;
3239 pi = netdev_priv(netdev);
5fbf816f 3240 pi->adapter = adapter;
47fd23fe 3241 pi->rx_offload = T3_RX_CSUM | T3_LRO;
4d22de3e
DLR		 3242 pi->port_id = i;
3243 netif_carrier_off(netdev);
82ad3329 3244 netif_tx_stop_all_queues(netdev);
4d22de3e
DLR		 3245 netdev->irq = pdev->irq;
3246 netdev->mem_start = mmio_start;
3247 netdev->mem_end = mmio_start + mmio_len - 1;
4d22de3e 3248 netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
7be2df45 3249 netdev->features |= NETIF_F_GRO;
4d22de3e
DLR		 3250 if (pci_using_dac)
3251 netdev->features |= NETIF_F_HIGHDMA;
3252
3253 netdev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
dd752696 3254 netdev->netdev_ops = &cxgb_netdev_ops;
4d22de3e
DLR		 3255 SET_ETHTOOL_OPS(netdev, &cxgb_ethtool_ops);
3256 }
3257
5fbf816f 3258 pci_set_drvdata(pdev, adapter);
4d22de3e
DLR		 3259 if (t3_prep_adapter(adapter, ai, 1) < 0) {
3260 err = -ENODEV;
3261 goto out_free_dev;
3262 }
2eab17ab 3263
4d22de3e
DLR		 3264 /*
3265 * The card is now ready to go. If any errors occur during device
3266 * registration we do not fail the whole card but rather proceed only
3267 * with the ports we manage to register successfully. However we must
3268 * register at least one net device.
3269 */
3270 for_each_port(adapter, i) {
3271 err = register_netdev(adapter->port[i]);
3272 if (err)
3273 dev_warn(&pdev->dev,
3274 "cannot register net device %s, skipping\n",
3275 adapter->port[i]->name);
3276 else {
3277 /*
3278 * Change the name we use for messages to the name of
3279 * the first successfully registered interface.
3280 */
3281 if (!adapter->registered_device_map)
3282 adapter->name = adapter->port[i]->name;
3283
3284 __set_bit(i, &adapter->registered_device_map);
3285 }
3286 }
3287 if (!adapter->registered_device_map) {
3288 dev_err(&pdev->dev, "could not register any net devices\n");
3289 goto out_free_dev;
3290 }
3291
f14d42f3
KX		 3292 for_each_port(adapter, i)
3293 cxgb3_init_iscsi_mac(adapter->port[i]);
3294
4d22de3e
DLR		 3295 /* Driver's ready. Reflect it on LEDs */
3296 t3_led_ready(adapter);
3297
3298 if (is_offload(adapter)) {
3299 __set_bit(OFFLOAD_DEVMAP_BIT, &adapter->registered_device_map);
3300 cxgb3_adapter_ofld(adapter);
3301 }
3302
3303 /* See what interrupts we'll be using */
3304 if (msi > 1 && cxgb_enable_msix(adapter) == 0)
3305 adapter->flags |= USING_MSIX;
3306 else if (msi > 0 && pci_enable_msi(pdev) == 0)
3307 adapter->flags |= USING_MSI;
3308
8c263761
DLR		 3309 set_nqsets(adapter);
3310
0ee8d33c 3311 err = sysfs_create_group(&adapter->port[0]->dev.kobj,
4d22de3e
DLR		 3312 &cxgb3_attr_group);
3313
3314 print_port_info(adapter, ai);
3315 return 0;
3316
3317out_free_dev:
3318 iounmap(adapter->regs);
952cdf33 3319 for (i = ai->nports0 + ai->nports1 - 1; i >= 0; --i)
4d22de3e
DLR		 3320 if (adapter->port[i])
3321 free_netdev(adapter->port[i]);
3322
3323out_free_adapter:
3324 kfree(adapter);
3325
3326out_disable_device:
3327 pci_disable_device(pdev);
3328out_release_regions:
3329 pci_release_regions(pdev);
3330 pci_set_drvdata(pdev, NULL);
3331 return err;
3332}
3333
3334static void __devexit remove_one(struct pci_dev *pdev)
3335{
5fbf816f 3336 struct adapter *adapter = pci_get_drvdata(pdev);
4d22de3e 3337
5fbf816f 3338 if (adapter) {
4d22de3e 3339 int i;
4d22de3e
DLR		 3340
3341 t3_sge_stop(adapter);
0ee8d33c 3342 sysfs_remove_group(&adapter->port[0]->dev.kobj,
4d22de3e
DLR		 3343 &cxgb3_attr_group);
3344
4d22de3e
DLR		 3345 if (is_offload(adapter)) {
3346 cxgb3_adapter_unofld(adapter);
3347 if (test_bit(OFFLOAD_DEVMAP_BIT,
3348 &adapter->open_device_map))
3349 offload_close(&adapter->tdev);
3350 }
3351
67d92ab7
DLR		 3352 for_each_port(adapter, i)
3353 if (test_bit(i, &adapter->registered_device_map))
3354 unregister_netdev(adapter->port[i]);
3355
0ca41c04 3356 t3_stop_sge_timers(adapter);
4d22de3e
DLR		 3357 t3_free_sge_resources(adapter);
3358 cxgb_disable_msi(adapter);
3359
4d22de3e
DLR		 3360 for_each_port(adapter, i)
3361 if (adapter->port[i])
3362 free_netdev(adapter->port[i]);
3363
3364 iounmap(adapter->regs);
74b793e1
DLR		 3365 if (adapter->nofail_skb)
3366 kfree_skb(adapter->nofail_skb);
4d22de3e
DLR		 3367 kfree(adapter);
3368 pci_release_regions(pdev);
3369 pci_disable_device(pdev);
3370 pci_set_drvdata(pdev, NULL);
3371 }
3372}
3373
3374static struct pci_driver driver = {
3375 .name = DRV_NAME,
3376 .id_table = cxgb3_pci_tbl,
3377 .probe = init_one,
3378 .remove = __devexit_p(remove_one),
91a6b50c 3379 .err_handler = &t3_err_handler,
4d22de3e
DLR		 3380};
3381
3382static int __init cxgb3_init_module(void)
3383{
3384 int ret;
3385
3386 cxgb3_offload_init();
3387
3388 ret = pci_register_driver(&driver);
3389 return ret;
3390}
3391
3392static void __exit cxgb3_cleanup_module(void)
3393{
3394 pci_unregister_driver(&driver);
3395 if (cxgb3_wq)
3396 destroy_workqueue(cxgb3_wq);
3397}
3398
3399module_init(cxgb3_init_module);
3400module_exit(cxgb3_cleanup_module);
Linux 6.x block layer and io_uring tree(s)