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chelsio: Use generic MDIO definitions and mdio_mii_ioctl()
[linux-2.6-block.git] / drivers / net / cxgb3 / cxgb3_main.c
CommitLineData
4d22de3e 1/*
a02d44a0 2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
4d22de3e 3 *
1d68e93d
DLR		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
4d22de3e 9 *
1d68e93d
DLR		 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
4d22de3e 31 */
4d22de3e
DLR		 32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/dma-mapping.h>
37#include <linux/netdevice.h>
38#include <linux/etherdevice.h>
39#include <linux/if_vlan.h>
40#include <linux/mii.h>
41#include <linux/sockios.h>
42#include <linux/workqueue.h>
43#include <linux/proc_fs.h>
44#include <linux/rtnetlink.h>
2e283962 45#include <linux/firmware.h>
d9da466a 46#include <linux/log2.h>
4d22de3e
DLR		 47#include <asm/uaccess.h>
48
49#include "common.h"
50#include "cxgb3_ioctl.h"
51#include "regs.h"
52#include "cxgb3_offload.h"
53#include "version.h"
54
55#include "cxgb3_ctl_defs.h"
56#include "t3_cpl.h"
57#include "firmware_exports.h"
58
59enum {
60 MAX_TXQ_ENTRIES = 16384,
61 MAX_CTRL_TXQ_ENTRIES = 1024,
62 MAX_RSPQ_ENTRIES = 16384,
63 MAX_RX_BUFFERS = 16384,
64 MAX_RX_JUMBO_BUFFERS = 16384,
65 MIN_TXQ_ENTRIES = 4,
66 MIN_CTRL_TXQ_ENTRIES = 4,
67 MIN_RSPQ_ENTRIES = 32,
68 MIN_FL_ENTRIES = 32
69};
70
71#define PORT_MASK ((1 << MAX_NPORTS) - 1)
72
73#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
74 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
75 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
76
77#define EEPROM_MAGIC 0x38E2F10C
78
678771d6
DLR		 79#define CH_DEVICE(devid, idx) \
80 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, PCI_ANY_ID, 0, 0, idx }
4d22de3e
DLR		 81
82static const struct pci_device_id cxgb3_pci_tbl[] = {
678771d6
DLR		 83 CH_DEVICE(0x20, 0), /* PE9000 */
84 CH_DEVICE(0x21, 1), /* T302E */
85 CH_DEVICE(0x22, 2), /* T310E */
86 CH_DEVICE(0x23, 3), /* T320X */
87 CH_DEVICE(0x24, 1), /* T302X */
88 CH_DEVICE(0x25, 3), /* T320E */
89 CH_DEVICE(0x26, 2), /* T310X */
90 CH_DEVICE(0x30, 2), /* T3B10 */
91 CH_DEVICE(0x31, 3), /* T3B20 */
92 CH_DEVICE(0x32, 1), /* T3B02 */
ce03aadd 93 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
4d22de3e
DLR		 94 {0,}
95};
96
97MODULE_DESCRIPTION(DRV_DESC);
98MODULE_AUTHOR("Chelsio Communications");
1d68e93d 99MODULE_LICENSE("Dual BSD/GPL");
4d22de3e
DLR		 100MODULE_VERSION(DRV_VERSION);
101MODULE_DEVICE_TABLE(pci, cxgb3_pci_tbl);
102
103static int dflt_msg_enable = DFLT_MSG_ENABLE;
104
105module_param(dflt_msg_enable, int, 0644);
106MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T3 default message enable bitmap");
107
108/*
109 * The driver uses the best interrupt scheme available on a platform in the
110 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
111 * of these schemes the driver may consider as follows:
112 *
113 * msi = 2: choose from among all three options
114 * msi = 1: only consider MSI and pin interrupts
115 * msi = 0: force pin interrupts
116 */
117static int msi = 2;
118
119module_param(msi, int, 0644);
120MODULE_PARM_DESC(msi, "whether to use MSI or MSI-X");
121
122/*
123 * The driver enables offload as a default.
124 * To disable it, use ofld_disable = 1.
125 */
126
127static int ofld_disable = 0;
128
129module_param(ofld_disable, int, 0644);
130MODULE_PARM_DESC(ofld_disable, "whether to enable offload at init time or not");
131
132/*
133 * We have work elements that we need to cancel when an interface is taken
134 * down. Normally the work elements would be executed by keventd but that
135 * can deadlock because of linkwatch. If our close method takes the rtnl
136 * lock and linkwatch is ahead of our work elements in keventd, linkwatch
137 * will block keventd as it needs the rtnl lock, and we'll deadlock waiting
138 * for our work to complete. Get our own work queue to solve this.
139 */
140static struct workqueue_struct *cxgb3_wq;
141
142/**
143 * link_report - show link status and link speed/duplex
144 * @p: the port whose settings are to be reported
145 *
146 * Shows the link status, speed, and duplex of a port.
147 */
148static void link_report(struct net_device *dev)
149{
150 if (!netif_carrier_ok(dev))
151 printk(KERN_INFO "%s: link down\n", dev->name);
152 else {
153 const char *s = "10Mbps";
154 const struct port_info *p = netdev_priv(dev);
155
156 switch (p->link_config.speed) {
157 case SPEED_10000:
158 s = "10Gbps";
159 break;
160 case SPEED_1000:
161 s = "1000Mbps";
162 break;
163 case SPEED_100:
164 s = "100Mbps";
165 break;
166 }
167
168 printk(KERN_INFO "%s: link up, %s, %s-duplex\n", dev->name, s,
169 p->link_config.duplex == DUPLEX_FULL ? "full" : "half");
170 }
171}
172
bf792094
DLR		 173void t3_os_link_fault(struct adapter *adap, int port_id, int state)
174{
175 struct net_device *dev = adap->port[port_id];
176 struct port_info *pi = netdev_priv(dev);
177
178 if (state == netif_carrier_ok(dev))
179 return;
180
181 if (state) {
182 struct cmac *mac = &pi->mac;
183
184 netif_carrier_on(dev);
185
186 /* Clear local faults */
187 t3_xgm_intr_disable(adap, pi->port_id);
188 t3_read_reg(adap, A_XGM_INT_STATUS +
189 pi->mac.offset);
190 t3_write_reg(adap,
191 A_XGM_INT_CAUSE + pi->mac.offset,
192 F_XGM_INT);
193
194 t3_set_reg_field(adap,
195 A_XGM_INT_ENABLE +
196 pi->mac.offset,
197 F_XGM_INT, F_XGM_INT);
198 t3_xgm_intr_enable(adap, pi->port_id);
199
200 t3_mac_enable(mac, MAC_DIRECTION_TX);
201 } else
202 netif_carrier_off(dev);
203
204 link_report(dev);
205}
206
4d22de3e
DLR		 207/**
208 * t3_os_link_changed - handle link status changes
209 * @adapter: the adapter associated with the link change
210 * @port_id: the port index whose limk status has changed
211 * @link_stat: the new status of the link
212 * @speed: the new speed setting
213 * @duplex: the new duplex setting
214 * @pause: the new flow-control setting
215 *
216 * This is the OS-dependent handler for link status changes. The OS
217 * neutral handler takes care of most of the processing for these events,
218 * then calls this handler for any OS-specific processing.
219 */
220void t3_os_link_changed(struct adapter *adapter, int port_id, int link_stat,
221 int speed, int duplex, int pause)
222{
223 struct net_device *dev = adapter->port[port_id];
6d6dabac
DLR		 224 struct port_info *pi = netdev_priv(dev);
225 struct cmac *mac = &pi->mac;
4d22de3e
DLR		 226
227 /* Skip changes from disabled ports. */
228 if (!netif_running(dev))
229 return;
230
231 if (link_stat != netif_carrier_ok(dev)) {
6d6dabac 232 if (link_stat) {
59cf8107 233 t3_mac_enable(mac, MAC_DIRECTION_RX);
bf792094
DLR		 234
235 /* Clear local faults */
236 t3_xgm_intr_disable(adapter, pi->port_id);
237 t3_read_reg(adapter, A_XGM_INT_STATUS +
238 pi->mac.offset);
239 t3_write_reg(adapter,
240 A_XGM_INT_CAUSE + pi->mac.offset,
241 F_XGM_INT);
242
243 t3_set_reg_field(adapter,
244 A_XGM_INT_ENABLE + pi->mac.offset,
245 F_XGM_INT, F_XGM_INT);
246 t3_xgm_intr_enable(adapter, pi->port_id);
247
4d22de3e 248 netif_carrier_on(dev);
6d6dabac 249 } else {
4d22de3e 250 netif_carrier_off(dev);
bf792094
DLR		 251
252 t3_xgm_intr_disable(adapter, pi->port_id);
253 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
254 t3_set_reg_field(adapter,
255 A_XGM_INT_ENABLE + pi->mac.offset,
256 F_XGM_INT, 0);
257
258 if (is_10G(adapter))
259 pi->phy.ops->power_down(&pi->phy, 1);
260
261 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
59cf8107
DLR		 262 t3_mac_disable(mac, MAC_DIRECTION_RX);
263 t3_link_start(&pi->phy, mac, &pi->link_config);
6d6dabac
DLR		 264 }
265
4d22de3e
DLR		 266 link_report(dev);
267 }
268}
269
1e882025
DLR		 270/**
271 * t3_os_phymod_changed - handle PHY module changes
272 * @phy: the PHY reporting the module change
273 * @mod_type: new module type
274 *
275 * This is the OS-dependent handler for PHY module changes. It is
276 * invoked when a PHY module is removed or inserted for any OS-specific
277 * processing.
278 */
279void t3_os_phymod_changed(struct adapter *adap, int port_id)
280{
281 static const char *mod_str[] = {
282 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown"
283 };
284
285 const struct net_device *dev = adap->port[port_id];
286 const struct port_info *pi = netdev_priv(dev);
287
288 if (pi->phy.modtype == phy_modtype_none)
289 printk(KERN_INFO "%s: PHY module unplugged\n", dev->name);
290 else
291 printk(KERN_INFO "%s: %s PHY module inserted\n", dev->name,
292 mod_str[pi->phy.modtype]);
293}
294
4d22de3e
DLR		 295static void cxgb_set_rxmode(struct net_device *dev)
296{
297 struct t3_rx_mode rm;
298 struct port_info *pi = netdev_priv(dev);
299
300 init_rx_mode(&rm, dev, dev->mc_list);
301 t3_mac_set_rx_mode(&pi->mac, &rm);
302}
303
304/**
305 * link_start - enable a port
306 * @dev: the device to enable
307 *
308 * Performs the MAC and PHY actions needed to enable a port.
309 */
310static void link_start(struct net_device *dev)
311{
312 struct t3_rx_mode rm;
313 struct port_info *pi = netdev_priv(dev);
314 struct cmac *mac = &pi->mac;
315
316 init_rx_mode(&rm, dev, dev->mc_list);
317 t3_mac_reset(mac);
318 t3_mac_set_mtu(mac, dev->mtu);
319 t3_mac_set_address(mac, 0, dev->dev_addr);
320 t3_mac_set_rx_mode(mac, &rm);
321 t3_link_start(&pi->phy, mac, &pi->link_config);
322 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
323}
324
325static inline void cxgb_disable_msi(struct adapter *adapter)
326{
327 if (adapter->flags & USING_MSIX) {
328 pci_disable_msix(adapter->pdev);
329 adapter->flags &= ~USING_MSIX;
330 } else if (adapter->flags & USING_MSI) {
331 pci_disable_msi(adapter->pdev);
332 adapter->flags &= ~USING_MSI;
333 }
334}
335
336/*
337 * Interrupt handler for asynchronous events used with MSI-X.
338 */
339static irqreturn_t t3_async_intr_handler(int irq, void *cookie)
340{
341 t3_slow_intr_handler(cookie);
342 return IRQ_HANDLED;
343}
344
345/*
346 * Name the MSI-X interrupts.
347 */
348static void name_msix_vecs(struct adapter *adap)
349{
350 int i, j, msi_idx = 1, n = sizeof(adap->msix_info[0].desc) - 1;
351
352 snprintf(adap->msix_info[0].desc, n, "%s", adap->name);
353 adap->msix_info[0].desc[n] = 0;
354
355 for_each_port(adap, j) {
356 struct net_device *d = adap->port[j];
357 const struct port_info *pi = netdev_priv(d);
358
359 for (i = 0; i < pi->nqsets; i++, msi_idx++) {
360 snprintf(adap->msix_info[msi_idx].desc, n,
8c263761 361 "%s-%d", d->name, pi->first_qset + i);
4d22de3e
DLR		 362 adap->msix_info[msi_idx].desc[n] = 0;
363 }
8c263761 364 }
4d22de3e
DLR		 365}
366
367static int request_msix_data_irqs(struct adapter *adap)
368{
369 int i, j, err, qidx = 0;
370
371 for_each_port(adap, i) {
372 int nqsets = adap2pinfo(adap, i)->nqsets;
373
374 for (j = 0; j < nqsets; ++j) {
375 err = request_irq(adap->msix_info[qidx + 1].vec,
376 t3_intr_handler(adap,
377 adap->sge.qs[qidx].
378 rspq.polling), 0,
379 adap->msix_info[qidx + 1].desc,
380 &adap->sge.qs[qidx]);
381 if (err) {
382 while (--qidx >= 0)
383 free_irq(adap->msix_info[qidx + 1].vec,
384 &adap->sge.qs[qidx]);
385 return err;
386 }
387 qidx++;
388 }
389 }
390 return 0;
391}
392
8c263761
DLR		 393static void free_irq_resources(struct adapter *adapter)
394{
395 if (adapter->flags & USING_MSIX) {
396 int i, n = 0;
397
398 free_irq(adapter->msix_info[0].vec, adapter);
399 for_each_port(adapter, i)
5cda9364 400 n += adap2pinfo(adapter, i)->nqsets;
8c263761
DLR		 401
402 for (i = 0; i < n; ++i)
403 free_irq(adapter->msix_info[i + 1].vec,
404 &adapter->sge.qs[i]);
405 } else
406 free_irq(adapter->pdev->irq, adapter);
407}
408
b881955b
DLR		 409static int await_mgmt_replies(struct adapter *adap, unsigned long init_cnt,
410 unsigned long n)
411{
412 int attempts = 5;
413
414 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) {
415 if (!--attempts)
416 return -ETIMEDOUT;
417 msleep(10);
418 }
419 return 0;
420}
421
422static int init_tp_parity(struct adapter *adap)
423{
424 int i;
425 struct sk_buff *skb;
426 struct cpl_set_tcb_field *greq;
427 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts;
428
429 t3_tp_set_offload_mode(adap, 1);
430
431 for (i = 0; i < 16; i++) {
432 struct cpl_smt_write_req *req;
433
434 skb = alloc_skb(sizeof(*req), GFP_KERNEL | __GFP_NOFAIL);
435 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
436 memset(req, 0, sizeof(*req));
437 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
438 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i));
439 req->iff = i;
440 t3_mgmt_tx(adap, skb);
441 }
442
443 for (i = 0; i < 2048; i++) {
444 struct cpl_l2t_write_req *req;
445
446 skb = alloc_skb(sizeof(*req), GFP_KERNEL | __GFP_NOFAIL);
447 req = (struct cpl_l2t_write_req *)__skb_put(skb, sizeof(*req));
448 memset(req, 0, sizeof(*req));
449 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
450 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i));
451 req->params = htonl(V_L2T_W_IDX(i));
452 t3_mgmt_tx(adap, skb);
453 }
454
455 for (i = 0; i < 2048; i++) {
456 struct cpl_rte_write_req *req;
457
458 skb = alloc_skb(sizeof(*req), GFP_KERNEL | __GFP_NOFAIL);
459 req = (struct cpl_rte_write_req *)__skb_put(skb, sizeof(*req));
460 memset(req, 0, sizeof(*req));
461 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
462 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i));
463 req->l2t_idx = htonl(V_L2T_W_IDX(i));
464 t3_mgmt_tx(adap, skb);
465 }
466
467 skb = alloc_skb(sizeof(*greq), GFP_KERNEL | __GFP_NOFAIL);
468 greq = (struct cpl_set_tcb_field *)__skb_put(skb, sizeof(*greq));
469 memset(greq, 0, sizeof(*greq));
470 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
471 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0));
472 greq->mask = cpu_to_be64(1);
473 t3_mgmt_tx(adap, skb);
474
475 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
476 t3_tp_set_offload_mode(adap, 0);
477 return i;
478}
479
4d22de3e
DLR		 480/**
481 * setup_rss - configure RSS
482 * @adap: the adapter
483 *
484 * Sets up RSS to distribute packets to multiple receive queues. We
485 * configure the RSS CPU lookup table to distribute to the number of HW
486 * receive queues, and the response queue lookup table to narrow that
487 * down to the response queues actually configured for each port.
488 * We always configure the RSS mapping for two ports since the mapping
489 * table has plenty of entries.
490 */
491static void setup_rss(struct adapter *adap)
492{
493 int i;
494 unsigned int nq0 = adap2pinfo(adap, 0)->nqsets;
495 unsigned int nq1 = adap->port[1] ? adap2pinfo(adap, 1)->nqsets : 1;
496 u8 cpus[SGE_QSETS + 1];
497 u16 rspq_map[RSS_TABLE_SIZE];
498
499 for (i = 0; i < SGE_QSETS; ++i)
500 cpus[i] = i;
501 cpus[SGE_QSETS] = 0xff; /* terminator */
502
503 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
504 rspq_map[i] = i % nq0;
505 rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq1) + nq0;
506 }
507
508 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
509 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN |
a2604be5 510 V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, cpus, rspq_map);
4d22de3e
DLR		 511}
512
bea3348e 513static void init_napi(struct adapter *adap)
4d22de3e 514{
bea3348e 515 int i;
4d22de3e 516
bea3348e
SH		 517 for (i = 0; i < SGE_QSETS; i++) {
518 struct sge_qset *qs = &adap->sge.qs[i];
4d22de3e 519
bea3348e
SH		 520 if (qs->adap)
521 netif_napi_add(qs->netdev, &qs->napi, qs->napi.poll,
522 64);
4d22de3e 523 }
48c4b6db
DLR		 524
525 /*
526 * netif_napi_add() can be called only once per napi_struct because it
527 * adds each new napi_struct to a list. Be careful not to call it a
528 * second time, e.g., during EEH recovery, by making a note of it.
529 */
530 adap->flags |= NAPI_INIT;
4d22de3e
DLR		 531}
532
533/*
534 * Wait until all NAPI handlers are descheduled. This includes the handlers of
535 * both netdevices representing interfaces and the dummy ones for the extra
536 * queues.
537 */
538static void quiesce_rx(struct adapter *adap)
539{
540 int i;
4d22de3e 541
bea3348e
SH		 542 for (i = 0; i < SGE_QSETS; i++)
543 if (adap->sge.qs[i].adap)
544 napi_disable(&adap->sge.qs[i].napi);
545}
4d22de3e 546
bea3348e
SH		 547static void enable_all_napi(struct adapter *adap)
548{
549 int i;
550 for (i = 0; i < SGE_QSETS; i++)
551 if (adap->sge.qs[i].adap)
552 napi_enable(&adap->sge.qs[i].napi);
4d22de3e
DLR		 553}
554
04ecb072
DLR		 555/**
556 * set_qset_lro - Turn a queue set's LRO capability on and off
557 * @dev: the device the qset is attached to
558 * @qset_idx: the queue set index
559 * @val: the LRO switch
560 *
561 * Sets LRO on or off for a particular queue set.
562 * the device's features flag is updated to reflect the LRO
563 * capability when all queues belonging to the device are
564 * in the same state.
565 */
566static void set_qset_lro(struct net_device *dev, int qset_idx, int val)
567{
568 struct port_info *pi = netdev_priv(dev);
569 struct adapter *adapter = pi->adapter;
04ecb072
DLR		 570
571 adapter->params.sge.qset[qset_idx].lro = !!val;
572 adapter->sge.qs[qset_idx].lro_enabled = !!val;
04ecb072
DLR		 573}
574
4d22de3e
DLR		 575/**
576 * setup_sge_qsets - configure SGE Tx/Rx/response queues
577 * @adap: the adapter
578 *
579 * Determines how many sets of SGE queues to use and initializes them.
580 * We support multiple queue sets per port if we have MSI-X, otherwise
581 * just one queue set per port.
582 */
583static int setup_sge_qsets(struct adapter *adap)
584{
bea3348e 585 int i, j, err, irq_idx = 0, qset_idx = 0;
8ac3ba68 586 unsigned int ntxq = SGE_TXQ_PER_SET;
4d22de3e
DLR		 587
588 if (adap->params.rev > 0 && !(adap->flags & USING_MSI))
589 irq_idx = -1;
590
591 for_each_port(adap, i) {
592 struct net_device *dev = adap->port[i];
bea3348e 593 struct port_info *pi = netdev_priv(dev);
4d22de3e 594
bea3348e 595 pi->qs = &adap->sge.qs[pi->first_qset];
8c263761
DLR		 596 for (j = pi->first_qset; j < pi->first_qset + pi->nqsets;
597 ++j, ++qset_idx) {
47fd23fe 598 set_qset_lro(dev, qset_idx, pi->rx_offload & T3_LRO);
4d22de3e
DLR		 599 err = t3_sge_alloc_qset(adap, qset_idx, 1,
600 (adap->flags & USING_MSIX) ? qset_idx + 1 :
601 irq_idx,
82ad3329
DLR		 602 &adap->params.sge.qset[qset_idx], ntxq, dev,
603 netdev_get_tx_queue(dev, j));
4d22de3e
DLR		 604 if (err) {
605 t3_free_sge_resources(adap);
606 return err;
607 }
608 }
609 }
610
611 return 0;
612}
613
3e5192ee 614static ssize_t attr_show(struct device *d, char *buf,
896392ef 615 ssize_t(*format) (struct net_device *, char *))
4d22de3e
DLR		 616{
617 ssize_t len;
4d22de3e
DLR		 618
619 /* Synchronize with ioctls that may shut down the device */
620 rtnl_lock();
896392ef 621 len = (*format) (to_net_dev(d), buf);
4d22de3e
DLR		 622 rtnl_unlock();
623 return len;
624}
625
3e5192ee 626static ssize_t attr_store(struct device *d,
0ee8d33c 627 const char *buf, size_t len,
896392ef 628 ssize_t(*set) (struct net_device *, unsigned int),
4d22de3e
DLR		 629 unsigned int min_val, unsigned int max_val)
630{
631 char *endp;
632 ssize_t ret;
633 unsigned int val;
4d22de3e
DLR		 634
635 if (!capable(CAP_NET_ADMIN))
636 return -EPERM;
637
638 val = simple_strtoul(buf, &endp, 0);
639 if (endp == buf || val < min_val || val > max_val)
640 return -EINVAL;
641
642 rtnl_lock();
896392ef 643 ret = (*set) (to_net_dev(d), val);
4d22de3e
DLR		 644 if (!ret)
645 ret = len;
646 rtnl_unlock();
647 return ret;
648}
649
650#define CXGB3_SHOW(name, val_expr) \
896392ef 651static ssize_t format_##name(struct net_device *dev, char *buf) \
4d22de3e 652{ \
5fbf816f
DLR		 653 struct port_info *pi = netdev_priv(dev); \
654 struct adapter *adap = pi->adapter; \
4d22de3e
DLR		 655 return sprintf(buf, "%u\n", val_expr); \
656} \
0ee8d33c
DLR		 657static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
658 char *buf) \
4d22de3e 659{ \
3e5192ee 660 return attr_show(d, buf, format_##name); \
4d22de3e
DLR		 661}
662
896392ef 663static ssize_t set_nfilters(struct net_device *dev, unsigned int val)
4d22de3e 664{
5fbf816f
DLR		 665 struct port_info *pi = netdev_priv(dev);
666 struct adapter *adap = pi->adapter;
9f238486 667 int min_tids = is_offload(adap) ? MC5_MIN_TIDS : 0;
896392ef 668
4d22de3e
DLR		 669 if (adap->flags & FULL_INIT_DONE)
670 return -EBUSY;
671 if (val && adap->params.rev == 0)
672 return -EINVAL;
9f238486
DLR		 673 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
674 min_tids)
4d22de3e
DLR		 675 return -EINVAL;
676 adap->params.mc5.nfilters = val;
677 return 0;
678}
679
0ee8d33c
DLR		 680static ssize_t store_nfilters(struct device *d, struct device_attribute *attr,
681 const char *buf, size_t len)
4d22de3e 682{
3e5192ee 683 return attr_store(d, buf, len, set_nfilters, 0, ~0);
4d22de3e
DLR		 684}
685
896392ef 686static ssize_t set_nservers(struct net_device *dev, unsigned int val)
4d22de3e 687{
5fbf816f
DLR		 688 struct port_info *pi = netdev_priv(dev);
689 struct adapter *adap = pi->adapter;
896392ef 690
4d22de3e
DLR		 691 if (adap->flags & FULL_INIT_DONE)
692 return -EBUSY;
9f238486
DLR		 693 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nfilters -
694 MC5_MIN_TIDS)
4d22de3e
DLR		 695 return -EINVAL;
696 adap->params.mc5.nservers = val;
697 return 0;
698}
699
0ee8d33c
DLR		 700static ssize_t store_nservers(struct device *d, struct device_attribute *attr,
701 const char *buf, size_t len)
4d22de3e 702{
3e5192ee 703 return attr_store(d, buf, len, set_nservers, 0, ~0);
4d22de3e
DLR		 704}
705
706#define CXGB3_ATTR_R(name, val_expr) \
707CXGB3_SHOW(name, val_expr) \
0ee8d33c 708static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
4d22de3e
DLR		 709
710#define CXGB3_ATTR_RW(name, val_expr, store_method) \
711CXGB3_SHOW(name, val_expr) \
0ee8d33c 712static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_method)
4d22de3e
DLR		 713
714CXGB3_ATTR_R(cam_size, t3_mc5_size(&adap->mc5));
715CXGB3_ATTR_RW(nfilters, adap->params.mc5.nfilters, store_nfilters);
716CXGB3_ATTR_RW(nservers, adap->params.mc5.nservers, store_nservers);
717
718static struct attribute *cxgb3_attrs[] = {
0ee8d33c
DLR		 719 &dev_attr_cam_size.attr,
720 &dev_attr_nfilters.attr,
721 &dev_attr_nservers.attr,
4d22de3e
DLR		 722 NULL
723};
724
725static struct attribute_group cxgb3_attr_group = {.attrs = cxgb3_attrs };
726
3e5192ee 727static ssize_t tm_attr_show(struct device *d,
0ee8d33c 728 char *buf, int sched)
4d22de3e 729{
5fbf816f
DLR		 730 struct port_info *pi = netdev_priv(to_net_dev(d));
731 struct adapter *adap = pi->adapter;
4d22de3e 732 unsigned int v, addr, bpt, cpt;
5fbf816f 733 ssize_t len;
4d22de3e
DLR		 734
735 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
736 rtnl_lock();
737 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
738 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
739 if (sched & 1)
740 v >>= 16;
741 bpt = (v >> 8) & 0xff;
742 cpt = v & 0xff;
743 if (!cpt)
744 len = sprintf(buf, "disabled\n");
745 else {
746 v = (adap->params.vpd.cclk * 1000) / cpt;
747 len = sprintf(buf, "%u Kbps\n", (v * bpt) / 125);
748 }
749 rtnl_unlock();
750 return len;
751}
752
3e5192ee 753static ssize_t tm_attr_store(struct device *d,
0ee8d33c 754 const char *buf, size_t len, int sched)
4d22de3e 755{
5fbf816f
DLR		 756 struct port_info *pi = netdev_priv(to_net_dev(d));
757 struct adapter *adap = pi->adapter;
758 unsigned int val;
4d22de3e
DLR		 759 char *endp;
760 ssize_t ret;
4d22de3e
DLR		 761
762 if (!capable(CAP_NET_ADMIN))
763 return -EPERM;
764
765 val = simple_strtoul(buf, &endp, 0);
766 if (endp == buf || val > 10000000)
767 return -EINVAL;
768
769 rtnl_lock();
770 ret = t3_config_sched(adap, val, sched);
771 if (!ret)
772 ret = len;
773 rtnl_unlock();
774 return ret;
775}
776
777#define TM_ATTR(name, sched) \
0ee8d33c
DLR		 778static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
779 char *buf) \
4d22de3e 780{ \
3e5192ee 781 return tm_attr_show(d, buf, sched); \
4d22de3e 782} \
0ee8d33c
DLR		 783static ssize_t store_##name(struct device *d, struct device_attribute *attr, \
784 const char *buf, size_t len) \
4d22de3e 785{ \
3e5192ee 786 return tm_attr_store(d, buf, len, sched); \
4d22de3e 787} \
0ee8d33c 788static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name)
4d22de3e
DLR		 789
790TM_ATTR(sched0, 0);
791TM_ATTR(sched1, 1);
792TM_ATTR(sched2, 2);
793TM_ATTR(sched3, 3);
794TM_ATTR(sched4, 4);
795TM_ATTR(sched5, 5);
796TM_ATTR(sched6, 6);
797TM_ATTR(sched7, 7);
798
799static struct attribute *offload_attrs[] = {
0ee8d33c
DLR		 800 &dev_attr_sched0.attr,
801 &dev_attr_sched1.attr,
802 &dev_attr_sched2.attr,
803 &dev_attr_sched3.attr,
804 &dev_attr_sched4.attr,
805 &dev_attr_sched5.attr,
806 &dev_attr_sched6.attr,
807 &dev_attr_sched7.attr,
4d22de3e
DLR		 808 NULL
809};
810
811static struct attribute_group offload_attr_group = {.attrs = offload_attrs };
812
813/*
814 * Sends an sk_buff to an offload queue driver
815 * after dealing with any active network taps.
816 */
817static inline int offload_tx(struct t3cdev *tdev, struct sk_buff *skb)
818{
819 int ret;
820
821 local_bh_disable();
822 ret = t3_offload_tx(tdev, skb);
823 local_bh_enable();
824 return ret;
825}
826
827static int write_smt_entry(struct adapter *adapter, int idx)
828{
829 struct cpl_smt_write_req *req;
830 struct sk_buff *skb = alloc_skb(sizeof(*req), GFP_KERNEL);
831
832 if (!skb)
833 return -ENOMEM;
834
835 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
836 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
837 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx));
838 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */
839 req->iff = idx;
840 memset(req->src_mac1, 0, sizeof(req->src_mac1));
841 memcpy(req->src_mac0, adapter->port[idx]->dev_addr, ETH_ALEN);
842 skb->priority = 1;
843 offload_tx(&adapter->tdev, skb);
844 return 0;
845}
846
847static int init_smt(struct adapter *adapter)
848{
849 int i;
850
851 for_each_port(adapter, i)
852 write_smt_entry(adapter, i);
853 return 0;
854}
855
856static void init_port_mtus(struct adapter *adapter)
857{
858 unsigned int mtus = adapter->port[0]->mtu;
859
860 if (adapter->port[1])
861 mtus |= adapter->port[1]->mtu << 16;
862 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus);
863}
864
8c263761 865static int send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo,
14ab9892
DLR		 866 int hi, int port)
867{
868 struct sk_buff *skb;
869 struct mngt_pktsched_wr *req;
8c263761 870 int ret;
14ab9892
DLR		 871
872 skb = alloc_skb(sizeof(*req), GFP_KERNEL | __GFP_NOFAIL);
873 req = (struct mngt_pktsched_wr *)skb_put(skb, sizeof(*req));
874 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT));
875 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET;
876 req->sched = sched;
877 req->idx = qidx;
878 req->min = lo;
879 req->max = hi;
880 req->binding = port;
8c263761
DLR		 881 ret = t3_mgmt_tx(adap, skb);
882
883 return ret;
14ab9892
DLR		 884}
885
8c263761 886static int bind_qsets(struct adapter *adap)
14ab9892 887{
8c263761 888 int i, j, err = 0;
14ab9892
DLR		 889
890 for_each_port(adap, i) {
891 const struct port_info *pi = adap2pinfo(adap, i);
892
8c263761
DLR		 893 for (j = 0; j < pi->nqsets; ++j) {
894 int ret = send_pktsched_cmd(adap, 1,
895 pi->first_qset + j, -1,
896 -1, i);
897 if (ret)
898 err = ret;
899 }
14ab9892 900 }
8c263761
DLR		 901
902 return err;
14ab9892
DLR		 903}
904
851fd7bd
DLR		 905#define FW_FNAME "cxgb3/t3fw-%d.%d.%d.bin"
906#define TPSRAM_NAME "cxgb3/t3%c_psram-%d.%d.%d.bin"
2e283962
DLR		 907
908static int upgrade_fw(struct adapter *adap)
909{
910 int ret;
911 char buf[64];
912 const struct firmware *fw;
913 struct device *dev = &adap->pdev->dev;
914
915 snprintf(buf, sizeof(buf), FW_FNAME, FW_VERSION_MAJOR,
7f672cf5 916 FW_VERSION_MINOR, FW_VERSION_MICRO);
2e283962
DLR		 917 ret = request_firmware(&fw, buf, dev);
918 if (ret < 0) {
919 dev_err(dev, "could not upgrade firmware: unable to load %s\n",
920 buf);
921 return ret;
922 }
923 ret = t3_load_fw(adap, fw->data, fw->size);
924 release_firmware(fw);
47330077
DLR		 925
926 if (ret == 0)
927 dev_info(dev, "successful upgrade to firmware %d.%d.%d\n",
928 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
929 else
930 dev_err(dev, "failed to upgrade to firmware %d.%d.%d\n",
931 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
2eab17ab 932
47330077
DLR		 933 return ret;
934}
935
936static inline char t3rev2char(struct adapter *adapter)
937{
938 char rev = 0;
939
940 switch(adapter->params.rev) {
941 case T3_REV_B:
942 case T3_REV_B2:
943 rev = 'b';
944 break;
1aafee26
DLR		 945 case T3_REV_C:
946 rev = 'c';
947 break;
47330077
DLR		 948 }
949 return rev;
950}
951
9265fabf 952static int update_tpsram(struct adapter *adap)
47330077
DLR		 953{
954 const struct firmware *tpsram;
955 char buf[64];
956 struct device *dev = &adap->pdev->dev;
957 int ret;
958 char rev;
2eab17ab 959
47330077
DLR		 960 rev = t3rev2char(adap);
961 if (!rev)
962 return 0;
963
964 snprintf(buf, sizeof(buf), TPSRAM_NAME, rev,
965 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
966
967 ret = request_firmware(&tpsram, buf, dev);
968 if (ret < 0) {
969 dev_err(dev, "could not load TP SRAM: unable to load %s\n",
970 buf);
971 return ret;
972 }
2eab17ab 973
47330077
DLR		 974 ret = t3_check_tpsram(adap, tpsram->data, tpsram->size);
975 if (ret)
2eab17ab 976 goto release_tpsram;
47330077
DLR		 977
978 ret = t3_set_proto_sram(adap, tpsram->data);
979 if (ret == 0)
980 dev_info(dev,
981 "successful update of protocol engine "
982 "to %d.%d.%d\n",
983 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
984 else
985 dev_err(dev, "failed to update of protocol engine %d.%d.%d\n",
986 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
987 if (ret)
988 dev_err(dev, "loading protocol SRAM failed\n");
989
990release_tpsram:
991 release_firmware(tpsram);
2eab17ab 992
2e283962
DLR		 993 return ret;
994}
995
4d22de3e
DLR		 996/**
997 * cxgb_up - enable the adapter
998 * @adapter: adapter being enabled
999 *
1000 * Called when the first port is enabled, this function performs the
1001 * actions necessary to make an adapter operational, such as completing
1002 * the initialization of HW modules, and enabling interrupts.
1003 *
1004 * Must be called with the rtnl lock held.
1005 */
1006static int cxgb_up(struct adapter *adap)
1007{
c54f5c24 1008 int err;
4d22de3e
DLR		 1009
1010 if (!(adap->flags & FULL_INIT_DONE)) {
8207befa 1011 err = t3_check_fw_version(adap);
a5a3b460 1012 if (err == -EINVAL) {
2e283962 1013 err = upgrade_fw(adap);
8207befa
DLR		 1014 CH_WARN(adap, "FW upgrade to %d.%d.%d %s\n",
1015 FW_VERSION_MAJOR, FW_VERSION_MINOR,
1016 FW_VERSION_MICRO, err ? "failed" : "succeeded");
a5a3b460 1017 }
4d22de3e 1018
8207befa 1019 err = t3_check_tpsram_version(adap);
47330077
DLR		 1020 if (err == -EINVAL) {
1021 err = update_tpsram(adap);
8207befa
DLR		 1022 CH_WARN(adap, "TP upgrade to %d.%d.%d %s\n",
1023 TP_VERSION_MAJOR, TP_VERSION_MINOR,
1024 TP_VERSION_MICRO, err ? "failed" : "succeeded");
47330077
DLR		 1025 }
1026
20d3fc11
DLR		 1027 /*
1028 * Clear interrupts now to catch errors if t3_init_hw fails.
1029 * We clear them again later as initialization may trigger
1030 * conditions that can interrupt.
1031 */
1032 t3_intr_clear(adap);
1033
4d22de3e
DLR		 1034 err = t3_init_hw(adap, 0);
1035 if (err)
1036 goto out;
1037
b881955b 1038 t3_set_reg_field(adap, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT);
6cdbd77e 1039 t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
bea3348e 1040
4d22de3e
DLR		 1041 err = setup_sge_qsets(adap);
1042 if (err)
1043 goto out;
1044
1045 setup_rss(adap);
48c4b6db
DLR		 1046 if (!(adap->flags & NAPI_INIT))
1047 init_napi(adap);
31563789
DLR		 1048
1049 t3_start_sge_timers(adap);
4d22de3e
DLR		 1050 adap->flags |= FULL_INIT_DONE;
1051 }
1052
1053 t3_intr_clear(adap);
1054
1055 if (adap->flags & USING_MSIX) {
1056 name_msix_vecs(adap);
1057 err = request_irq(adap->msix_info[0].vec,
1058 t3_async_intr_handler, 0,
1059 adap->msix_info[0].desc, adap);
1060 if (err)
1061 goto irq_err;
1062
42256f57
DLR		 1063 err = request_msix_data_irqs(adap);
1064 if (err) {
4d22de3e
DLR		 1065 free_irq(adap->msix_info[0].vec, adap);
1066 goto irq_err;
1067 }
1068 } else if ((err = request_irq(adap->pdev->irq,
1069 t3_intr_handler(adap,
1070 adap->sge.qs[0].rspq.
1071 polling),
2db6346f
TG		 1072 (adap->flags & USING_MSI) ?
1073 0 : IRQF_SHARED,
4d22de3e
DLR		 1074 adap->name, adap)))
1075 goto irq_err;
1076
bea3348e 1077 enable_all_napi(adap);
4d22de3e
DLR		 1078 t3_sge_start(adap);
1079 t3_intr_enable(adap);
14ab9892 1080
b881955b
DLR		 1081 if (adap->params.rev >= T3_REV_C && !(adap->flags & TP_PARITY_INIT) &&
1082 is_offload(adap) && init_tp_parity(adap) == 0)
1083 adap->flags |= TP_PARITY_INIT;
1084
1085 if (adap->flags & TP_PARITY_INIT) {
1086 t3_write_reg(adap, A_TP_INT_CAUSE,
1087 F_CMCACHEPERR | F_ARPLUTPERR);
1088 t3_write_reg(adap, A_TP_INT_ENABLE, 0x7fbfffff);
1089 }
1090
8c263761
DLR		 1091 if (!(adap->flags & QUEUES_BOUND)) {
1092 err = bind_qsets(adap);
1093 if (err) {
1094 CH_ERR(adap, "failed to bind qsets, err %d\n", err);
1095 t3_intr_disable(adap);
1096 free_irq_resources(adap);
1097 goto out;
1098 }
1099 adap->flags |= QUEUES_BOUND;
1100 }
14ab9892 1101
4d22de3e
DLR		 1102out:
1103 return err;
1104irq_err:
1105 CH_ERR(adap, "request_irq failed, err %d\n", err);
1106 goto out;
1107}
1108
1109/*
1110 * Release resources when all the ports and offloading have been stopped.
1111 */
1112static void cxgb_down(struct adapter *adapter)
1113{
1114 t3_sge_stop(adapter);
1115 spin_lock_irq(&adapter->work_lock); /* sync with PHY intr task */
1116 t3_intr_disable(adapter);
1117 spin_unlock_irq(&adapter->work_lock);
1118
8c263761 1119 free_irq_resources(adapter);
4d22de3e 1120 quiesce_rx(adapter);
c80b0c28 1121 flush_workqueue(cxgb3_wq); /* wait for external IRQ handler */
4d22de3e
DLR		 1122}
1123
1124static void schedule_chk_task(struct adapter *adap)
1125{
1126 unsigned int timeo;
1127
1128 timeo = adap->params.linkpoll_period ?
1129 (HZ * adap->params.linkpoll_period) / 10 :
1130 adap->params.stats_update_period * HZ;
1131 if (timeo)
1132 queue_delayed_work(cxgb3_wq, &adap->adap_check_task, timeo);
1133}
1134
1135static int offload_open(struct net_device *dev)
1136{
5fbf816f
DLR		 1137 struct port_info *pi = netdev_priv(dev);
1138 struct adapter *adapter = pi->adapter;
1139 struct t3cdev *tdev = dev2t3cdev(dev);
4d22de3e 1140 int adap_up = adapter->open_device_map & PORT_MASK;
c54f5c24 1141 int err;
4d22de3e
DLR		 1142
1143 if (test_and_set_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1144 return 0;
1145
1146 if (!adap_up && (err = cxgb_up(adapter)) < 0)
48c4b6db 1147 goto out;
4d22de3e
DLR		 1148
1149 t3_tp_set_offload_mode(adapter, 1);
1150 tdev->lldev = adapter->port[0];
1151 err = cxgb3_offload_activate(adapter);
1152 if (err)
1153 goto out;
1154
1155 init_port_mtus(adapter);
1156 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd,
1157 adapter->params.b_wnd,
1158 adapter->params.rev == 0 ?
1159 adapter->port[0]->mtu : 0xffff);
1160 init_smt(adapter);
1161
d96a51f6
DN		 1162 if (sysfs_create_group(&tdev->lldev->dev.kobj, &offload_attr_group))
1163 dev_dbg(&dev->dev, "cannot create sysfs group\n");
4d22de3e
DLR		 1164
1165 /* Call back all registered clients */
1166 cxgb3_add_clients(tdev);
1167
1168out:
1169 /* restore them in case the offload module has changed them */
1170 if (err) {
1171 t3_tp_set_offload_mode(adapter, 0);
1172 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1173 cxgb3_set_dummy_ops(tdev);
1174 }
1175 return err;
1176}
1177
1178static int offload_close(struct t3cdev *tdev)
1179{
1180 struct adapter *adapter = tdev2adap(tdev);
1181
1182 if (!test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1183 return 0;
1184
1185 /* Call back all registered clients */
1186 cxgb3_remove_clients(tdev);
1187
0ee8d33c 1188 sysfs_remove_group(&tdev->lldev->dev.kobj, &offload_attr_group);
4d22de3e 1189
c80b0c28
DLR		 1190 /* Flush work scheduled while releasing TIDs */
1191 flush_scheduled_work();
1192
4d22de3e
DLR		 1193 tdev->lldev = NULL;
1194 cxgb3_set_dummy_ops(tdev);
1195 t3_tp_set_offload_mode(adapter, 0);
1196 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1197
1198 if (!adapter->open_device_map)
1199 cxgb_down(adapter);
1200
1201 cxgb3_offload_deactivate(adapter);
1202 return 0;
1203}
1204
1205static int cxgb_open(struct net_device *dev)
1206{
4d22de3e 1207 struct port_info *pi = netdev_priv(dev);
5fbf816f 1208 struct adapter *adapter = pi->adapter;
4d22de3e 1209 int other_ports = adapter->open_device_map & PORT_MASK;
5fbf816f 1210 int err;
4d22de3e 1211
48c4b6db 1212 if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0)
4d22de3e
DLR		 1213 return err;
1214
1215 set_bit(pi->port_id, &adapter->open_device_map);
8ac3ba68 1216 if (is_offload(adapter) && !ofld_disable) {
4d22de3e
DLR		 1217 err = offload_open(dev);
1218 if (err)
1219 printk(KERN_WARNING
1220 "Could not initialize offload capabilities\n");
1221 }
1222
82ad3329 1223 dev->real_num_tx_queues = pi->nqsets;
4d22de3e
DLR		 1224 link_start(dev);
1225 t3_port_intr_enable(adapter, pi->port_id);
82ad3329 1226 netif_tx_start_all_queues(dev);
4d22de3e
DLR		 1227 if (!other_ports)
1228 schedule_chk_task(adapter);
1229
1230 return 0;
1231}
1232
1233static int cxgb_close(struct net_device *dev)
1234{
5fbf816f
DLR		 1235 struct port_info *pi = netdev_priv(dev);
1236 struct adapter *adapter = pi->adapter;
4d22de3e 1237
e8d19370
DLR		 1238
1239 if (!adapter->open_device_map)
1240 return 0;
1241
bf792094
DLR		 1242 /* Stop link fault interrupts */
1243 t3_xgm_intr_disable(adapter, pi->port_id);
1244 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
1245
5fbf816f 1246 t3_port_intr_disable(adapter, pi->port_id);
82ad3329 1247 netif_tx_stop_all_queues(dev);
5fbf816f 1248 pi->phy.ops->power_down(&pi->phy, 1);
4d22de3e 1249 netif_carrier_off(dev);
5fbf816f 1250 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX);
4d22de3e 1251
20d3fc11 1252 spin_lock_irq(&adapter->work_lock); /* sync with update task */
5fbf816f 1253 clear_bit(pi->port_id, &adapter->open_device_map);
20d3fc11 1254 spin_unlock_irq(&adapter->work_lock);
4d22de3e
DLR		 1255
1256 if (!(adapter->open_device_map & PORT_MASK))
c80b0c28 1257 cancel_delayed_work_sync(&adapter->adap_check_task);
4d22de3e
DLR		 1258
1259 if (!adapter->open_device_map)
1260 cxgb_down(adapter);
1261
1262 return 0;
1263}
1264
1265static struct net_device_stats *cxgb_get_stats(struct net_device *dev)
1266{
5fbf816f
DLR		 1267 struct port_info *pi = netdev_priv(dev);
1268 struct adapter *adapter = pi->adapter;
1269 struct net_device_stats *ns = &pi->netstats;
4d22de3e
DLR		 1270 const struct mac_stats *pstats;
1271
1272 spin_lock(&adapter->stats_lock);
5fbf816f 1273 pstats = t3_mac_update_stats(&pi->mac);
4d22de3e
DLR		 1274 spin_unlock(&adapter->stats_lock);
1275
1276 ns->tx_bytes = pstats->tx_octets;
1277 ns->tx_packets = pstats->tx_frames;
1278 ns->rx_bytes = pstats->rx_octets;
1279 ns->rx_packets = pstats->rx_frames;
1280 ns->multicast = pstats->rx_mcast_frames;
1281
1282 ns->tx_errors = pstats->tx_underrun;
1283 ns->rx_errors = pstats->rx_symbol_errs + pstats->rx_fcs_errs +
1284 pstats->rx_too_long + pstats->rx_jabber + pstats->rx_short +
1285 pstats->rx_fifo_ovfl;
1286
1287 /* detailed rx_errors */
1288 ns->rx_length_errors = pstats->rx_jabber + pstats->rx_too_long;
1289 ns->rx_over_errors = 0;
1290 ns->rx_crc_errors = pstats->rx_fcs_errs;
1291 ns->rx_frame_errors = pstats->rx_symbol_errs;
1292 ns->rx_fifo_errors = pstats->rx_fifo_ovfl;
1293 ns->rx_missed_errors = pstats->rx_cong_drops;
1294
1295 /* detailed tx_errors */
1296 ns->tx_aborted_errors = 0;
1297 ns->tx_carrier_errors = 0;
1298 ns->tx_fifo_errors = pstats->tx_underrun;
1299 ns->tx_heartbeat_errors = 0;
1300 ns->tx_window_errors = 0;
1301 return ns;
1302}
1303
1304static u32 get_msglevel(struct net_device *dev)
1305{
5fbf816f
DLR		 1306 struct port_info *pi = netdev_priv(dev);
1307 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1308
1309 return adapter->msg_enable;
1310}
1311
1312static void set_msglevel(struct net_device *dev, u32 val)
1313{
5fbf816f
DLR		 1314 struct port_info *pi = netdev_priv(dev);
1315 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1316
1317 adapter->msg_enable = val;
1318}
1319
1320static char stats_strings[][ETH_GSTRING_LEN] = {
1321 "TxOctetsOK ",
1322 "TxFramesOK ",
1323 "TxMulticastFramesOK",
1324 "TxBroadcastFramesOK",
1325 "TxPauseFrames ",
1326 "TxUnderrun ",
1327 "TxExtUnderrun ",
1328
1329 "TxFrames64 ",
1330 "TxFrames65To127 ",
1331 "TxFrames128To255 ",
1332 "TxFrames256To511 ",
1333 "TxFrames512To1023 ",
1334 "TxFrames1024To1518 ",
1335 "TxFrames1519ToMax ",
1336
1337 "RxOctetsOK ",
1338 "RxFramesOK ",
1339 "RxMulticastFramesOK",
1340 "RxBroadcastFramesOK",
1341 "RxPauseFrames ",
1342 "RxFCSErrors ",
1343 "RxSymbolErrors ",
1344 "RxShortErrors ",
1345 "RxJabberErrors ",
1346 "RxLengthErrors ",
1347 "RxFIFOoverflow ",
1348
1349 "RxFrames64 ",
1350 "RxFrames65To127 ",
1351 "RxFrames128To255 ",
1352 "RxFrames256To511 ",
1353 "RxFrames512To1023 ",
1354 "RxFrames1024To1518 ",
1355 "RxFrames1519ToMax ",
1356
1357 "PhyFIFOErrors ",
1358 "TSO ",
1359 "VLANextractions ",
1360 "VLANinsertions ",
1361 "TxCsumOffload ",
1362 "RxCsumGood ",
b47385bd
DLR		 1363 "LroAggregated ",
1364 "LroFlushed ",
1365 "LroNoDesc ",
fc90664e
DLR		 1366 "RxDrops ",
1367
1368 "CheckTXEnToggled ",
1369 "CheckResets ",
1370
bf792094 1371 "LinkFaults ",
4d22de3e
DLR		 1372};
1373
b9f2c044 1374static int get_sset_count(struct net_device *dev, int sset)
4d22de3e 1375{
b9f2c044
JG		 1376 switch (sset) {
1377 case ETH_SS_STATS:
1378 return ARRAY_SIZE(stats_strings);
1379 default:
1380 return -EOPNOTSUPP;
1381 }
4d22de3e
DLR		 1382}
1383
1384#define T3_REGMAP_SIZE (3 * 1024)
1385
1386static int get_regs_len(struct net_device *dev)
1387{
1388 return T3_REGMAP_SIZE;
1389}
1390
1391static int get_eeprom_len(struct net_device *dev)
1392{
1393 return EEPROMSIZE;
1394}
1395
1396static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1397{
5fbf816f
DLR		 1398 struct port_info *pi = netdev_priv(dev);
1399 struct adapter *adapter = pi->adapter;
4d22de3e 1400 u32 fw_vers = 0;
47330077 1401 u32 tp_vers = 0;
4d22de3e 1402
cf3760da 1403 spin_lock(&adapter->stats_lock);
4d22de3e 1404 t3_get_fw_version(adapter, &fw_vers);
47330077 1405 t3_get_tp_version(adapter, &tp_vers);
cf3760da 1406 spin_unlock(&adapter->stats_lock);
4d22de3e
DLR		 1407
1408 strcpy(info->driver, DRV_NAME);
1409 strcpy(info->version, DRV_VERSION);
1410 strcpy(info->bus_info, pci_name(adapter->pdev));
1411 if (!fw_vers)
1412 strcpy(info->fw_version, "N/A");
4aac3899 1413 else {
4d22de3e 1414 snprintf(info->fw_version, sizeof(info->fw_version),
47330077 1415 "%s %u.%u.%u TP %u.%u.%u",
4aac3899
DLR		 1416 G_FW_VERSION_TYPE(fw_vers) ? "T" : "N",
1417 G_FW_VERSION_MAJOR(fw_vers),
1418 G_FW_VERSION_MINOR(fw_vers),
47330077
DLR		 1419 G_FW_VERSION_MICRO(fw_vers),
1420 G_TP_VERSION_MAJOR(tp_vers),
1421 G_TP_VERSION_MINOR(tp_vers),
1422 G_TP_VERSION_MICRO(tp_vers));
4aac3899 1423 }
4d22de3e
DLR		 1424}
1425
1426static void get_strings(struct net_device *dev, u32 stringset, u8 * data)
1427{
1428 if (stringset == ETH_SS_STATS)
1429 memcpy(data, stats_strings, sizeof(stats_strings));
1430}
1431
1432static unsigned long collect_sge_port_stats(struct adapter *adapter,
1433 struct port_info *p, int idx)
1434{
1435 int i;
1436 unsigned long tot = 0;
1437
8c263761
DLR		 1438 for (i = p->first_qset; i < p->first_qset + p->nqsets; ++i)
1439 tot += adapter->sge.qs[i].port_stats[idx];
4d22de3e
DLR		 1440 return tot;
1441}
1442
1443static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1444 u64 *data)
1445{
4d22de3e 1446 struct port_info *pi = netdev_priv(dev);
5fbf816f 1447 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1448 const struct mac_stats *s;
1449
1450 spin_lock(&adapter->stats_lock);
1451 s = t3_mac_update_stats(&pi->mac);
1452 spin_unlock(&adapter->stats_lock);
1453
1454 *data++ = s->tx_octets;
1455 *data++ = s->tx_frames;
1456 *data++ = s->tx_mcast_frames;
1457 *data++ = s->tx_bcast_frames;
1458 *data++ = s->tx_pause;
1459 *data++ = s->tx_underrun;
1460 *data++ = s->tx_fifo_urun;
1461
1462 *data++ = s->tx_frames_64;
1463 *data++ = s->tx_frames_65_127;
1464 *data++ = s->tx_frames_128_255;
1465 *data++ = s->tx_frames_256_511;
1466 *data++ = s->tx_frames_512_1023;
1467 *data++ = s->tx_frames_1024_1518;
1468 *data++ = s->tx_frames_1519_max;
1469
1470 *data++ = s->rx_octets;
1471 *data++ = s->rx_frames;
1472 *data++ = s->rx_mcast_frames;
1473 *data++ = s->rx_bcast_frames;
1474 *data++ = s->rx_pause;
1475 *data++ = s->rx_fcs_errs;
1476 *data++ = s->rx_symbol_errs;
1477 *data++ = s->rx_short;
1478 *data++ = s->rx_jabber;
1479 *data++ = s->rx_too_long;
1480 *data++ = s->rx_fifo_ovfl;
1481
1482 *data++ = s->rx_frames_64;
1483 *data++ = s->rx_frames_65_127;
1484 *data++ = s->rx_frames_128_255;
1485 *data++ = s->rx_frames_256_511;
1486 *data++ = s->rx_frames_512_1023;
1487 *data++ = s->rx_frames_1024_1518;
1488 *data++ = s->rx_frames_1519_max;
1489
1490 *data++ = pi->phy.fifo_errors;
1491
1492 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TSO);
1493 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANEX);
1494 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANINS);
1495 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM);
1496 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD);
7be2df45
HX		 1497 *data++ = 0;
1498 *data++ = 0;
1499 *data++ = 0;
4d22de3e 1500 *data++ = s->rx_cong_drops;
fc90664e
DLR		 1501
1502 *data++ = s->num_toggled;
1503 *data++ = s->num_resets;
bf792094
DLR		 1504
1505 *data++ = s->link_faults;
4d22de3e
DLR		 1506}
1507
1508static inline void reg_block_dump(struct adapter *ap, void *buf,
1509 unsigned int start, unsigned int end)
1510{
1511 u32 *p = buf + start;
1512
1513 for (; start <= end; start += sizeof(u32))
1514 *p++ = t3_read_reg(ap, start);
1515}
1516
1517static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1518 void *buf)
1519{
5fbf816f
DLR		 1520 struct port_info *pi = netdev_priv(dev);
1521 struct adapter *ap = pi->adapter;
4d22de3e
DLR		 1522
1523 /*
1524 * Version scheme:
1525 * bits 0..9: chip version
1526 * bits 10..15: chip revision
1527 * bit 31: set for PCIe cards
1528 */
1529 regs->version = 3 | (ap->params.rev << 10) | (is_pcie(ap) << 31);
1530
1531 /*
1532 * We skip the MAC statistics registers because they are clear-on-read.
1533 * Also reading multi-register stats would need to synchronize with the
1534 * periodic mac stats accumulation. Hard to justify the complexity.
1535 */
1536 memset(buf, 0, T3_REGMAP_SIZE);
1537 reg_block_dump(ap, buf, 0, A_SG_RSPQ_CREDIT_RETURN);
1538 reg_block_dump(ap, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT);
1539 reg_block_dump(ap, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE);
1540 reg_block_dump(ap, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA);
1541 reg_block_dump(ap, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3);
1542 reg_block_dump(ap, buf, A_XGM_SERDES_STATUS0,
1543 XGM_REG(A_XGM_SERDES_STAT3, 1));
1544 reg_block_dump(ap, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1),
1545 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1));
1546}
1547
1548static int restart_autoneg(struct net_device *dev)
1549{
1550 struct port_info *p = netdev_priv(dev);
1551
1552 if (!netif_running(dev))
1553 return -EAGAIN;
1554 if (p->link_config.autoneg != AUTONEG_ENABLE)
1555 return -EINVAL;
1556 p->phy.ops->autoneg_restart(&p->phy);
1557 return 0;
1558}
1559
1560static int cxgb3_phys_id(struct net_device *dev, u32 data)
1561{
5fbf816f
DLR		 1562 struct port_info *pi = netdev_priv(dev);
1563 struct adapter *adapter = pi->adapter;
4d22de3e 1564 int i;
4d22de3e
DLR		 1565
1566 if (data == 0)
1567 data = 2;
1568
1569 for (i = 0; i < data * 2; i++) {
1570 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1571 (i & 1) ? F_GPIO0_OUT_VAL : 0);
1572 if (msleep_interruptible(500))
1573 break;
1574 }
1575 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1576 F_GPIO0_OUT_VAL);
1577 return 0;
1578}
1579
1580static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1581{
1582 struct port_info *p = netdev_priv(dev);
1583
1584 cmd->supported = p->link_config.supported;
1585 cmd->advertising = p->link_config.advertising;
1586
1587 if (netif_carrier_ok(dev)) {
1588 cmd->speed = p->link_config.speed;
1589 cmd->duplex = p->link_config.duplex;
1590 } else {
1591 cmd->speed = -1;
1592 cmd->duplex = -1;
1593 }
1594
1595 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
1596 cmd->phy_address = p->phy.addr;
1597 cmd->transceiver = XCVR_EXTERNAL;
1598 cmd->autoneg = p->link_config.autoneg;
1599 cmd->maxtxpkt = 0;
1600 cmd->maxrxpkt = 0;
1601 return 0;
1602}
1603
1604static int speed_duplex_to_caps(int speed, int duplex)
1605{
1606 int cap = 0;
1607
1608 switch (speed) {
1609 case SPEED_10:
1610 if (duplex == DUPLEX_FULL)
1611 cap = SUPPORTED_10baseT_Full;
1612 else
1613 cap = SUPPORTED_10baseT_Half;
1614 break;
1615 case SPEED_100:
1616 if (duplex == DUPLEX_FULL)
1617 cap = SUPPORTED_100baseT_Full;
1618 else
1619 cap = SUPPORTED_100baseT_Half;
1620 break;
1621 case SPEED_1000:
1622 if (duplex == DUPLEX_FULL)
1623 cap = SUPPORTED_1000baseT_Full;
1624 else
1625 cap = SUPPORTED_1000baseT_Half;
1626 break;
1627 case SPEED_10000:
1628 if (duplex == DUPLEX_FULL)
1629 cap = SUPPORTED_10000baseT_Full;
1630 }
1631 return cap;
1632}
1633
1634#define ADVERTISED_MASK (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1635 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1636 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | \
1637 ADVERTISED_10000baseT_Full)
1638
1639static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1640{
1641 struct port_info *p = netdev_priv(dev);
1642 struct link_config *lc = &p->link_config;
1643
9b1e3656
DLR		 1644 if (!(lc->supported & SUPPORTED_Autoneg)) {
1645 /*
1646 * PHY offers a single speed/duplex. See if that's what's
1647 * being requested.
1648 */
1649 if (cmd->autoneg == AUTONEG_DISABLE) {
97915b5b 1650 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
9b1e3656
DLR		 1651 if (lc->supported & cap)
1652 return 0;
1653 }
1654 return -EINVAL;
1655 }
4d22de3e
DLR		 1656
1657 if (cmd->autoneg == AUTONEG_DISABLE) {
1658 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
1659
1660 if (!(lc->supported & cap) || cmd->speed == SPEED_1000)
1661 return -EINVAL;
1662 lc->requested_speed = cmd->speed;
1663 lc->requested_duplex = cmd->duplex;
1664 lc->advertising = 0;
1665 } else {
1666 cmd->advertising &= ADVERTISED_MASK;
1667 cmd->advertising &= lc->supported;
1668 if (!cmd->advertising)
1669 return -EINVAL;
1670 lc->requested_speed = SPEED_INVALID;
1671 lc->requested_duplex = DUPLEX_INVALID;
1672 lc->advertising = cmd->advertising | ADVERTISED_Autoneg;
1673 }
1674 lc->autoneg = cmd->autoneg;
1675 if (netif_running(dev))
1676 t3_link_start(&p->phy, &p->mac, lc);
1677 return 0;
1678}
1679
1680static void get_pauseparam(struct net_device *dev,
1681 struct ethtool_pauseparam *epause)
1682{
1683 struct port_info *p = netdev_priv(dev);
1684
1685 epause->autoneg = (p->link_config.requested_fc & PAUSE_AUTONEG) != 0;
1686 epause->rx_pause = (p->link_config.fc & PAUSE_RX) != 0;
1687 epause->tx_pause = (p->link_config.fc & PAUSE_TX) != 0;
1688}
1689
1690static int set_pauseparam(struct net_device *dev,
1691 struct ethtool_pauseparam *epause)
1692{
1693 struct port_info *p = netdev_priv(dev);
1694 struct link_config *lc = &p->link_config;
1695
1696 if (epause->autoneg == AUTONEG_DISABLE)
1697 lc->requested_fc = 0;
1698 else if (lc->supported & SUPPORTED_Autoneg)
1699 lc->requested_fc = PAUSE_AUTONEG;
1700 else
1701 return -EINVAL;
1702
1703 if (epause->rx_pause)
1704 lc->requested_fc |= PAUSE_RX;
1705 if (epause->tx_pause)
1706 lc->requested_fc |= PAUSE_TX;
1707 if (lc->autoneg == AUTONEG_ENABLE) {
1708 if (netif_running(dev))
1709 t3_link_start(&p->phy, &p->mac, lc);
1710 } else {
1711 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1712 if (netif_running(dev))
1713 t3_mac_set_speed_duplex_fc(&p->mac, -1, -1, lc->fc);
1714 }
1715 return 0;
1716}
1717
1718static u32 get_rx_csum(struct net_device *dev)
1719{
1720 struct port_info *p = netdev_priv(dev);
1721
47fd23fe 1722 return p->rx_offload & T3_RX_CSUM;
4d22de3e
DLR		 1723}
1724
1725static int set_rx_csum(struct net_device *dev, u32 data)
1726{
1727 struct port_info *p = netdev_priv(dev);
1728
47fd23fe
RD		 1729 if (data) {
1730 p->rx_offload |= T3_RX_CSUM;
1731 } else {
b47385bd
DLR		 1732 int i;
1733
47fd23fe 1734 p->rx_offload &= ~(T3_RX_CSUM | T3_LRO);
04ecb072
DLR		 1735 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++)
1736 set_qset_lro(dev, i, 0);
b47385bd 1737 }
4d22de3e
DLR		 1738 return 0;
1739}
1740
1741static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1742{
5fbf816f
DLR		 1743 struct port_info *pi = netdev_priv(dev);
1744 struct adapter *adapter = pi->adapter;
05b97b30 1745 const struct qset_params *q = &adapter->params.sge.qset[pi->first_qset];
4d22de3e
DLR		 1746
1747 e->rx_max_pending = MAX_RX_BUFFERS;
1748 e->rx_mini_max_pending = 0;
1749 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS;
1750 e->tx_max_pending = MAX_TXQ_ENTRIES;
1751
05b97b30
DLR		 1752 e->rx_pending = q->fl_size;
1753 e->rx_mini_pending = q->rspq_size;
1754 e->rx_jumbo_pending = q->jumbo_size;
1755 e->tx_pending = q->txq_size[0];
4d22de3e
DLR		 1756}
1757
1758static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1759{
5fbf816f
DLR		 1760 struct port_info *pi = netdev_priv(dev);
1761 struct adapter *adapter = pi->adapter;
05b97b30 1762 struct qset_params *q;
5fbf816f 1763 int i;
4d22de3e
DLR		 1764
1765 if (e->rx_pending > MAX_RX_BUFFERS ||
1766 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS ||
1767 e->tx_pending > MAX_TXQ_ENTRIES ||
1768 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1769 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1770 e->rx_pending < MIN_FL_ENTRIES ||
1771 e->rx_jumbo_pending < MIN_FL_ENTRIES ||
1772 e->tx_pending < adapter->params.nports * MIN_TXQ_ENTRIES)
1773 return -EINVAL;
1774
1775 if (adapter->flags & FULL_INIT_DONE)
1776 return -EBUSY;
1777
05b97b30
DLR		 1778 q = &adapter->params.sge.qset[pi->first_qset];
1779 for (i = 0; i < pi->nqsets; ++i, ++q) {
4d22de3e
DLR		 1780 q->rspq_size = e->rx_mini_pending;
1781 q->fl_size = e->rx_pending;
1782 q->jumbo_size = e->rx_jumbo_pending;
1783 q->txq_size[0] = e->tx_pending;
1784 q->txq_size[1] = e->tx_pending;
1785 q->txq_size[2] = e->tx_pending;
1786 }
1787 return 0;
1788}
1789
1790static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1791{
5fbf816f
DLR		 1792 struct port_info *pi = netdev_priv(dev);
1793 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1794 struct qset_params *qsp = &adapter->params.sge.qset[0];
1795 struct sge_qset *qs = &adapter->sge.qs[0];
1796
1797 if (c->rx_coalesce_usecs * 10 > M_NEWTIMER)
1798 return -EINVAL;
1799
1800 qsp->coalesce_usecs = c->rx_coalesce_usecs;
1801 t3_update_qset_coalesce(qs, qsp);
1802 return 0;
1803}
1804
1805static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1806{
5fbf816f
DLR		 1807 struct port_info *pi = netdev_priv(dev);
1808 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1809 struct qset_params *q = adapter->params.sge.qset;
1810
1811 c->rx_coalesce_usecs = q->coalesce_usecs;
1812 return 0;
1813}
1814
1815static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
1816 u8 * data)
1817{
5fbf816f
DLR		 1818 struct port_info *pi = netdev_priv(dev);
1819 struct adapter *adapter = pi->adapter;
4d22de3e 1820 int i, err = 0;
4d22de3e
DLR		 1821
1822 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
1823 if (!buf)
1824 return -ENOMEM;
1825
1826 e->magic = EEPROM_MAGIC;
1827 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
05e5c116 1828 err = t3_seeprom_read(adapter, i, (__le32 *) & buf[i]);
4d22de3e
DLR		 1829
1830 if (!err)
1831 memcpy(data, buf + e->offset, e->len);
1832 kfree(buf);
1833 return err;
1834}
1835
1836static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
1837 u8 * data)
1838{
5fbf816f
DLR		 1839 struct port_info *pi = netdev_priv(dev);
1840 struct adapter *adapter = pi->adapter;
05e5c116
AV		 1841 u32 aligned_offset, aligned_len;
1842 __le32 *p;
4d22de3e 1843 u8 *buf;
c54f5c24 1844 int err;
4d22de3e
DLR		 1845
1846 if (eeprom->magic != EEPROM_MAGIC)
1847 return -EINVAL;
1848
1849 aligned_offset = eeprom->offset & ~3;
1850 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
1851
1852 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
1853 buf = kmalloc(aligned_len, GFP_KERNEL);
1854 if (!buf)
1855 return -ENOMEM;
05e5c116 1856 err = t3_seeprom_read(adapter, aligned_offset, (__le32 *) buf);
4d22de3e
DLR		 1857 if (!err && aligned_len > 4)
1858 err = t3_seeprom_read(adapter,
1859 aligned_offset + aligned_len - 4,
05e5c116 1860 (__le32 *) & buf[aligned_len - 4]);
4d22de3e
DLR		 1861 if (err)
1862 goto out;
1863 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
1864 } else
1865 buf = data;
1866
1867 err = t3_seeprom_wp(adapter, 0);
1868 if (err)
1869 goto out;
1870
05e5c116 1871 for (p = (__le32 *) buf; !err && aligned_len; aligned_len -= 4, p++) {
4d22de3e
DLR		 1872 err = t3_seeprom_write(adapter, aligned_offset, *p);
1873 aligned_offset += 4;
1874 }
1875
1876 if (!err)
1877 err = t3_seeprom_wp(adapter, 1);
1878out:
1879 if (buf != data)
1880 kfree(buf);
1881 return err;
1882}
1883
1884static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1885{
1886 wol->supported = 0;
1887 wol->wolopts = 0;
1888 memset(&wol->sopass, 0, sizeof(wol->sopass));
1889}
1890
1891static const struct ethtool_ops cxgb_ethtool_ops = {
1892 .get_settings = get_settings,
1893 .set_settings = set_settings,
1894 .get_drvinfo = get_drvinfo,
1895 .get_msglevel = get_msglevel,
1896 .set_msglevel = set_msglevel,
1897 .get_ringparam = get_sge_param,
1898 .set_ringparam = set_sge_param,
1899 .get_coalesce = get_coalesce,
1900 .set_coalesce = set_coalesce,
1901 .get_eeprom_len = get_eeprom_len,
1902 .get_eeprom = get_eeprom,
1903 .set_eeprom = set_eeprom,
1904 .get_pauseparam = get_pauseparam,
1905 .set_pauseparam = set_pauseparam,
1906 .get_rx_csum = get_rx_csum,
1907 .set_rx_csum = set_rx_csum,
4d22de3e 1908 .set_tx_csum = ethtool_op_set_tx_csum,
4d22de3e
DLR		 1909 .set_sg = ethtool_op_set_sg,
1910 .get_link = ethtool_op_get_link,
1911 .get_strings = get_strings,
1912 .phys_id = cxgb3_phys_id,
1913 .nway_reset = restart_autoneg,
b9f2c044 1914 .get_sset_count = get_sset_count,
4d22de3e
DLR		 1915 .get_ethtool_stats = get_stats,
1916 .get_regs_len = get_regs_len,
1917 .get_regs = get_regs,
1918 .get_wol = get_wol,
4d22de3e 1919 .set_tso = ethtool_op_set_tso,
4d22de3e
DLR		 1920};
1921
1922static int in_range(int val, int lo, int hi)
1923{
1924 return val < 0 || (val <= hi && val >= lo);
1925}
1926
1927static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr)
1928{
5fbf816f
DLR		 1929 struct port_info *pi = netdev_priv(dev);
1930 struct adapter *adapter = pi->adapter;
4d22de3e 1931 u32 cmd;
5fbf816f 1932 int ret;
4d22de3e
DLR		 1933
1934 if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
1935 return -EFAULT;
1936
1937 switch (cmd) {
4d22de3e
DLR		 1938 case CHELSIO_SET_QSET_PARAMS:{
1939 int i;
1940 struct qset_params *q;
1941 struct ch_qset_params t;
8c263761
DLR		 1942 int q1 = pi->first_qset;
1943 int nqsets = pi->nqsets;
4d22de3e
DLR		 1944
1945 if (!capable(CAP_NET_ADMIN))
1946 return -EPERM;
1947 if (copy_from_user(&t, useraddr, sizeof(t)))
1948 return -EFAULT;
1949 if (t.qset_idx >= SGE_QSETS)
1950 return -EINVAL;
1951 if (!in_range(t.intr_lat, 0, M_NEWTIMER) ||
1952 !in_range(t.cong_thres, 0, 255) ||
1953 !in_range(t.txq_size[0], MIN_TXQ_ENTRIES,
1954 MAX_TXQ_ENTRIES) ||
1955 !in_range(t.txq_size[1], MIN_TXQ_ENTRIES,
1956 MAX_TXQ_ENTRIES) ||
1957 !in_range(t.txq_size[2], MIN_CTRL_TXQ_ENTRIES,
1958 MAX_CTRL_TXQ_ENTRIES) ||
1959 !in_range(t.fl_size[0], MIN_FL_ENTRIES,
1960 MAX_RX_BUFFERS)
1961 || !in_range(t.fl_size[1], MIN_FL_ENTRIES,
1962 MAX_RX_JUMBO_BUFFERS)
1963 || !in_range(t.rspq_size, MIN_RSPQ_ENTRIES,
1964 MAX_RSPQ_ENTRIES))
1965 return -EINVAL;
8c263761
DLR		 1966
1967 if ((adapter->flags & FULL_INIT_DONE) && t.lro > 0)
1968 for_each_port(adapter, i) {
1969 pi = adap2pinfo(adapter, i);
1970 if (t.qset_idx >= pi->first_qset &&
1971 t.qset_idx < pi->first_qset + pi->nqsets &&
47fd23fe 1972 !(pi->rx_offload & T3_RX_CSUM))
8c263761
DLR		 1973 return -EINVAL;
1974 }
1975
4d22de3e
DLR		 1976 if ((adapter->flags & FULL_INIT_DONE) &&
1977 (t.rspq_size >= 0 || t.fl_size[0] >= 0 ||
1978 t.fl_size[1] >= 0 || t.txq_size[0] >= 0 ||
1979 t.txq_size[1] >= 0 || t.txq_size[2] >= 0 ||
1980 t.polling >= 0 || t.cong_thres >= 0))
1981 return -EBUSY;
1982
8c263761
DLR		 1983 /* Allow setting of any available qset when offload enabled */
1984 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
1985 q1 = 0;
1986 for_each_port(adapter, i) {
1987 pi = adap2pinfo(adapter, i);
1988 nqsets += pi->first_qset + pi->nqsets;
1989 }
1990 }
1991
1992 if (t.qset_idx < q1)
1993 return -EINVAL;
1994 if (t.qset_idx > q1 + nqsets - 1)
1995 return -EINVAL;
1996
4d22de3e
DLR		 1997 q = &adapter->params.sge.qset[t.qset_idx];
1998
1999 if (t.rspq_size >= 0)
2000 q->rspq_size = t.rspq_size;
2001 if (t.fl_size[0] >= 0)
2002 q->fl_size = t.fl_size[0];
2003 if (t.fl_size[1] >= 0)
2004 q->jumbo_size = t.fl_size[1];
2005 if (t.txq_size[0] >= 0)
2006 q->txq_size[0] = t.txq_size[0];
2007 if (t.txq_size[1] >= 0)
2008 q->txq_size[1] = t.txq_size[1];
2009 if (t.txq_size[2] >= 0)
2010 q->txq_size[2] = t.txq_size[2];
2011 if (t.cong_thres >= 0)
2012 q->cong_thres = t.cong_thres;
2013 if (t.intr_lat >= 0) {
2014 struct sge_qset *qs =
2015 &adapter->sge.qs[t.qset_idx];
2016
2017 q->coalesce_usecs = t.intr_lat;
2018 t3_update_qset_coalesce(qs, q);
2019 }
2020 if (t.polling >= 0) {
2021 if (adapter->flags & USING_MSIX)
2022 q->polling = t.polling;
2023 else {
2024 /* No polling with INTx for T3A */
2025 if (adapter->params.rev == 0 &&
2026 !(adapter->flags & USING_MSI))
2027 t.polling = 0;
2028
2029 for (i = 0; i < SGE_QSETS; i++) {
2030 q = &adapter->params.sge.
2031 qset[i];
2032 q->polling = t.polling;
2033 }
2034 }
2035 }
04ecb072
DLR		 2036 if (t.lro >= 0)
2037 set_qset_lro(dev, t.qset_idx, t.lro);
2038
4d22de3e
DLR		 2039 break;
2040 }
2041 case CHELSIO_GET_QSET_PARAMS:{
2042 struct qset_params *q;
2043 struct ch_qset_params t;
8c263761
DLR		 2044 int q1 = pi->first_qset;
2045 int nqsets = pi->nqsets;
2046 int i;
4d22de3e
DLR		 2047
2048 if (copy_from_user(&t, useraddr, sizeof(t)))
2049 return -EFAULT;
8c263761
DLR		 2050
2051 /* Display qsets for all ports when offload enabled */
2052 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2053 q1 = 0;
2054 for_each_port(adapter, i) {
2055 pi = adap2pinfo(adapter, i);
2056 nqsets = pi->first_qset + pi->nqsets;
2057 }
2058 }
2059
2060 if (t.qset_idx >= nqsets)
4d22de3e
DLR		 2061 return -EINVAL;
2062
8c263761 2063 q = &adapter->params.sge.qset[q1 + t.qset_idx];
4d22de3e
DLR		 2064 t.rspq_size = q->rspq_size;
2065 t.txq_size[0] = q->txq_size[0];
2066 t.txq_size[1] = q->txq_size[1];
2067 t.txq_size[2] = q->txq_size[2];
2068 t.fl_size[0] = q->fl_size;
2069 t.fl_size[1] = q->jumbo_size;
2070 t.polling = q->polling;
b47385bd 2071 t.lro = q->lro;
4d22de3e
DLR		 2072 t.intr_lat = q->coalesce_usecs;
2073 t.cong_thres = q->cong_thres;
8c263761
DLR		 2074 t.qnum = q1;
2075
2076 if (adapter->flags & USING_MSIX)
2077 t.vector = adapter->msix_info[q1 + t.qset_idx + 1].vec;
2078 else
2079 t.vector = adapter->pdev->irq;
4d22de3e
DLR		 2080
2081 if (copy_to_user(useraddr, &t, sizeof(t)))
2082 return -EFAULT;
2083 break;
2084 }
2085 case CHELSIO_SET_QSET_NUM:{
2086 struct ch_reg edata;
4d22de3e
DLR		 2087 unsigned int i, first_qset = 0, other_qsets = 0;
2088
2089 if (!capable(CAP_NET_ADMIN))
2090 return -EPERM;
2091 if (adapter->flags & FULL_INIT_DONE)
2092 return -EBUSY;
2093 if (copy_from_user(&edata, useraddr, sizeof(edata)))
2094 return -EFAULT;
2095 if (edata.val < 1 ||
2096 (edata.val > 1 && !(adapter->flags & USING_MSIX)))
2097 return -EINVAL;
2098
2099 for_each_port(adapter, i)
2100 if (adapter->port[i] && adapter->port[i] != dev)
2101 other_qsets += adap2pinfo(adapter, i)->nqsets;
2102
2103 if (edata.val + other_qsets > SGE_QSETS)
2104 return -EINVAL;
2105
2106 pi->nqsets = edata.val;
2107
2108 for_each_port(adapter, i)
2109 if (adapter->port[i]) {
2110 pi = adap2pinfo(adapter, i);
2111 pi->first_qset = first_qset;
2112 first_qset += pi->nqsets;
2113 }
2114 break;
2115 }
2116 case CHELSIO_GET_QSET_NUM:{
2117 struct ch_reg edata;
4d22de3e
DLR		 2118
2119 edata.cmd = CHELSIO_GET_QSET_NUM;
2120 edata.val = pi->nqsets;
2121 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2122 return -EFAULT;
2123 break;
2124 }
2125 case CHELSIO_LOAD_FW:{
2126 u8 *fw_data;
2127 struct ch_mem_range t;
2128
1b3aa7af 2129 if (!capable(CAP_SYS_RAWIO))
4d22de3e
DLR		 2130 return -EPERM;
2131 if (copy_from_user(&t, useraddr, sizeof(t)))
2132 return -EFAULT;
1b3aa7af 2133 /* Check t.len sanity ? */
4d22de3e
DLR		 2134 fw_data = kmalloc(t.len, GFP_KERNEL);
2135 if (!fw_data)
2136 return -ENOMEM;
2137
2138 if (copy_from_user
2139 (fw_data, useraddr + sizeof(t), t.len)) {
2140 kfree(fw_data);
2141 return -EFAULT;
2142 }
2143
2144 ret = t3_load_fw(adapter, fw_data, t.len);
2145 kfree(fw_data);
2146 if (ret)
2147 return ret;
2148 break;
2149 }
2150 case CHELSIO_SETMTUTAB:{
2151 struct ch_mtus m;
2152 int i;
2153
2154 if (!is_offload(adapter))
2155 return -EOPNOTSUPP;
2156 if (!capable(CAP_NET_ADMIN))
2157 return -EPERM;
2158 if (offload_running(adapter))
2159 return -EBUSY;
2160 if (copy_from_user(&m, useraddr, sizeof(m)))
2161 return -EFAULT;
2162 if (m.nmtus != NMTUS)
2163 return -EINVAL;
2164 if (m.mtus[0] < 81) /* accommodate SACK */
2165 return -EINVAL;
2166
2167 /* MTUs must be in ascending order */
2168 for (i = 1; i < NMTUS; ++i)
2169 if (m.mtus[i] < m.mtus[i - 1])
2170 return -EINVAL;
2171
2172 memcpy(adapter->params.mtus, m.mtus,
2173 sizeof(adapter->params.mtus));
2174 break;
2175 }
2176 case CHELSIO_GET_PM:{
2177 struct tp_params *p = &adapter->params.tp;
2178 struct ch_pm m = {.cmd = CHELSIO_GET_PM };
2179
2180 if (!is_offload(adapter))
2181 return -EOPNOTSUPP;
2182 m.tx_pg_sz = p->tx_pg_size;
2183 m.tx_num_pg = p->tx_num_pgs;
2184 m.rx_pg_sz = p->rx_pg_size;
2185 m.rx_num_pg = p->rx_num_pgs;
2186 m.pm_total = p->pmtx_size + p->chan_rx_size * p->nchan;
2187 if (copy_to_user(useraddr, &m, sizeof(m)))
2188 return -EFAULT;
2189 break;
2190 }
2191 case CHELSIO_SET_PM:{
2192 struct ch_pm m;
2193 struct tp_params *p = &adapter->params.tp;
2194
2195 if (!is_offload(adapter))
2196 return -EOPNOTSUPP;
2197 if (!capable(CAP_NET_ADMIN))
2198 return -EPERM;
2199 if (adapter->flags & FULL_INIT_DONE)
2200 return -EBUSY;
2201 if (copy_from_user(&m, useraddr, sizeof(m)))
2202 return -EFAULT;
d9da466a 2203 if (!is_power_of_2(m.rx_pg_sz) ||
2204 !is_power_of_2(m.tx_pg_sz))
4d22de3e
DLR		 2205 return -EINVAL; /* not power of 2 */
2206 if (!(m.rx_pg_sz & 0x14000))
2207 return -EINVAL; /* not 16KB or 64KB */
2208 if (!(m.tx_pg_sz & 0x1554000))
2209 return -EINVAL;
2210 if (m.tx_num_pg == -1)
2211 m.tx_num_pg = p->tx_num_pgs;
2212 if (m.rx_num_pg == -1)
2213 m.rx_num_pg = p->rx_num_pgs;
2214 if (m.tx_num_pg % 24 || m.rx_num_pg % 24)
2215 return -EINVAL;
2216 if (m.rx_num_pg * m.rx_pg_sz > p->chan_rx_size ||
2217 m.tx_num_pg * m.tx_pg_sz > p->chan_tx_size)
2218 return -EINVAL;
2219 p->rx_pg_size = m.rx_pg_sz;
2220 p->tx_pg_size = m.tx_pg_sz;
2221 p->rx_num_pgs = m.rx_num_pg;
2222 p->tx_num_pgs = m.tx_num_pg;
2223 break;
2224 }
2225 case CHELSIO_GET_MEM:{
2226 struct ch_mem_range t;
2227 struct mc7 *mem;
2228 u64 buf[32];
2229
2230 if (!is_offload(adapter))
2231 return -EOPNOTSUPP;
2232 if (!(adapter->flags & FULL_INIT_DONE))
2233 return -EIO; /* need the memory controllers */
2234 if (copy_from_user(&t, useraddr, sizeof(t)))
2235 return -EFAULT;
2236 if ((t.addr & 7) || (t.len & 7))
2237 return -EINVAL;
2238 if (t.mem_id == MEM_CM)
2239 mem = &adapter->cm;
2240 else if (t.mem_id == MEM_PMRX)
2241 mem = &adapter->pmrx;
2242 else if (t.mem_id == MEM_PMTX)
2243 mem = &adapter->pmtx;
2244 else
2245 return -EINVAL;
2246
2247 /*
1825494a
DLR		 2248 * Version scheme:
2249 * bits 0..9: chip version
2250 * bits 10..15: chip revision
2251 */
4d22de3e
DLR		 2252 t.version = 3 | (adapter->params.rev << 10);
2253 if (copy_to_user(useraddr, &t, sizeof(t)))
2254 return -EFAULT;
2255
2256 /*
2257 * Read 256 bytes at a time as len can be large and we don't
2258 * want to use huge intermediate buffers.
2259 */
2260 useraddr += sizeof(t); /* advance to start of buffer */
2261 while (t.len) {
2262 unsigned int chunk =
2263 min_t(unsigned int, t.len, sizeof(buf));
2264
2265 ret =
2266 t3_mc7_bd_read(mem, t.addr / 8, chunk / 8,
2267 buf);
2268 if (ret)
2269 return ret;
2270 if (copy_to_user(useraddr, buf, chunk))
2271 return -EFAULT;
2272 useraddr += chunk;
2273 t.addr += chunk;
2274 t.len -= chunk;
2275 }
2276 break;
2277 }
2278 case CHELSIO_SET_TRACE_FILTER:{
2279 struct ch_trace t;
2280 const struct trace_params *tp;
2281
2282 if (!capable(CAP_NET_ADMIN))
2283 return -EPERM;
2284 if (!offload_running(adapter))
2285 return -EAGAIN;
2286 if (copy_from_user(&t, useraddr, sizeof(t)))
2287 return -EFAULT;
2288
2289 tp = (const struct trace_params *)&t.sip;
2290 if (t.config_tx)
2291 t3_config_trace_filter(adapter, tp, 0,
2292 t.invert_match,
2293 t.trace_tx);
2294 if (t.config_rx)
2295 t3_config_trace_filter(adapter, tp, 1,
2296 t.invert_match,
2297 t.trace_rx);
2298 break;
2299 }
4d22de3e
DLR		 2300 default:
2301 return -EOPNOTSUPP;
2302 }
2303 return 0;
2304}
2305
2306static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2307{
4d22de3e 2308 struct mii_ioctl_data *data = if_mii(req);
5fbf816f
DLR		 2309 struct port_info *pi = netdev_priv(dev);
2310 struct adapter *adapter = pi->adapter;
2311 int ret, mmd;
4d22de3e
DLR		 2312
2313 switch (cmd) {
2314 case SIOCGMIIPHY:
2315 data->phy_id = pi->phy.addr;
2316 /* FALLTHRU */
2317 case SIOCGMIIREG:{
2318 u32 val;
2319 struct cphy *phy = &pi->phy;
2320
2321 if (!phy->mdio_read)
2322 return -EOPNOTSUPP;
2323 if (is_10G(adapter)) {
2324 mmd = data->phy_id >> 8;
2325 if (!mmd)
2326 mmd = MDIO_DEV_PCS;
9b1e3656 2327 else if (mmd > MDIO_DEV_VEND2)
4d22de3e
DLR		 2328 return -EINVAL;
2329
2330 ret =
2331 phy->mdio_read(adapter, data->phy_id & 0x1f,
2332 mmd, data->reg_num, &val);
2333 } else
2334 ret =
2335 phy->mdio_read(adapter, data->phy_id & 0x1f,
2336 0, data->reg_num & 0x1f,
2337 &val);
2338 if (!ret)
2339 data->val_out = val;
2340 break;
2341 }
2342 case SIOCSMIIREG:{
2343 struct cphy *phy = &pi->phy;
2344
2345 if (!capable(CAP_NET_ADMIN))
2346 return -EPERM;
2347 if (!phy->mdio_write)
2348 return -EOPNOTSUPP;
2349 if (is_10G(adapter)) {
2350 mmd = data->phy_id >> 8;
2351 if (!mmd)
2352 mmd = MDIO_DEV_PCS;
9b1e3656 2353 else if (mmd > MDIO_DEV_VEND2)
4d22de3e
DLR		 2354 return -EINVAL;
2355
2356 ret =
2357 phy->mdio_write(adapter,
2358 data->phy_id & 0x1f, mmd,
2359 data->reg_num,
2360 data->val_in);
2361 } else
2362 ret =
2363 phy->mdio_write(adapter,
2364 data->phy_id & 0x1f, 0,
2365 data->reg_num & 0x1f,
2366 data->val_in);
2367 break;
2368 }
2369 case SIOCCHIOCTL:
2370 return cxgb_extension_ioctl(dev, req->ifr_data);
2371 default:
2372 return -EOPNOTSUPP;
2373 }
2374 return ret;
2375}
2376
2377static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2378{
4d22de3e 2379 struct port_info *pi = netdev_priv(dev);
5fbf816f
DLR		 2380 struct adapter *adapter = pi->adapter;
2381 int ret;
4d22de3e
DLR		 2382
2383 if (new_mtu < 81) /* accommodate SACK */
2384 return -EINVAL;
2385 if ((ret = t3_mac_set_mtu(&pi->mac, new_mtu)))
2386 return ret;
2387 dev->mtu = new_mtu;
2388 init_port_mtus(adapter);
2389 if (adapter->params.rev == 0 && offload_running(adapter))
2390 t3_load_mtus(adapter, adapter->params.mtus,
2391 adapter->params.a_wnd, adapter->params.b_wnd,
2392 adapter->port[0]->mtu);
2393 return 0;
2394}
2395
2396static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2397{
4d22de3e 2398 struct port_info *pi = netdev_priv(dev);
5fbf816f 2399 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2400 struct sockaddr *addr = p;
2401
2402 if (!is_valid_ether_addr(addr->sa_data))
2403 return -EINVAL;
2404
2405 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2406 t3_mac_set_address(&pi->mac, 0, dev->dev_addr);
2407 if (offload_running(adapter))
2408 write_smt_entry(adapter, pi->port_id);
2409 return 0;
2410}
2411
2412/**
2413 * t3_synchronize_rx - wait for current Rx processing on a port to complete
2414 * @adap: the adapter
2415 * @p: the port
2416 *
2417 * Ensures that current Rx processing on any of the queues associated with
2418 * the given port completes before returning. We do this by acquiring and
2419 * releasing the locks of the response queues associated with the port.
2420 */
2421static void t3_synchronize_rx(struct adapter *adap, const struct port_info *p)
2422{
2423 int i;
2424
8c263761
DLR		 2425 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
2426 struct sge_rspq *q = &adap->sge.qs[i].rspq;
4d22de3e
DLR		 2427
2428 spin_lock_irq(&q->lock);
2429 spin_unlock_irq(&q->lock);
2430 }
2431}
2432
2433static void vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2434{
4d22de3e 2435 struct port_info *pi = netdev_priv(dev);
5fbf816f 2436 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2437
2438 pi->vlan_grp = grp;
2439 if (adapter->params.rev > 0)
2440 t3_set_vlan_accel(adapter, 1 << pi->port_id, grp != NULL);
2441 else {
2442 /* single control for all ports */
2443 unsigned int i, have_vlans = 0;
2444 for_each_port(adapter, i)
2445 have_vlans |= adap2pinfo(adapter, i)->vlan_grp != NULL;
2446
2447 t3_set_vlan_accel(adapter, 1, have_vlans);
2448 }
2449 t3_synchronize_rx(adapter, pi);
2450}
2451
4d22de3e
DLR		 2452#ifdef CONFIG_NET_POLL_CONTROLLER
2453static void cxgb_netpoll(struct net_device *dev)
2454{
890de332 2455 struct port_info *pi = netdev_priv(dev);
5fbf816f 2456 struct adapter *adapter = pi->adapter;
890de332 2457 int qidx;
4d22de3e 2458
890de332
DLR		 2459 for (qidx = pi->first_qset; qidx < pi->first_qset + pi->nqsets; qidx++) {
2460 struct sge_qset *qs = &adapter->sge.qs[qidx];
2461 void *source;
2eab17ab 2462
890de332
DLR		 2463 if (adapter->flags & USING_MSIX)
2464 source = qs;
2465 else
2466 source = adapter;
2467
2468 t3_intr_handler(adapter, qs->rspq.polling) (0, source);
2469 }
4d22de3e
DLR		 2470}
2471#endif
2472
2473/*
2474 * Periodic accumulation of MAC statistics.
2475 */
2476static void mac_stats_update(struct adapter *adapter)
2477{
2478 int i;
2479
2480 for_each_port(adapter, i) {
2481 struct net_device *dev = adapter->port[i];
2482 struct port_info *p = netdev_priv(dev);
2483
2484 if (netif_running(dev)) {
2485 spin_lock(&adapter->stats_lock);
2486 t3_mac_update_stats(&p->mac);
2487 spin_unlock(&adapter->stats_lock);
2488 }
2489 }
2490}
2491
2492static void check_link_status(struct adapter *adapter)
2493{
2494 int i;
2495
2496 for_each_port(adapter, i) {
2497 struct net_device *dev = adapter->port[i];
2498 struct port_info *p = netdev_priv(dev);
2499
bf792094
DLR		 2500 spin_lock_irq(&adapter->work_lock);
2501 if (p->link_fault) {
3851c66c 2502 t3_link_fault(adapter, i);
bf792094
DLR		 2503 spin_unlock_irq(&adapter->work_lock);
2504 continue;
2505 }
2506 spin_unlock_irq(&adapter->work_lock);
2507
2508 if (!(p->phy.caps & SUPPORTED_IRQ) && netif_running(dev)) {
2509 t3_xgm_intr_disable(adapter, i);
2510 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2511
4d22de3e 2512 t3_link_changed(adapter, i);
bf792094
DLR		 2513 t3_xgm_intr_enable(adapter, i);
2514 }
4d22de3e
DLR		 2515 }
2516}
2517
fc90664e
DLR		 2518static void check_t3b2_mac(struct adapter *adapter)
2519{
2520 int i;
2521
f2d961c9
DLR		 2522 if (!rtnl_trylock()) /* synchronize with ifdown */
2523 return;
2524
fc90664e
DLR		 2525 for_each_port(adapter, i) {
2526 struct net_device *dev = adapter->port[i];
2527 struct port_info *p = netdev_priv(dev);
2528 int status;
2529
2530 if (!netif_running(dev))
2531 continue;
2532
2533 status = 0;
6d6dabac 2534 if (netif_running(dev) && netif_carrier_ok(dev))
fc90664e
DLR		 2535 status = t3b2_mac_watchdog_task(&p->mac);
2536 if (status == 1)
2537 p->mac.stats.num_toggled++;
2538 else if (status == 2) {
2539 struct cmac *mac = &p->mac;
2540
2541 t3_mac_set_mtu(mac, dev->mtu);
2542 t3_mac_set_address(mac, 0, dev->dev_addr);
2543 cxgb_set_rxmode(dev);
2544 t3_link_start(&p->phy, mac, &p->link_config);
2545 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
2546 t3_port_intr_enable(adapter, p->port_id);
2547 p->mac.stats.num_resets++;
2548 }
2549 }
2550 rtnl_unlock();
2551}
2552
2553
4d22de3e
DLR		 2554static void t3_adap_check_task(struct work_struct *work)
2555{
2556 struct adapter *adapter = container_of(work, struct adapter,
2557 adap_check_task.work);
2558 const struct adapter_params *p = &adapter->params;
fc882196
DLR		 2559 int port;
2560 unsigned int v, status, reset;
4d22de3e
DLR		 2561
2562 adapter->check_task_cnt++;
2563
3851c66c 2564 check_link_status(adapter);
4d22de3e
DLR		 2565
2566 /* Accumulate MAC stats if needed */
2567 if (!p->linkpoll_period ||
2568 (adapter->check_task_cnt * p->linkpoll_period) / 10 >=
2569 p->stats_update_period) {
2570 mac_stats_update(adapter);
2571 adapter->check_task_cnt = 0;
2572 }
2573
fc90664e
DLR		 2574 if (p->rev == T3_REV_B2)
2575 check_t3b2_mac(adapter);
2576
fc882196
DLR		 2577 /*
2578 * Scan the XGMAC's to check for various conditions which we want to
2579 * monitor in a periodic polling manner rather than via an interrupt
2580 * condition. This is used for conditions which would otherwise flood
2581 * the system with interrupts and we only really need to know that the
2582 * conditions are "happening" ... For each condition we count the
2583 * detection of the condition and reset it for the next polling loop.
2584 */
2585 for_each_port(adapter, port) {
2586 struct cmac *mac = &adap2pinfo(adapter, port)->mac;
2587 u32 cause;
2588
2589 cause = t3_read_reg(adapter, A_XGM_INT_CAUSE + mac->offset);
2590 reset = 0;
2591 if (cause & F_RXFIFO_OVERFLOW) {
2592 mac->stats.rx_fifo_ovfl++;
2593 reset |= F_RXFIFO_OVERFLOW;
2594 }
2595
2596 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, reset);
2597 }
2598
2599 /*
2600 * We do the same as above for FL_EMPTY interrupts.
2601 */
2602 status = t3_read_reg(adapter, A_SG_INT_CAUSE);
2603 reset = 0;
2604
2605 if (status & F_FLEMPTY) {
2606 struct sge_qset *qs = &adapter->sge.qs[0];
2607 int i = 0;
2608
2609 reset |= F_FLEMPTY;
2610
2611 v = (t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS) >> S_FL0EMPTY) &
2612 0xffff;
2613
2614 while (v) {
2615 qs->fl[i].empty += (v & 1);
2616 if (i)
2617 qs++;
2618 i ^= 1;
2619 v >>= 1;
2620 }
2621 }
2622
2623 t3_write_reg(adapter, A_SG_INT_CAUSE, reset);
2624
4d22de3e 2625 /* Schedule the next check update if any port is active. */
20d3fc11 2626 spin_lock_irq(&adapter->work_lock);
4d22de3e
DLR		 2627 if (adapter->open_device_map & PORT_MASK)
2628 schedule_chk_task(adapter);
20d3fc11 2629 spin_unlock_irq(&adapter->work_lock);
4d22de3e
DLR		 2630}
2631
2632/*
2633 * Processes external (PHY) interrupts in process context.
2634 */
2635static void ext_intr_task(struct work_struct *work)
2636{
2637 struct adapter *adapter = container_of(work, struct adapter,
2638 ext_intr_handler_task);
bf792094
DLR		 2639 int i;
2640
2641 /* Disable link fault interrupts */
2642 for_each_port(adapter, i) {
2643 struct net_device *dev = adapter->port[i];
2644 struct port_info *p = netdev_priv(dev);
2645
2646 t3_xgm_intr_disable(adapter, i);
2647 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2648 }
4d22de3e 2649
bf792094 2650 /* Re-enable link fault interrupts */
4d22de3e
DLR		 2651 t3_phy_intr_handler(adapter);
2652
bf792094
DLR		 2653 for_each_port(adapter, i)
2654 t3_xgm_intr_enable(adapter, i);
2655
4d22de3e
DLR		 2656 /* Now reenable external interrupts */
2657 spin_lock_irq(&adapter->work_lock);
2658 if (adapter->slow_intr_mask) {
2659 adapter->slow_intr_mask |= F_T3DBG;
2660 t3_write_reg(adapter, A_PL_INT_CAUSE0, F_T3DBG);
2661 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2662 adapter->slow_intr_mask);
2663 }
2664 spin_unlock_irq(&adapter->work_lock);
2665}
2666
2667/*
2668 * Interrupt-context handler for external (PHY) interrupts.
2669 */
2670void t3_os_ext_intr_handler(struct adapter *adapter)
2671{
2672 /*
2673 * Schedule a task to handle external interrupts as they may be slow
2674 * and we use a mutex to protect MDIO registers. We disable PHY
2675 * interrupts in the meantime and let the task reenable them when
2676 * it's done.
2677 */
2678 spin_lock(&adapter->work_lock);
2679 if (adapter->slow_intr_mask) {
2680 adapter->slow_intr_mask &= ~F_T3DBG;
2681 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2682 adapter->slow_intr_mask);
2683 queue_work(cxgb3_wq, &adapter->ext_intr_handler_task);
2684 }
2685 spin_unlock(&adapter->work_lock);
2686}
2687
bf792094
DLR		 2688void t3_os_link_fault_handler(struct adapter *adapter, int port_id)
2689{
2690 struct net_device *netdev = adapter->port[port_id];
2691 struct port_info *pi = netdev_priv(netdev);
2692
2693 spin_lock(&adapter->work_lock);
2694 pi->link_fault = 1;
bf792094
DLR		 2695 spin_unlock(&adapter->work_lock);
2696}
2697
20d3fc11
DLR		 2698static int t3_adapter_error(struct adapter *adapter, int reset)
2699{
2700 int i, ret = 0;
2701
cb0bc205
DLR		 2702 if (is_offload(adapter) &&
2703 test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2704 cxgb3_err_notify(&adapter->tdev, OFFLOAD_STATUS_DOWN, 0);
2705 offload_close(&adapter->tdev);
2706 }
2707
20d3fc11
DLR		 2708 /* Stop all ports */
2709 for_each_port(adapter, i) {
2710 struct net_device *netdev = adapter->port[i];
2711
2712 if (netif_running(netdev))
2713 cxgb_close(netdev);
2714 }
2715
20d3fc11
DLR		 2716 /* Stop SGE timers */
2717 t3_stop_sge_timers(adapter);
2718
2719 adapter->flags &= ~FULL_INIT_DONE;
2720
2721 if (reset)
2722 ret = t3_reset_adapter(adapter);
2723
2724 pci_disable_device(adapter->pdev);
2725
2726 return ret;
2727}
2728
2729static int t3_reenable_adapter(struct adapter *adapter)
2730{
2731 if (pci_enable_device(adapter->pdev)) {
2732 dev_err(&adapter->pdev->dev,
2733 "Cannot re-enable PCI device after reset.\n");
2734 goto err;
2735 }
2736 pci_set_master(adapter->pdev);
2737 pci_restore_state(adapter->pdev);
2738
2739 /* Free sge resources */
2740 t3_free_sge_resources(adapter);
2741
2742 if (t3_replay_prep_adapter(adapter))
2743 goto err;
2744
2745 return 0;
2746err:
2747 return -1;
2748}
2749
2750static void t3_resume_ports(struct adapter *adapter)
2751{
2752 int i;
2753
2754 /* Restart the ports */
2755 for_each_port(adapter, i) {
2756 struct net_device *netdev = adapter->port[i];
2757
2758 if (netif_running(netdev)) {
2759 if (cxgb_open(netdev)) {
2760 dev_err(&adapter->pdev->dev,
2761 "can't bring device back up"
2762 " after reset\n");
2763 continue;
2764 }
2765 }
2766 }
cb0bc205
DLR		 2767
2768 if (is_offload(adapter) && !ofld_disable)
2769 cxgb3_err_notify(&adapter->tdev, OFFLOAD_STATUS_UP, 0);
20d3fc11
DLR		 2770}
2771
2772/*
2773 * processes a fatal error.
2774 * Bring the ports down, reset the chip, bring the ports back up.
2775 */
2776static void fatal_error_task(struct work_struct *work)
2777{
2778 struct adapter *adapter = container_of(work, struct adapter,
2779 fatal_error_handler_task);
2780 int err = 0;
2781
2782 rtnl_lock();
2783 err = t3_adapter_error(adapter, 1);
2784 if (!err)
2785 err = t3_reenable_adapter(adapter);
2786 if (!err)
2787 t3_resume_ports(adapter);
2788
2789 CH_ALERT(adapter, "adapter reset %s\n", err ? "failed" : "succeeded");
2790 rtnl_unlock();
2791}
2792
4d22de3e
DLR		 2793void t3_fatal_err(struct adapter *adapter)
2794{
2795 unsigned int fw_status[4];
2796
2797 if (adapter->flags & FULL_INIT_DONE) {
2798 t3_sge_stop(adapter);
c64c2eae
DLR		 2799 t3_write_reg(adapter, A_XGM_TX_CTRL, 0);
2800 t3_write_reg(adapter, A_XGM_RX_CTRL, 0);
2801 t3_write_reg(adapter, XGM_REG(A_XGM_TX_CTRL, 1), 0);
2802 t3_write_reg(adapter, XGM_REG(A_XGM_RX_CTRL, 1), 0);
20d3fc11
DLR		 2803
2804 spin_lock(&adapter->work_lock);
4d22de3e 2805 t3_intr_disable(adapter);
20d3fc11
DLR		 2806 queue_work(cxgb3_wq, &adapter->fatal_error_handler_task);
2807 spin_unlock(&adapter->work_lock);
4d22de3e
DLR		 2808 }
2809 CH_ALERT(adapter, "encountered fatal error, operation suspended\n");
2810 if (!t3_cim_ctl_blk_read(adapter, 0xa0, 4, fw_status))
2811 CH_ALERT(adapter, "FW status: 0x%x, 0x%x, 0x%x, 0x%x\n",
2812 fw_status[0], fw_status[1],
2813 fw_status[2], fw_status[3]);
4d22de3e
DLR		 2814}
2815
91a6b50c
DLR		 2816/**
2817 * t3_io_error_detected - called when PCI error is detected
2818 * @pdev: Pointer to PCI device
2819 * @state: The current pci connection state
2820 *
2821 * This function is called after a PCI bus error affecting
2822 * this device has been detected.
2823 */
2824static pci_ers_result_t t3_io_error_detected(struct pci_dev *pdev,
2825 pci_channel_state_t state)
2826{
bc4b6b52 2827 struct adapter *adapter = pci_get_drvdata(pdev);
20d3fc11 2828 int ret;
91a6b50c 2829
e8d19370
DLR		 2830 if (state == pci_channel_io_perm_failure)
2831 return PCI_ERS_RESULT_DISCONNECT;
2832
20d3fc11 2833 ret = t3_adapter_error(adapter, 0);
91a6b50c 2834
48c4b6db 2835 /* Request a slot reset. */
91a6b50c
DLR		 2836 return PCI_ERS_RESULT_NEED_RESET;
2837}
2838
2839/**
2840 * t3_io_slot_reset - called after the pci bus has been reset.
2841 * @pdev: Pointer to PCI device
2842 *
2843 * Restart the card from scratch, as if from a cold-boot.
2844 */
2845static pci_ers_result_t t3_io_slot_reset(struct pci_dev *pdev)
2846{
bc4b6b52 2847 struct adapter *adapter = pci_get_drvdata(pdev);
91a6b50c 2848
20d3fc11
DLR		 2849 if (!t3_reenable_adapter(adapter))
2850 return PCI_ERS_RESULT_RECOVERED;
91a6b50c 2851
48c4b6db 2852 return PCI_ERS_RESULT_DISCONNECT;
91a6b50c
DLR		 2853}
2854
2855/**
2856 * t3_io_resume - called when traffic can start flowing again.
2857 * @pdev: Pointer to PCI device
2858 *
2859 * This callback is called when the error recovery driver tells us that
2860 * its OK to resume normal operation.
2861 */
2862static void t3_io_resume(struct pci_dev *pdev)
2863{
bc4b6b52 2864 struct adapter *adapter = pci_get_drvdata(pdev);
91a6b50c 2865
68f40c10
DLR		 2866 CH_ALERT(adapter, "adapter recovering, PEX ERR 0x%x\n",
2867 t3_read_reg(adapter, A_PCIE_PEX_ERR));
2868
20d3fc11 2869 t3_resume_ports(adapter);
91a6b50c
DLR		 2870}
2871
2872static struct pci_error_handlers t3_err_handler = {
2873 .error_detected = t3_io_error_detected,
2874 .slot_reset = t3_io_slot_reset,
2875 .resume = t3_io_resume,
2876};
2877
8c263761
DLR		 2878/*
2879 * Set the number of qsets based on the number of CPUs and the number of ports,
2880 * not to exceed the number of available qsets, assuming there are enough qsets
2881 * per port in HW.
2882 */
2883static void set_nqsets(struct adapter *adap)
2884{
2885 int i, j = 0;
2886 int num_cpus = num_online_cpus();
2887 int hwports = adap->params.nports;
5cda9364 2888 int nqsets = adap->msix_nvectors - 1;
8c263761 2889
f9ee3882 2890 if (adap->params.rev > 0 && adap->flags & USING_MSIX) {
8c263761
DLR		 2891 if (hwports == 2 &&
2892 (hwports * nqsets > SGE_QSETS ||
2893 num_cpus >= nqsets / hwports))
2894 nqsets /= hwports;
2895 if (nqsets > num_cpus)
2896 nqsets = num_cpus;
2897 if (nqsets < 1 || hwports == 4)
2898 nqsets = 1;
2899 } else
2900 nqsets = 1;
2901
2902 for_each_port(adap, i) {
2903 struct port_info *pi = adap2pinfo(adap, i);
2904
2905 pi->first_qset = j;
2906 pi->nqsets = nqsets;
2907 j = pi->first_qset + nqsets;
2908
2909 dev_info(&adap->pdev->dev,
2910 "Port %d using %d queue sets.\n", i, nqsets);
2911 }
2912}
2913
4d22de3e
DLR		 2914static int __devinit cxgb_enable_msix(struct adapter *adap)
2915{
2916 struct msix_entry entries[SGE_QSETS + 1];
5cda9364 2917 int vectors;
4d22de3e
DLR		 2918 int i, err;
2919
5cda9364
DLR		 2920 vectors = ARRAY_SIZE(entries);
2921 for (i = 0; i < vectors; ++i)
4d22de3e
DLR		 2922 entries[i].entry = i;
2923
5cda9364
DLR		 2924 while ((err = pci_enable_msix(adap->pdev, entries, vectors)) > 0)
2925 vectors = err;
2926
2c2f409f
DLR		 2927 if (err < 0)
2928 pci_disable_msix(adap->pdev);
2929
2930 if (!err && vectors < (adap->params.nports + 1)) {
2931 pci_disable_msix(adap->pdev);
5cda9364 2932 err = -1;
2c2f409f 2933 }
5cda9364 2934
4d22de3e 2935 if (!err) {
5cda9364 2936 for (i = 0; i < vectors; ++i)
4d22de3e 2937 adap->msix_info[i].vec = entries[i].vector;
5cda9364
DLR		 2938 adap->msix_nvectors = vectors;
2939 }
2940
4d22de3e
DLR		 2941 return err;
2942}
2943
2944static void __devinit print_port_info(struct adapter *adap,
2945 const struct adapter_info *ai)
2946{
2947 static const char *pci_variant[] = {
2948 "PCI", "PCI-X", "PCI-X ECC", "PCI-X 266", "PCI Express"
2949 };
2950
2951 int i;
2952 char buf[80];
2953
2954 if (is_pcie(adap))
2955 snprintf(buf, sizeof(buf), "%s x%d",
2956 pci_variant[adap->params.pci.variant],
2957 adap->params.pci.width);
2958 else
2959 snprintf(buf, sizeof(buf), "%s %dMHz/%d-bit",
2960 pci_variant[adap->params.pci.variant],
2961 adap->params.pci.speed, adap->params.pci.width);
2962
2963 for_each_port(adap, i) {
2964 struct net_device *dev = adap->port[i];
2965 const struct port_info *pi = netdev_priv(dev);
2966
2967 if (!test_bit(i, &adap->registered_device_map))
2968 continue;
8ac3ba68 2969 printk(KERN_INFO "%s: %s %s %sNIC (rev %d) %s%s\n",
04497982 2970 dev->name, ai->desc, pi->phy.desc,
8ac3ba68 2971 is_offload(adap) ? "R" : "", adap->params.rev, buf,
4d22de3e
DLR		 2972 (adap->flags & USING_MSIX) ? " MSI-X" :
2973 (adap->flags & USING_MSI) ? " MSI" : "");
2974 if (adap->name == dev->name && adap->params.vpd.mclk)
167cdf5f
DLR		 2975 printk(KERN_INFO
2976 "%s: %uMB CM, %uMB PMTX, %uMB PMRX, S/N: %s\n",
4d22de3e
DLR		 2977 adap->name, t3_mc7_size(&adap->cm) >> 20,
2978 t3_mc7_size(&adap->pmtx) >> 20,
167cdf5f
DLR		 2979 t3_mc7_size(&adap->pmrx) >> 20,
2980 adap->params.vpd.sn);
4d22de3e
DLR		 2981 }
2982}
2983
dd752696
SH		 2984static const struct net_device_ops cxgb_netdev_ops = {
2985 .ndo_open = cxgb_open,
2986 .ndo_stop = cxgb_close,
43a944f3 2987 .ndo_start_xmit = t3_eth_xmit,
dd752696
SH		 2988 .ndo_get_stats = cxgb_get_stats,
2989 .ndo_validate_addr = eth_validate_addr,
2990 .ndo_set_multicast_list = cxgb_set_rxmode,
2991 .ndo_do_ioctl = cxgb_ioctl,
2992 .ndo_change_mtu = cxgb_change_mtu,
2993 .ndo_set_mac_address = cxgb_set_mac_addr,
2994 .ndo_vlan_rx_register = vlan_rx_register,
2995#ifdef CONFIG_NET_POLL_CONTROLLER
2996 .ndo_poll_controller = cxgb_netpoll,
2997#endif
2998};
2999
4d22de3e
DLR		 3000static int __devinit init_one(struct pci_dev *pdev,
3001 const struct pci_device_id *ent)
3002{
3003 static int version_printed;
3004
3005 int i, err, pci_using_dac = 0;
68f40c10 3006 resource_size_t mmio_start, mmio_len;
4d22de3e
DLR		 3007 const struct adapter_info *ai;
3008 struct adapter *adapter = NULL;
3009 struct port_info *pi;
3010
3011 if (!version_printed) {
3012 printk(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
3013 ++version_printed;
3014 }
3015
3016 if (!cxgb3_wq) {
3017 cxgb3_wq = create_singlethread_workqueue(DRV_NAME);
3018 if (!cxgb3_wq) {
3019 printk(KERN_ERR DRV_NAME
3020 ": cannot initialize work queue\n");
3021 return -ENOMEM;
3022 }
3023 }
3024
3025 err = pci_request_regions(pdev, DRV_NAME);
3026 if (err) {
3027 /* Just info, some other driver may have claimed the device. */
3028 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
3029 return err;
3030 }
3031
3032 err = pci_enable_device(pdev);
3033 if (err) {
3034 dev_err(&pdev->dev, "cannot enable PCI device\n");
3035 goto out_release_regions;
3036 }
3037
6a35528a 3038 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4d22de3e 3039 pci_using_dac = 1;
6a35528a 3040 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4d22de3e
DLR		 3041 if (err) {
3042 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
3043 "coherent allocations\n");
3044 goto out_disable_device;
3045 }
284901a9 3046 } else if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
4d22de3e
DLR		 3047 dev_err(&pdev->dev, "no usable DMA configuration\n");
3048 goto out_disable_device;
3049 }
3050
3051 pci_set_master(pdev);
204e2f98 3052 pci_save_state(pdev);
4d22de3e
DLR		 3053
3054 mmio_start = pci_resource_start(pdev, 0);
3055 mmio_len = pci_resource_len(pdev, 0);
3056 ai = t3_get_adapter_info(ent->driver_data);
3057
3058 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
3059 if (!adapter) {
3060 err = -ENOMEM;
3061 goto out_disable_device;
3062 }
3063
3064 adapter->regs = ioremap_nocache(mmio_start, mmio_len);
3065 if (!adapter->regs) {
3066 dev_err(&pdev->dev, "cannot map device registers\n");
3067 err = -ENOMEM;
3068 goto out_free_adapter;
3069 }
3070
3071 adapter->pdev = pdev;
3072 adapter->name = pci_name(pdev);
3073 adapter->msg_enable = dflt_msg_enable;
3074 adapter->mmio_len = mmio_len;
3075
3076 mutex_init(&adapter->mdio_lock);
3077 spin_lock_init(&adapter->work_lock);
3078 spin_lock_init(&adapter->stats_lock);
3079
3080 INIT_LIST_HEAD(&adapter->adapter_list);
3081 INIT_WORK(&adapter->ext_intr_handler_task, ext_intr_task);
20d3fc11 3082 INIT_WORK(&adapter->fatal_error_handler_task, fatal_error_task);
4d22de3e
DLR		 3083 INIT_DELAYED_WORK(&adapter->adap_check_task, t3_adap_check_task);
3084
952cdf33 3085 for (i = 0; i < ai->nports0 + ai->nports1; ++i) {
4d22de3e
DLR		 3086 struct net_device *netdev;
3087
82ad3329 3088 netdev = alloc_etherdev_mq(sizeof(struct port_info), SGE_QSETS);
4d22de3e
DLR		 3089 if (!netdev) {
3090 err = -ENOMEM;
3091 goto out_free_dev;
3092 }
3093
4d22de3e
DLR		 3094 SET_NETDEV_DEV(netdev, &pdev->dev);
3095
3096 adapter->port[i] = netdev;
3097 pi = netdev_priv(netdev);
5fbf816f 3098 pi->adapter = adapter;
47fd23fe 3099 pi->rx_offload = T3_RX_CSUM | T3_LRO;
4d22de3e
DLR		 3100 pi->port_id = i;
3101 netif_carrier_off(netdev);
82ad3329 3102 netif_tx_stop_all_queues(netdev);
4d22de3e
DLR		 3103 netdev->irq = pdev->irq;
3104 netdev->mem_start = mmio_start;
3105 netdev->mem_end = mmio_start + mmio_len - 1;
4d22de3e
DLR		 3106 netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3107 netdev->features |= NETIF_F_LLTX;
7be2df45 3108 netdev->features |= NETIF_F_GRO;
4d22de3e
DLR		 3109 if (pci_using_dac)
3110 netdev->features |= NETIF_F_HIGHDMA;
3111
3112 netdev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
dd752696 3113 netdev->netdev_ops = &cxgb_netdev_ops;
4d22de3e
DLR		 3114 SET_ETHTOOL_OPS(netdev, &cxgb_ethtool_ops);
3115 }
3116
5fbf816f 3117 pci_set_drvdata(pdev, adapter);
4d22de3e
DLR		 3118 if (t3_prep_adapter(adapter, ai, 1) < 0) {
3119 err = -ENODEV;
3120 goto out_free_dev;
3121 }
2eab17ab 3122
4d22de3e
DLR		 3123 /*
3124 * The card is now ready to go. If any errors occur during device
3125 * registration we do not fail the whole card but rather proceed only
3126 * with the ports we manage to register successfully. However we must
3127 * register at least one net device.
3128 */
3129 for_each_port(adapter, i) {
3130 err = register_netdev(adapter->port[i]);
3131 if (err)
3132 dev_warn(&pdev->dev,
3133 "cannot register net device %s, skipping\n",
3134 adapter->port[i]->name);
3135 else {
3136 /*
3137 * Change the name we use for messages to the name of
3138 * the first successfully registered interface.
3139 */
3140 if (!adapter->registered_device_map)
3141 adapter->name = adapter->port[i]->name;
3142
3143 __set_bit(i, &adapter->registered_device_map);
3144 }
3145 }
3146 if (!adapter->registered_device_map) {
3147 dev_err(&pdev->dev, "could not register any net devices\n");
3148 goto out_free_dev;
3149 }
3150
3151 /* Driver's ready. Reflect it on LEDs */
3152 t3_led_ready(adapter);
3153
3154 if (is_offload(adapter)) {
3155 __set_bit(OFFLOAD_DEVMAP_BIT, &adapter->registered_device_map);
3156 cxgb3_adapter_ofld(adapter);
3157 }
3158
3159 /* See what interrupts we'll be using */
3160 if (msi > 1 && cxgb_enable_msix(adapter) == 0)
3161 adapter->flags |= USING_MSIX;
3162 else if (msi > 0 && pci_enable_msi(pdev) == 0)
3163 adapter->flags |= USING_MSI;
3164
8c263761
DLR		 3165 set_nqsets(adapter);
3166
0ee8d33c 3167 err = sysfs_create_group(&adapter->port[0]->dev.kobj,
4d22de3e
DLR		 3168 &cxgb3_attr_group);
3169
3170 print_port_info(adapter, ai);
3171 return 0;
3172
3173out_free_dev:
3174 iounmap(adapter->regs);
952cdf33 3175 for (i = ai->nports0 + ai->nports1 - 1; i >= 0; --i)
4d22de3e
DLR		 3176 if (adapter->port[i])
3177 free_netdev(adapter->port[i]);
3178
3179out_free_adapter:
3180 kfree(adapter);
3181
3182out_disable_device:
3183 pci_disable_device(pdev);
3184out_release_regions:
3185 pci_release_regions(pdev);
3186 pci_set_drvdata(pdev, NULL);
3187 return err;
3188}
3189
3190static void __devexit remove_one(struct pci_dev *pdev)
3191{
5fbf816f 3192 struct adapter *adapter = pci_get_drvdata(pdev);
4d22de3e 3193
5fbf816f 3194 if (adapter) {
4d22de3e 3195 int i;
4d22de3e
DLR		 3196
3197 t3_sge_stop(adapter);
0ee8d33c 3198 sysfs_remove_group(&adapter->port[0]->dev.kobj,
4d22de3e
DLR		 3199 &cxgb3_attr_group);
3200
4d22de3e
DLR		 3201 if (is_offload(adapter)) {
3202 cxgb3_adapter_unofld(adapter);
3203 if (test_bit(OFFLOAD_DEVMAP_BIT,
3204 &adapter->open_device_map))
3205 offload_close(&adapter->tdev);
3206 }
3207
67d92ab7
DLR		 3208 for_each_port(adapter, i)
3209 if (test_bit(i, &adapter->registered_device_map))
3210 unregister_netdev(adapter->port[i]);
3211
0ca41c04 3212 t3_stop_sge_timers(adapter);
4d22de3e
DLR		 3213 t3_free_sge_resources(adapter);
3214 cxgb_disable_msi(adapter);
3215
4d22de3e
DLR		 3216 for_each_port(adapter, i)
3217 if (adapter->port[i])
3218 free_netdev(adapter->port[i]);
3219
3220 iounmap(adapter->regs);
3221 kfree(adapter);
3222 pci_release_regions(pdev);
3223 pci_disable_device(pdev);
3224 pci_set_drvdata(pdev, NULL);
3225 }
3226}
3227
3228static struct pci_driver driver = {
3229 .name = DRV_NAME,
3230 .id_table = cxgb3_pci_tbl,
3231 .probe = init_one,
3232 .remove = __devexit_p(remove_one),
91a6b50c 3233 .err_handler = &t3_err_handler,
4d22de3e
DLR		 3234};
3235
3236static int __init cxgb3_init_module(void)
3237{
3238 int ret;
3239
3240 cxgb3_offload_init();
3241
3242 ret = pci_register_driver(&driver);
3243 return ret;
3244}
3245
3246static void __exit cxgb3_cleanup_module(void)
3247{
3248 pci_unregister_driver(&driver);
3249 if (cxgb3_wq)
3250 destroy_workqueue(cxgb3_wq);
3251}
3252
3253module_init(cxgb3_init_module);
3254module_exit(cxgb3_cleanup_module);
Linux 6.x block layer and io_uring tree(s)