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2b144023 | 1 | /* Copyright 2008-2009 Broadcom Corporation |
ea4e040a YR |
2 | * |
3 | * Unless you and Broadcom execute a separate written software license | |
4 | * agreement governing use of this software, this software is licensed to you | |
5 | * under the terms of the GNU General Public License version 2, available | |
6 | * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). | |
7 | * | |
8 | * Notwithstanding the above, under no circumstances may you combine this | |
9 | * software in any way with any other Broadcom software provided under a | |
10 | * license other than the GPL, without Broadcom's express prior written | |
11 | * consent. | |
12 | * | |
13 | * Written by Yaniv Rosner | |
14 | * | |
15 | */ | |
16 | ||
17 | #ifndef BNX2X_LINK_H | |
18 | #define BNX2X_LINK_H | |
19 | ||
20 | ||
21 | ||
22 | /***********************************************************/ | |
23 | /* Defines */ | |
24 | /***********************************************************/ | |
25 | #define DEFAULT_PHY_DEV_ADDR 3 | |
26 | ||
27 | ||
28 | ||
c0700f90 DM |
29 | #define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO |
30 | #define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX | |
31 | #define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX | |
32 | #define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH | |
33 | #define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE | |
ea4e040a YR |
34 | |
35 | #define SPEED_AUTO_NEG 0 | |
36 | #define SPEED_12000 12000 | |
37 | #define SPEED_12500 12500 | |
38 | #define SPEED_13000 13000 | |
39 | #define SPEED_15000 15000 | |
40 | #define SPEED_16000 16000 | |
41 | ||
4d295db0 EG |
42 | #define SFP_EEPROM_VENDOR_NAME_ADDR 0x14 |
43 | #define SFP_EEPROM_VENDOR_NAME_SIZE 16 | |
44 | #define SFP_EEPROM_VENDOR_OUI_ADDR 0x25 | |
45 | #define SFP_EEPROM_VENDOR_OUI_SIZE 3 | |
46 | #define SFP_EEPROM_PART_NO_ADDR 0x28 | |
47 | #define SFP_EEPROM_PART_NO_SIZE 16 | |
48 | #define PWR_FLT_ERR_MSG_LEN 250 | |
ea4e040a YR |
49 | /***********************************************************/ |
50 | /* Structs */ | |
51 | /***********************************************************/ | |
52 | /* Inputs parameters to the CLC */ | |
53 | struct link_params { | |
54 | ||
55 | u8 port; | |
56 | ||
57 | /* Default / User Configuration */ | |
58 | u8 loopback_mode; | |
59 | #define LOOPBACK_NONE 0 | |
60 | #define LOOPBACK_EMAC 1 | |
61 | #define LOOPBACK_BMAC 2 | |
62 | #define LOOPBACK_XGXS_10 3 | |
63 | #define LOOPBACK_EXT_PHY 4 | |
6bbca910 | 64 | #define LOOPBACK_EXT 5 |
ea4e040a YR |
65 | |
66 | u16 req_duplex; | |
67 | u16 req_flow_ctrl; | |
8c99e7b0 YR |
68 | u16 req_fc_auto_adv; /* Should be set to TX / BOTH when |
69 | req_flow_ctrl is set to AUTO */ | |
ea4e040a YR |
70 | u16 req_line_speed; /* Also determine AutoNeg */ |
71 | ||
72 | /* Device parameters */ | |
73 | u8 mac_addr[6]; | |
8c99e7b0 | 74 | |
ea4e040a YR |
75 | /* shmem parameters */ |
76 | u32 shmem_base; | |
77 | u32 speed_cap_mask; | |
78 | u32 switch_cfg; | |
79 | #define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH | |
80 | #define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH | |
81 | #define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT | |
82 | ||
83 | u16 hw_led_mode; /* part of the hw_config read from the shmem */ | |
1ef70b9c EG |
84 | |
85 | /* phy_addr populated by the phy_init function */ | |
86 | u8 phy_addr; | |
87 | /*u8 reserved1;*/ | |
88 | ||
ea4e040a YR |
89 | u32 lane_config; |
90 | u32 ext_phy_config; | |
659bc5c4 EG |
91 | #define XGXS_EXT_PHY_TYPE(ext_phy_config) \ |
92 | ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) | |
93 | #define XGXS_EXT_PHY_ADDR(ext_phy_config) \ | |
94 | (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \ | |
95 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT) | |
96 | #define SERDES_EXT_PHY_TYPE(ext_phy_config) \ | |
97 | ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) | |
98 | ||
ea4e040a YR |
99 | /* Phy register parameter */ |
100 | u32 chip_id; | |
101 | ||
c2c8b03e | 102 | u16 xgxs_config_rx[4]; /* preemphasis values for the rx side */ |
c2c8b03e | 103 | u16 xgxs_config_tx[4]; /* preemphasis values for the tx side */ |
1ef70b9c | 104 | |
589abe3a EG |
105 | u32 feature_config_flags; |
106 | #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) | |
4d295db0 EG |
107 | #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2) |
108 | #define FEATURE_CONFIG_BCM8727_NOC (1<<3) | |
1ef70b9c | 109 | |
ea4e040a YR |
110 | /* Device pointer passed to all callback functions */ |
111 | struct bnx2x *bp; | |
112 | }; | |
113 | ||
114 | /* Output parameters */ | |
115 | struct link_vars { | |
1ef70b9c EG |
116 | u8 phy_flags; |
117 | ||
118 | u8 mac_type; | |
119 | #define MAC_TYPE_NONE 0 | |
120 | #define MAC_TYPE_EMAC 1 | |
121 | #define MAC_TYPE_BMAC 2 | |
122 | ||
ea4e040a YR |
123 | u8 phy_link_up; /* internal phy link indication */ |
124 | u8 link_up; | |
1ef70b9c EG |
125 | |
126 | u16 line_speed; | |
ea4e040a | 127 | u16 duplex; |
1ef70b9c | 128 | |
ea4e040a | 129 | u16 flow_ctrl; |
1ef70b9c | 130 | u16 ieee_fc; |
ea4e040a | 131 | |
ea4e040a YR |
132 | u32 autoneg; |
133 | #define AUTO_NEG_DISABLED 0x0 | |
134 | #define AUTO_NEG_ENABLED 0x1 | |
135 | #define AUTO_NEG_COMPLETE 0x2 | |
1ef70b9c | 136 | #define AUTO_NEG_PARALLEL_DETECTION_USED 0x3 |
ea4e040a YR |
137 | |
138 | /* The same definitions as the shmem parameter */ | |
139 | u32 link_status; | |
140 | }; | |
141 | ||
142 | /***********************************************************/ | |
143 | /* Functions */ | |
144 | /***********************************************************/ | |
145 | ||
146 | /* Initialize the phy */ | |
147 | u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output); | |
148 | ||
589abe3a EG |
149 | /* Reset the link. Should be called when driver or interface goes down |
150 | Before calling phy firmware upgrade, the reset_ext_phy should be set | |
151 | to 0 */ | |
152 | u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars, | |
153 | u8 reset_ext_phy); | |
ea4e040a YR |
154 | |
155 | /* bnx2x_link_update should be called upon link interrupt */ | |
156 | u8 bnx2x_link_update(struct link_params *input, struct link_vars *output); | |
157 | ||
158 | /* use the following cl45 functions to read/write from external_phy | |
159 | In order to use it to read/write internal phy registers, use | |
160 | DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as | |
161 | Use ext_phy_type of 0 in case of cl22 over cl45 | |
162 | the register */ | |
163 | u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type, | |
164 | u8 phy_addr, u8 devad, u16 reg, u16 *ret_val); | |
165 | ||
166 | u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type, | |
167 | u8 phy_addr, u8 devad, u16 reg, u16 val); | |
168 | ||
169 | /* Reads the link_status from the shmem, | |
33471629 | 170 | and update the link vars accordingly */ |
ea4e040a YR |
171 | void bnx2x_link_status_update(struct link_params *input, |
172 | struct link_vars *output); | |
173 | /* returns string representing the fw_version of the external phy */ | |
174 | u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, | |
175 | u8 *version, u16 len); | |
176 | ||
177 | /* Set/Unset the led | |
178 | Basically, the CLC takes care of the led for the link, but in case one needs | |
33471629 | 179 | to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to |
ea4e040a | 180 | blink the led, and LED_MODE_OFF to set the led off.*/ |
7846e471 | 181 | u8 bnx2x_set_led(struct link_params *params, u8 mode, u32 speed); |
ea4e040a YR |
182 | #define LED_MODE_OFF 0 |
183 | #define LED_MODE_OPER 2 | |
184 | ||
185 | u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port, u32 led_idx, u32 value); | |
186 | ||
589abe3a EG |
187 | /* bnx2x_handle_module_detect_int should be called upon module detection |
188 | interrupt */ | |
189 | void bnx2x_handle_module_detect_int(struct link_params *params); | |
190 | ||
ea4e040a YR |
191 | /* Get the actual link status. In case it returns 0, link is up, |
192 | otherwise link is down*/ | |
193 | u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars); | |
194 | ||
6bbca910 YR |
195 | /* One-time initialization for external phy after power up */ |
196 | u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base); | |
ea4e040a | 197 | |
f57a6025 EG |
198 | /* Reset the external PHY using GPIO */ |
199 | void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port); | |
200 | ||
201 | void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr); | |
356e2385 | 202 | |
4d295db0 EG |
203 | u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr, |
204 | u8 byte_cnt, u8 *o_buf); | |
205 | ||
ea4e040a | 206 | #endif /* BNX2X_LINK_H */ |