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bnx2x: avoid release of unrequested irqs
[linux-2.6-block.git] / drivers / net / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
5de92408 3 * Copyright (c) 2007-2011 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
a2fbb9ea
ET		 18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/kernel.h>
21#include <linux/device.h> /* for dev_info() */
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
a2fbb9ea
ET		 26#include <linux/interrupt.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/dma-mapping.h>
33#include <linux/bitops.h>
34#include <linux/irq.h>
35#include <linux/delay.h>
36#include <asm/byteorder.h>
37#include <linux/time.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
0c6671b0 40#include <linux/if_vlan.h>
a2fbb9ea
ET		 41#include <net/ip.h>
42#include <net/tcp.h>
43#include <net/checksum.h>
34f80b04 44#include <net/ip6_checksum.h>
a2fbb9ea
ET		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
34f80b04 47#include <linux/crc32c.h>
a2fbb9ea
ET		 48#include <linux/prefetch.h>
49#include <linux/zlib.h>
a2fbb9ea 50#include <linux/io.h>
45229b42 51#include <linux/stringify.h>
a2fbb9ea 52
b0efbb99 53#define BNX2X_MAIN
a2fbb9ea
ET		 54#include "bnx2x.h"
55#include "bnx2x_init.h"
94a78b79 56#include "bnx2x_init_ops.h"
9f6c9258 57#include "bnx2x_cmn.h"
e4901dde 58#include "bnx2x_dcb.h"
a2fbb9ea 59
94a78b79
VZ		 60#include <linux/firmware.h>
61#include "bnx2x_fw_file_hdr.h"
62/* FW files */
45229b42
BH		 63#define FW_FILE_VERSION \
64 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
65 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
66 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
67 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 68#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
69#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 70#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 71
34f80b04
EG		 72/* Time in jiffies before concluding the transmitter is hung */
73#define TX_TIMEOUT (5*HZ)
a2fbb9ea 74
53a10565 75static char version[] __devinitdata =
34f80b04 76 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
a2fbb9ea
ET		 77 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
78
24e3fcef 79MODULE_AUTHOR("Eliezer Tamir");
f2e0899f
DK		 80MODULE_DESCRIPTION("Broadcom NetXtreme II "
81 "BCM57710/57711/57711E/57712/57712E Driver");
a2fbb9ea
ET		 82MODULE_LICENSE("GPL");
83MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 84MODULE_FIRMWARE(FW_FILE_NAME_E1);
85MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 86MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 87
555f6c78
EG		 88static int multi_mode = 1;
89module_param(multi_mode, int, 0);
ca00392c
EG		 90MODULE_PARM_DESC(multi_mode, " Multi queue mode "
91 "(0 Disable; 1 Enable (default))");
92
d6214d7a 93int num_queues;
54b9ddaa
VZ		 94module_param(num_queues, int, 0);
95MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
96 " (default is as a number of CPUs)");
555f6c78 97
19680c48 98static int disable_tpa;
19680c48 99module_param(disable_tpa, int, 0);
9898f86d 100MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a
EG		 101
102static int int_mode;
103module_param(int_mode, int, 0);
cdaa7cb8
VZ		 104MODULE_PARM_DESC(int_mode, " Force interrupt mode other then MSI-X "
105 "(1 INT#x; 2 MSI)");
8badd27a 106
a18f5128
EG		 107static int dropless_fc;
108module_param(dropless_fc, int, 0);
109MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
110
9898f86d 111static int poll;
a2fbb9ea 112module_param(poll, int, 0);
9898f86d 113MODULE_PARM_DESC(poll, " Use polling (for debug)");
8d5726c4
EG		 114
115static int mrrs = -1;
116module_param(mrrs, int, 0);
117MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
9898f86d 119static int debug;
a2fbb9ea 120module_param(debug, int, 0);
9898f86d
EG		 121MODULE_PARM_DESC(debug, " Default debug msglevel");
122
1cf167f2 123static struct workqueue_struct *bnx2x_wq;
a2fbb9ea 124
ec6ba945
VZ		 125#ifdef BCM_CNIC
126static u8 ALL_ENODE_MACS[] = {0x01, 0x10, 0x18, 0x01, 0x00, 0x01};
127#endif
128
a2fbb9ea
ET		 129enum bnx2x_board_type {
130 BCM57710 = 0,
34f80b04
EG		 131 BCM57711 = 1,
132 BCM57711E = 2,
f2e0899f
DK		 133 BCM57712 = 3,
134 BCM57712E = 4
a2fbb9ea
ET		 135};
136
34f80b04 137/* indexed by board_type, above */
53a10565 138static struct {
a2fbb9ea
ET		 139 char *name;
140} board_info[] __devinitdata = {
34f80b04
EG		 141 { "Broadcom NetXtreme II BCM57710 XGb" },
142 { "Broadcom NetXtreme II BCM57711 XGb" },
f2e0899f
DK		 143 { "Broadcom NetXtreme II BCM57711E XGb" },
144 { "Broadcom NetXtreme II BCM57712 XGb" },
145 { "Broadcom NetXtreme II BCM57712E XGb" }
a2fbb9ea
ET		 146};
147
a3aa1884 148static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 149 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
150 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
151 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f
DK		 152 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
153 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712E), BCM57712E },
a2fbb9ea
ET		 154 { 0 }
155};
156
157MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
158
159/****************************************************************************
160* General service functions
161****************************************************************************/
162
523224a3
DK		 163static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
164 u32 addr, dma_addr_t mapping)
165{
166 REG_WR(bp, addr, U64_LO(mapping));
167 REG_WR(bp, addr + 4, U64_HI(mapping));
168}
169
170static inline void __storm_memset_fill(struct bnx2x *bp,
171 u32 addr, size_t size, u32 val)
172{
173 int i;
174 for (i = 0; i < size/4; i++)
175 REG_WR(bp, addr + (i * 4), val);
176}
177
178static inline void storm_memset_ustats_zero(struct bnx2x *bp,
179 u8 port, u16 stat_id)
180{
181 size_t size = sizeof(struct ustorm_per_client_stats);
182
183 u32 addr = BAR_USTRORM_INTMEM +
184 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
185
186 __storm_memset_fill(bp, addr, size, 0);
187}
188
189static inline void storm_memset_tstats_zero(struct bnx2x *bp,
190 u8 port, u16 stat_id)
191{
192 size_t size = sizeof(struct tstorm_per_client_stats);
193
194 u32 addr = BAR_TSTRORM_INTMEM +
195 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
196
197 __storm_memset_fill(bp, addr, size, 0);
198}
199
200static inline void storm_memset_xstats_zero(struct bnx2x *bp,
201 u8 port, u16 stat_id)
202{
203 size_t size = sizeof(struct xstorm_per_client_stats);
204
205 u32 addr = BAR_XSTRORM_INTMEM +
206 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
207
208 __storm_memset_fill(bp, addr, size, 0);
209}
210
211
212static inline void storm_memset_spq_addr(struct bnx2x *bp,
213 dma_addr_t mapping, u16 abs_fid)
214{
215 u32 addr = XSEM_REG_FAST_MEMORY +
216 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
217
218 __storm_memset_dma_mapping(bp, addr, mapping);
219}
220
221static inline void storm_memset_ov(struct bnx2x *bp, u16 ov, u16 abs_fid)
222{
223 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(abs_fid), ov);
224}
225
226static inline void storm_memset_func_cfg(struct bnx2x *bp,
227 struct tstorm_eth_function_common_config *tcfg,
228 u16 abs_fid)
229{
230 size_t size = sizeof(struct tstorm_eth_function_common_config);
231
232 u32 addr = BAR_TSTRORM_INTMEM +
233 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
234
235 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
236}
237
238static inline void storm_memset_xstats_flags(struct bnx2x *bp,
239 struct stats_indication_flags *flags,
240 u16 abs_fid)
241{
242 size_t size = sizeof(struct stats_indication_flags);
243
244 u32 addr = BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(abs_fid);
245
246 __storm_memset_struct(bp, addr, size, (u32 *)flags);
247}
248
249static inline void storm_memset_tstats_flags(struct bnx2x *bp,
250 struct stats_indication_flags *flags,
251 u16 abs_fid)
252{
253 size_t size = sizeof(struct stats_indication_flags);
254
255 u32 addr = BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(abs_fid);
256
257 __storm_memset_struct(bp, addr, size, (u32 *)flags);
258}
259
260static inline void storm_memset_ustats_flags(struct bnx2x *bp,
261 struct stats_indication_flags *flags,
262 u16 abs_fid)
263{
264 size_t size = sizeof(struct stats_indication_flags);
265
266 u32 addr = BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(abs_fid);
267
268 __storm_memset_struct(bp, addr, size, (u32 *)flags);
269}
270
271static inline void storm_memset_cstats_flags(struct bnx2x *bp,
272 struct stats_indication_flags *flags,
273 u16 abs_fid)
274{
275 size_t size = sizeof(struct stats_indication_flags);
276
277 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(abs_fid);
278
279 __storm_memset_struct(bp, addr, size, (u32 *)flags);
280}
281
282static inline void storm_memset_xstats_addr(struct bnx2x *bp,
283 dma_addr_t mapping, u16 abs_fid)
284{
285 u32 addr = BAR_XSTRORM_INTMEM +
286 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
287
288 __storm_memset_dma_mapping(bp, addr, mapping);
289}
290
291static inline void storm_memset_tstats_addr(struct bnx2x *bp,
292 dma_addr_t mapping, u16 abs_fid)
293{
294 u32 addr = BAR_TSTRORM_INTMEM +
295 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
296
297 __storm_memset_dma_mapping(bp, addr, mapping);
298}
299
300static inline void storm_memset_ustats_addr(struct bnx2x *bp,
301 dma_addr_t mapping, u16 abs_fid)
302{
303 u32 addr = BAR_USTRORM_INTMEM +
304 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
305
306 __storm_memset_dma_mapping(bp, addr, mapping);
307}
308
309static inline void storm_memset_cstats_addr(struct bnx2x *bp,
310 dma_addr_t mapping, u16 abs_fid)
311{
312 u32 addr = BAR_CSTRORM_INTMEM +
313 CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
314
315 __storm_memset_dma_mapping(bp, addr, mapping);
316}
317
318static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
319 u16 pf_id)
320{
321 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
322 pf_id);
323 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
324 pf_id);
325 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
326 pf_id);
327 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
328 pf_id);
329}
330
331static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
332 u8 enable)
333{
334 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
335 enable);
336 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
337 enable);
338 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
339 enable);
340 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
341 enable);
342}
343
344static inline void storm_memset_eq_data(struct bnx2x *bp,
345 struct event_ring_data *eq_data,
346 u16 pfid)
347{
348 size_t size = sizeof(struct event_ring_data);
349
350 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
351
352 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
353}
354
355static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
356 u16 pfid)
357{
358 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
359 REG_WR16(bp, addr, eq_prod);
360}
361
362static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
363 u16 fw_sb_id, u8 sb_index,
364 u8 ticks)
365{
366
f2e0899f
DK		 367 int index_offset = CHIP_IS_E2(bp) ?
368 offsetof(struct hc_status_block_data_e2, index_data) :
523224a3
DK		 369 offsetof(struct hc_status_block_data_e1x, index_data);
370 u32 addr = BAR_CSTRORM_INTMEM +
371 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
372 index_offset +
373 sizeof(struct hc_index_data)*sb_index +
374 offsetof(struct hc_index_data, timeout);
375 REG_WR8(bp, addr, ticks);
376 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d ticks %d\n",
377 port, fw_sb_id, sb_index, ticks);
378}
379static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
380 u16 fw_sb_id, u8 sb_index,
381 u8 disable)
382{
383 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
f2e0899f
DK		 384 int index_offset = CHIP_IS_E2(bp) ?
385 offsetof(struct hc_status_block_data_e2, index_data) :
523224a3
DK		 386 offsetof(struct hc_status_block_data_e1x, index_data);
387 u32 addr = BAR_CSTRORM_INTMEM +
388 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
389 index_offset +
390 sizeof(struct hc_index_data)*sb_index +
391 offsetof(struct hc_index_data, flags);
392 u16 flags = REG_RD16(bp, addr);
393 /* clear and set */
394 flags &= ~HC_INDEX_DATA_HC_ENABLED;
395 flags |= enable_flag;
396 REG_WR16(bp, addr, flags);
397 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d disable %d\n",
398 port, fw_sb_id, sb_index, disable);
399}
400
a2fbb9ea
ET		 401/* used only at init
402 * locking is done by mcp
403 */
8d96286a 404static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 405{
406 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
407 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
408 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
409 PCICFG_VENDOR_ID_OFFSET);
410}
411
a2fbb9ea
ET		 412static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
413{
414 u32 val;
415
416 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
417 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
418 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
419 PCICFG_VENDOR_ID_OFFSET);
420
421 return val;
422}
a2fbb9ea 423
f2e0899f
DK		 424#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
425#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
426#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
427#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
428#define DMAE_DP_DST_NONE "dst_addr [none]"
429
8d96286a 430static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
431 int msglvl)
f2e0899f
DK		 432{
433 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
434
435 switch (dmae->opcode & DMAE_COMMAND_DST) {
436 case DMAE_CMD_DST_PCI:
437 if (src_type == DMAE_CMD_SRC_PCI)
438 DP(msglvl, "DMAE: opcode 0x%08x\n"
439 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
440 "comp_addr [%x:%08x], comp_val 0x%08x\n",
441 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
442 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
443 dmae->comp_addr_hi, dmae->comp_addr_lo,
444 dmae->comp_val);
445 else
446 DP(msglvl, "DMAE: opcode 0x%08x\n"
447 "src [%08x], len [%d*4], dst [%x:%08x]\n"
448 "comp_addr [%x:%08x], comp_val 0x%08x\n",
449 dmae->opcode, dmae->src_addr_lo >> 2,
450 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
451 dmae->comp_addr_hi, dmae->comp_addr_lo,
452 dmae->comp_val);
453 break;
454 case DMAE_CMD_DST_GRC:
455 if (src_type == DMAE_CMD_SRC_PCI)
456 DP(msglvl, "DMAE: opcode 0x%08x\n"
457 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
458 "comp_addr [%x:%08x], comp_val 0x%08x\n",
459 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
460 dmae->len, dmae->dst_addr_lo >> 2,
461 dmae->comp_addr_hi, dmae->comp_addr_lo,
462 dmae->comp_val);
463 else
464 DP(msglvl, "DMAE: opcode 0x%08x\n"
465 "src [%08x], len [%d*4], dst [%08x]\n"
466 "comp_addr [%x:%08x], comp_val 0x%08x\n",
467 dmae->opcode, dmae->src_addr_lo >> 2,
468 dmae->len, dmae->dst_addr_lo >> 2,
469 dmae->comp_addr_hi, dmae->comp_addr_lo,
470 dmae->comp_val);
471 break;
472 default:
473 if (src_type == DMAE_CMD_SRC_PCI)
474 DP(msglvl, "DMAE: opcode 0x%08x\n"
475 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
476 "dst_addr [none]\n"
477 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
478 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
479 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
480 dmae->comp_val);
481 else
482 DP(msglvl, "DMAE: opcode 0x%08x\n"
483 DP_LEVEL "src_addr [%08x] len [%d * 4] "
484 "dst_addr [none]\n"
485 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
486 dmae->opcode, dmae->src_addr_lo >> 2,
487 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
488 dmae->comp_val);
489 break;
490 }
491
492}
493
6c719d00 494const u32 dmae_reg_go_c[] = {
a2fbb9ea
ET		 495 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
496 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
497 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
498 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
499};
500
501/* copy command into DMAE command memory and set DMAE command go */
6c719d00 502void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 503{
504 u32 cmd_offset;
505 int i;
506
507 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
508 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
509 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
510
ad8d3948
EG		 511 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
512 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 513 }
514 REG_WR(bp, dmae_reg_go_c[idx], 1);
515}
516
f2e0899f 517u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 518{
f2e0899f
DK		 519 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
520 DMAE_CMD_C_ENABLE);
521}
ad8d3948 522
f2e0899f
DK		 523u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
524{
525 return opcode & ~DMAE_CMD_SRC_RESET;
526}
ad8d3948 527
f2e0899f
DK		 528u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
529 bool with_comp, u8 comp_type)
530{
531 u32 opcode = 0;
532
533 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
534 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 535
f2e0899f
DK		 536 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
537
538 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
539 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
540 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
541 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 542
a2fbb9ea 543#ifdef __BIG_ENDIAN
f2e0899f 544 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 545#else
f2e0899f 546 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 547#endif
f2e0899f
DK		 548 if (with_comp)
549 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
550 return opcode;
551}
552
8d96286a 553static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
554 struct dmae_command *dmae,
555 u8 src_type, u8 dst_type)
f2e0899f
DK		 556{
557 memset(dmae, 0, sizeof(struct dmae_command));
558
559 /* set the opcode */
560 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
561 true, DMAE_COMP_PCI);
562
563 /* fill in the completion parameters */
564 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
565 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
566 dmae->comp_val = DMAE_COMP_VAL;
567}
568
569/* issue a dmae command over the init-channel and wailt for completion */
8d96286a 570static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
571 struct dmae_command *dmae)
f2e0899f
DK		 572{
573 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
5e374b5a 574 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 575 int rc = 0;
576
577 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
a2fbb9ea
ET		 578 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
579 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
a2fbb9ea 580
f2e0899f 581 /* lock the dmae channel */
6e30dd4e 582 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 583
f2e0899f 584 /* reset completion */
a2fbb9ea
ET		 585 *wb_comp = 0;
586
f2e0899f
DK		 587 /* post the command on the channel used for initializations */
588 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 589
f2e0899f 590 /* wait for completion */
a2fbb9ea 591 udelay(5);
f2e0899f 592 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948
EG		 593 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
594
ad8d3948 595 if (!cnt) {
c3eefaf6 596 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 597 rc = DMAE_TIMEOUT;
598 goto unlock;
a2fbb9ea 599 }
ad8d3948 600 cnt--;
f2e0899f 601 udelay(50);
a2fbb9ea 602 }
f2e0899f
DK		 603 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
604 BNX2X_ERR("DMAE PCI error!\n");
605 rc = DMAE_PCI_ERROR;
606 }
607
608 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
609 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
610 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
ad8d3948 611
f2e0899f 612unlock:
6e30dd4e 613 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 614 return rc;
615}
616
617void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
618 u32 len32)
619{
620 struct dmae_command dmae;
621
622 if (!bp->dmae_ready) {
623 u32 *data = bnx2x_sp(bp, wb_data[0]);
624
625 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
626 " using indirect\n", dst_addr, len32);
627 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
628 return;
629 }
630
631 /* set opcode and fixed command fields */
632 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
633
634 /* fill in addresses and len */
635 dmae.src_addr_lo = U64_LO(dma_addr);
636 dmae.src_addr_hi = U64_HI(dma_addr);
637 dmae.dst_addr_lo = dst_addr >> 2;
638 dmae.dst_addr_hi = 0;
639 dmae.len = len32;
640
641 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
642
643 /* issue the command and wait for completion */
644 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 645}
646
c18487ee 647void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 648{
5ff7b6d4 649 struct dmae_command dmae;
ad8d3948
EG		 650
651 if (!bp->dmae_ready) {
652 u32 *data = bnx2x_sp(bp, wb_data[0]);
653 int i;
654
655 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
656 " using indirect\n", src_addr, len32);
657 for (i = 0; i < len32; i++)
658 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
659 return;
660 }
661
f2e0899f
DK		 662 /* set opcode and fixed command fields */
663 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 664
f2e0899f 665 /* fill in addresses and len */
5ff7b6d4
EG		 666 dmae.src_addr_lo = src_addr >> 2;
667 dmae.src_addr_hi = 0;
668 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
669 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
670 dmae.len = len32;
ad8d3948 671
f2e0899f 672 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
ad8d3948 673
f2e0899f
DK		 674 /* issue the command and wait for completion */
675 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 676}
677
8d96286a 678static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
679 u32 addr, u32 len)
573f2035 680{
02e3c6cb 681 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 682 int offset = 0;
683
02e3c6cb 684 while (len > dmae_wr_max) {
573f2035 685 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 686 addr + offset, dmae_wr_max);
687 offset += dmae_wr_max * 4;
688 len -= dmae_wr_max;
573f2035
EG		 689 }
690
691 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
692}
693
ad8d3948
EG		 694/* used only for slowpath so not inlined */
695static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
696{
697 u32 wb_write[2];
698
699 wb_write[0] = val_hi;
700 wb_write[1] = val_lo;
701 REG_WR_DMAE(bp, reg, wb_write, 2);
a2fbb9ea 702}
a2fbb9ea 703
ad8d3948
EG		 704#ifdef USE_WB_RD
705static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
706{
707 u32 wb_data[2];
708
709 REG_RD_DMAE(bp, reg, wb_data, 2);
710
711 return HILO_U64(wb_data[0], wb_data[1]);
712}
713#endif
714
a2fbb9ea
ET		 715static int bnx2x_mc_assert(struct bnx2x *bp)
716{
a2fbb9ea 717 char last_idx;
34f80b04
EG		 718 int i, rc = 0;
719 u32 row0, row1, row2, row3;
720
721 /* XSTORM */
722 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
723 XSTORM_ASSERT_LIST_INDEX_OFFSET);
724 if (last_idx)
725 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
726
727 /* print the asserts */
728 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
729
730 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
731 XSTORM_ASSERT_LIST_OFFSET(i));
732 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
733 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
734 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
735 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
736 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
737 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
738
739 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
740 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
741 " 0x%08x 0x%08x 0x%08x\n",
742 i, row3, row2, row1, row0);
743 rc++;
744 } else {
745 break;
746 }
747 }
748
749 /* TSTORM */
750 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
751 TSTORM_ASSERT_LIST_INDEX_OFFSET);
752 if (last_idx)
753 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
754
755 /* print the asserts */
756 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
757
758 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
759 TSTORM_ASSERT_LIST_OFFSET(i));
760 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
761 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
762 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
763 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
764 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
765 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
766
767 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
768 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
769 " 0x%08x 0x%08x 0x%08x\n",
770 i, row3, row2, row1, row0);
771 rc++;
772 } else {
773 break;
774 }
775 }
776
777 /* CSTORM */
778 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
779 CSTORM_ASSERT_LIST_INDEX_OFFSET);
780 if (last_idx)
781 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
782
783 /* print the asserts */
784 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
785
786 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
787 CSTORM_ASSERT_LIST_OFFSET(i));
788 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
789 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
790 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
791 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
792 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
793 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
794
795 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
796 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
797 " 0x%08x 0x%08x 0x%08x\n",
798 i, row3, row2, row1, row0);
799 rc++;
800 } else {
801 break;
802 }
803 }
804
805 /* USTORM */
806 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
807 USTORM_ASSERT_LIST_INDEX_OFFSET);
808 if (last_idx)
809 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
810
811 /* print the asserts */
812 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
813
814 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
815 USTORM_ASSERT_LIST_OFFSET(i));
816 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
817 USTORM_ASSERT_LIST_OFFSET(i) + 4);
818 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
819 USTORM_ASSERT_LIST_OFFSET(i) + 8);
820 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
821 USTORM_ASSERT_LIST_OFFSET(i) + 12);
822
823 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
824 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
825 " 0x%08x 0x%08x 0x%08x\n",
826 i, row3, row2, row1, row0);
827 rc++;
828 } else {
829 break;
a2fbb9ea
ET		 830 }
831 }
34f80b04 832
a2fbb9ea
ET		 833 return rc;
834}
c14423fe 835
a2fbb9ea
ET		 836static void bnx2x_fw_dump(struct bnx2x *bp)
837{
cdaa7cb8 838 u32 addr;
a2fbb9ea 839 u32 mark, offset;
4781bfad 840 __be32 data[9];
a2fbb9ea 841 int word;
f2e0899f 842 u32 trace_shmem_base;
2145a920
VZ		 843 if (BP_NOMCP(bp)) {
844 BNX2X_ERR("NO MCP - can not dump\n");
845 return;
846 }
cdaa7cb8 847
f2e0899f
DK		 848 if (BP_PATH(bp) == 0)
849 trace_shmem_base = bp->common.shmem_base;
850 else
851 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
852 addr = trace_shmem_base - 0x0800 + 4;
cdaa7cb8 853 mark = REG_RD(bp, addr);
f2e0899f
DK		 854 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
855 + ((mark + 0x3) & ~0x3) - 0x08000000;
7995c64e 856 pr_err("begin fw dump (mark 0x%x)\n", mark);
a2fbb9ea 857
7995c64e 858 pr_err("");
f2e0899f 859 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 860 for (word = 0; word < 8; word++)
cdaa7cb8 861 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 862 data[8] = 0x0;
7995c64e 863 pr_cont("%s", (char *)data);
a2fbb9ea 864 }
cdaa7cb8 865 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 866 for (word = 0; word < 8; word++)
cdaa7cb8 867 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 868 data[8] = 0x0;
7995c64e 869 pr_cont("%s", (char *)data);
a2fbb9ea 870 }
7995c64e 871 pr_err("end of fw dump\n");
a2fbb9ea
ET		 872}
873
6c719d00 874void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 875{
876 int i;
523224a3
DK		 877 u16 j;
878 struct hc_sp_status_block_data sp_sb_data;
879 int func = BP_FUNC(bp);
880#ifdef BNX2X_STOP_ON_ERROR
881 u16 start = 0, end = 0;
882#endif
a2fbb9ea 883
66e855f3
YG		 884 bp->stats_state = STATS_STATE_DISABLED;
885 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
886
a2fbb9ea
ET		 887 BNX2X_ERR("begin crash dump -----------------\n");
888
8440d2b6
EG		 889 /* Indices */
890 /* Common */
523224a3 891 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
cdaa7cb8 892 " spq_prod_idx(0x%x)\n",
523224a3
DK		 893 bp->def_idx, bp->def_att_idx,
894 bp->attn_state, bp->spq_prod_idx);
895 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
896 bp->def_status_blk->atten_status_block.attn_bits,
897 bp->def_status_blk->atten_status_block.attn_bits_ack,
898 bp->def_status_blk->atten_status_block.status_block_id,
899 bp->def_status_blk->atten_status_block.attn_bits_index);
900 BNX2X_ERR(" def (");
901 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
902 pr_cont("0x%x%s",
903 bp->def_status_blk->sp_sb.index_values[i],
904 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
905
906 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
907 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
908 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
909 i*sizeof(u32));
910
911 pr_cont("igu_sb_id(0x%x) igu_seg_id (0x%x) "
912 "pf_id(0x%x) vnic_id(0x%x) "
913 "vf_id(0x%x) vf_valid (0x%x)\n",
914 sp_sb_data.igu_sb_id,
915 sp_sb_data.igu_seg_id,
916 sp_sb_data.p_func.pf_id,
917 sp_sb_data.p_func.vnic_id,
918 sp_sb_data.p_func.vf_id,
919 sp_sb_data.p_func.vf_valid);
920
8440d2b6 921
ec6ba945 922 for_each_eth_queue(bp, i) {
a2fbb9ea 923 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 924 int loop;
f2e0899f 925 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 926 struct hc_status_block_data_e1x sb_data_e1x;
927 struct hc_status_block_sm *hc_sm_p =
f2e0899f
DK		 928 CHIP_IS_E2(bp) ?
929 sb_data_e2.common.state_machine :
523224a3
DK		 930 sb_data_e1x.common.state_machine;
931 struct hc_index_data *hc_index_p =
f2e0899f
DK		 932 CHIP_IS_E2(bp) ?
933 sb_data_e2.index_data :
523224a3
DK		 934 sb_data_e1x.index_data;
935 int data_size;
936 u32 *sb_data_p;
937
938 /* Rx */
cdaa7cb8 939 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
523224a3 940 " rx_comp_prod(0x%x)"
cdaa7cb8 941 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 942 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 943 fp->rx_comp_prod,
66e855f3 944 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
cdaa7cb8 945 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
523224a3 946 " fp_hc_idx(0x%x)\n",
8440d2b6 947 fp->rx_sge_prod, fp->last_max_sge,
523224a3 948 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 949
523224a3 950 /* Tx */
cdaa7cb8
VZ		 951 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
952 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
953 " *tx_cons_sb(0x%x)\n",
8440d2b6
EG		 954 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
955 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
523224a3 956
f2e0899f
DK		 957 loop = CHIP_IS_E2(bp) ?
958 HC_SB_MAX_INDICES_E2 : HC_SB_MAX_INDICES_E1X;
523224a3
DK		 959
960 /* host sb data */
961
ec6ba945
VZ		 962#ifdef BCM_CNIC
963 if (IS_FCOE_FP(fp))
964 continue;
965#endif
523224a3
DK		 966 BNX2X_ERR(" run indexes (");
967 for (j = 0; j < HC_SB_MAX_SM; j++)
968 pr_cont("0x%x%s",
969 fp->sb_running_index[j],
970 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
971
972 BNX2X_ERR(" indexes (");
973 for (j = 0; j < loop; j++)
974 pr_cont("0x%x%s",
975 fp->sb_index_values[j],
976 (j == loop - 1) ? ")" : " ");
977 /* fw sb data */
f2e0899f
DK		 978 data_size = CHIP_IS_E2(bp) ?
979 sizeof(struct hc_status_block_data_e2) :
523224a3
DK		 980 sizeof(struct hc_status_block_data_e1x);
981 data_size /= sizeof(u32);
f2e0899f
DK		 982 sb_data_p = CHIP_IS_E2(bp) ?
983 (u32 *)&sb_data_e2 :
984 (u32 *)&sb_data_e1x;
523224a3
DK		 985 /* copy sb data in here */
986 for (j = 0; j < data_size; j++)
987 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
988 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
989 j * sizeof(u32));
990
f2e0899f
DK		 991 if (CHIP_IS_E2(bp)) {
992 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
993 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
994 sb_data_e2.common.p_func.pf_id,
995 sb_data_e2.common.p_func.vf_id,
996 sb_data_e2.common.p_func.vf_valid,
997 sb_data_e2.common.p_func.vnic_id,
998 sb_data_e2.common.same_igu_sb_1b);
999 } else {
1000 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1001 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1002 sb_data_e1x.common.p_func.pf_id,
1003 sb_data_e1x.common.p_func.vf_id,
1004 sb_data_e1x.common.p_func.vf_valid,
1005 sb_data_e1x.common.p_func.vnic_id,
1006 sb_data_e1x.common.same_igu_sb_1b);
1007 }
523224a3
DK		 1008
1009 /* SB_SMs data */
1010 for (j = 0; j < HC_SB_MAX_SM; j++) {
1011 pr_cont("SM[%d] __flags (0x%x) "
1012 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
1013 "time_to_expire (0x%x) "
1014 "timer_value(0x%x)\n", j,
1015 hc_sm_p[j].__flags,
1016 hc_sm_p[j].igu_sb_id,
1017 hc_sm_p[j].igu_seg_id,
1018 hc_sm_p[j].time_to_expire,
1019 hc_sm_p[j].timer_value);
1020 }
1021
1022 /* Indecies data */
1023 for (j = 0; j < loop; j++) {
1024 pr_cont("INDEX[%d] flags (0x%x) "
1025 "timeout (0x%x)\n", j,
1026 hc_index_p[j].flags,
1027 hc_index_p[j].timeout);
1028 }
8440d2b6 1029 }
a2fbb9ea 1030
523224a3 1031#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 1032 /* Rings */
1033 /* Rx */
ec6ba945 1034 for_each_rx_queue(bp, i) {
8440d2b6 1035 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 1036
1037 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1038 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1039 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1040 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1041 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1042
c3eefaf6
EG		 1043 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1044 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
a2fbb9ea
ET		 1045 }
1046
3196a88a
EG		 1047 start = RX_SGE(fp->rx_sge_prod);
1048 end = RX_SGE(fp->last_max_sge);
8440d2b6 1049 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1050 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1051 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1052
c3eefaf6
EG		 1053 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1054 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1055 }
1056
a2fbb9ea
ET		 1057 start = RCQ_BD(fp->rx_comp_cons - 10);
1058 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1059 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1060 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1061
c3eefaf6
EG		 1062 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1063 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1064 }
1065 }
1066
8440d2b6 1067 /* Tx */
ec6ba945 1068 for_each_tx_queue(bp, i) {
8440d2b6
EG		 1069 struct bnx2x_fastpath *fp = &bp->fp[i];
1070
1071 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
1072 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
1073 for (j = start; j != end; j = TX_BD(j + 1)) {
1074 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
1075
c3eefaf6
EG		 1076 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
1077 i, j, sw_bd->skb, sw_bd->first_bd);
8440d2b6
EG		 1078 }
1079
1080 start = TX_BD(fp->tx_bd_cons - 10);
1081 end = TX_BD(fp->tx_bd_cons + 254);
1082 for (j = start; j != end; j = TX_BD(j + 1)) {
1083 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
1084
c3eefaf6
EG		 1085 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
1086 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
8440d2b6
EG		 1087 }
1088 }
523224a3 1089#endif
34f80b04 1090 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 1091 bnx2x_mc_assert(bp);
1092 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1093}
1094
f2e0899f 1095static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1096{
34f80b04 1097 int port = BP_PORT(bp);
a2fbb9ea
ET		 1098 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1099 u32 val = REG_RD(bp, addr);
1100 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1101 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
a2fbb9ea
ET		 1102
1103 if (msix) {
8badd27a
EG		 1104 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1105 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1106 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1107 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
8badd27a
EG		 1108 } else if (msi) {
1109 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1110 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1111 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1112 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1113 } else {
1114 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1115 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1116 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1117 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1118
a0fd065c
DK		 1119 if (!CHIP_IS_E1(bp)) {
1120 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1121 val, port, addr);
615f8fd9 1122
a0fd065c 1123 REG_WR(bp, addr, val);
615f8fd9 1124
a0fd065c
DK		 1125 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1126 }
a2fbb9ea
ET		 1127 }
1128
a0fd065c
DK		 1129 if (CHIP_IS_E1(bp))
1130 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1131
8badd27a
EG		 1132 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1133 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1134
1135 REG_WR(bp, addr, val);
37dbbf32
EG		 1136 /*
1137 * Ensure that HC_CONFIG is written before leading/trailing edge config
1138 */
1139 mmiowb();
1140 barrier();
34f80b04 1141
f2e0899f 1142 if (!CHIP_IS_E1(bp)) {
34f80b04 1143 /* init leading/trailing edge */
fb3bff17 1144 if (IS_MF(bp)) {
8badd27a 1145 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
34f80b04 1146 if (bp->port.pmf)
4acac6a5
EG		 1147 /* enable nig and gpio3 attention */
1148 val |= 0x1100;
34f80b04
EG		 1149 } else
1150 val = 0xffff;
1151
1152 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1153 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1154 }
37dbbf32
EG		 1155
1156 /* Make sure that interrupts are indeed enabled from here on */
1157 mmiowb();
a2fbb9ea
ET		 1158}
1159
f2e0899f
DK		 1160static void bnx2x_igu_int_enable(struct bnx2x *bp)
1161{
1162 u32 val;
1163 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1164 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1165
1166 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1167
1168 if (msix) {
1169 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1170 IGU_PF_CONF_SINGLE_ISR_EN);
1171 val |= (IGU_PF_CONF_FUNC_EN |
1172 IGU_PF_CONF_MSI_MSIX_EN |
1173 IGU_PF_CONF_ATTN_BIT_EN);
1174 } else if (msi) {
1175 val &= ~IGU_PF_CONF_INT_LINE_EN;
1176 val |= (IGU_PF_CONF_FUNC_EN |
1177 IGU_PF_CONF_MSI_MSIX_EN |
1178 IGU_PF_CONF_ATTN_BIT_EN |
1179 IGU_PF_CONF_SINGLE_ISR_EN);
1180 } else {
1181 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1182 val |= (IGU_PF_CONF_FUNC_EN |
1183 IGU_PF_CONF_INT_LINE_EN |
1184 IGU_PF_CONF_ATTN_BIT_EN |
1185 IGU_PF_CONF_SINGLE_ISR_EN);
1186 }
1187
1188 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1189 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1190
1191 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1192
1193 barrier();
1194
1195 /* init leading/trailing edge */
1196 if (IS_MF(bp)) {
1197 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1198 if (bp->port.pmf)
1199 /* enable nig and gpio3 attention */
1200 val |= 0x1100;
1201 } else
1202 val = 0xffff;
1203
1204 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1205 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1206
1207 /* Make sure that interrupts are indeed enabled from here on */
1208 mmiowb();
1209}
1210
1211void bnx2x_int_enable(struct bnx2x *bp)
1212{
1213 if (bp->common.int_block == INT_BLOCK_HC)
1214 bnx2x_hc_int_enable(bp);
1215 else
1216 bnx2x_igu_int_enable(bp);
1217}
1218
1219static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1220{
34f80b04 1221 int port = BP_PORT(bp);
a2fbb9ea
ET		 1222 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1223 u32 val = REG_RD(bp, addr);
1224
a0fd065c
DK		 1225 /*
1226 * in E1 we must use only PCI configuration space to disable
1227 * MSI/MSIX capablility
1228 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1229 */
1230 if (CHIP_IS_E1(bp)) {
1231 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1232 * Use mask register to prevent from HC sending interrupts
1233 * after we exit the function
1234 */
1235 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1236
1237 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1238 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1239 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1240 } else
1241 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1242 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1243 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1244 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1245
1246 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1247 val, port, addr);
1248
8badd27a
EG		 1249 /* flush all outstanding writes */
1250 mmiowb();
1251
a2fbb9ea
ET		 1252 REG_WR(bp, addr, val);
1253 if (REG_RD(bp, addr) != val)
1254 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1255}
1256
f2e0899f
DK		 1257static void bnx2x_igu_int_disable(struct bnx2x *bp)
1258{
1259 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1260
1261 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1262 IGU_PF_CONF_INT_LINE_EN |
1263 IGU_PF_CONF_ATTN_BIT_EN);
1264
1265 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1266
1267 /* flush all outstanding writes */
1268 mmiowb();
1269
1270 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1271 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1272 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1273}
1274
8d96286a 1275static void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1276{
1277 if (bp->common.int_block == INT_BLOCK_HC)
1278 bnx2x_hc_int_disable(bp);
1279 else
1280 bnx2x_igu_int_disable(bp);
1281}
1282
9f6c9258 1283void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1284{
a2fbb9ea 1285 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1286 int i, offset;
a2fbb9ea 1287
f8ef6e44
YG		 1288 if (disable_hw)
1289 /* prevent the HW from sending interrupts */
1290 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1291
1292 /* make sure all ISRs are done */
1293 if (msix) {
8badd27a
EG		 1294 synchronize_irq(bp->msix_table[0].vector);
1295 offset = 1;
37b091ba
MC		 1296#ifdef BCM_CNIC
1297 offset++;
1298#endif
ec6ba945 1299 for_each_eth_queue(bp, i)
8badd27a 1300 synchronize_irq(bp->msix_table[i + offset].vector);
a2fbb9ea
ET		 1301 } else
1302 synchronize_irq(bp->pdev->irq);
1303
1304 /* make sure sp_task is not running */
1cf167f2
EG		 1305 cancel_delayed_work(&bp->sp_task);
1306 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1307}
1308
34f80b04 1309/* fast path */
a2fbb9ea
ET		 1310
1311/*
34f80b04 1312 * General service functions
a2fbb9ea
ET		 1313 */
1314
72fd0718
VZ		 1315/* Return true if succeeded to acquire the lock */
1316static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1317{
1318 u32 lock_status;
1319 u32 resource_bit = (1 << resource);
1320 int func = BP_FUNC(bp);
1321 u32 hw_lock_control_reg;
1322
1323 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1324
1325 /* Validating that the resource is within range */
1326 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1327 DP(NETIF_MSG_HW,
1328 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1329 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1330 return false;
72fd0718
VZ		 1331 }
1332
1333 if (func <= 5)
1334 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1335 else
1336 hw_lock_control_reg =
1337 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1338
1339 /* Try to acquire the lock */
1340 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1341 lock_status = REG_RD(bp, hw_lock_control_reg);
1342 if (lock_status & resource_bit)
1343 return true;
1344
1345 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1346 return false;
1347}
1348
993ac7b5
MC		 1349#ifdef BCM_CNIC
1350static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
1351#endif
3196a88a 1352
9f6c9258 1353void bnx2x_sp_event(struct bnx2x_fastpath *fp,
a2fbb9ea
ET		 1354 union eth_rx_cqe *rr_cqe)
1355{
1356 struct bnx2x *bp = fp->bp;
1357 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1358 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1359
34f80b04 1360 DP(BNX2X_MSG_SP,
a2fbb9ea 1361 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1362 fp->index, cid, command, bp->state,
34f80b04 1363 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1364
523224a3
DK		 1365 switch (command | fp->state) {
1366 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BNX2X_FP_STATE_OPENING):
1367 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1368 fp->state = BNX2X_FP_STATE_OPEN;
a2fbb9ea
ET		 1369 break;
1370
523224a3
DK		 1371 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
1372 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
a2fbb9ea
ET		 1373 fp->state = BNX2X_FP_STATE_HALTED;
1374 break;
1375
523224a3
DK		 1376 case (RAMROD_CMD_ID_ETH_TERMINATE | BNX2X_FP_STATE_TERMINATING):
1377 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1378 fp->state = BNX2X_FP_STATE_TERMINATED;
a2fbb9ea
ET		 1379 break;
1380
523224a3
DK		 1381 default:
1382 BNX2X_ERR("unexpected MC reply (%d) "
1383 "fp[%d] state is %x\n",
1384 command, fp->index, fp->state);
993ac7b5 1385 break;
523224a3 1386 }
3196a88a 1387
8fe23fbd 1388 smp_mb__before_atomic_inc();
6e30dd4e 1389 atomic_inc(&bp->cq_spq_left);
523224a3
DK		 1390 /* push the change in fp->state and towards the memory */
1391 smp_wmb();
49d66772 1392
523224a3 1393 return;
a2fbb9ea
ET		 1394}
1395
9f6c9258 1396irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1397{
555f6c78 1398 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1399 u16 status = bnx2x_ack_int(bp);
34f80b04 1400 u16 mask;
ca00392c 1401 int i;
a2fbb9ea 1402
34f80b04 1403 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1404 if (unlikely(status == 0)) {
1405 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1406 return IRQ_NONE;
1407 }
f5372251 1408 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1409
3196a88a
EG		 1410#ifdef BNX2X_STOP_ON_ERROR
1411 if (unlikely(bp->panic))
1412 return IRQ_HANDLED;
1413#endif
1414
ec6ba945 1415 for_each_eth_queue(bp, i) {
ca00392c 1416 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1417
523224a3 1418 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
ca00392c 1419 if (status & mask) {
54b9ddaa
VZ		 1420 /* Handle Rx and Tx according to SB id */
1421 prefetch(fp->rx_cons_sb);
54b9ddaa 1422 prefetch(fp->tx_cons_sb);
523224a3 1423 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1424 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1425 status &= ~mask;
1426 }
a2fbb9ea
ET		 1427 }
1428
993ac7b5 1429#ifdef BCM_CNIC
523224a3 1430 mask = 0x2;
993ac7b5
MC		 1431 if (status & (mask | 0x1)) {
1432 struct cnic_ops *c_ops = NULL;
1433
1434 rcu_read_lock();
1435 c_ops = rcu_dereference(bp->cnic_ops);
1436 if (c_ops)
1437 c_ops->cnic_handler(bp->cnic_data, NULL);
1438 rcu_read_unlock();
1439
1440 status &= ~mask;
1441 }
1442#endif
a2fbb9ea 1443
34f80b04 1444 if (unlikely(status & 0x1)) {
1cf167f2 1445 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 1446
1447 status &= ~0x1;
1448 if (!status)
1449 return IRQ_HANDLED;
1450 }
1451
cdaa7cb8
VZ		 1452 if (unlikely(status))
1453 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1454 status);
a2fbb9ea 1455
c18487ee 1456 return IRQ_HANDLED;
a2fbb9ea
ET		 1457}
1458
c18487ee 1459/* end of fast path */
a2fbb9ea 1460
a2fbb9ea 1461
c18487ee
YR		 1462/* Link */
1463
1464/*
1465 * General service functions
1466 */
a2fbb9ea 1467
9f6c9258 1468int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1469{
1470 u32 lock_status;
1471 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1472 int func = BP_FUNC(bp);
1473 u32 hw_lock_control_reg;
c18487ee 1474 int cnt;
a2fbb9ea 1475
c18487ee
YR		 1476 /* Validating that the resource is within range */
1477 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1478 DP(NETIF_MSG_HW,
1479 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1480 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1481 return -EINVAL;
1482 }
a2fbb9ea 1483
4a37fb66
YG		 1484 if (func <= 5) {
1485 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1486 } else {
1487 hw_lock_control_reg =
1488 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1489 }
1490
c18487ee 1491 /* Validating that the resource is not already taken */
4a37fb66 1492 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1493 if (lock_status & resource_bit) {
1494 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1495 lock_status, resource_bit);
1496 return -EEXIST;
1497 }
a2fbb9ea 1498
46230476
EG		 1499 /* Try for 5 second every 5ms */
1500 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1501 /* Try to acquire the lock */
4a37fb66
YG		 1502 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1503 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1504 if (lock_status & resource_bit)
1505 return 0;
a2fbb9ea 1506
c18487ee 1507 msleep(5);
a2fbb9ea 1508 }
c18487ee
YR		 1509 DP(NETIF_MSG_HW, "Timeout\n");
1510 return -EAGAIN;
1511}
a2fbb9ea 1512
9f6c9258 1513int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1514{
1515 u32 lock_status;
1516 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1517 int func = BP_FUNC(bp);
1518 u32 hw_lock_control_reg;
a2fbb9ea 1519
72fd0718
VZ		 1520 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1521
c18487ee
YR		 1522 /* Validating that the resource is within range */
1523 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1524 DP(NETIF_MSG_HW,
1525 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1526 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1527 return -EINVAL;
1528 }
1529
4a37fb66
YG		 1530 if (func <= 5) {
1531 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1532 } else {
1533 hw_lock_control_reg =
1534 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1535 }
1536
c18487ee 1537 /* Validating that the resource is currently taken */
4a37fb66 1538 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1539 if (!(lock_status & resource_bit)) {
1540 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1541 lock_status, resource_bit);
1542 return -EFAULT;
a2fbb9ea
ET		 1543 }
1544
9f6c9258
DK		 1545 REG_WR(bp, hw_lock_control_reg, resource_bit);
1546 return 0;
c18487ee 1547}
a2fbb9ea 1548
9f6c9258 1549
4acac6a5
EG		 1550int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1551{
1552 /* The GPIO should be swapped if swap register is set and active */
1553 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1554 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1555 int gpio_shift = gpio_num +
1556 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1557 u32 gpio_mask = (1 << gpio_shift);
1558 u32 gpio_reg;
1559 int value;
1560
1561 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1562 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1563 return -EINVAL;
1564 }
1565
1566 /* read GPIO value */
1567 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1568
1569 /* get the requested pin value */
1570 if ((gpio_reg & gpio_mask) == gpio_mask)
1571 value = 1;
1572 else
1573 value = 0;
1574
1575 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1576
1577 return value;
1578}
1579
17de50b7 1580int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1581{
1582 /* The GPIO should be swapped if swap register is set and active */
1583 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1584 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1585 int gpio_shift = gpio_num +
1586 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1587 u32 gpio_mask = (1 << gpio_shift);
1588 u32 gpio_reg;
a2fbb9ea 1589
c18487ee
YR		 1590 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1591 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1592 return -EINVAL;
1593 }
a2fbb9ea 1594
4a37fb66 1595 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1596 /* read GPIO and mask except the float bits */
1597 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1598
c18487ee
YR		 1599 switch (mode) {
1600 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1601 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1602 gpio_num, gpio_shift);
1603 /* clear FLOAT and set CLR */
1604 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1605 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1606 break;
a2fbb9ea 1607
c18487ee
YR		 1608 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1609 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1610 gpio_num, gpio_shift);
1611 /* clear FLOAT and set SET */
1612 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1613 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1614 break;
a2fbb9ea 1615
17de50b7 1616 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
c18487ee
YR		 1617 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1618 gpio_num, gpio_shift);
1619 /* set FLOAT */
1620 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1621 break;
a2fbb9ea 1622
c18487ee
YR		 1623 default:
1624 break;
a2fbb9ea
ET		 1625 }
1626
c18487ee 1627 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 1628 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 1629
c18487ee 1630 return 0;
a2fbb9ea
ET		 1631}
1632
4acac6a5
EG		 1633int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1634{
1635 /* The GPIO should be swapped if swap register is set and active */
1636 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1637 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1638 int gpio_shift = gpio_num +
1639 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1640 u32 gpio_mask = (1 << gpio_shift);
1641 u32 gpio_reg;
1642
1643 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1644 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1645 return -EINVAL;
1646 }
1647
1648 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1649 /* read GPIO int */
1650 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1651
1652 switch (mode) {
1653 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1654 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1655 "output low\n", gpio_num, gpio_shift);
1656 /* clear SET and set CLR */
1657 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1658 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1659 break;
1660
1661 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1662 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1663 "output high\n", gpio_num, gpio_shift);
1664 /* clear CLR and set SET */
1665 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1666 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1667 break;
1668
1669 default:
1670 break;
1671 }
1672
1673 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1674 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1675
1676 return 0;
1677}
1678
c18487ee 1679static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
a2fbb9ea 1680{
c18487ee
YR		 1681 u32 spio_mask = (1 << spio_num);
1682 u32 spio_reg;
a2fbb9ea 1683
c18487ee
YR		 1684 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1685 (spio_num > MISC_REGISTERS_SPIO_7)) {
1686 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1687 return -EINVAL;
a2fbb9ea
ET		 1688 }
1689
4a37fb66 1690 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee
YR		 1691 /* read SPIO and mask except the float bits */
1692 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
a2fbb9ea 1693
c18487ee 1694 switch (mode) {
6378c025 1695 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
c18487ee
YR		 1696 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1697 /* clear FLOAT and set CLR */
1698 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1699 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1700 break;
a2fbb9ea 1701
6378c025 1702 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
c18487ee
YR		 1703 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1704 /* clear FLOAT and set SET */
1705 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1706 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1707 break;
a2fbb9ea 1708
c18487ee
YR		 1709 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1710 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1711 /* set FLOAT */
1712 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1713 break;
a2fbb9ea 1714
c18487ee
YR		 1715 default:
1716 break;
a2fbb9ea
ET		 1717 }
1718
c18487ee 1719 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 1720 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 1721
a2fbb9ea
ET		 1722 return 0;
1723}
1724
9f6c9258 1725void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 1726{
a22f0788 1727 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 1728 switch (bp->link_vars.ieee_fc &
1729 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 1730 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 1731 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 1732 ADVERTISED_Pause);
c18487ee 1733 break;
356e2385 1734
c18487ee 1735 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 1736 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 1737 ADVERTISED_Pause);
c18487ee 1738 break;
356e2385 1739
c18487ee 1740 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 1741 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 1742 break;
356e2385 1743
c18487ee 1744 default:
a22f0788 1745 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 1746 ADVERTISED_Pause);
c18487ee
YR		 1747 break;
1748 }
1749}
f1410647 1750
9f6c9258 1751u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
c18487ee 1752{
19680c48
EG		 1753 if (!BP_NOMCP(bp)) {
1754 u8 rc;
a22f0788
YR		 1755 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
1756 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
19680c48 1757 /* Initialize link parameters structure variables */
8c99e7b0
YR		 1758 /* It is recommended to turn off RX FC for jumbo frames
1759 for better performance */
f2e0899f 1760 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
c0700f90 1761 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
8c99e7b0 1762 else
c0700f90 1763 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
a2fbb9ea 1764
4a37fb66 1765 bnx2x_acquire_phy_lock(bp);
b5bf9068 1766
a22f0788 1767 if (load_mode == LOAD_DIAG) {
de6eae1f 1768 bp->link_params.loopback_mode = LOOPBACK_XGXS;
a22f0788
YR		 1769 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
1770 }
b5bf9068 1771
19680c48 1772 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 1773
4a37fb66 1774 bnx2x_release_phy_lock(bp);
a2fbb9ea 1775
3c96c68b
EG		 1776 bnx2x_calc_fc_adv(bp);
1777
b5bf9068
EG		 1778 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
1779 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 1780 bnx2x_link_report(bp);
b5bf9068 1781 }
a22f0788 1782 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 1783 return rc;
1784 }
f5372251 1785 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 1786 return -EINVAL;
a2fbb9ea
ET		 1787}
1788
9f6c9258 1789void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 1790{
19680c48 1791 if (!BP_NOMCP(bp)) {
4a37fb66 1792 bnx2x_acquire_phy_lock(bp);
54c2fb78 1793 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
19680c48 1794 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 1795 bnx2x_release_phy_lock(bp);
a2fbb9ea 1796
19680c48
EG		 1797 bnx2x_calc_fc_adv(bp);
1798 } else
f5372251 1799 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 1800}
a2fbb9ea 1801
c18487ee
YR		 1802static void bnx2x__link_reset(struct bnx2x *bp)
1803{
19680c48 1804 if (!BP_NOMCP(bp)) {
4a37fb66 1805 bnx2x_acquire_phy_lock(bp);
589abe3a 1806 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
4a37fb66 1807 bnx2x_release_phy_lock(bp);
19680c48 1808 } else
f5372251 1809 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 1810}
a2fbb9ea 1811
a22f0788 1812u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 1813{
2145a920 1814 u8 rc = 0;
a2fbb9ea 1815
2145a920
VZ		 1816 if (!BP_NOMCP(bp)) {
1817 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 1818 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
1819 is_serdes);
2145a920
VZ		 1820 bnx2x_release_phy_lock(bp);
1821 } else
1822 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 1823
c18487ee
YR		 1824 return rc;
1825}
a2fbb9ea 1826
8a1c38d1 1827static void bnx2x_init_port_minmax(struct bnx2x *bp)
34f80b04 1828{
8a1c38d1
EG		 1829 u32 r_param = bp->link_vars.line_speed / 8;
1830 u32 fair_periodic_timeout_usec;
1831 u32 t_fair;
34f80b04 1832
8a1c38d1
EG		 1833 memset(&(bp->cmng.rs_vars), 0,
1834 sizeof(struct rate_shaping_vars_per_port));
1835 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
34f80b04 1836
8a1c38d1
EG		 1837 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
1838 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
34f80b04 1839
8a1c38d1
EG		 1840 /* this is the threshold below which no timer arming will occur
1841 1.25 coefficient is for the threshold to be a little bigger
1842 than the real time, to compensate for timer in-accuracy */
1843 bp->cmng.rs_vars.rs_threshold =
34f80b04
EG		 1844 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
1845
8a1c38d1
EG		 1846 /* resolution of fairness timer */
1847 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
1848 /* for 10G it is 1000usec. for 1G it is 10000usec. */
1849 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
34f80b04 1850
8a1c38d1
EG		 1851 /* this is the threshold below which we won't arm the timer anymore */
1852 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
34f80b04 1853
8a1c38d1
EG		 1854 /* we multiply by 1e3/8 to get bytes/msec.
1855 We don't want the credits to pass a credit
1856 of the t_fair*FAIR_MEM (algorithm resolution) */
1857 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
1858 /* since each tick is 4 usec */
1859 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
34f80b04
EG		 1860}
1861
2691d51d
EG		 1862/* Calculates the sum of vn_min_rates.
1863 It's needed for further normalizing of the min_rates.
1864 Returns:
1865 sum of vn_min_rates.
1866 or
1867 0 - if all the min_rates are 0.
1868 In the later case fainess algorithm should be deactivated.
1869 If not all min_rates are zero then those that are zeroes will be set to 1.
1870 */
1871static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
1872{
1873 int all_zero = 1;
2691d51d
EG		 1874 int vn;
1875
1876 bp->vn_weight_sum = 0;
1877 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
f2e0899f 1878 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 1879 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1880 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1881
1882 /* Skip hidden vns */
1883 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
1884 continue;
1885
1886 /* If min rate is zero - set it to 1 */
1887 if (!vn_min_rate)
1888 vn_min_rate = DEF_MIN_RATE;
1889 else
1890 all_zero = 0;
1891
1892 bp->vn_weight_sum += vn_min_rate;
1893 }
1894
1895 /* ... only if all min rates are zeros - disable fairness */
b015e3d1
EG		 1896 if (all_zero) {
1897 bp->cmng.flags.cmng_enables &=
1898 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1899 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
1900 " fairness will be disabled\n");
1901 } else
1902 bp->cmng.flags.cmng_enables |=
1903 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 1904}
1905
f2e0899f 1906static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
34f80b04
EG		 1907{
1908 struct rate_shaping_vars_per_vn m_rs_vn;
1909 struct fairness_vars_per_vn m_fair_vn;
f2e0899f
DK		 1910 u32 vn_cfg = bp->mf_config[vn];
1911 int func = 2*vn + BP_PORT(bp);
34f80b04
EG		 1912 u16 vn_min_rate, vn_max_rate;
1913 int i;
1914
1915 /* If function is hidden - set min and max to zeroes */
1916 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
1917 vn_min_rate = 0;
1918 vn_max_rate = 0;
1919
1920 } else {
faa6fcbb
DK		 1921 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
1922
34f80b04
EG		 1923 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1924 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
faa6fcbb
DK		 1925 /* If fairness is enabled (not all min rates are zeroes) and
1926 if current min rate is zero - set it to 1.
1927 This is a requirement of the algorithm. */
f2e0899f 1928 if (bp->vn_weight_sum && (vn_min_rate == 0))
34f80b04 1929 vn_min_rate = DEF_MIN_RATE;
faa6fcbb
DK		 1930
1931 if (IS_MF_SI(bp))
1932 /* maxCfg in percents of linkspeed */
1933 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
1934 else
1935 /* maxCfg is absolute in 100Mb units */
1936 vn_max_rate = maxCfg * 100;
34f80b04 1937 }
f85582f8 1938
8a1c38d1 1939 DP(NETIF_MSG_IFUP,
b015e3d1 1940 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
8a1c38d1 1941 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
34f80b04
EG		 1942
1943 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
1944 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
1945
1946 /* global vn counter - maximal Mbps for this vn */
1947 m_rs_vn.vn_counter.rate = vn_max_rate;
1948
1949 /* quota - number of bytes transmitted in this period */
1950 m_rs_vn.vn_counter.quota =
1951 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
1952
8a1c38d1 1953 if (bp->vn_weight_sum) {
34f80b04
EG		 1954 /* credit for each period of the fairness algorithm:
1955 number of bytes in T_FAIR (the vn share the port rate).
8a1c38d1
EG		 1956 vn_weight_sum should not be larger than 10000, thus
1957 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
1958 than zero */
34f80b04 1959 m_fair_vn.vn_credit_delta =
cdaa7cb8
VZ		 1960 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
1961 (8 * bp->vn_weight_sum))),
ff80ee02
DK		 1962 (bp->cmng.fair_vars.fair_threshold +
1963 MIN_ABOVE_THRESH));
cdaa7cb8 1964 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
34f80b04
EG		 1965 m_fair_vn.vn_credit_delta);
1966 }
1967
34f80b04
EG		 1968 /* Store it to internal memory */
1969 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
1970 REG_WR(bp, BAR_XSTRORM_INTMEM +
1971 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
1972 ((u32 *)(&m_rs_vn))[i]);
1973
1974 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
1975 REG_WR(bp, BAR_XSTRORM_INTMEM +
1976 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
1977 ((u32 *)(&m_fair_vn))[i]);
1978}
f85582f8 1979
523224a3
DK		 1980static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
1981{
1982 if (CHIP_REV_IS_SLOW(bp))
1983 return CMNG_FNS_NONE;
fb3bff17 1984 if (IS_MF(bp))
523224a3
DK		 1985 return CMNG_FNS_MINMAX;
1986
1987 return CMNG_FNS_NONE;
1988}
1989
2ae17f66 1990void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 1991{
0793f83f 1992 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 1993
1994 if (BP_NOMCP(bp))
1995 return; /* what should be the default bvalue in this case */
1996
0793f83f
DK		 1997 /* For 2 port configuration the absolute function number formula
1998 * is:
1999 * abs_func = 2 * vn + BP_PORT + BP_PATH
2000 *
2001 * and there are 4 functions per port
2002 *
2003 * For 4 port configuration it is
2004 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2005 *
2006 * and there are 2 functions per port
2007 */
523224a3 2008 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
0793f83f
DK		 2009 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2010
2011 if (func >= E1H_FUNC_MAX)
2012 break;
2013
f2e0899f 2014 bp->mf_config[vn] =
523224a3
DK		 2015 MF_CFG_RD(bp, func_mf_config[func].config);
2016 }
2017}
2018
2019static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2020{
2021
2022 if (cmng_type == CMNG_FNS_MINMAX) {
2023 int vn;
2024
2025 /* clear cmng_enables */
2026 bp->cmng.flags.cmng_enables = 0;
2027
2028 /* read mf conf from shmem */
2029 if (read_cfg)
2030 bnx2x_read_mf_cfg(bp);
2031
2032 /* Init rate shaping and fairness contexts */
2033 bnx2x_init_port_minmax(bp);
2034
2035 /* vn_weight_sum and enable fairness if not 0 */
2036 bnx2x_calc_vn_weight_sum(bp);
2037
2038 /* calculate and set min-max rate for each vn */
c4154f25
DK		 2039 if (bp->port.pmf)
2040 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2041 bnx2x_init_vn_minmax(bp, vn);
523224a3
DK		 2042
2043 /* always enable rate shaping and fairness */
2044 bp->cmng.flags.cmng_enables |=
2045 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2046 if (!bp->vn_weight_sum)
2047 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2048 " fairness will be disabled\n");
2049 return;
2050 }
2051
2052 /* rate shaping and fairness are disabled */
2053 DP(NETIF_MSG_IFUP,
2054 "rate shaping and fairness are disabled\n");
2055}
34f80b04 2056
523224a3
DK		 2057static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2058{
2059 int port = BP_PORT(bp);
2060 int func;
2061 int vn;
2062
2063 /* Set the attention towards other drivers on the same port */
2064 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2065 if (vn == BP_E1HVN(bp))
2066 continue;
2067
2068 func = ((vn << 1) | port);
2069 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2070 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2071 }
2072}
8a1c38d1 2073
c18487ee
YR		 2074/* This function is called upon link interrupt */
2075static void bnx2x_link_attn(struct bnx2x *bp)
2076{
bb2a0f7a
YG		 2077 /* Make sure that we are synced with the current statistics */
2078 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2079
c18487ee 2080 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2081
bb2a0f7a
YG		 2082 if (bp->link_vars.link_up) {
2083
1c06328c 2084 /* dropless flow control */
f2e0899f 2085 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2086 int port = BP_PORT(bp);
2087 u32 pause_enabled = 0;
2088
2089 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2090 pause_enabled = 1;
2091
2092 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2093 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2094 pause_enabled);
2095 }
2096
bb2a0f7a
YG		 2097 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2098 struct host_port_stats *pstats;
2099
2100 pstats = bnx2x_sp(bp, port_stats);
2101 /* reset old bmac stats */
2102 memset(&(pstats->mac_stx[0]), 0,
2103 sizeof(struct mac_stx));
2104 }
f34d28ea 2105 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2106 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2107 }
2108
f2e0899f
DK		 2109 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2110 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2111
f2e0899f
DK		 2112 if (cmng_fns != CMNG_FNS_NONE) {
2113 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2114 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2115 } else
2116 /* rate shaping and fairness are disabled */
2117 DP(NETIF_MSG_IFUP,
2118 "single function mode without fairness\n");
34f80b04 2119 }
9fdc3e95 2120
2ae17f66
VZ		 2121 __bnx2x_link_report(bp);
2122
9fdc3e95
DK		 2123 if (IS_MF(bp))
2124 bnx2x_link_sync_notify(bp);
c18487ee 2125}
a2fbb9ea 2126
9f6c9258 2127void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2128{
2ae17f66 2129 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2130 return;
a2fbb9ea 2131
c18487ee 2132 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2133
bb2a0f7a
YG		 2134 if (bp->link_vars.link_up)
2135 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2136 else
2137 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2138
c18487ee
YR		 2139 /* indicate link status */
2140 bnx2x_link_report(bp);
a2fbb9ea 2141}
a2fbb9ea 2142
34f80b04
EG		 2143static void bnx2x_pmf_update(struct bnx2x *bp)
2144{
2145 int port = BP_PORT(bp);
2146 u32 val;
2147
2148 bp->port.pmf = 1;
2149 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2150
2151 /* enable nig attention */
2152 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
f2e0899f
DK		 2153 if (bp->common.int_block == INT_BLOCK_HC) {
2154 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2155 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2156 } else if (CHIP_IS_E2(bp)) {
2157 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2158 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2159 }
bb2a0f7a
YG		 2160
2161 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2162}
2163
c18487ee 2164/* end of Link */
a2fbb9ea
ET		 2165
2166/* slow path */
2167
2168/*
2169 * General service functions
2170 */
2171
2691d51d 2172/* send the MCP a request, block until there is a reply */
a22f0788 2173u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2174{
f2e0899f 2175 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2176 u32 seq;
2691d51d
EG		 2177 u32 rc = 0;
2178 u32 cnt = 1;
2179 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2180
c4ff7cbf 2181 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2182 seq = ++bp->fw_seq;
f2e0899f
DK		 2183 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2184 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2185
2691d51d
EG		 2186 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
2187
2188 do {
2189 /* let the FW do it's magic ... */
2190 msleep(delay);
2191
f2e0899f 2192 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2193
c4ff7cbf
EG		 2194 /* Give the FW up to 5 second (500*10ms) */
2195 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2196
2197 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2198 cnt*delay, rc, seq);
2199
2200 /* is this a reply to our command? */
2201 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2202 rc &= FW_MSG_CODE_MASK;
2203 else {
2204 /* FW BUG! */
2205 BNX2X_ERR("FW failed to respond!\n");
2206 bnx2x_fw_dump(bp);
2207 rc = 0;
2208 }
c4ff7cbf 2209 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2210
2211 return rc;
2212}
2213
ec6ba945
VZ		 2214static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2215{
2216#ifdef BCM_CNIC
2217 if (IS_FCOE_FP(fp) && IS_MF(bp))
2218 return false;
2219#endif
2220 return true;
2221}
2222
523224a3 2223/* must be called under rtnl_lock */
8d96286a 2224static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
2691d51d 2225{
523224a3 2226 u32 mask = (1 << cl_id);
2691d51d 2227
523224a3
DK		 2228 /* initial seeting is BNX2X_ACCEPT_NONE */
2229 u8 drop_all_ucast = 1, drop_all_bcast = 1, drop_all_mcast = 1;
2230 u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2231 u8 unmatched_unicast = 0;
2691d51d 2232
0793f83f
DK		 2233 if (filters & BNX2X_ACCEPT_UNMATCHED_UCAST)
2234 unmatched_unicast = 1;
2235
523224a3
DK		 2236 if (filters & BNX2X_PROMISCUOUS_MODE) {
2237 /* promiscious - accept all, drop none */
2238 drop_all_ucast = drop_all_bcast = drop_all_mcast = 0;
2239 accp_all_ucast = accp_all_bcast = accp_all_mcast = 1;
0793f83f
DK		 2240 if (IS_MF_SI(bp)) {
2241 /*
2242 * SI mode defines to accept in promiscuos mode
2243 * only unmatched packets
2244 */
2245 unmatched_unicast = 1;
2246 accp_all_ucast = 0;
2247 }
523224a3
DK		 2248 }
2249 if (filters & BNX2X_ACCEPT_UNICAST) {
2250 /* accept matched ucast */
2251 drop_all_ucast = 0;
2252 }
d9c8f498 2253 if (filters & BNX2X_ACCEPT_MULTICAST)
523224a3
DK		 2254 /* accept matched mcast */
2255 drop_all_mcast = 0;
d9c8f498 2256
523224a3
DK		 2257 if (filters & BNX2X_ACCEPT_ALL_UNICAST) {
2258 /* accept all mcast */
2259 drop_all_ucast = 0;
2260 accp_all_ucast = 1;
2261 }
2262 if (filters & BNX2X_ACCEPT_ALL_MULTICAST) {
2263 /* accept all mcast */
2264 drop_all_mcast = 0;
2265 accp_all_mcast = 1;
2266 }
2267 if (filters & BNX2X_ACCEPT_BROADCAST) {
2268 /* accept (all) bcast */
2269 drop_all_bcast = 0;
2270 accp_all_bcast = 1;
2271 }
2691d51d 2272
523224a3
DK		 2273 bp->mac_filters.ucast_drop_all = drop_all_ucast ?
2274 bp->mac_filters.ucast_drop_all | mask :
2275 bp->mac_filters.ucast_drop_all & ~mask;
2691d51d 2276
523224a3
DK		 2277 bp->mac_filters.mcast_drop_all = drop_all_mcast ?
2278 bp->mac_filters.mcast_drop_all | mask :
2279 bp->mac_filters.mcast_drop_all & ~mask;
2691d51d 2280
523224a3
DK		 2281 bp->mac_filters.bcast_drop_all = drop_all_bcast ?
2282 bp->mac_filters.bcast_drop_all | mask :
2283 bp->mac_filters.bcast_drop_all & ~mask;
2691d51d 2284
523224a3
DK		 2285 bp->mac_filters.ucast_accept_all = accp_all_ucast ?
2286 bp->mac_filters.ucast_accept_all | mask :
2287 bp->mac_filters.ucast_accept_all & ~mask;
2691d51d 2288
523224a3
DK		 2289 bp->mac_filters.mcast_accept_all = accp_all_mcast ?
2290 bp->mac_filters.mcast_accept_all | mask :
2291 bp->mac_filters.mcast_accept_all & ~mask;
2292
2293 bp->mac_filters.bcast_accept_all = accp_all_bcast ?
2294 bp->mac_filters.bcast_accept_all | mask :
2295 bp->mac_filters.bcast_accept_all & ~mask;
2296
2297 bp->mac_filters.unmatched_unicast = unmatched_unicast ?
2298 bp->mac_filters.unmatched_unicast | mask :
2299 bp->mac_filters.unmatched_unicast & ~mask;
2691d51d
EG		 2300}
2301
8d96286a 2302static void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2691d51d 2303{
030f3356
DK		 2304 struct tstorm_eth_function_common_config tcfg = {0};
2305 u16 rss_flgs;
2691d51d 2306
030f3356
DK		 2307 /* tpa */
2308 if (p->func_flgs & FUNC_FLG_TPA)
2309 tcfg.config_flags |=
2310 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
2691d51d 2311
030f3356
DK		 2312 /* set rss flags */
2313 rss_flgs = (p->rss->mode <<
2314 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT);
2315
2316 if (p->rss->cap & RSS_IPV4_CAP)
2317 rss_flgs |= RSS_IPV4_CAP_MASK;
2318 if (p->rss->cap & RSS_IPV4_TCP_CAP)
2319 rss_flgs |= RSS_IPV4_TCP_CAP_MASK;
2320 if (p->rss->cap & RSS_IPV6_CAP)
2321 rss_flgs |= RSS_IPV6_CAP_MASK;
2322 if (p->rss->cap & RSS_IPV6_TCP_CAP)
2323 rss_flgs |= RSS_IPV6_TCP_CAP_MASK;
2324
2325 tcfg.config_flags |= rss_flgs;
2326 tcfg.rss_result_mask = p->rss->result_mask;
2327
2328 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2691d51d 2329
523224a3
DK		 2330 /* Enable the function in the FW */
2331 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2332 storm_memset_func_en(bp, p->func_id, 1);
2691d51d 2333
523224a3
DK		 2334 /* statistics */
2335 if (p->func_flgs & FUNC_FLG_STATS) {
2336 struct stats_indication_flags stats_flags = {0};
2337 stats_flags.collect_eth = 1;
2691d51d 2338
523224a3
DK		 2339 storm_memset_xstats_flags(bp, &stats_flags, p->func_id);
2340 storm_memset_xstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2341
523224a3
DK		 2342 storm_memset_tstats_flags(bp, &stats_flags, p->func_id);
2343 storm_memset_tstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2344
523224a3
DK		 2345 storm_memset_ustats_flags(bp, &stats_flags, p->func_id);
2346 storm_memset_ustats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2347
523224a3
DK		 2348 storm_memset_cstats_flags(bp, &stats_flags, p->func_id);
2349 storm_memset_cstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d
EG		 2350 }
2351
523224a3
DK		 2352 /* spq */
2353 if (p->func_flgs & FUNC_FLG_SPQ) {
2354 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2355 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2356 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2357 }
2691d51d
EG		 2358}
2359
523224a3
DK		 2360static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
2361 struct bnx2x_fastpath *fp)
28912902 2362{
523224a3 2363 u16 flags = 0;
28912902 2364
523224a3
DK		 2365 /* calculate queue flags */
2366 flags |= QUEUE_FLG_CACHE_ALIGN;
2367 flags |= QUEUE_FLG_HC;
0793f83f 2368 flags |= IS_MF_SD(bp) ? QUEUE_FLG_OV : 0;
28912902 2369
523224a3
DK		 2370 flags |= QUEUE_FLG_VLAN;
2371 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
523224a3
DK		 2372
2373 if (!fp->disable_tpa)
2374 flags |= QUEUE_FLG_TPA;
2375
ec6ba945
VZ		 2376 flags = stat_counter_valid(bp, fp) ?
2377 (flags | QUEUE_FLG_STATS) : (flags & ~QUEUE_FLG_STATS);
523224a3
DK		 2378
2379 return flags;
2380}
2381
2382static void bnx2x_pf_rx_cl_prep(struct bnx2x *bp,
2383 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2384 struct bnx2x_rxq_init_params *rxq_init)
2385{
2386 u16 max_sge = 0;
2387 u16 sge_sz = 0;
2388 u16 tpa_agg_size = 0;
2389
2390 /* calculate queue flags */
2391 u16 flags = bnx2x_get_cl_flags(bp, fp);
2392
2393 if (!fp->disable_tpa) {
2394 pause->sge_th_hi = 250;
2395 pause->sge_th_lo = 150;
2396 tpa_agg_size = min_t(u32,
2397 (min_t(u32, 8, MAX_SKB_FRAGS) *
2398 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2399 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2400 SGE_PAGE_SHIFT;
2401 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2402 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2403 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2404 0xffff);
2405 }
2406
2407 /* pause - not for e1 */
2408 if (!CHIP_IS_E1(bp)) {
2409 pause->bd_th_hi = 350;
2410 pause->bd_th_lo = 250;
2411 pause->rcq_th_hi = 350;
2412 pause->rcq_th_lo = 250;
2413 pause->sge_th_hi = 0;
2414 pause->sge_th_lo = 0;
2415 pause->pri_map = 1;
2416 }
2417
2418 /* rxq setup */
2419 rxq_init->flags = flags;
2420 rxq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2421 rxq_init->dscr_map = fp->rx_desc_mapping;
2422 rxq_init->sge_map = fp->rx_sge_mapping;
2423 rxq_init->rcq_map = fp->rx_comp_mapping;
2424 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91
VZ		 2425
2426 /* Always use mini-jumbo MTU for FCoE L2 ring */
2427 if (IS_FCOE_FP(fp))
2428 rxq_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2429 else
2430 rxq_init->mtu = bp->dev->mtu;
2431
2432 rxq_init->buf_sz = fp->rx_buf_size;
523224a3
DK		 2433 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2434 rxq_init->cl_id = fp->cl_id;
2435 rxq_init->spcl_id = fp->cl_id;
2436 rxq_init->stat_id = fp->cl_id;
2437 rxq_init->tpa_agg_sz = tpa_agg_size;
2438 rxq_init->sge_buf_sz = sge_sz;
2439 rxq_init->max_sges_pkt = max_sge;
2440 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2441 rxq_init->fw_sb_id = fp->fw_sb_id;
2442
ec6ba945
VZ		 2443 if (IS_FCOE_FP(fp))
2444 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2445 else
2446 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
523224a3
DK		 2447
2448 rxq_init->cid = HW_CID(bp, fp->cid);
2449
2450 rxq_init->hc_rate = bp->rx_ticks ? (1000000 / bp->rx_ticks) : 0;
2451}
2452
2453static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
2454 struct bnx2x_fastpath *fp, struct bnx2x_txq_init_params *txq_init)
2455{
2456 u16 flags = bnx2x_get_cl_flags(bp, fp);
2457
2458 txq_init->flags = flags;
2459 txq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2460 txq_init->dscr_map = fp->tx_desc_mapping;
2461 txq_init->stat_id = fp->cl_id;
2462 txq_init->cid = HW_CID(bp, fp->cid);
2463 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2464 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2465 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945
VZ		 2466
2467 if (IS_FCOE_FP(fp)) {
2468 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2469 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2470 }
2471
523224a3
DK		 2472 txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
2473}
2474
8d96286a 2475static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 2476{
2477 struct bnx2x_func_init_params func_init = {0};
2478 struct bnx2x_rss_params rss = {0};
2479 struct event_ring_data eq_data = { {0} };
2480 u16 flags;
2481
2482 /* pf specific setups */
2483 if (!CHIP_IS_E1(bp))
fb3bff17 2484 storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp));
523224a3 2485
f2e0899f
DK		 2486 if (CHIP_IS_E2(bp)) {
2487 /* reset IGU PF statistics: MSIX + ATTN */
2488 /* PF */
2489 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2490 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2491 (CHIP_MODE_IS_4_PORT(bp) ?
2492 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2493 /* ATTN */
2494 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2495 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2496 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2497 (CHIP_MODE_IS_4_PORT(bp) ?
2498 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2499 }
2500
523224a3
DK		 2501 /* function setup flags */
2502 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2503
f2e0899f
DK		 2504 if (CHIP_IS_E1x(bp))
2505 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2506 else
2507 flags |= FUNC_FLG_TPA;
523224a3 2508
030f3356
DK		 2509 /* function setup */
2510
523224a3
DK		 2511 /**
2512 * Although RSS is meaningless when there is a single HW queue we
2513 * still need it enabled in order to have HW Rx hash generated.
523224a3 2514 */
030f3356
DK		 2515 rss.cap = (RSS_IPV4_CAP | RSS_IPV4_TCP_CAP |
2516 RSS_IPV6_CAP | RSS_IPV6_TCP_CAP);
2517 rss.mode = bp->multi_mode;
2518 rss.result_mask = MULTI_MASK;
2519 func_init.rss = &rss;
523224a3
DK		 2520
2521 func_init.func_flgs = flags;
2522 func_init.pf_id = BP_FUNC(bp);
2523 func_init.func_id = BP_FUNC(bp);
2524 func_init.fw_stat_map = bnx2x_sp_mapping(bp, fw_stats);
2525 func_init.spq_map = bp->spq_mapping;
2526 func_init.spq_prod = bp->spq_prod_idx;
2527
2528 bnx2x_func_init(bp, &func_init);
2529
2530 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2531
2532 /*
2533 Congestion management values depend on the link rate
2534 There is no active link so initial link rate is set to 10 Gbps.
2535 When the link comes up The congestion management values are
2536 re-calculated according to the actual link rate.
2537 */
2538 bp->link_vars.line_speed = SPEED_10000;
2539 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2540
2541 /* Only the PMF sets the HW */
2542 if (bp->port.pmf)
2543 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2544
2545 /* no rx until link is up */
2546 bp->rx_mode = BNX2X_RX_MODE_NONE;
2547 bnx2x_set_storm_rx_mode(bp);
2548
2549 /* init Event Queue */
2550 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2551 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2552 eq_data.producer = bp->eq_prod;
2553 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2554 eq_data.sb_id = DEF_SB_ID;
2555 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2556}
2557
2558
2559static void bnx2x_e1h_disable(struct bnx2x *bp)
2560{
2561 int port = BP_PORT(bp);
2562
2563 netif_tx_disable(bp->dev);
2564
2565 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2566
2567 netif_carrier_off(bp->dev);
2568}
2569
2570static void bnx2x_e1h_enable(struct bnx2x *bp)
2571{
2572 int port = BP_PORT(bp);
2573
2574 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2575
2576 /* Tx queue should be only reenabled */
2577 netif_tx_wake_all_queues(bp->dev);
2578
2579 /*
2580 * Should not call netif_carrier_on since it will be called if the link
2581 * is up when checking for link state
2582 */
2583}
2584
0793f83f
DK		 2585/* called due to MCP event (on pmf):
2586 * reread new bandwidth configuration
2587 * configure FW
2588 * notify others function about the change
2589 */
2590static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2591{
2592 if (bp->link_vars.link_up) {
2593 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2594 bnx2x_link_sync_notify(bp);
2595 }
2596 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2597}
2598
2599static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2600{
2601 bnx2x_config_mf_bw(bp);
2602 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2603}
2604
523224a3
DK		 2605static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2606{
2607 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2608
2609 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2610
2611 /*
2612 * This is the only place besides the function initialization
2613 * where the bp->flags can change so it is done without any
2614 * locks
2615 */
f2e0899f 2616 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
523224a3
DK		 2617 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2618 bp->flags |= MF_FUNC_DIS;
2619
2620 bnx2x_e1h_disable(bp);
2621 } else {
2622 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2623 bp->flags &= ~MF_FUNC_DIS;
2624
2625 bnx2x_e1h_enable(bp);
2626 }
2627 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2628 }
2629 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 2630 bnx2x_config_mf_bw(bp);
523224a3
DK		 2631 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2632 }
2633
2634 /* Report results to MCP */
2635 if (dcc_event)
2636 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2637 else
2638 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2639}
2640
2641/* must be called under the spq lock */
2642static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2643{
2644 struct eth_spe *next_spe = bp->spq_prod_bd;
2645
2646 if (bp->spq_prod_bd == bp->spq_last_bd) {
2647 bp->spq_prod_bd = bp->spq;
2648 bp->spq_prod_idx = 0;
2649 DP(NETIF_MSG_TIMER, "end of spq\n");
2650 } else {
2651 bp->spq_prod_bd++;
2652 bp->spq_prod_idx++;
2653 }
2654 return next_spe;
2655}
2656
2657/* must be called under the spq lock */
28912902
MC		 2658static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2659{
2660 int func = BP_FUNC(bp);
2661
2662 /* Make sure that BD data is updated before writing the producer */
2663 wmb();
2664
523224a3 2665 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 2666 bp->spq_prod_idx);
28912902
MC		 2667 mmiowb();
2668}
2669
a2fbb9ea 2670/* the slow path queue is odd since completions arrive on the fastpath ring */
9f6c9258 2671int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
f85582f8 2672 u32 data_hi, u32 data_lo, int common)
a2fbb9ea 2673{
28912902 2674 struct eth_spe *spe;
523224a3 2675 u16 type;
a2fbb9ea 2676
a2fbb9ea
ET		 2677#ifdef BNX2X_STOP_ON_ERROR
2678 if (unlikely(bp->panic))
2679 return -EIO;
2680#endif
2681
34f80b04 2682 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 2683
6e30dd4e
VZ		 2684 if (common) {
2685 if (!atomic_read(&bp->eq_spq_left)) {
2686 BNX2X_ERR("BUG! EQ ring full!\n");
2687 spin_unlock_bh(&bp->spq_lock);
2688 bnx2x_panic();
2689 return -EBUSY;
2690 }
2691 } else if (!atomic_read(&bp->cq_spq_left)) {
2692 BNX2X_ERR("BUG! SPQ ring full!\n");
2693 spin_unlock_bh(&bp->spq_lock);
2694 bnx2x_panic();
2695 return -EBUSY;
a2fbb9ea 2696 }
f1410647 2697
28912902
MC		 2698 spe = bnx2x_sp_get_next(bp);
2699
a2fbb9ea 2700 /* CID needs port number to be encoded int it */
28912902 2701 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 2702 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
2703 HW_CID(bp, cid));
523224a3 2704
a2fbb9ea 2705 if (common)
523224a3
DK		 2706 /* Common ramrods:
2707 * FUNC_START, FUNC_STOP, CFC_DEL, STATS, SET_MAC
2708 * TRAFFIC_STOP, TRAFFIC_START
2709 */
2710 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2711 & SPE_HDR_CONN_TYPE;
2712 else
2713 /* ETH ramrods: SETUP, HALT */
2714 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2715 & SPE_HDR_CONN_TYPE;
a2fbb9ea 2716
523224a3
DK		 2717 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2718 SPE_HDR_FUNCTION_ID);
a2fbb9ea 2719
523224a3
DK		 2720 spe->hdr.type = cpu_to_le16(type);
2721
2722 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2723 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2724
2725 /* stats ramrod has it's own slot on the spq */
6e30dd4e 2726 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
523224a3
DK		 2727 /* It's ok if the actual decrement is issued towards the memory
2728 * somewhere between the spin_lock and spin_unlock. Thus no
2729 * more explict memory barrier is needed.
2730 */
6e30dd4e
VZ		 2731 if (common)
2732 atomic_dec(&bp->eq_spq_left);
2733 else
2734 atomic_dec(&bp->cq_spq_left);
2735 }
2736
a2fbb9ea 2737
cdaa7cb8 2738 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
523224a3 2739 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
6e30dd4e 2740 "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
cdaa7cb8
VZ		 2741 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
2742 (u32)(U64_LO(bp->spq_mapping) +
2743 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
6e30dd4e
VZ		 2744 HW_CID(bp, cid), data_hi, data_lo, type,
2745 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 2746
28912902 2747 bnx2x_sp_prod_update(bp);
34f80b04 2748 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 2749 return 0;
2750}
2751
2752/* acquire split MCP access lock register */
4a37fb66 2753static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 2754{
72fd0718 2755 u32 j, val;
34f80b04 2756 int rc = 0;
a2fbb9ea
ET		 2757
2758 might_sleep();
72fd0718 2759 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 2760 val = (1UL << 31);
2761 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2762 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2763 if (val & (1L << 31))
2764 break;
2765
2766 msleep(5);
2767 }
a2fbb9ea 2768 if (!(val & (1L << 31))) {
19680c48 2769 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 2770 rc = -EBUSY;
2771 }
2772
2773 return rc;
2774}
2775
4a37fb66
YG		 2776/* release split MCP access lock register */
2777static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 2778{
72fd0718 2779 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 2780}
2781
523224a3
DK		 2782#define BNX2X_DEF_SB_ATT_IDX 0x0001
2783#define BNX2X_DEF_SB_IDX 0x0002
2784
a2fbb9ea
ET		 2785static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2786{
523224a3 2787 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 2788 u16 rc = 0;
2789
2790 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 2791 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2792 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 2793 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 2794 }
523224a3
DK		 2795
2796 if (bp->def_idx != def_sb->sp_sb.running_index) {
2797 bp->def_idx = def_sb->sp_sb.running_index;
2798 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 2799 }
523224a3
DK		 2800
2801 /* Do not reorder: indecies reading should complete before handling */
2802 barrier();
a2fbb9ea
ET		 2803 return rc;
2804}
2805
2806/*
2807 * slow path service functions
2808 */
2809
2810static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2811{
34f80b04 2812 int port = BP_PORT(bp);
a2fbb9ea
ET		 2813 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2814 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 2815 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2816 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 2817 u32 aeu_mask;
87942b46 2818 u32 nig_mask = 0;
f2e0899f 2819 u32 reg_addr;
a2fbb9ea 2820
a2fbb9ea
ET		 2821 if (bp->attn_state & asserted)
2822 BNX2X_ERR("IGU ERROR\n");
2823
3fcaf2e5
EG		 2824 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2825 aeu_mask = REG_RD(bp, aeu_addr);
2826
a2fbb9ea 2827 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 2828 aeu_mask, asserted);
72fd0718 2829 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 2830 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 2831
3fcaf2e5
EG		 2832 REG_WR(bp, aeu_addr, aeu_mask);
2833 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 2834
3fcaf2e5 2835 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 2836 bp->attn_state |= asserted;
3fcaf2e5 2837 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 2838
2839 if (asserted & ATTN_HARD_WIRED_MASK) {
2840 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 2841
a5e9a7cf
EG		 2842 bnx2x_acquire_phy_lock(bp);
2843
877e9aa4 2844 /* save nig interrupt mask */
87942b46 2845 nig_mask = REG_RD(bp, nig_int_mask_addr);
877e9aa4 2846 REG_WR(bp, nig_int_mask_addr, 0);
a2fbb9ea 2847
c18487ee 2848 bnx2x_link_attn(bp);
a2fbb9ea
ET		 2849
2850 /* handle unicore attn? */
2851 }
2852 if (asserted & ATTN_SW_TIMER_4_FUNC)
2853 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2854
2855 if (asserted & GPIO_2_FUNC)
2856 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2857
2858 if (asserted & GPIO_3_FUNC)
2859 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2860
2861 if (asserted & GPIO_4_FUNC)
2862 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2863
2864 if (port == 0) {
2865 if (asserted & ATTN_GENERAL_ATTN_1) {
2866 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2867 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2868 }
2869 if (asserted & ATTN_GENERAL_ATTN_2) {
2870 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2871 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2872 }
2873 if (asserted & ATTN_GENERAL_ATTN_3) {
2874 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2875 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2876 }
2877 } else {
2878 if (asserted & ATTN_GENERAL_ATTN_4) {
2879 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2880 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2881 }
2882 if (asserted & ATTN_GENERAL_ATTN_5) {
2883 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2884 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2885 }
2886 if (asserted & ATTN_GENERAL_ATTN_6) {
2887 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2888 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2889 }
2890 }
2891
2892 } /* if hardwired */
2893
f2e0899f
DK		 2894 if (bp->common.int_block == INT_BLOCK_HC)
2895 reg_addr = (HC_REG_COMMAND_REG + port*32 +
2896 COMMAND_REG_ATTN_BITS_SET);
2897 else
2898 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
2899
2900 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
2901 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
2902 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 2903
2904 /* now set back the mask */
a5e9a7cf 2905 if (asserted & ATTN_NIG_FOR_FUNC) {
87942b46 2906 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 2907 bnx2x_release_phy_lock(bp);
2908 }
a2fbb9ea
ET		 2909}
2910
fd4ef40d
EG		 2911static inline void bnx2x_fan_failure(struct bnx2x *bp)
2912{
2913 int port = BP_PORT(bp);
b7737c9b 2914 u32 ext_phy_config;
fd4ef40d 2915 /* mark the failure */
b7737c9b
YR		 2916 ext_phy_config =
2917 SHMEM_RD(bp,
2918 dev_info.port_hw_config[port].external_phy_config);
2919
2920 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2921 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 2922 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 2923 ext_phy_config);
fd4ef40d
EG		 2924
2925 /* log the failure */
cdaa7cb8
VZ		 2926 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
2927 " the driver to shutdown the card to prevent permanent"
2928 " damage. Please contact OEM Support for assistance\n");
fd4ef40d 2929}
ab6ad5a4 2930
877e9aa4 2931static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 2932{
34f80b04 2933 int port = BP_PORT(bp);
877e9aa4 2934 int reg_offset;
d90d96ba 2935 u32 val;
877e9aa4 2936
34f80b04
EG		 2937 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2938 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 2939
34f80b04 2940 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 2941
2942 val = REG_RD(bp, reg_offset);
2943 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2944 REG_WR(bp, reg_offset, val);
2945
2946 BNX2X_ERR("SPIO5 hw attention\n");
2947
fd4ef40d 2948 /* Fan failure attention */
d90d96ba 2949 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 2950 bnx2x_fan_failure(bp);
877e9aa4 2951 }
34f80b04 2952
589abe3a
EG		 2953 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
2954 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
2955 bnx2x_acquire_phy_lock(bp);
2956 bnx2x_handle_module_detect_int(&bp->link_params);
2957 bnx2x_release_phy_lock(bp);
2958 }
2959
34f80b04
EG		 2960 if (attn & HW_INTERRUT_ASSERT_SET_0) {
2961
2962 val = REG_RD(bp, reg_offset);
2963 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
2964 REG_WR(bp, reg_offset, val);
2965
2966 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 2967 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 2968 bnx2x_panic();
2969 }
877e9aa4
ET		 2970}
2971
2972static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
2973{
2974 u32 val;
2975
0626b899 2976 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 2977
2978 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
2979 BNX2X_ERR("DB hw attention 0x%x\n", val);
2980 /* DORQ discard attention */
2981 if (val & 0x2)
2982 BNX2X_ERR("FATAL error from DORQ\n");
2983 }
34f80b04
EG		 2984
2985 if (attn & HW_INTERRUT_ASSERT_SET_1) {
2986
2987 int port = BP_PORT(bp);
2988 int reg_offset;
2989
2990 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
2991 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
2992
2993 val = REG_RD(bp, reg_offset);
2994 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
2995 REG_WR(bp, reg_offset, val);
2996
2997 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 2998 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 2999 bnx2x_panic();
3000 }
877e9aa4
ET		 3001}
3002
3003static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3004{
3005 u32 val;
3006
3007 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3008
3009 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3010 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3011 /* CFC error attention */
3012 if (val & 0x2)
3013 BNX2X_ERR("FATAL error from CFC\n");
3014 }
3015
3016 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3017
3018 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3019 BNX2X_ERR("PXP hw attention 0x%x\n", val);
3020 /* RQ_USDMDP_FIFO_OVERFLOW */
3021 if (val & 0x18000)
3022 BNX2X_ERR("FATAL error from PXP\n");
f2e0899f
DK		 3023 if (CHIP_IS_E2(bp)) {
3024 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3025 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3026 }
877e9aa4 3027 }
34f80b04
EG		 3028
3029 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3030
3031 int port = BP_PORT(bp);
3032 int reg_offset;
3033
3034 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3035 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3036
3037 val = REG_RD(bp, reg_offset);
3038 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3039 REG_WR(bp, reg_offset, val);
3040
3041 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3042 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3043 bnx2x_panic();
3044 }
877e9aa4
ET		 3045}
3046
3047static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3048{
34f80b04
EG		 3049 u32 val;
3050
877e9aa4
ET		 3051 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3052
34f80b04
EG		 3053 if (attn & BNX2X_PMF_LINK_ASSERT) {
3054 int func = BP_FUNC(bp);
3055
3056 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
f2e0899f
DK		 3057 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3058 func_mf_config[BP_ABS_FUNC(bp)].config);
3059 val = SHMEM_RD(bp,
3060 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3061 if (val & DRV_STATUS_DCC_EVENT_MASK)
3062 bnx2x_dcc_event(bp,
3063 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3064
3065 if (val & DRV_STATUS_SET_MF_BW)
3066 bnx2x_set_mf_bw(bp);
3067
2691d51d 3068 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3069 bnx2x_pmf_update(bp);
3070
2ae17f66
VZ		 3071 /* Always call it here: bnx2x_link_report() will
3072 * prevent the link indication duplication.
3073 */
3074 bnx2x__link_status_update(bp);
3075
e4901dde 3076 if (bp->port.pmf &&
785b9b1a
SR		 3077 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3078 bp->dcbx_enabled > 0)
e4901dde
VZ		 3079 /* start dcbx state machine */
3080 bnx2x_dcbx_set_params(bp,
3081 BNX2X_DCBX_STATE_NEG_RECEIVED);
34f80b04 3082 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3083
3084 BNX2X_ERR("MC assert!\n");
3085 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3086 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3087 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3088 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3089 bnx2x_panic();
3090
3091 } else if (attn & BNX2X_MCP_ASSERT) {
3092
3093 BNX2X_ERR("MCP assert!\n");
3094 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3095 bnx2x_fw_dump(bp);
877e9aa4
ET		 3096
3097 } else
3098 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3099 }
3100
3101 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3102 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3103 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3104 val = CHIP_IS_E1(bp) ? 0 :
3105 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3106 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3107 }
3108 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3109 val = CHIP_IS_E1(bp) ? 0 :
3110 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3111 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3112 }
877e9aa4 3113 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3114 }
3115}
3116
72fd0718
VZ		 3117#define BNX2X_MISC_GEN_REG MISC_REG_GENERIC_POR_1
3118#define LOAD_COUNTER_BITS 16 /* Number of bits for load counter */
3119#define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
3120#define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
3121#define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
f85582f8 3122
72fd0718
VZ		 3123/*
3124 * should be run under rtnl lock
3125 */
3126static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3127{
3128 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3129 val &= ~(1 << RESET_DONE_FLAG_SHIFT);
3130 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3131 barrier();
3132 mmiowb();
3133}
3134
3135/*
3136 * should be run under rtnl lock
3137 */
3138static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3139{
3140 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3141 val |= (1 << 16);
3142 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3143 barrier();
3144 mmiowb();
3145}
3146
3147/*
3148 * should be run under rtnl lock
3149 */
9f6c9258 3150bool bnx2x_reset_is_done(struct bnx2x *bp)
72fd0718
VZ		 3151{
3152 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3153 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3154 return (val & RESET_DONE_FLAG_MASK) ? false : true;
3155}
3156
3157/*
3158 * should be run under rtnl lock
3159 */
9f6c9258 3160inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
72fd0718
VZ		 3161{
3162 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3163
3164 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3165
3166 val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
3167 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3168 barrier();
3169 mmiowb();
3170}
3171
3172/*
3173 * should be run under rtnl lock
3174 */
9f6c9258 3175u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
72fd0718
VZ		 3176{
3177 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3178
3179 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3180
3181 val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
3182 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3183 barrier();
3184 mmiowb();
3185
3186 return val1;
3187}
3188
3189/*
3190 * should be run under rtnl lock
3191 */
3192static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
3193{
3194 return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
3195}
3196
3197static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3198{
3199 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3200 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
3201}
3202
3203static inline void _print_next_block(int idx, const char *blk)
3204{
3205 if (idx)
3206 pr_cont(", ");
3207 pr_cont("%s", blk);
3208}
3209
3210static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3211{
3212 int i = 0;
3213 u32 cur_bit = 0;
3214 for (i = 0; sig; i++) {
3215 cur_bit = ((u32)0x1 << i);
3216 if (sig & cur_bit) {
3217 switch (cur_bit) {
3218 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3219 _print_next_block(par_num++, "BRB");
3220 break;
3221 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3222 _print_next_block(par_num++, "PARSER");
3223 break;
3224 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3225 _print_next_block(par_num++, "TSDM");
3226 break;
3227 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3228 _print_next_block(par_num++, "SEARCHER");
3229 break;
3230 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3231 _print_next_block(par_num++, "TSEMI");
3232 break;
3233 }
3234
3235 /* Clear the bit */
3236 sig &= ~cur_bit;
3237 }
3238 }
3239
3240 return par_num;
3241}
3242
3243static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3244{
3245 int i = 0;
3246 u32 cur_bit = 0;
3247 for (i = 0; sig; i++) {
3248 cur_bit = ((u32)0x1 << i);
3249 if (sig & cur_bit) {
3250 switch (cur_bit) {
3251 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3252 _print_next_block(par_num++, "PBCLIENT");
3253 break;
3254 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3255 _print_next_block(par_num++, "QM");
3256 break;
3257 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3258 _print_next_block(par_num++, "XSDM");
3259 break;
3260 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3261 _print_next_block(par_num++, "XSEMI");
3262 break;
3263 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3264 _print_next_block(par_num++, "DOORBELLQ");
3265 break;
3266 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3267 _print_next_block(par_num++, "VAUX PCI CORE");
3268 break;
3269 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3270 _print_next_block(par_num++, "DEBUG");
3271 break;
3272 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3273 _print_next_block(par_num++, "USDM");
3274 break;
3275 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3276 _print_next_block(par_num++, "USEMI");
3277 break;
3278 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3279 _print_next_block(par_num++, "UPB");
3280 break;
3281 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3282 _print_next_block(par_num++, "CSDM");
3283 break;
3284 }
3285
3286 /* Clear the bit */
3287 sig &= ~cur_bit;
3288 }
3289 }
3290
3291 return par_num;
3292}
3293
3294static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3295{
3296 int i = 0;
3297 u32 cur_bit = 0;
3298 for (i = 0; sig; i++) {
3299 cur_bit = ((u32)0x1 << i);
3300 if (sig & cur_bit) {
3301 switch (cur_bit) {
3302 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3303 _print_next_block(par_num++, "CSEMI");
3304 break;
3305 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3306 _print_next_block(par_num++, "PXP");
3307 break;
3308 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3309 _print_next_block(par_num++,
3310 "PXPPCICLOCKCLIENT");
3311 break;
3312 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3313 _print_next_block(par_num++, "CFC");
3314 break;
3315 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3316 _print_next_block(par_num++, "CDU");
3317 break;
3318 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3319 _print_next_block(par_num++, "IGU");
3320 break;
3321 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3322 _print_next_block(par_num++, "MISC");
3323 break;
3324 }
3325
3326 /* Clear the bit */
3327 sig &= ~cur_bit;
3328 }
3329 }
3330
3331 return par_num;
3332}
3333
3334static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3335{
3336 int i = 0;
3337 u32 cur_bit = 0;
3338 for (i = 0; sig; i++) {
3339 cur_bit = ((u32)0x1 << i);
3340 if (sig & cur_bit) {
3341 switch (cur_bit) {
3342 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3343 _print_next_block(par_num++, "MCP ROM");
3344 break;
3345 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3346 _print_next_block(par_num++, "MCP UMP RX");
3347 break;
3348 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3349 _print_next_block(par_num++, "MCP UMP TX");
3350 break;
3351 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3352 _print_next_block(par_num++, "MCP SCPAD");
3353 break;
3354 }
3355
3356 /* Clear the bit */
3357 sig &= ~cur_bit;
3358 }
3359 }
3360
3361 return par_num;
3362}
3363
3364static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3365 u32 sig2, u32 sig3)
3366{
3367 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3368 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3369 int par_num = 0;
3370 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3371 "[0]:0x%08x [1]:0x%08x "
3372 "[2]:0x%08x [3]:0x%08x\n",
3373 sig0 & HW_PRTY_ASSERT_SET_0,
3374 sig1 & HW_PRTY_ASSERT_SET_1,
3375 sig2 & HW_PRTY_ASSERT_SET_2,
3376 sig3 & HW_PRTY_ASSERT_SET_3);
3377 printk(KERN_ERR"%s: Parity errors detected in blocks: ",
3378 bp->dev->name);
3379 par_num = bnx2x_print_blocks_with_parity0(
3380 sig0 & HW_PRTY_ASSERT_SET_0, par_num);
3381 par_num = bnx2x_print_blocks_with_parity1(
3382 sig1 & HW_PRTY_ASSERT_SET_1, par_num);
3383 par_num = bnx2x_print_blocks_with_parity2(
3384 sig2 & HW_PRTY_ASSERT_SET_2, par_num);
3385 par_num = bnx2x_print_blocks_with_parity3(
3386 sig3 & HW_PRTY_ASSERT_SET_3, par_num);
3387 printk("\n");
3388 return true;
3389 } else
3390 return false;
3391}
3392
9f6c9258 3393bool bnx2x_chk_parity_attn(struct bnx2x *bp)
877e9aa4 3394{
a2fbb9ea 3395 struct attn_route attn;
72fd0718
VZ		 3396 int port = BP_PORT(bp);
3397
3398 attn.sig[0] = REG_RD(bp,
3399 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3400 port*4);
3401 attn.sig[1] = REG_RD(bp,
3402 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3403 port*4);
3404 attn.sig[2] = REG_RD(bp,
3405 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3406 port*4);
3407 attn.sig[3] = REG_RD(bp,
3408 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3409 port*4);
3410
3411 return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
3412 attn.sig[3]);
3413}
3414
f2e0899f
DK		 3415
3416static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3417{
3418 u32 val;
3419 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3420
3421 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3422 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3423 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3424 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3425 "ADDRESS_ERROR\n");
3426 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3427 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3428 "INCORRECT_RCV_BEHAVIOR\n");
3429 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3430 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3431 "WAS_ERROR_ATTN\n");
3432 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3433 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3434 "VF_LENGTH_VIOLATION_ATTN\n");
3435 if (val &
3436 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3437 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3438 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3439 if (val &
3440 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3441 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3442 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3443 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3444 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3445 "TCPL_ERROR_ATTN\n");
3446 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3447 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3448 "TCPL_IN_TWO_RCBS_ATTN\n");
3449 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3450 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3451 "CSSNOOP_FIFO_OVERFLOW\n");
3452 }
3453 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3454 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3455 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3456 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3457 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3458 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3459 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3460 "_ATC_TCPL_TO_NOT_PEND\n");
3461 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3462 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3463 "ATC_GPA_MULTIPLE_HITS\n");
3464 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3465 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3466 "ATC_RCPL_TO_EMPTY_CNT\n");
3467 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3468 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3469 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3470 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3471 "ATC_IREQ_LESS_THAN_STU\n");
3472 }
3473
3474 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3475 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3476 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3477 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3478 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3479 }
3480
3481}
3482
72fd0718
VZ		 3483static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3484{
3485 struct attn_route attn, *group_mask;
34f80b04 3486 int port = BP_PORT(bp);
877e9aa4 3487 int index;
a2fbb9ea
ET		 3488 u32 reg_addr;
3489 u32 val;
3fcaf2e5 3490 u32 aeu_mask;
a2fbb9ea
ET		 3491
3492 /* need to take HW lock because MCP or other port might also
3493 try to handle this event */
4a37fb66 3494 bnx2x_acquire_alr(bp);
a2fbb9ea 3495
4a33bc03 3496 if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
72fd0718
VZ		 3497 bp->recovery_state = BNX2X_RECOVERY_INIT;
3498 bnx2x_set_reset_in_progress(bp);
3499 schedule_delayed_work(&bp->reset_task, 0);
3500 /* Disable HW interrupts */
3501 bnx2x_int_disable(bp);
3502 bnx2x_release_alr(bp);
3503 /* In case of parity errors don't handle attentions so that
3504 * other function would "see" parity errors.
3505 */
3506 return;
3507 }
3508
a2fbb9ea
ET		 3509 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3510 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3511 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3512 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
f2e0899f
DK		 3513 if (CHIP_IS_E2(bp))
3514 attn.sig[4] =
3515 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3516 else
3517 attn.sig[4] = 0;
3518
3519 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3520 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 3521
3522 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3523 if (deasserted & (1 << index)) {
72fd0718 3524 group_mask = &bp->attn_group[index];
a2fbb9ea 3525
f2e0899f
DK		 3526 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
3527 "%08x %08x %08x\n",
3528 index,
3529 group_mask->sig[0], group_mask->sig[1],
3530 group_mask->sig[2], group_mask->sig[3],
3531 group_mask->sig[4]);
a2fbb9ea 3532
f2e0899f
DK		 3533 bnx2x_attn_int_deasserted4(bp,
3534 attn.sig[4] & group_mask->sig[4]);
877e9aa4 3535 bnx2x_attn_int_deasserted3(bp,
72fd0718 3536 attn.sig[3] & group_mask->sig[3]);
877e9aa4 3537 bnx2x_attn_int_deasserted1(bp,
72fd0718 3538 attn.sig[1] & group_mask->sig[1]);
877e9aa4 3539 bnx2x_attn_int_deasserted2(bp,
72fd0718 3540 attn.sig[2] & group_mask->sig[2]);
877e9aa4 3541 bnx2x_attn_int_deasserted0(bp,
72fd0718 3542 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 3543 }
3544 }
3545
4a37fb66 3546 bnx2x_release_alr(bp);
a2fbb9ea 3547
f2e0899f
DK		 3548 if (bp->common.int_block == INT_BLOCK_HC)
3549 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3550 COMMAND_REG_ATTN_BITS_CLR);
3551 else
3552 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 3553
3554 val = ~deasserted;
f2e0899f
DK		 3555 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
3556 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 3557 REG_WR(bp, reg_addr, val);
a2fbb9ea 3558
a2fbb9ea 3559 if (~bp->attn_state & deasserted)
3fcaf2e5 3560 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 3561
3562 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3563 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3564
3fcaf2e5
EG		 3565 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3566 aeu_mask = REG_RD(bp, reg_addr);
3567
3568 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
3569 aeu_mask, deasserted);
72fd0718 3570 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 3571 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3572
3fcaf2e5
EG		 3573 REG_WR(bp, reg_addr, aeu_mask);
3574 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 3575
3576 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3577 bp->attn_state &= ~deasserted;
3578 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3579}
3580
3581static void bnx2x_attn_int(struct bnx2x *bp)
3582{
3583 /* read local copy of bits */
68d59484
EG		 3584 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
3585 attn_bits);
3586 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
3587 attn_bits_ack);
a2fbb9ea
ET		 3588 u32 attn_state = bp->attn_state;
3589
3590 /* look for changed bits */
3591 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
3592 u32 deasserted = ~attn_bits & attn_ack & attn_state;
3593
3594 DP(NETIF_MSG_HW,
3595 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
3596 attn_bits, attn_ack, asserted, deasserted);
3597
3598 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 3599 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 3600
3601 /* handle bits that were raised */
3602 if (asserted)
3603 bnx2x_attn_int_asserted(bp, asserted);
3604
3605 if (deasserted)
3606 bnx2x_attn_int_deasserted(bp, deasserted);
3607}
3608
523224a3
DK		 3609static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
3610{
3611 /* No memory barriers */
3612 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
3613 mmiowb(); /* keep prod updates ordered */
3614}
3615
3616#ifdef BCM_CNIC
3617static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
3618 union event_ring_elem *elem)
3619{
3620 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 3621 (cid < bp->cnic_eth_dev.starting_cid &&
3622 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 3623 return 1;
3624
3625 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
3626
3627 if (unlikely(elem->message.data.cfc_del_event.error)) {
3628 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
3629 cid);
3630 bnx2x_panic_dump(bp);
3631 }
3632 bnx2x_cnic_cfc_comp(bp, cid);
3633 return 0;
3634}
3635#endif
3636
3637static void bnx2x_eq_int(struct bnx2x *bp)
3638{
3639 u16 hw_cons, sw_cons, sw_prod;
3640 union event_ring_elem *elem;
3641 u32 cid;
3642 u8 opcode;
3643 int spqe_cnt = 0;
3644
3645 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
3646
3647 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
3648 * when we get the the next-page we nned to adjust so the loop
3649 * condition below will be met. The next element is the size of a
3650 * regular element and hence incrementing by 1
3651 */
3652 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
3653 hw_cons++;
3654
25985edc 3655 /* This function may never run in parallel with itself for a
523224a3
DK		 3656 * specific bp, thus there is no need in "paired" read memory
3657 * barrier here.
3658 */
3659 sw_cons = bp->eq_cons;
3660 sw_prod = bp->eq_prod;
3661
6e30dd4e
VZ		 3662 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",
3663 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 3664
3665 for (; sw_cons != hw_cons;
3666 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
3667
3668
3669 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
3670
3671 cid = SW_CID(elem->message.data.cfc_del_event.cid);
3672 opcode = elem->message.opcode;
3673
3674
3675 /* handle eq element */
3676 switch (opcode) {
3677 case EVENT_RING_OPCODE_STAT_QUERY:
3678 DP(NETIF_MSG_TIMER, "got statistics comp event\n");
3679 /* nothing to do with stats comp */
3680 continue;
3681
3682 case EVENT_RING_OPCODE_CFC_DEL:
3683 /* handle according to cid range */
3684 /*
3685 * we may want to verify here that the bp state is
3686 * HALTING
3687 */
3688 DP(NETIF_MSG_IFDOWN,
3689 "got delete ramrod for MULTI[%d]\n", cid);
3690#ifdef BCM_CNIC
3691 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
3692 goto next_spqe;
ec6ba945
VZ		 3693 if (cid == BNX2X_FCOE_ETH_CID)
3694 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
3695 else
523224a3 3696#endif
ec6ba945 3697 bnx2x_fp(bp, cid, state) =
523224a3
DK		 3698 BNX2X_FP_STATE_CLOSED;
3699
3700 goto next_spqe;
e4901dde
VZ		 3701
3702 case EVENT_RING_OPCODE_STOP_TRAFFIC:
3703 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
3704 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
3705 goto next_spqe;
3706 case EVENT_RING_OPCODE_START_TRAFFIC:
3707 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
3708 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
3709 goto next_spqe;
523224a3
DK		 3710 }
3711
3712 switch (opcode | bp->state) {
3713 case (EVENT_RING_OPCODE_FUNCTION_START |
3714 BNX2X_STATE_OPENING_WAIT4_PORT):
3715 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
3716 bp->state = BNX2X_STATE_FUNC_STARTED;
3717 break;
3718
3719 case (EVENT_RING_OPCODE_FUNCTION_STOP |
3720 BNX2X_STATE_CLOSING_WAIT4_HALT):
3721 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
3722 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
3723 break;
3724
3725 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
3726 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
3727 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
6e30dd4e
VZ		 3728 if (elem->message.data.set_mac_event.echo)
3729 bp->set_mac_pending = 0;
523224a3
DK		 3730 break;
3731
3732 case (EVENT_RING_OPCODE_SET_MAC |
3733 BNX2X_STATE_CLOSING_WAIT4_HALT):
3734 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
6e30dd4e
VZ		 3735 if (elem->message.data.set_mac_event.echo)
3736 bp->set_mac_pending = 0;
523224a3
DK		 3737 break;
3738 default:
3739 /* unknown event log error and continue */
3740 BNX2X_ERR("Unknown EQ event %d\n",
3741 elem->message.opcode);
3742 }
3743next_spqe:
3744 spqe_cnt++;
3745 } /* for */
3746
8fe23fbd 3747 smp_mb__before_atomic_inc();
6e30dd4e 3748 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 3749
3750 bp->eq_cons = sw_cons;
3751 bp->eq_prod = sw_prod;
3752 /* Make sure that above mem writes were issued towards the memory */
3753 smp_wmb();
3754
3755 /* update producer */
3756 bnx2x_update_eq_prod(bp, bp->eq_prod);
3757}
3758
a2fbb9ea
ET		 3759static void bnx2x_sp_task(struct work_struct *work)
3760{
1cf167f2 3761 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea
ET		 3762 u16 status;
3763
a2fbb9ea 3764 status = bnx2x_update_dsb_idx(bp);
34f80b04
EG		 3765/* if (status == 0) */
3766/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
a2fbb9ea 3767
cdaa7cb8 3768 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
a2fbb9ea 3769
877e9aa4 3770 /* HW attentions */
523224a3 3771 if (status & BNX2X_DEF_SB_ATT_IDX) {
a2fbb9ea 3772 bnx2x_attn_int(bp);
523224a3 3773 status &= ~BNX2X_DEF_SB_ATT_IDX;
cdaa7cb8
VZ		 3774 }
3775
523224a3
DK		 3776 /* SP events: STAT_QUERY and others */
3777 if (status & BNX2X_DEF_SB_IDX) {
ec6ba945
VZ		 3778#ifdef BCM_CNIC
3779 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 3780
ec6ba945
VZ		 3781 if ((!NO_FCOE(bp)) &&
3782 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
3783 napi_schedule(&bnx2x_fcoe(bp, napi));
3784#endif
523224a3
DK		 3785 /* Handle EQ completions */
3786 bnx2x_eq_int(bp);
3787
3788 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
3789 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
3790
3791 status &= ~BNX2X_DEF_SB_IDX;
cdaa7cb8
VZ		 3792 }
3793
3794 if (unlikely(status))
3795 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
3796 status);
a2fbb9ea 3797
523224a3
DK		 3798 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
3799 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
a2fbb9ea
ET		 3800}
3801
9f6c9258 3802irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 3803{
3804 struct net_device *dev = dev_instance;
3805 struct bnx2x *bp = netdev_priv(dev);
3806
523224a3
DK		 3807 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
3808 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 3809
3810#ifdef BNX2X_STOP_ON_ERROR
3811 if (unlikely(bp->panic))
3812 return IRQ_HANDLED;
3813#endif
3814
993ac7b5
MC		 3815#ifdef BCM_CNIC
3816 {
3817 struct cnic_ops *c_ops;
3818
3819 rcu_read_lock();
3820 c_ops = rcu_dereference(bp->cnic_ops);
3821 if (c_ops)
3822 c_ops->cnic_handler(bp->cnic_data, NULL);
3823 rcu_read_unlock();
3824 }
3825#endif
1cf167f2 3826 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 3827
3828 return IRQ_HANDLED;
3829}
3830
3831/* end of slow path */
3832
a2fbb9ea
ET		 3833static void bnx2x_timer(unsigned long data)
3834{
3835 struct bnx2x *bp = (struct bnx2x *) data;
3836
3837 if (!netif_running(bp->dev))
3838 return;
3839
a2fbb9ea
ET		 3840 if (poll) {
3841 struct bnx2x_fastpath *fp = &bp->fp[0];
a2fbb9ea 3842
7961f791 3843 bnx2x_tx_int(fp);
b8ee8328 3844 bnx2x_rx_int(fp, 1000);
a2fbb9ea
ET		 3845 }
3846
34f80b04 3847 if (!BP_NOMCP(bp)) {
f2e0899f 3848 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 3849 u32 drv_pulse;
3850 u32 mcp_pulse;
3851
3852 ++bp->fw_drv_pulse_wr_seq;
3853 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3854 /* TBD - add SYSTEM_TIME */
3855 drv_pulse = bp->fw_drv_pulse_wr_seq;
f2e0899f 3856 SHMEM_WR(bp, func_mb[mb_idx].drv_pulse_mb, drv_pulse);
a2fbb9ea 3857
f2e0899f 3858 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 3859 MCP_PULSE_SEQ_MASK);
3860 /* The delta between driver pulse and mcp response
3861 * should be 1 (before mcp response) or 0 (after mcp response)
3862 */
3863 if ((drv_pulse != mcp_pulse) &&
3864 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3865 /* someone lost a heartbeat... */
3866 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3867 drv_pulse, mcp_pulse);
3868 }
3869 }
3870
f34d28ea 3871 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 3872 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 3873
a2fbb9ea
ET		 3874 mod_timer(&bp->timer, jiffies + bp->current_interval);
3875}
3876
3877/* end of Statistics */
3878
3879/* nic init */
3880
3881/*
3882 * nic init service functions
3883 */
3884
523224a3 3885static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 3886{
523224a3
DK		 3887 u32 i;
3888 if (!(len%4) && !(addr%4))
3889 for (i = 0; i < len; i += 4)
3890 REG_WR(bp, addr + i, fill);
3891 else
3892 for (i = 0; i < len; i++)
3893 REG_WR8(bp, addr + i, fill);
34f80b04 3894
34f80b04
EG		 3895}
3896
523224a3
DK		 3897/* helper: writes FP SP data to FW - data_size in dwords */
3898static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
3899 int fw_sb_id,
3900 u32 *sb_data_p,
3901 u32 data_size)
34f80b04 3902{
a2fbb9ea 3903 int index;
523224a3
DK		 3904 for (index = 0; index < data_size; index++)
3905 REG_WR(bp, BAR_CSTRORM_INTMEM +
3906 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
3907 sizeof(u32)*index,
3908 *(sb_data_p + index));
3909}
a2fbb9ea 3910
523224a3
DK		 3911static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
3912{
3913 u32 *sb_data_p;
3914 u32 data_size = 0;
f2e0899f 3915 struct hc_status_block_data_e2 sb_data_e2;
523224a3 3916 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 3917
523224a3 3918 /* disable the function first */
f2e0899f
DK		 3919 if (CHIP_IS_E2(bp)) {
3920 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
3921 sb_data_e2.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3922 sb_data_e2.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3923 sb_data_e2.common.p_func.vf_valid = false;
3924 sb_data_p = (u32 *)&sb_data_e2;
3925 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
3926 } else {
3927 memset(&sb_data_e1x, 0,
3928 sizeof(struct hc_status_block_data_e1x));
3929 sb_data_e1x.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3930 sb_data_e1x.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3931 sb_data_e1x.common.p_func.vf_valid = false;
3932 sb_data_p = (u32 *)&sb_data_e1x;
3933 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
3934 }
523224a3 3935 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 3936
523224a3
DK		 3937 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3938 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
3939 CSTORM_STATUS_BLOCK_SIZE);
3940 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3941 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
3942 CSTORM_SYNC_BLOCK_SIZE);
3943}
34f80b04 3944
523224a3
DK		 3945/* helper: writes SP SB data to FW */
3946static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
3947 struct hc_sp_status_block_data *sp_sb_data)
3948{
3949 int func = BP_FUNC(bp);
3950 int i;
3951 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
3952 REG_WR(bp, BAR_CSTRORM_INTMEM +
3953 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
3954 i*sizeof(u32),
3955 *((u32 *)sp_sb_data + i));
34f80b04
EG		 3956}
3957
523224a3 3958static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 3959{
3960 int func = BP_FUNC(bp);
523224a3
DK		 3961 struct hc_sp_status_block_data sp_sb_data;
3962 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 3963
523224a3
DK		 3964 sp_sb_data.p_func.pf_id = HC_FUNCTION_DISABLED;
3965 sp_sb_data.p_func.vf_id = HC_FUNCTION_DISABLED;
3966 sp_sb_data.p_func.vf_valid = false;
3967
3968 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
3969
3970 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3971 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
3972 CSTORM_SP_STATUS_BLOCK_SIZE);
3973 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3974 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
3975 CSTORM_SP_SYNC_BLOCK_SIZE);
3976
3977}
3978
3979
3980static inline
3981void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
3982 int igu_sb_id, int igu_seg_id)
3983{
3984 hc_sm->igu_sb_id = igu_sb_id;
3985 hc_sm->igu_seg_id = igu_seg_id;
3986 hc_sm->timer_value = 0xFF;
3987 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 3988}
3989
8d96286a 3990static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 3991 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 3992{
523224a3
DK		 3993 int igu_seg_id;
3994
f2e0899f 3995 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 3996 struct hc_status_block_data_e1x sb_data_e1x;
3997 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 3998 int data_size;
3999 u32 *sb_data_p;
4000
f2e0899f
DK		 4001 if (CHIP_INT_MODE_IS_BC(bp))
4002 igu_seg_id = HC_SEG_ACCESS_NORM;
4003 else
4004 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 4005
4006 bnx2x_zero_fp_sb(bp, fw_sb_id);
4007
f2e0899f
DK		 4008 if (CHIP_IS_E2(bp)) {
4009 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4010 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4011 sb_data_e2.common.p_func.vf_id = vfid;
4012 sb_data_e2.common.p_func.vf_valid = vf_valid;
4013 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4014 sb_data_e2.common.same_igu_sb_1b = true;
4015 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4016 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4017 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 4018 sb_data_p = (u32 *)&sb_data_e2;
4019 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4020 } else {
4021 memset(&sb_data_e1x, 0,
4022 sizeof(struct hc_status_block_data_e1x));
4023 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4024 sb_data_e1x.common.p_func.vf_id = 0xff;
4025 sb_data_e1x.common.p_func.vf_valid = false;
4026 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4027 sb_data_e1x.common.same_igu_sb_1b = true;
4028 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4029 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4030 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 4031 sb_data_p = (u32 *)&sb_data_e1x;
4032 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4033 }
523224a3
DK		 4034
4035 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4036 igu_sb_id, igu_seg_id);
4037 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4038 igu_sb_id, igu_seg_id);
4039
4040 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4041
4042 /* write indecies to HW */
4043 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4044}
4045
4046static void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u16 fw_sb_id,
4047 u8 sb_index, u8 disable, u16 usec)
4048{
4049 int port = BP_PORT(bp);
4050 u8 ticks = usec / BNX2X_BTR;
4051
4052 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4053
4054 disable = disable ? 1 : (usec ? 0 : 1);
4055 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4056}
4057
4058static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u16 fw_sb_id,
4059 u16 tx_usec, u16 rx_usec)
4060{
4061 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4062 false, rx_usec);
4063 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4064 false, tx_usec);
4065}
f2e0899f 4066
523224a3
DK		 4067static void bnx2x_init_def_sb(struct bnx2x *bp)
4068{
4069 struct host_sp_status_block *def_sb = bp->def_status_blk;
4070 dma_addr_t mapping = bp->def_status_blk_mapping;
4071 int igu_sp_sb_index;
4072 int igu_seg_id;
34f80b04
EG		 4073 int port = BP_PORT(bp);
4074 int func = BP_FUNC(bp);
523224a3 4075 int reg_offset;
a2fbb9ea 4076 u64 section;
523224a3
DK		 4077 int index;
4078 struct hc_sp_status_block_data sp_sb_data;
4079 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4080
f2e0899f
DK		 4081 if (CHIP_INT_MODE_IS_BC(bp)) {
4082 igu_sp_sb_index = DEF_SB_IGU_ID;
4083 igu_seg_id = HC_SEG_ACCESS_DEF;
4084 } else {
4085 igu_sp_sb_index = bp->igu_dsb_id;
4086 igu_seg_id = IGU_SEG_ACCESS_DEF;
4087 }
a2fbb9ea
ET		 4088
4089 /* ATTN */
523224a3 4090 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 4091 atten_status_block);
523224a3 4092 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 4093
49d66772
ET		 4094 bp->attn_state = 0;
4095
a2fbb9ea
ET		 4096 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4097 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
34f80b04 4098 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 4099 int sindex;
4100 /* take care of sig[0]..sig[4] */
4101 for (sindex = 0; sindex < 4; sindex++)
4102 bp->attn_group[index].sig[sindex] =
4103 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f
DK		 4104
4105 if (CHIP_IS_E2(bp))
4106 /*
4107 * enable5 is separate from the rest of the registers,
4108 * and therefore the address skip is 4
4109 * and not 16 between the different groups
4110 */
4111 bp->attn_group[index].sig[4] = REG_RD(bp,
4112 reg_offset + 0x10 + 0x4*index);
4113 else
4114 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 4115 }
4116
f2e0899f
DK		 4117 if (bp->common.int_block == INT_BLOCK_HC) {
4118 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4119 HC_REG_ATTN_MSG0_ADDR_L);
4120
4121 REG_WR(bp, reg_offset, U64_LO(section));
4122 REG_WR(bp, reg_offset + 4, U64_HI(section));
4123 } else if (CHIP_IS_E2(bp)) {
4124 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4125 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4126 }
a2fbb9ea 4127
523224a3
DK		 4128 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4129 sp_sb);
a2fbb9ea 4130
523224a3 4131 bnx2x_zero_sp_sb(bp);
a2fbb9ea 4132
523224a3
DK		 4133 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4134 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4135 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4136 sp_sb_data.igu_seg_id = igu_seg_id;
4137 sp_sb_data.p_func.pf_id = func;
f2e0899f 4138 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 4139 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 4140
523224a3 4141 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 4142
bb2a0f7a 4143 bp->stats_pending = 0;
66e855f3 4144 bp->set_mac_pending = 0;
bb2a0f7a 4145
523224a3 4146 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 4147}
4148
9f6c9258 4149void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 4150{
a2fbb9ea
ET		 4151 int i;
4152
ec6ba945 4153 for_each_eth_queue(bp, i)
523224a3 4154 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 4155 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 4156}
4157
a2fbb9ea
ET		 4158static void bnx2x_init_sp_ring(struct bnx2x *bp)
4159{
a2fbb9ea 4160 spin_lock_init(&bp->spq_lock);
6e30dd4e 4161 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 4162
a2fbb9ea 4163 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 4164 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4165 bp->spq_prod_bd = bp->spq;
4166 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 4167}
4168
523224a3 4169static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 4170{
4171 int i;
523224a3
DK		 4172 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4173 union event_ring_elem *elem =
4174 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 4175
523224a3
DK		 4176 elem->next_page.addr.hi =
4177 cpu_to_le32(U64_HI(bp->eq_mapping +
4178 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4179 elem->next_page.addr.lo =
4180 cpu_to_le32(U64_LO(bp->eq_mapping +
4181 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 4182 }
523224a3
DK		 4183 bp->eq_cons = 0;
4184 bp->eq_prod = NUM_EQ_DESC;
4185 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6e30dd4e
VZ		 4186 /* we want a warning message before it gets rought... */
4187 atomic_set(&bp->eq_spq_left,
4188 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 4189}
4190
ab532cf3 4191void bnx2x_push_indir_table(struct bnx2x *bp)
a2fbb9ea 4192{
26c8fa4d 4193 int func = BP_FUNC(bp);
a2fbb9ea
ET		 4194 int i;
4195
555f6c78 4196 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
a2fbb9ea
ET		 4197 return;
4198
4199 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
34f80b04 4200 REG_WR8(bp, BAR_TSTRORM_INTMEM +
26c8fa4d 4201 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
ab532cf3
TH		 4202 bp->fp->cl_id + bp->rx_indir_table[i]);
4203}
4204
4205static void bnx2x_init_ind_table(struct bnx2x *bp)
4206{
4207 int i;
4208
4209 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4210 bp->rx_indir_table[i] = i % BNX2X_NUM_ETH_QUEUES(bp);
4211
4212 bnx2x_push_indir_table(bp);
a2fbb9ea
ET		 4213}
4214
9f6c9258 4215void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
a2fbb9ea 4216{
34f80b04 4217 int mode = bp->rx_mode;
ec6ba945 4218 int port = BP_PORT(bp);
523224a3 4219 u16 cl_id;
ec6ba945 4220 u32 def_q_filters = 0;
523224a3 4221
581ce43d
EG		 4222 /* All but management unicast packets should pass to the host as well */
4223 u32 llh_mask =
4224 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
4225 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
4226 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
4227 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
a2fbb9ea 4228
a2fbb9ea
ET		 4229 switch (mode) {
4230 case BNX2X_RX_MODE_NONE: /* no Rx */
ec6ba945
VZ		 4231 def_q_filters = BNX2X_ACCEPT_NONE;
4232#ifdef BCM_CNIC
4233 if (!NO_FCOE(bp)) {
4234 cl_id = bnx2x_fcoe(bp, cl_id);
4235 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4236 }
4237#endif
a2fbb9ea 4238 break;
356e2385 4239
a2fbb9ea 4240 case BNX2X_RX_MODE_NORMAL:
ec6ba945
VZ		 4241 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4242 BNX2X_ACCEPT_MULTICAST;
4243#ifdef BCM_CNIC
711c9146
VZ		 4244 if (!NO_FCOE(bp)) {
4245 cl_id = bnx2x_fcoe(bp, cl_id);
4246 bnx2x_rxq_set_mac_filters(bp, cl_id,
4247 BNX2X_ACCEPT_UNICAST |
4248 BNX2X_ACCEPT_MULTICAST);
4249 }
ec6ba945 4250#endif
a2fbb9ea 4251 break;
356e2385 4252
a2fbb9ea 4253 case BNX2X_RX_MODE_ALLMULTI:
ec6ba945
VZ		 4254 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4255 BNX2X_ACCEPT_ALL_MULTICAST;
4256#ifdef BCM_CNIC
711c9146
VZ		 4257 /*
4258 * Prevent duplication of multicast packets by configuring FCoE
4259 * L2 Client to receive only matched unicast frames.
4260 */
4261 if (!NO_FCOE(bp)) {
4262 cl_id = bnx2x_fcoe(bp, cl_id);
4263 bnx2x_rxq_set_mac_filters(bp, cl_id,
4264 BNX2X_ACCEPT_UNICAST);
4265 }
ec6ba945 4266#endif
a2fbb9ea 4267 break;
356e2385 4268
a2fbb9ea 4269 case BNX2X_RX_MODE_PROMISC:
ec6ba945
VZ		 4270 def_q_filters |= BNX2X_PROMISCUOUS_MODE;
4271#ifdef BCM_CNIC
711c9146
VZ		 4272 /*
4273 * Prevent packets duplication by configuring DROP_ALL for FCoE
4274 * L2 Client.
4275 */
4276 if (!NO_FCOE(bp)) {
4277 cl_id = bnx2x_fcoe(bp, cl_id);
4278 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4279 }
ec6ba945 4280#endif
581ce43d
EG		 4281 /* pass management unicast packets as well */
4282 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
a2fbb9ea 4283 break;
356e2385 4284
a2fbb9ea 4285 default:
34f80b04
EG		 4286 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4287 break;
a2fbb9ea
ET		 4288 }
4289
ec6ba945
VZ		 4290 cl_id = BP_L_ID(bp);
4291 bnx2x_rxq_set_mac_filters(bp, cl_id, def_q_filters);
4292
581ce43d 4293 REG_WR(bp,
ec6ba945
VZ		 4294 (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
4295 NIG_REG_LLH0_BRB1_DRV_MASK), llh_mask);
581ce43d 4296
523224a3
DK		 4297 DP(NETIF_MSG_IFUP, "rx mode %d\n"
4298 "drop_ucast 0x%x\ndrop_mcast 0x%x\ndrop_bcast 0x%x\n"
ec6ba945
VZ		 4299 "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n"
4300 "unmatched_ucast 0x%x\n", mode,
523224a3
DK		 4301 bp->mac_filters.ucast_drop_all,
4302 bp->mac_filters.mcast_drop_all,
4303 bp->mac_filters.bcast_drop_all,
4304 bp->mac_filters.ucast_accept_all,
4305 bp->mac_filters.mcast_accept_all,
ec6ba945
VZ		 4306 bp->mac_filters.bcast_accept_all,
4307 bp->mac_filters.unmatched_unicast
523224a3 4308 );
a2fbb9ea 4309
523224a3 4310 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
a2fbb9ea
ET		 4311}
4312
471de716
EG		 4313static void bnx2x_init_internal_common(struct bnx2x *bp)
4314{
4315 int i;
4316
523224a3 4317 if (!CHIP_IS_E1(bp)) {
de832a55 4318
523224a3
DK		 4319 /* xstorm needs to know whether to add ovlan to packets or not,
4320 * in switch-independent we'll write 0 to here... */
34f80b04 4321 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4322 bp->mf_mode);
34f80b04 4323 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4324 bp->mf_mode);
34f80b04 4325 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4326 bp->mf_mode);
34f80b04 4327 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4328 bp->mf_mode);
34f80b04
EG		 4329 }
4330
0793f83f
DK		 4331 if (IS_MF_SI(bp))
4332 /*
4333 * In switch independent mode, the TSTORM needs to accept
4334 * packets that failed classification, since approximate match
4335 * mac addresses aren't written to NIG LLH
4336 */
4337 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4338 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
4339
523224a3
DK		 4340 /* Zero this manually as its initialization is
4341 currently missing in the initTool */
4342 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 4343 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 4344 USTORM_AGG_DATA_OFFSET + i * 4, 0);
f2e0899f
DK		 4345 if (CHIP_IS_E2(bp)) {
4346 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4347 CHIP_INT_MODE_IS_BC(bp) ?
4348 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4349 }
523224a3 4350}
8a1c38d1 4351
523224a3
DK		 4352static void bnx2x_init_internal_port(struct bnx2x *bp)
4353{
4354 /* port */
e4901dde 4355 bnx2x_dcb_init_intmem_pfc(bp);
a2fbb9ea
ET		 4356}
4357
471de716
EG		 4358static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4359{
4360 switch (load_code) {
4361 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 4362 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 4363 bnx2x_init_internal_common(bp);
4364 /* no break */
4365
4366 case FW_MSG_CODE_DRV_LOAD_PORT:
4367 bnx2x_init_internal_port(bp);
4368 /* no break */
4369
4370 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 4371 /* internal memory per function is
4372 initialized inside bnx2x_pf_init */
471de716
EG		 4373 break;
4374
4375 default:
4376 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4377 break;
4378 }
4379}
4380
523224a3
DK		 4381static void bnx2x_init_fp_sb(struct bnx2x *bp, int fp_idx)
4382{
4383 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4384
4385 fp->state = BNX2X_FP_STATE_CLOSED;
4386
b3b83c3f 4387 fp->cid = fp_idx;
523224a3
DK		 4388 fp->cl_id = BP_L_ID(bp) + fp_idx;
4389 fp->fw_sb_id = bp->base_fw_ndsb + fp->cl_id + CNIC_CONTEXT_USE;
4390 fp->igu_sb_id = bp->igu_base_sb + fp_idx + CNIC_CONTEXT_USE;
4391 /* qZone id equals to FW (per path) client id */
4392 fp->cl_qzone_id = fp->cl_id +
f2e0899f
DK		 4393 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
4394 ETH_MAX_RX_CLIENTS_E1H);
523224a3 4395 /* init shortcut */
f2e0899f
DK		 4396 fp->ustorm_rx_prods_offset = CHIP_IS_E2(bp) ?
4397 USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id) :
523224a3
DK		 4398 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
4399 /* Setup SB indicies */
4400 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4401 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4402
4403 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
4404 "cl_id %d fw_sb %d igu_sb %d\n",
4405 fp_idx, bp, fp->status_blk.e1x_sb, fp->cl_id, fp->fw_sb_id,
4406 fp->igu_sb_id);
4407 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
4408 fp->fw_sb_id, fp->igu_sb_id);
4409
4410 bnx2x_update_fpsb_idx(fp);
4411}
4412
9f6c9258 4413void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
a2fbb9ea
ET		 4414{
4415 int i;
4416
ec6ba945 4417 for_each_eth_queue(bp, i)
523224a3 4418 bnx2x_init_fp_sb(bp, i);
37b091ba 4419#ifdef BCM_CNIC
ec6ba945
VZ		 4420 if (!NO_FCOE(bp))
4421 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 4422
4423 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
4424 BNX2X_VF_ID_INVALID, false,
4425 CNIC_SB_ID(bp), CNIC_IGU_SB_ID(bp));
4426
37b091ba 4427#endif
a2fbb9ea 4428
020c7e3f
YR		 4429 /* Initialize MOD_ABS interrupts */
4430 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
4431 bp->common.shmem_base, bp->common.shmem2_base,
4432 BP_PORT(bp));
16119785
EG		 4433 /* ensure status block indices were read */
4434 rmb();
4435
523224a3 4436 bnx2x_init_def_sb(bp);
5c862848 4437 bnx2x_update_dsb_idx(bp);
a2fbb9ea 4438 bnx2x_init_rx_rings(bp);
523224a3 4439 bnx2x_init_tx_rings(bp);
a2fbb9ea 4440 bnx2x_init_sp_ring(bp);
523224a3 4441 bnx2x_init_eq_ring(bp);
471de716 4442 bnx2x_init_internal(bp, load_code);
523224a3 4443 bnx2x_pf_init(bp);
a2fbb9ea 4444 bnx2x_init_ind_table(bp);
0ef00459
EG		 4445 bnx2x_stats_init(bp);
4446
0ef00459
EG		 4447 /* flush all before enabling interrupts */
4448 mb();
4449 mmiowb();
4450
615f8fd9 4451 bnx2x_int_enable(bp);
eb8da205
EG		 4452
4453 /* Check for SPIO5 */
4454 bnx2x_attn_int_deasserted0(bp,
4455 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
4456 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 4457}
4458
4459/* end of nic init */
4460
4461/*
4462 * gzip service functions
4463 */
4464
4465static int bnx2x_gunzip_init(struct bnx2x *bp)
4466{
1a983142
FT		 4467 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
4468 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 4469 if (bp->gunzip_buf == NULL)
4470 goto gunzip_nomem1;
4471
4472 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4473 if (bp->strm == NULL)
4474 goto gunzip_nomem2;
4475
4476 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4477 GFP_KERNEL);
4478 if (bp->strm->workspace == NULL)
4479 goto gunzip_nomem3;
4480
4481 return 0;
4482
4483gunzip_nomem3:
4484 kfree(bp->strm);
4485 bp->strm = NULL;
4486
4487gunzip_nomem2:
1a983142
FT		 4488 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4489 bp->gunzip_mapping);
a2fbb9ea
ET		 4490 bp->gunzip_buf = NULL;
4491
4492gunzip_nomem1:
cdaa7cb8
VZ		 4493 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
4494 " un-compression\n");
a2fbb9ea
ET		 4495 return -ENOMEM;
4496}
4497
4498static void bnx2x_gunzip_end(struct bnx2x *bp)
4499{
b3b83c3f
DK		 4500 if (bp->strm) {
4501 kfree(bp->strm->workspace);
4502 kfree(bp->strm);
4503 bp->strm = NULL;
4504 }
a2fbb9ea
ET		 4505
4506 if (bp->gunzip_buf) {
1a983142
FT		 4507 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4508 bp->gunzip_mapping);
a2fbb9ea
ET		 4509 bp->gunzip_buf = NULL;
4510 }
4511}
4512
94a78b79 4513static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 4514{
4515 int n, rc;
4516
4517 /* check gzip header */
94a78b79
VZ		 4518 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
4519 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 4520 return -EINVAL;
94a78b79 4521 }
a2fbb9ea
ET		 4522
4523 n = 10;
4524
34f80b04 4525#define FNAME 0x8
a2fbb9ea
ET		 4526
4527 if (zbuf[3] & FNAME)
4528 while ((zbuf[n++] != 0) && (n < len));
4529
94a78b79 4530 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 4531 bp->strm->avail_in = len - n;
4532 bp->strm->next_out = bp->gunzip_buf;
4533 bp->strm->avail_out = FW_BUF_SIZE;
4534
4535 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4536 if (rc != Z_OK)
4537 return rc;
4538
4539 rc = zlib_inflate(bp->strm, Z_FINISH);
4540 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 4541 netdev_err(bp->dev, "Firmware decompression error: %s\n",
4542 bp->strm->msg);
a2fbb9ea
ET		 4543
4544 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4545 if (bp->gunzip_outlen & 0x3)
cdaa7cb8
VZ		 4546 netdev_err(bp->dev, "Firmware decompression error:"
4547 " gunzip_outlen (%d) not aligned\n",
4548 bp->gunzip_outlen);
a2fbb9ea
ET		 4549 bp->gunzip_outlen >>= 2;
4550
4551 zlib_inflateEnd(bp->strm);
4552
4553 if (rc == Z_STREAM_END)
4554 return 0;
4555
4556 return rc;
4557}
4558
4559/* nic load/unload */
4560
4561/*
34f80b04 4562 * General service functions
a2fbb9ea
ET		 4563 */
4564
4565/* send a NIG loopback debug packet */
4566static void bnx2x_lb_pckt(struct bnx2x *bp)
4567{
a2fbb9ea 4568 u32 wb_write[3];
a2fbb9ea
ET		 4569
4570 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 4571 wb_write[0] = 0x55555555;
4572 wb_write[1] = 0x55555555;
34f80b04 4573 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 4574 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 4575
4576 /* NON-IP protocol */
a2fbb9ea
ET		 4577 wb_write[0] = 0x09000000;
4578 wb_write[1] = 0x55555555;
34f80b04 4579 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 4580 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 4581}
4582
4583/* some of the internal memories
4584 * are not directly readable from the driver
4585 * to test them we send debug packets
4586 */
4587static int bnx2x_int_mem_test(struct bnx2x *bp)
4588{
4589 int factor;
4590 int count, i;
4591 u32 val = 0;
4592
ad8d3948 4593 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 4594 factor = 120;
ad8d3948
EG		 4595 else if (CHIP_REV_IS_EMUL(bp))
4596 factor = 200;
4597 else
a2fbb9ea 4598 factor = 1;
a2fbb9ea 4599
a2fbb9ea
ET		 4600 /* Disable inputs of parser neighbor blocks */
4601 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4602 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4603 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 4604 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 4605
4606 /* Write 0 to parser credits for CFC search request */
4607 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4608
4609 /* send Ethernet packet */
4610 bnx2x_lb_pckt(bp);
4611
4612 /* TODO do i reset NIG statistic? */
4613 /* Wait until NIG register shows 1 packet of size 0x10 */
4614 count = 1000 * factor;
4615 while (count) {
34f80b04 4616
a2fbb9ea
ET		 4617 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4618 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 4619 if (val == 0x10)
4620 break;
4621
4622 msleep(10);
4623 count--;
4624 }
4625 if (val != 0x10) {
4626 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4627 return -1;
4628 }
4629
4630 /* Wait until PRS register shows 1 packet */
4631 count = 1000 * factor;
4632 while (count) {
4633 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 4634 if (val == 1)
4635 break;
4636
4637 msleep(10);
4638 count--;
4639 }
4640 if (val != 0x1) {
4641 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4642 return -2;
4643 }
4644
4645 /* Reset and init BRB, PRS */
34f80b04 4646 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 4647 msleep(50);
34f80b04 4648 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 4649 msleep(50);
94a78b79
VZ		 4650 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4651 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
a2fbb9ea
ET		 4652
4653 DP(NETIF_MSG_HW, "part2\n");
4654
4655 /* Disable inputs of parser neighbor blocks */
4656 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4657 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4658 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 4659 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 4660
4661 /* Write 0 to parser credits for CFC search request */
4662 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4663
4664 /* send 10 Ethernet packets */
4665 for (i = 0; i < 10; i++)
4666 bnx2x_lb_pckt(bp);
4667
4668 /* Wait until NIG register shows 10 + 1
4669 packets of size 11*0x10 = 0xb0 */
4670 count = 1000 * factor;
4671 while (count) {
34f80b04 4672
a2fbb9ea
ET		 4673 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4674 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 4675 if (val == 0xb0)
4676 break;
4677
4678 msleep(10);
4679 count--;
4680 }
4681 if (val != 0xb0) {
4682 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4683 return -3;
4684 }
4685
4686 /* Wait until PRS register shows 2 packets */
4687 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4688 if (val != 2)
4689 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4690
4691 /* Write 1 to parser credits for CFC search request */
4692 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
4693
4694 /* Wait until PRS register shows 3 packets */
4695 msleep(10 * factor);
4696 /* Wait until NIG register shows 1 packet of size 0x10 */
4697 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4698 if (val != 3)
4699 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4700
4701 /* clear NIG EOP FIFO */
4702 for (i = 0; i < 11; i++)
4703 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
4704 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
4705 if (val != 1) {
4706 BNX2X_ERR("clear of NIG failed\n");
4707 return -4;
4708 }
4709
4710 /* Reset and init BRB, PRS, NIG */
4711 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4712 msleep(50);
4713 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4714 msleep(50);
94a78b79
VZ		 4715 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4716 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
37b091ba 4717#ifndef BCM_CNIC
a2fbb9ea
ET		 4718 /* set NIC mode */
4719 REG_WR(bp, PRS_REG_NIC_MODE, 1);
4720#endif
4721
4722 /* Enable inputs of parser neighbor blocks */
4723 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
4724 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
4725 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 4726 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 4727
4728 DP(NETIF_MSG_HW, "done\n");
4729
4730 return 0; /* OK */
4731}
4732
4a33bc03 4733static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea
ET		 4734{
4735 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
f2e0899f
DK		 4736 if (CHIP_IS_E2(bp))
4737 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
4738 else
4739 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 4740 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
4741 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 4742 /*
4743 * mask read length error interrupts in brb for parser
4744 * (parsing unit and 'checksum and crc' unit)
4745 * these errors are legal (PU reads fixed length and CAC can cause
4746 * read length error on truncated packets)
4747 */
4748 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 4749 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
4750 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
4751 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
4752 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
4753 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 4754/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
4755/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4756 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
4757 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
4758 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 4759/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
4760/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4761 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
4762 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
4763 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
4764 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 4765/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
4766/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 4767
34f80b04
EG		 4768 if (CHIP_REV_IS_FPGA(bp))
4769 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
f2e0899f
DK		 4770 else if (CHIP_IS_E2(bp))
4771 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
4772 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
4773 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
4774 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
4775 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
4776 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
34f80b04
EG		 4777 else
4778 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
a2fbb9ea
ET		 4779 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
4780 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
4781 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04
EG		 4782/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
4783/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4784 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
4785 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 4786/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 4787 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 4788}
4789
81f75bbf
EG		 4790static void bnx2x_reset_common(struct bnx2x *bp)
4791{
4792 /* reset_common */
4793 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
4794 0xd3ffff7f);
4795 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
4796}
4797
573f2035
EG		 4798static void bnx2x_init_pxp(struct bnx2x *bp)
4799{
4800 u16 devctl;
4801 int r_order, w_order;
4802
4803 pci_read_config_word(bp->pdev,
4804 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
4805 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
4806 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4807 if (bp->mrrs == -1)
4808 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4809 else {
4810 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
4811 r_order = bp->mrrs;
4812 }
4813
4814 bnx2x_init_pxp_arb(bp, r_order, w_order);
4815}
fd4ef40d
EG		 4816
4817static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
4818{
2145a920 4819 int is_required;
fd4ef40d 4820 u32 val;
2145a920 4821 int port;
fd4ef40d 4822
2145a920
VZ		 4823 if (BP_NOMCP(bp))
4824 return;
4825
4826 is_required = 0;
fd4ef40d
EG		 4827 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
4828 SHARED_HW_CFG_FAN_FAILURE_MASK;
4829
4830 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
4831 is_required = 1;
4832
4833 /*
4834 * The fan failure mechanism is usually related to the PHY type since
4835 * the power consumption of the board is affected by the PHY. Currently,
4836 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
4837 */
4838 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
4839 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 4840 is_required |=
d90d96ba
YR		 4841 bnx2x_fan_failure_det_req(
4842 bp,
4843 bp->common.shmem_base,
a22f0788 4844 bp->common.shmem2_base,
d90d96ba 4845 port);
fd4ef40d
EG		 4846 }
4847
4848 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
4849
4850 if (is_required == 0)
4851 return;
4852
4853 /* Fan failure is indicated by SPIO 5 */
4854 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
4855 MISC_REGISTERS_SPIO_INPUT_HI_Z);
4856
4857 /* set to active low mode */
4858 val = REG_RD(bp, MISC_REG_SPIO_INT);
4859 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
cdaa7cb8 4860 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 4861 REG_WR(bp, MISC_REG_SPIO_INT, val);
4862
4863 /* enable interrupt to signal the IGU */
4864 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
4865 val |= (1 << MISC_REGISTERS_SPIO_5);
4866 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
4867}
4868
f2e0899f
DK		 4869static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
4870{
4871 u32 offset = 0;
4872
4873 if (CHIP_IS_E1(bp))
4874 return;
4875 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
4876 return;
4877
4878 switch (BP_ABS_FUNC(bp)) {
4879 case 0:
4880 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
4881 break;
4882 case 1:
4883 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
4884 break;
4885 case 2:
4886 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
4887 break;
4888 case 3:
4889 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
4890 break;
4891 case 4:
4892 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
4893 break;
4894 case 5:
4895 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
4896 break;
4897 case 6:
4898 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
4899 break;
4900 case 7:
4901 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
4902 break;
4903 default:
4904 return;
4905 }
4906
4907 REG_WR(bp, offset, pretend_func_num);
4908 REG_RD(bp, offset);
4909 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
4910}
4911
4912static void bnx2x_pf_disable(struct bnx2x *bp)
4913{
4914 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
4915 val &= ~IGU_PF_CONF_FUNC_EN;
4916
4917 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
4918 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
4919 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
4920}
4921
523224a3 4922static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
a2fbb9ea 4923{
a2fbb9ea 4924 u32 val, i;
a2fbb9ea 4925
f2e0899f 4926 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 4927
81f75bbf 4928 bnx2x_reset_common(bp);
34f80b04
EG		 4929 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
4930 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
a2fbb9ea 4931
94a78b79 4932 bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
f2e0899f 4933 if (!CHIP_IS_E1(bp))
fb3bff17 4934 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp));
a2fbb9ea 4935
f2e0899f
DK		 4936 if (CHIP_IS_E2(bp)) {
4937 u8 fid;
4938
4939 /**
4940 * 4-port mode or 2-port mode we need to turn of master-enable
4941 * for everyone, after that, turn it back on for self.
4942 * so, we disregard multi-function or not, and always disable
4943 * for all functions on the given path, this means 0,2,4,6 for
4944 * path 0 and 1,3,5,7 for path 1
4945 */
4946 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX*2; fid += 2) {
4947 if (fid == BP_ABS_FUNC(bp)) {
4948 REG_WR(bp,
4949 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
4950 1);
4951 continue;
4952 }
4953
4954 bnx2x_pretend_func(bp, fid);
4955 /* clear pf enable */
4956 bnx2x_pf_disable(bp);
4957 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
4958 }
4959 }
a2fbb9ea 4960
94a78b79 4961 bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
34f80b04
EG		 4962 if (CHIP_IS_E1(bp)) {
4963 /* enable HW interrupt from PXP on USDM overflow
4964 bit 16 on INT_MASK_0 */
4965 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
4966 }
a2fbb9ea 4967
94a78b79 4968 bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
34f80b04 4969 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 4970
4971#ifdef __BIG_ENDIAN
34f80b04
EG		 4972 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
4973 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
4974 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
4975 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
4976 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 4977 /* make sure this value is 0 */
4978 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 4979
4980/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
4981 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
4982 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
4983 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
4984 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 4985#endif
4986
523224a3
DK		 4987 bnx2x_ilt_init_page_size(bp, INITOP_SET);
4988
34f80b04
EG		 4989 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
4990 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 4991
34f80b04
EG		 4992 /* let the HW do it's magic ... */
4993 msleep(100);
4994 /* finish PXP init */
4995 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
4996 if (val != 1) {
4997 BNX2X_ERR("PXP2 CFG failed\n");
4998 return -EBUSY;
4999 }
5000 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5001 if (val != 1) {
5002 BNX2X_ERR("PXP2 RD_INIT failed\n");
5003 return -EBUSY;
5004 }
a2fbb9ea 5005
f2e0899f
DK		 5006 /* Timers bug workaround E2 only. We need to set the entire ILT to
5007 * have entries with value "0" and valid bit on.
5008 * This needs to be done by the first PF that is loaded in a path
5009 * (i.e. common phase)
5010 */
5011 if (CHIP_IS_E2(bp)) {
5012 struct ilt_client_info ilt_cli;
5013 struct bnx2x_ilt ilt;
5014 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5015 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5016
b595076a 5017 /* initialize dummy TM client */
f2e0899f
DK		 5018 ilt_cli.start = 0;
5019 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5020 ilt_cli.client_num = ILT_CLIENT_TM;
5021
5022 /* Step 1: set zeroes to all ilt page entries with valid bit on
5023 * Step 2: set the timers first/last ilt entry to point
5024 * to the entire range to prevent ILT range error for 3rd/4th
25985edc 5025 * vnic (this code assumes existence of the vnic)
f2e0899f
DK		 5026 *
5027 * both steps performed by call to bnx2x_ilt_client_init_op()
5028 * with dummy TM client
5029 *
5030 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5031 * and his brother are split registers
5032 */
5033 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5034 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5035 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5036
5037 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5038 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5039 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5040 }
5041
5042
34f80b04
EG		 5043 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5044 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 5045
f2e0899f
DK		 5046 if (CHIP_IS_E2(bp)) {
5047 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5048 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5049 bnx2x_init_block(bp, PGLUE_B_BLOCK, COMMON_STAGE);
5050
5051 bnx2x_init_block(bp, ATC_BLOCK, COMMON_STAGE);
5052
5053 /* let the HW do it's magic ... */
5054 do {
5055 msleep(200);
5056 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5057 } while (factor-- && (val != 1));
5058
5059 if (val != 1) {
5060 BNX2X_ERR("ATC_INIT failed\n");
5061 return -EBUSY;
5062 }
5063 }
5064
94a78b79 5065 bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
a2fbb9ea 5066
34f80b04
EG		 5067 /* clean the DMAE memory */
5068 bp->dmae_ready = 1;
5069 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
a2fbb9ea 5070
94a78b79
VZ		 5071 bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
5072 bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
5073 bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
5074 bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
a2fbb9ea 5075
34f80b04
EG		 5076 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5077 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5078 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5079 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5080
94a78b79 5081 bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
37b091ba 5082
f2e0899f
DK		 5083 if (CHIP_MODE_IS_4_PORT(bp))
5084 bnx2x_init_block(bp, QM_4PORT_BLOCK, COMMON_STAGE);
f85582f8 5085
523224a3
DK		 5086 /* QM queues pointers table */
5087 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5088
34f80b04
EG		 5089 /* soft reset pulse */
5090 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5091 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 5092
37b091ba 5093#ifdef BCM_CNIC
94a78b79 5094 bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
a2fbb9ea 5095#endif
a2fbb9ea 5096
94a78b79 5097 bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
523224a3
DK		 5098 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5099
34f80b04
EG		 5100 if (!CHIP_REV_IS_SLOW(bp)) {
5101 /* enable hw interrupt from doorbell Q */
5102 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5103 }
a2fbb9ea 5104
94a78b79 5105 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
f2e0899f
DK		 5106 if (CHIP_MODE_IS_4_PORT(bp)) {
5107 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 248);
5108 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 328);
5109 }
5110
94a78b79 5111 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
26c8fa4d 5112 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
37b091ba 5113#ifndef BCM_CNIC
3196a88a
EG		 5114 /* set NIC mode */
5115 REG_WR(bp, PRS_REG_NIC_MODE, 1);
37b091ba 5116#endif
f2e0899f 5117 if (!CHIP_IS_E1(bp))
0793f83f 5118 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp));
f85582f8 5119
f2e0899f
DK		 5120 if (CHIP_IS_E2(bp)) {
5121 /* Bit-map indicating which L2 hdrs may appear after the
5122 basic Ethernet header */
0793f83f 5123 int has_ovlan = IS_MF_SD(bp);
f2e0899f
DK		 5124 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5125 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5126 }
a2fbb9ea 5127
94a78b79
VZ		 5128 bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
5129 bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
5130 bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
5131 bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
a2fbb9ea 5132
ca00392c
EG		 5133 bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5134 bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5135 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5136 bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
a2fbb9ea 5137
94a78b79
VZ		 5138 bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
5139 bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
5140 bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
5141 bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
a2fbb9ea 5142
f2e0899f
DK		 5143 if (CHIP_MODE_IS_4_PORT(bp))
5144 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, COMMON_STAGE);
5145
34f80b04
EG		 5146 /* sync semi rtc */
5147 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5148 0x80000000);
5149 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5150 0x80000000);
a2fbb9ea 5151
94a78b79
VZ		 5152 bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
5153 bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
5154 bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
a2fbb9ea 5155
f2e0899f 5156 if (CHIP_IS_E2(bp)) {
0793f83f 5157 int has_ovlan = IS_MF_SD(bp);
f2e0899f
DK		 5158 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5159 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5160 }
5161
34f80b04 5162 REG_WR(bp, SRC_REG_SOFT_RST, 1);
c68ed255
TH		 5163 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
5164 REG_WR(bp, i, random32());
f85582f8 5165
94a78b79 5166 bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
37b091ba
MC		 5167#ifdef BCM_CNIC
5168 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5169 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5170 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5171 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5172 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5173 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5174 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5175 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5176 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5177 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5178#endif
34f80b04 5179 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 5180
34f80b04
EG		 5181 if (sizeof(union cdu_context) != 1024)
5182 /* we currently assume that a context is 1024 bytes */
cdaa7cb8
VZ		 5183 dev_alert(&bp->pdev->dev, "please adjust the size "
5184 "of cdu_context(%ld)\n",
7995c64e 5185 (long)sizeof(union cdu_context));
a2fbb9ea 5186
94a78b79 5187 bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
34f80b04
EG		 5188 val = (4 << 24) + (0 << 12) + 1024;
5189 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 5190
94a78b79 5191 bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
34f80b04 5192 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 5193 /* enable context validation interrupt from CFC */
5194 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5195
5196 /* set the thresholds to prevent CFC/CDU race */
5197 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 5198
94a78b79 5199 bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
f2e0899f
DK		 5200
5201 if (CHIP_IS_E2(bp) && BP_NOMCP(bp))
5202 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5203
5204 bnx2x_init_block(bp, IGU_BLOCK, COMMON_STAGE);
94a78b79 5205 bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
a2fbb9ea 5206
94a78b79 5207 bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
34f80b04
EG		 5208 /* Reset PCIE errors for debug */
5209 REG_WR(bp, 0x2814, 0xffffffff);
5210 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 5211
f2e0899f
DK		 5212 if (CHIP_IS_E2(bp)) {
5213 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5214 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5215 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5216 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5217 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5218 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5219 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5220 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5221 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5222 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5223 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5224 }
5225
94a78b79 5226 bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
94a78b79 5227 bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
94a78b79 5228 bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
94a78b79 5229 bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
34f80b04 5230
94a78b79 5231 bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
f2e0899f 5232 if (!CHIP_IS_E1(bp)) {
fb3bff17 5233 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
0793f83f 5234 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04 5235 }
f2e0899f
DK		 5236 if (CHIP_IS_E2(bp)) {
5237 /* Bit-map indicating which L2 hdrs may appear after the
5238 basic Ethernet header */
0793f83f 5239 REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6));
f2e0899f 5240 }
34f80b04
EG		 5241
5242 if (CHIP_REV_IS_SLOW(bp))
5243 msleep(200);
5244
5245 /* finish CFC init */
5246 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5247 if (val != 1) {
5248 BNX2X_ERR("CFC LL_INIT failed\n");
5249 return -EBUSY;
5250 }
5251 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5252 if (val != 1) {
5253 BNX2X_ERR("CFC AC_INIT failed\n");
5254 return -EBUSY;
5255 }
5256 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5257 if (val != 1) {
5258 BNX2X_ERR("CFC CAM_INIT failed\n");
5259 return -EBUSY;
5260 }
5261 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 5262
f2e0899f
DK		 5263 if (CHIP_IS_E1(bp)) {
5264 /* read NIG statistic
5265 to see if this is our first up since powerup */
5266 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5267 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 5268
f2e0899f
DK		 5269 /* do internal memory self test */
5270 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5271 BNX2X_ERR("internal mem self test failed\n");
5272 return -EBUSY;
5273 }
34f80b04
EG		 5274 }
5275
fd4ef40d
EG		 5276 bnx2x_setup_fan_failure_detection(bp);
5277
34f80b04
EG		 5278 /* clear PXP2 attentions */
5279 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 5280
4a33bc03
VZ		 5281 bnx2x_enable_blocks_attention(bp);
5282 if (CHIP_PARITY_ENABLED(bp))
5283 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 5284
6bbca910 5285 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 5286 /* In E2 2-PORT mode, same ext phy is used for the two paths */
5287 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
5288 CHIP_IS_E1x(bp)) {
5289 u32 shmem_base[2], shmem2_base[2];
5290 shmem_base[0] = bp->common.shmem_base;
5291 shmem2_base[0] = bp->common.shmem2_base;
5292 if (CHIP_IS_E2(bp)) {
5293 shmem_base[1] =
5294 SHMEM2_RD(bp, other_shmem_base_addr);
5295 shmem2_base[1] =
5296 SHMEM2_RD(bp, other_shmem2_base_addr);
5297 }
5298 bnx2x_acquire_phy_lock(bp);
5299 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5300 bp->common.chip_id);
5301 bnx2x_release_phy_lock(bp);
5302 }
6bbca910
YR		 5303 } else
5304 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5305
34f80b04
EG		 5306 return 0;
5307}
a2fbb9ea 5308
523224a3 5309static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 5310{
5311 int port = BP_PORT(bp);
94a78b79 5312 int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
1c06328c 5313 u32 low, high;
34f80b04 5314 u32 val;
a2fbb9ea 5315
cdaa7cb8 5316 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
34f80b04
EG		 5317
5318 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 5319
94a78b79 5320 bnx2x_init_block(bp, PXP_BLOCK, init_stage);
94a78b79 5321 bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
ca00392c 5322
f2e0899f
DK		 5323 /* Timers bug workaround: disables the pf_master bit in pglue at
5324 * common phase, we need to enable it here before any dmae access are
5325 * attempted. Therefore we manually added the enable-master to the
5326 * port phase (it also happens in the function phase)
5327 */
5328 if (CHIP_IS_E2(bp))
5329 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5330
ca00392c
EG		 5331 bnx2x_init_block(bp, TCM_BLOCK, init_stage);
5332 bnx2x_init_block(bp, UCM_BLOCK, init_stage);
5333 bnx2x_init_block(bp, CCM_BLOCK, init_stage);
94a78b79 5334 bnx2x_init_block(bp, XCM_BLOCK, init_stage);
a2fbb9ea 5335
523224a3
DK		 5336 /* QM cid (connection) count */
5337 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 5338
523224a3 5339#ifdef BCM_CNIC
94a78b79 5340 bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
37b091ba
MC		 5341 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
5342 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
a2fbb9ea 5343#endif
cdaa7cb8 5344
94a78b79 5345 bnx2x_init_block(bp, DQ_BLOCK, init_stage);
1c06328c 5346
f2e0899f
DK		 5347 if (CHIP_MODE_IS_4_PORT(bp))
5348 bnx2x_init_block(bp, QM_4PORT_BLOCK, init_stage);
5349
5350 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
5351 bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
5352 if (CHIP_REV_IS_SLOW(bp) && CHIP_IS_E1(bp)) {
5353 /* no pause for emulation and FPGA */
5354 low = 0;
5355 high = 513;
5356 } else {
5357 if (IS_MF(bp))
5358 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5359 else if (bp->dev->mtu > 4096) {
5360 if (bp->flags & ONE_PORT_FLAG)
5361 low = 160;
5362 else {
5363 val = bp->dev->mtu;
5364 /* (24*1024 + val*4)/256 */
5365 low = 96 + (val/64) +
5366 ((val % 64) ? 1 : 0);
5367 }
5368 } else
5369 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5370 high = low + 56; /* 14*1024/256 */
5371 }
5372 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5373 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 5374 }
1c06328c 5375
f2e0899f
DK		 5376 if (CHIP_MODE_IS_4_PORT(bp)) {
5377 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 + port*8, 248);
5378 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 + port*8, 328);
5379 REG_WR(bp, (BP_PORT(bp) ? BRB1_REG_MAC_GUARANTIED_1 :
5380 BRB1_REG_MAC_GUARANTIED_0), 40);
5381 }
1c06328c 5382
94a78b79 5383 bnx2x_init_block(bp, PRS_BLOCK, init_stage);
ca00392c 5384
94a78b79 5385 bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
94a78b79 5386 bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
94a78b79 5387 bnx2x_init_block(bp, USDM_BLOCK, init_stage);
94a78b79 5388 bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
356e2385 5389
94a78b79
VZ		 5390 bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
5391 bnx2x_init_block(bp, USEM_BLOCK, init_stage);
5392 bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
5393 bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
f2e0899f
DK		 5394 if (CHIP_MODE_IS_4_PORT(bp))
5395 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, init_stage);
356e2385 5396
94a78b79 5397 bnx2x_init_block(bp, UPB_BLOCK, init_stage);
94a78b79 5398 bnx2x_init_block(bp, XPB_BLOCK, init_stage);
34f80b04 5399
94a78b79 5400 bnx2x_init_block(bp, PBF_BLOCK, init_stage);
a2fbb9ea 5401
f2e0899f
DK		 5402 if (!CHIP_IS_E2(bp)) {
5403 /* configure PBF to work without PAUSE mtu 9000 */
5404 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 5405
f2e0899f
DK		 5406 /* update threshold */
5407 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5408 /* update init credit */
5409 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 5410
f2e0899f
DK		 5411 /* probe changes */
5412 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5413 udelay(50);
5414 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5415 }
a2fbb9ea 5416
37b091ba
MC		 5417#ifdef BCM_CNIC
5418 bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
a2fbb9ea 5419#endif
94a78b79 5420 bnx2x_init_block(bp, CDU_BLOCK, init_stage);
94a78b79 5421 bnx2x_init_block(bp, CFC_BLOCK, init_stage);
34f80b04
EG		 5422
5423 if (CHIP_IS_E1(bp)) {
5424 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5425 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5426 }
94a78b79 5427 bnx2x_init_block(bp, HC_BLOCK, init_stage);
34f80b04 5428
f2e0899f
DK		 5429 bnx2x_init_block(bp, IGU_BLOCK, init_stage);
5430
94a78b79 5431 bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
34f80b04
EG		 5432 /* init aeu_mask_attn_func_0/1:
5433 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5434 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5435 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 5436 val = IS_MF(bp) ? 0xF7 : 0x7;
5437 /* Enable DCBX attention for all but E1 */
5438 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5439 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 5440
94a78b79 5441 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
94a78b79 5442 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
94a78b79 5443 bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
94a78b79 5444 bnx2x_init_block(bp, DBU_BLOCK, init_stage);
94a78b79 5445 bnx2x_init_block(bp, DBG_BLOCK, init_stage);
356e2385 5446
94a78b79 5447 bnx2x_init_block(bp, NIG_BLOCK, init_stage);
34f80b04
EG		 5448
5449 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5450
f2e0899f 5451 if (!CHIP_IS_E1(bp)) {
fb3bff17 5452 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 5453 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 5454 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 5455
f2e0899f
DK		 5456 if (CHIP_IS_E2(bp)) {
5457 val = 0;
5458 switch (bp->mf_mode) {
5459 case MULTI_FUNCTION_SD:
5460 val = 1;
5461 break;
5462 case MULTI_FUNCTION_SI:
5463 val = 2;
5464 break;
5465 }
5466
5467 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
5468 NIG_REG_LLH0_CLS_TYPE), val);
5469 }
1c06328c
EG		 5470 {
5471 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
5472 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
5473 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
5474 }
34f80b04
EG		 5475 }
5476
94a78b79 5477 bnx2x_init_block(bp, MCP_BLOCK, init_stage);
94a78b79 5478 bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
d90d96ba 5479 if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
a22f0788 5480 bp->common.shmem2_base, port)) {
4d295db0
EG		 5481 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5482 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5483 val = REG_RD(bp, reg_addr);
f1410647 5484 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 5485 REG_WR(bp, reg_addr, val);
f1410647 5486 }
c18487ee 5487 bnx2x__link_reset(bp);
a2fbb9ea 5488
34f80b04
EG		 5489 return 0;
5490}
5491
34f80b04
EG		 5492static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5493{
5494 int reg;
5495
f2e0899f 5496 if (CHIP_IS_E1(bp))
34f80b04 5497 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 5498 else
5499 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04
EG		 5500
5501 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5502}
5503
f2e0899f
DK		 5504static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
5505{
5506 bnx2x_igu_clear_sb_gen(bp, idu_sb_id, true /*PF*/);
5507}
5508
5509static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
5510{
5511 u32 i, base = FUNC_ILT_BASE(func);
5512 for (i = base; i < base + ILT_PER_FUNC; i++)
5513 bnx2x_ilt_wr(bp, i, 0);
5514}
5515
523224a3 5516static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 5517{
5518 int port = BP_PORT(bp);
5519 int func = BP_FUNC(bp);
523224a3
DK		 5520 struct bnx2x_ilt *ilt = BP_ILT(bp);
5521 u16 cdu_ilt_start;
8badd27a 5522 u32 addr, val;
f4a66897
VZ		 5523 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
5524 int i, main_mem_width;
34f80b04 5525
cdaa7cb8 5526 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
34f80b04 5527
8badd27a 5528 /* set MSI reconfigure capability */
f2e0899f
DK		 5529 if (bp->common.int_block == INT_BLOCK_HC) {
5530 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
5531 val = REG_RD(bp, addr);
5532 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
5533 REG_WR(bp, addr, val);
5534 }
8badd27a 5535
523224a3
DK		 5536 ilt = BP_ILT(bp);
5537 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 5538
523224a3
DK		 5539 for (i = 0; i < L2_ILT_LINES(bp); i++) {
5540 ilt->lines[cdu_ilt_start + i].page =
5541 bp->context.vcxt + (ILT_PAGE_CIDS * i);
5542 ilt->lines[cdu_ilt_start + i].page_mapping =
5543 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
5544 /* cdu ilt pages are allocated manually so there's no need to
5545 set the size */
37b091ba 5546 }
523224a3 5547 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 5548
523224a3
DK		 5549#ifdef BCM_CNIC
5550 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
37b091ba 5551
523224a3
DK		 5552 /* T1 hash bits value determines the T1 number of entries */
5553 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
5554#endif
37b091ba 5555
523224a3
DK		 5556#ifndef BCM_CNIC
5557 /* set NIC mode */
5558 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5559#endif /* BCM_CNIC */
37b091ba 5560
f2e0899f
DK		 5561 if (CHIP_IS_E2(bp)) {
5562 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
5563
5564 /* Turn on a single ISR mode in IGU if driver is going to use
5565 * INT#x or MSI
5566 */
5567 if (!(bp->flags & USING_MSIX_FLAG))
5568 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
5569 /*
5570 * Timers workaround bug: function init part.
5571 * Need to wait 20msec after initializing ILT,
5572 * needed to make sure there are no requests in
5573 * one of the PXP internal queues with "old" ILT addresses
5574 */
5575 msleep(20);
5576 /*
5577 * Master enable - Due to WB DMAE writes performed before this
5578 * register is re-initialized as part of the regular function
5579 * init
5580 */
5581 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5582 /* Enable the function in IGU */
5583 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
5584 }
5585
523224a3 5586 bp->dmae_ready = 1;
34f80b04 5587
523224a3
DK		 5588 bnx2x_init_block(bp, PGLUE_B_BLOCK, FUNC0_STAGE + func);
5589
f2e0899f
DK		 5590 if (CHIP_IS_E2(bp))
5591 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
5592
523224a3
DK		 5593 bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
5594 bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
5595 bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
5596 bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
5597 bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
5598 bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
5599 bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
5600 bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
5601 bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
5602
f2e0899f
DK		 5603 if (CHIP_IS_E2(bp)) {
5604 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_PATH_ID_OFFSET,
5605 BP_PATH(bp));
5606 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_PATH_ID_OFFSET,
5607 BP_PATH(bp));
5608 }
5609
5610 if (CHIP_MODE_IS_4_PORT(bp))
5611 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, FUNC0_STAGE + func);
5612
5613 if (CHIP_IS_E2(bp))
5614 REG_WR(bp, QM_REG_PF_EN, 1);
5615
523224a3 5616 bnx2x_init_block(bp, QM_BLOCK, FUNC0_STAGE + func);
f2e0899f
DK		 5617
5618 if (CHIP_MODE_IS_4_PORT(bp))
5619 bnx2x_init_block(bp, QM_4PORT_BLOCK, FUNC0_STAGE + func);
5620
523224a3
DK		 5621 bnx2x_init_block(bp, TIMERS_BLOCK, FUNC0_STAGE + func);
5622 bnx2x_init_block(bp, DQ_BLOCK, FUNC0_STAGE + func);
5623 bnx2x_init_block(bp, BRB1_BLOCK, FUNC0_STAGE + func);
5624 bnx2x_init_block(bp, PRS_BLOCK, FUNC0_STAGE + func);
5625 bnx2x_init_block(bp, TSDM_BLOCK, FUNC0_STAGE + func);
5626 bnx2x_init_block(bp, CSDM_BLOCK, FUNC0_STAGE + func);
5627 bnx2x_init_block(bp, USDM_BLOCK, FUNC0_STAGE + func);
5628 bnx2x_init_block(bp, XSDM_BLOCK, FUNC0_STAGE + func);
5629 bnx2x_init_block(bp, UPB_BLOCK, FUNC0_STAGE + func);
5630 bnx2x_init_block(bp, XPB_BLOCK, FUNC0_STAGE + func);
5631 bnx2x_init_block(bp, PBF_BLOCK, FUNC0_STAGE + func);
f2e0899f
DK		 5632 if (CHIP_IS_E2(bp))
5633 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
5634
523224a3
DK		 5635 bnx2x_init_block(bp, CDU_BLOCK, FUNC0_STAGE + func);
5636
5637 bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func);
34f80b04 5638
f2e0899f
DK		 5639 if (CHIP_IS_E2(bp))
5640 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
5641
fb3bff17 5642 if (IS_MF(bp)) {
34f80b04 5643 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 5644 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 5645 }
5646
523224a3
DK		 5647 bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func);
5648
34f80b04 5649 /* HC init per function */
f2e0899f
DK		 5650 if (bp->common.int_block == INT_BLOCK_HC) {
5651 if (CHIP_IS_E1H(bp)) {
5652 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5653
5654 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5655 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5656 }
5657 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
5658
5659 } else {
5660 int num_segs, sb_idx, prod_offset;
5661
34f80b04
EG		 5662 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5663
f2e0899f
DK		 5664 if (CHIP_IS_E2(bp)) {
5665 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
5666 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
5667 }
5668
5669 bnx2x_init_block(bp, IGU_BLOCK, FUNC0_STAGE + func);
5670
5671 if (CHIP_IS_E2(bp)) {
5672 int dsb_idx = 0;
5673 /**
5674 * Producer memory:
5675 * E2 mode: address 0-135 match to the mapping memory;
5676 * 136 - PF0 default prod; 137 - PF1 default prod;
5677 * 138 - PF2 default prod; 139 - PF3 default prod;
5678 * 140 - PF0 attn prod; 141 - PF1 attn prod;
5679 * 142 - PF2 attn prod; 143 - PF3 attn prod;
5680 * 144-147 reserved.
5681 *
5682 * E1.5 mode - In backward compatible mode;
5683 * for non default SB; each even line in the memory
5684 * holds the U producer and each odd line hold
5685 * the C producer. The first 128 producers are for
5686 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
5687 * producers are for the DSB for each PF.
5688 * Each PF has five segments: (the order inside each
5689 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
5690 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
5691 * 144-147 attn prods;
5692 */
5693 /* non-default-status-blocks */
5694 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5695 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
5696 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
5697 prod_offset = (bp->igu_base_sb + sb_idx) *
5698 num_segs;
5699
5700 for (i = 0; i < num_segs; i++) {
5701 addr = IGU_REG_PROD_CONS_MEMORY +
5702 (prod_offset + i) * 4;
5703 REG_WR(bp, addr, 0);
5704 }
5705 /* send consumer update with value 0 */
5706 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
5707 USTORM_ID, 0, IGU_INT_NOP, 1);
5708 bnx2x_igu_clear_sb(bp,
5709 bp->igu_base_sb + sb_idx);
5710 }
5711
5712 /* default-status-blocks */
5713 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5714 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
5715
5716 if (CHIP_MODE_IS_4_PORT(bp))
5717 dsb_idx = BP_FUNC(bp);
5718 else
5719 dsb_idx = BP_E1HVN(bp);
5720
5721 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
5722 IGU_BC_BASE_DSB_PROD + dsb_idx :
5723 IGU_NORM_BASE_DSB_PROD + dsb_idx);
5724
5725 for (i = 0; i < (num_segs * E1HVN_MAX);
5726 i += E1HVN_MAX) {
5727 addr = IGU_REG_PROD_CONS_MEMORY +
5728 (prod_offset + i)*4;
5729 REG_WR(bp, addr, 0);
5730 }
5731 /* send consumer update with 0 */
5732 if (CHIP_INT_MODE_IS_BC(bp)) {
5733 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5734 USTORM_ID, 0, IGU_INT_NOP, 1);
5735 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5736 CSTORM_ID, 0, IGU_INT_NOP, 1);
5737 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5738 XSTORM_ID, 0, IGU_INT_NOP, 1);
5739 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5740 TSTORM_ID, 0, IGU_INT_NOP, 1);
5741 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5742 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5743 } else {
5744 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5745 USTORM_ID, 0, IGU_INT_NOP, 1);
5746 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5747 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5748 }
5749 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
5750
5751 /* !!! these should become driver const once
5752 rf-tool supports split-68 const */
5753 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
5754 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
5755 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
5756 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
5757 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
5758 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
5759 }
34f80b04 5760 }
34f80b04 5761
c14423fe 5762 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 5763 REG_WR(bp, 0x2114, 0xffffffff);
5764 REG_WR(bp, 0x2120, 0xffffffff);
523224a3
DK		 5765
5766 bnx2x_init_block(bp, EMAC0_BLOCK, FUNC0_STAGE + func);
5767 bnx2x_init_block(bp, EMAC1_BLOCK, FUNC0_STAGE + func);
5768 bnx2x_init_block(bp, DBU_BLOCK, FUNC0_STAGE + func);
5769 bnx2x_init_block(bp, DBG_BLOCK, FUNC0_STAGE + func);
5770 bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
5771 bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
5772
f4a66897
VZ		 5773 if (CHIP_IS_E1x(bp)) {
5774 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
5775 main_mem_base = HC_REG_MAIN_MEMORY +
5776 BP_PORT(bp) * (main_mem_size * 4);
5777 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
5778 main_mem_width = 8;
5779
5780 val = REG_RD(bp, main_mem_prty_clr);
5781 if (val)
5782 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
5783 "block during "
5784 "function init (0x%x)!\n", val);
5785
5786 /* Clear "false" parity errors in MSI-X table */
5787 for (i = main_mem_base;
5788 i < main_mem_base + main_mem_size * 4;
5789 i += main_mem_width) {
5790 bnx2x_read_dmae(bp, i, main_mem_width / 4);
5791 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
5792 i, main_mem_width / 4);
5793 }
5794 /* Clear HC parity attention */
5795 REG_RD(bp, main_mem_prty_clr);
5796 }
5797
b7737c9b 5798 bnx2x_phy_probe(&bp->link_params);
f85582f8 5799
34f80b04
EG		 5800 return 0;
5801}
5802
9f6c9258 5803int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
34f80b04 5804{
523224a3 5805 int rc = 0;
a2fbb9ea 5806
34f80b04 5807 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
f2e0899f 5808 BP_ABS_FUNC(bp), load_code);
a2fbb9ea 5809
34f80b04 5810 bp->dmae_ready = 0;
6e30dd4e 5811 spin_lock_init(&bp->dmae_lock);
a2fbb9ea 5812
34f80b04
EG		 5813 switch (load_code) {
5814 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5815 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
523224a3 5816 rc = bnx2x_init_hw_common(bp, load_code);
34f80b04
EG		 5817 if (rc)
5818 goto init_hw_err;
5819 /* no break */
5820
5821 case FW_MSG_CODE_DRV_LOAD_PORT:
523224a3 5822 rc = bnx2x_init_hw_port(bp);
34f80b04
EG		 5823 if (rc)
5824 goto init_hw_err;
5825 /* no break */
5826
5827 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3 5828 rc = bnx2x_init_hw_func(bp);
34f80b04
EG		 5829 if (rc)
5830 goto init_hw_err;
5831 break;
5832
5833 default:
5834 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5835 break;
5836 }
5837
5838 if (!BP_NOMCP(bp)) {
f2e0899f 5839 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 5840
5841 bp->fw_drv_pulse_wr_seq =
f2e0899f 5842 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
a2fbb9ea 5843 DRV_PULSE_SEQ_MASK);
6fe49bb9
EG		 5844 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
5845 }
a2fbb9ea 5846
34f80b04
EG		 5847init_hw_err:
5848 bnx2x_gunzip_end(bp);
5849
5850 return rc;
a2fbb9ea
ET		 5851}
5852
9f6c9258 5853void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 5854{
b3b83c3f 5855 bnx2x_gunzip_end(bp);
a2fbb9ea
ET		 5856
5857 /* fastpath */
b3b83c3f 5858 bnx2x_free_fp_mem(bp);
a2fbb9ea
ET		 5859 /* end of fastpath */
5860
5861 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 5862 sizeof(struct host_sp_status_block));
a2fbb9ea
ET		 5863
5864 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 5865 sizeof(struct bnx2x_slowpath));
a2fbb9ea 5866
523224a3
DK		 5867 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
5868 bp->context.size);
5869
5870 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
5871
5872 BNX2X_FREE(bp->ilt->lines);
f85582f8 5873
37b091ba 5874#ifdef BCM_CNIC
f2e0899f
DK		 5875 if (CHIP_IS_E2(bp))
5876 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
5877 sizeof(struct host_hc_status_block_e2));
5878 else
5879 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
5880 sizeof(struct host_hc_status_block_e1x));
f85582f8 5881
523224a3 5882 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
a2fbb9ea 5883#endif
f85582f8 5884
7a9b2557 5885 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 5886
523224a3
DK		 5887 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
5888 BCM_PAGE_SIZE * NUM_EQ_PAGES);
5889
ab532cf3 5890 BNX2X_FREE(bp->rx_indir_table);
a2fbb9ea
ET		 5891}
5892
f2e0899f 5893
9f6c9258 5894int bnx2x_alloc_mem(struct bnx2x *bp)
a2fbb9ea 5895{
b3b83c3f
DK		 5896 if (bnx2x_gunzip_init(bp))
5897 return -ENOMEM;
8badd27a 5898
523224a3 5899#ifdef BCM_CNIC
f2e0899f
DK		 5900 if (CHIP_IS_E2(bp))
5901 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
5902 sizeof(struct host_hc_status_block_e2));
5903 else
5904 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
5905 sizeof(struct host_hc_status_block_e1x));
8badd27a 5906
523224a3
DK		 5907 /* allocate searcher T2 table */
5908 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
5909#endif
a2fbb9ea 5910
8badd27a 5911
523224a3
DK		 5912 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
5913 sizeof(struct host_sp_status_block));
a2fbb9ea 5914
523224a3
DK		 5915 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
5916 sizeof(struct bnx2x_slowpath));
a2fbb9ea 5917
523224a3 5918 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
f85582f8 5919
523224a3
DK		 5920 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
5921 bp->context.size);
65abd74d 5922
523224a3 5923 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 5924
523224a3
DK		 5925 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
5926 goto alloc_mem_err;
65abd74d 5927
9f6c9258
DK		 5928 /* Slow path ring */
5929 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 5930
523224a3
DK		 5931 /* EQ */
5932 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
5933 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3
TH		 5934
5935 BNX2X_ALLOC(bp->rx_indir_table, sizeof(bp->rx_indir_table[0]) *
5936 TSTORM_INDIRECTION_TABLE_SIZE);
b3b83c3f
DK		 5937
5938 /* fastpath */
5939 /* need to be done at the end, since it's self adjusting to amount
5940 * of memory available for RSS queues
5941 */
5942 if (bnx2x_alloc_fp_mem(bp))
5943 goto alloc_mem_err;
9f6c9258 5944 return 0;
e1510706 5945
9f6c9258
DK		 5946alloc_mem_err:
5947 bnx2x_free_mem(bp);
5948 return -ENOMEM;
65abd74d
YG		 5949}
5950
a2fbb9ea
ET		 5951/*
5952 * Init service functions
5953 */
8d96286a 5954static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
5955 int *state_p, int flags);
5956
523224a3 5957int bnx2x_func_start(struct bnx2x *bp)
a2fbb9ea 5958{
523224a3 5959 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 0, 0, 1);
a2fbb9ea 5960
523224a3
DK		 5961 /* Wait for completion */
5962 return bnx2x_wait_ramrod(bp, BNX2X_STATE_FUNC_STARTED, 0, &(bp->state),
5963 WAIT_RAMROD_COMMON);
5964}
a2fbb9ea 5965
8d96286a 5966static int bnx2x_func_stop(struct bnx2x *bp)
523224a3
DK		 5967{
5968 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 1);
a2fbb9ea 5969
523224a3
DK		 5970 /* Wait for completion */
5971 return bnx2x_wait_ramrod(bp, BNX2X_STATE_CLOSING_WAIT4_UNLOAD,
5972 0, &(bp->state), WAIT_RAMROD_COMMON);
a2fbb9ea
ET		 5973}
5974
e665bfda 5975/**
e8920674 5976 * bnx2x_set_mac_addr_gen - set a MAC in a CAM for a few L2 Clients for E1x chips
e665bfda 5977 *
e8920674
DK		 5978 * @bp: driver handle
5979 * @set: set or clear an entry (1 or 0)
5980 * @mac: pointer to a buffer containing a MAC
5981 * @cl_bit_vec: bit vector of clients to register a MAC for
5982 * @cam_offset: offset in a CAM to use
5983 * @is_bcast: is the set MAC a broadcast address (for E1 only)
e665bfda 5984 */
215faf9c 5985static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,
f85582f8
DK		 5986 u32 cl_bit_vec, u8 cam_offset,
5987 u8 is_bcast)
34f80b04 5988{
523224a3
DK		 5989 struct mac_configuration_cmd *config =
5990 (struct mac_configuration_cmd *)bnx2x_sp(bp, mac_config);
5991 int ramrod_flags = WAIT_RAMROD_COMMON;
5992
5993 bp->set_mac_pending = 1;
523224a3 5994
8d9c5f34 5995 config->hdr.length = 1;
e665bfda
MC		 5996 config->hdr.offset = cam_offset;
5997 config->hdr.client_id = 0xff;
6e30dd4e
VZ		 5998 /* Mark the single MAC configuration ramrod as opposed to a
5999 * UC/MC list configuration).
6000 */
6001 config->hdr.echo = 1;
34f80b04
EG		 6002
6003 /* primary MAC */
6004 config->config_table[0].msb_mac_addr =
e665bfda 6005 swab16(*(u16 *)&mac[0]);
34f80b04 6006 config->config_table[0].middle_mac_addr =
e665bfda 6007 swab16(*(u16 *)&mac[2]);
34f80b04 6008 config->config_table[0].lsb_mac_addr =
e665bfda 6009 swab16(*(u16 *)&mac[4]);
ca00392c 6010 config->config_table[0].clients_bit_vector =
e665bfda 6011 cpu_to_le32(cl_bit_vec);
34f80b04 6012 config->config_table[0].vlan_id = 0;
523224a3 6013 config->config_table[0].pf_id = BP_FUNC(bp);
3101c2bc 6014 if (set)
523224a3
DK		 6015 SET_FLAG(config->config_table[0].flags,
6016 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6017 T_ETH_MAC_COMMAND_SET);
3101c2bc 6018 else
523224a3
DK		 6019 SET_FLAG(config->config_table[0].flags,
6020 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6021 T_ETH_MAC_COMMAND_INVALIDATE);
34f80b04 6022
523224a3
DK		 6023 if (is_bcast)
6024 SET_FLAG(config->config_table[0].flags,
6025 MAC_CONFIGURATION_ENTRY_BROADCAST, 1);
6026
6027 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) PF_ID %d CLID mask %d\n",
3101c2bc 6028 (set ? "setting" : "clearing"),
34f80b04
EG		 6029 config->config_table[0].msb_mac_addr,
6030 config->config_table[0].middle_mac_addr,
523224a3 6031 config->config_table[0].lsb_mac_addr, BP_FUNC(bp), cl_bit_vec);
34f80b04 6032
6e30dd4e
VZ		 6033 mb();
6034
523224a3 6035 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
34f80b04 6036 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
523224a3
DK		 6037 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
6038
6039 /* Wait for a completion */
6040 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, ramrod_flags);
34f80b04
EG		 6041}
6042
8d96286a 6043static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6044 int *state_p, int flags)
a2fbb9ea
ET		 6045{
6046 /* can take a while if any port is running */
8b3a0f0b 6047 int cnt = 5000;
523224a3
DK		 6048 u8 poll = flags & WAIT_RAMROD_POLL;
6049 u8 common = flags & WAIT_RAMROD_COMMON;
a2fbb9ea 6050
c14423fe
ET		 6051 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6052 poll ? "polling" : "waiting", state, idx);
a2fbb9ea
ET		 6053
6054 might_sleep();
34f80b04 6055 while (cnt--) {
a2fbb9ea 6056 if (poll) {
523224a3
DK		 6057 if (common)
6058 bnx2x_eq_int(bp);
6059 else {
6060 bnx2x_rx_int(bp->fp, 10);
6061 /* if index is different from 0
6062 * the reply for some commands will
6063 * be on the non default queue
6064 */
6065 if (idx)
6066 bnx2x_rx_int(&bp->fp[idx], 10);
6067 }
a2fbb9ea 6068 }
a2fbb9ea 6069
3101c2bc 6070 mb(); /* state is changed by bnx2x_sp_event() */
8b3a0f0b
EG		 6071 if (*state_p == state) {
6072#ifdef BNX2X_STOP_ON_ERROR
6073 DP(NETIF_MSG_IFUP, "exit (cnt %d)\n", 5000 - cnt);
6074#endif
a2fbb9ea 6075 return 0;
8b3a0f0b 6076 }
a2fbb9ea 6077
a2fbb9ea 6078 msleep(1);
e3553b29
EG		 6079
6080 if (bp->panic)
6081 return -EIO;
a2fbb9ea
ET		 6082 }
6083
a2fbb9ea 6084 /* timeout! */
49d66772
ET		 6085 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6086 poll ? "polling" : "waiting", state, idx);
34f80b04
EG		 6087#ifdef BNX2X_STOP_ON_ERROR
6088 bnx2x_panic();
6089#endif
a2fbb9ea 6090
49d66772 6091 return -EBUSY;
a2fbb9ea
ET		 6092}
6093
8d96286a 6094static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
e665bfda 6095{
f2e0899f
DK		 6096 if (CHIP_IS_E1H(bp))
6097 return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);
6098 else if (CHIP_MODE_IS_4_PORT(bp))
6e30dd4e 6099 return E2_FUNC_MAX * rel_offset + BP_FUNC(bp);
f2e0899f 6100 else
6e30dd4e 6101 return E2_FUNC_MAX * rel_offset + BP_VN(bp);
523224a3
DK		 6102}
6103
0793f83f
DK		 6104/**
6105 * LLH CAM line allocations: currently only iSCSI and ETH macs are
6106 * relevant. In addition, current implementation is tuned for a
6107 * single ETH MAC.
0793f83f
DK		 6108 */
6109enum {
6110 LLH_CAM_ISCSI_ETH_LINE = 0,
6111 LLH_CAM_ETH_LINE,
6112 LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE
6113};
6114
6115static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
6116 int set,
6117 unsigned char *dev_addr,
6118 int index)
6119{
6120 u32 wb_data[2];
6121 u32 mem_offset, ena_offset, mem_index;
6122 /**
6123 * indexes mapping:
6124 * 0..7 - goes to MEM
6125 * 8..15 - goes to MEM2
6126 */
6127
6128 if (!IS_MF_SI(bp) || index > LLH_CAM_MAX_PF_LINE)
6129 return;
6130
6131 /* calculate memory start offset according to the mapping
6132 * and index in the memory */
6133 if (index < NIG_LLH_FUNC_MEM_MAX_OFFSET) {
6134 mem_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
6135 NIG_REG_LLH0_FUNC_MEM;
6136 ena_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
6137 NIG_REG_LLH0_FUNC_MEM_ENABLE;
6138 mem_index = index;
6139 } else {
6140 mem_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2 :
6141 NIG_REG_P0_LLH_FUNC_MEM2;
6142 ena_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE :
6143 NIG_REG_P0_LLH_FUNC_MEM2_ENABLE;
6144 mem_index = index - NIG_LLH_FUNC_MEM_MAX_OFFSET;
6145 }
6146
6147 if (set) {
6148 /* LLH_FUNC_MEM is a u64 WB register */
6149 mem_offset += 8*mem_index;
6150
6151 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
6152 (dev_addr[4] << 8) | dev_addr[5]);
6153 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
6154
6155 REG_WR_DMAE(bp, mem_offset, wb_data, 2);
6156 }
6157
6158 /* enable/disable the entry */
6159 REG_WR(bp, ena_offset + 4*mem_index, set);
6160
6161}
6162
523224a3
DK		 6163void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
6164{
6165 u8 cam_offset = (CHIP_IS_E1(bp) ? (BP_PORT(bp) ? 32 : 0) :
6166 bnx2x_e1h_cam_offset(bp, CAM_ETH_LINE));
e665bfda 6167
523224a3
DK		 6168 /* networking MAC */
6169 bnx2x_set_mac_addr_gen(bp, set, bp->dev->dev_addr,
6170 (1 << bp->fp->cl_id), cam_offset , 0);
e665bfda 6171
0793f83f
DK		 6172 bnx2x_set_mac_in_nig(bp, set, bp->dev->dev_addr, LLH_CAM_ETH_LINE);
6173
523224a3
DK		 6174 if (CHIP_IS_E1(bp)) {
6175 /* broadcast MAC */
215faf9c
JP		 6176 static const u8 bcast[ETH_ALEN] = {
6177 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
6178 };
523224a3
DK		 6179 bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);
6180 }
e665bfda 6181}
6e30dd4e
VZ		 6182
6183static inline u8 bnx2x_e1_cam_mc_offset(struct bnx2x *bp)
6184{
6185 return CHIP_REV_IS_SLOW(bp) ?
6186 (BNX2X_MAX_EMUL_MULTI * (1 + BP_PORT(bp))) :
6187 (BNX2X_MAX_MULTICAST * (1 + BP_PORT(bp)));
6188}
6189
6190/* set mc list, do not wait as wait implies sleep and
6191 * set_rx_mode can be invoked from non-sleepable context.
6192 *
6193 * Instead we use the same ramrod data buffer each time we need
6194 * to configure a list of addresses, and use the fact that the
6195 * list of MACs is changed in an incremental way and that the
6196 * function is called under the netif_addr_lock. A temporary
6197 * inconsistent CAM configuration (possible in case of a very fast
6198 * sequence of add/del/add on the host side) will shortly be
6199 * restored by the handler of the last ramrod.
6200 */
6201static int bnx2x_set_e1_mc_list(struct bnx2x *bp)
523224a3
DK		 6202{
6203 int i = 0, old;
6204 struct net_device *dev = bp->dev;
6e30dd4e 6205 u8 offset = bnx2x_e1_cam_mc_offset(bp);
523224a3
DK		 6206 struct netdev_hw_addr *ha;
6207 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6208 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6209
6e30dd4e
VZ		 6210 if (netdev_mc_count(dev) > BNX2X_MAX_MULTICAST)
6211 return -EINVAL;
6212
523224a3
DK		 6213 netdev_for_each_mc_addr(ha, dev) {
6214 /* copy mac */
6215 config_cmd->config_table[i].msb_mac_addr =
6216 swab16(*(u16 *)&bnx2x_mc_addr(ha)[0]);
6217 config_cmd->config_table[i].middle_mac_addr =
6218 swab16(*(u16 *)&bnx2x_mc_addr(ha)[2]);
6219 config_cmd->config_table[i].lsb_mac_addr =
6220 swab16(*(u16 *)&bnx2x_mc_addr(ha)[4]);
e665bfda 6221
523224a3
DK		 6222 config_cmd->config_table[i].vlan_id = 0;
6223 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
6224 config_cmd->config_table[i].clients_bit_vector =
6225 cpu_to_le32(1 << BP_L_ID(bp));
6226
6227 SET_FLAG(config_cmd->config_table[i].flags,
6228 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6229 T_ETH_MAC_COMMAND_SET);
6230
6231 DP(NETIF_MSG_IFUP,
6232 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
6233 config_cmd->config_table[i].msb_mac_addr,
6234 config_cmd->config_table[i].middle_mac_addr,
6235 config_cmd->config_table[i].lsb_mac_addr);
6236 i++;
6237 }
6238 old = config_cmd->hdr.length;
6239 if (old > i) {
6240 for (; i < old; i++) {
6241 if (CAM_IS_INVALID(config_cmd->
6242 config_table[i])) {
6243 /* already invalidated */
6244 break;
6245 }
6246 /* invalidate */
6247 SET_FLAG(config_cmd->config_table[i].flags,
6248 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6249 T_ETH_MAC_COMMAND_INVALIDATE);
6250 }
6251 }
6252
6e30dd4e
VZ		 6253 wmb();
6254
523224a3
DK		 6255 config_cmd->hdr.length = i;
6256 config_cmd->hdr.offset = offset;
6257 config_cmd->hdr.client_id = 0xff;
6e30dd4e
VZ		 6258 /* Mark that this ramrod doesn't use bp->set_mac_pending for
6259 * synchronization.
6260 */
6261 config_cmd->hdr.echo = 0;
523224a3 6262
6e30dd4e 6263 mb();
523224a3 6264
6e30dd4e 6265 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
523224a3
DK		 6266 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6267}
6e30dd4e
VZ		 6268
6269void bnx2x_invalidate_e1_mc_list(struct bnx2x *bp)
e665bfda 6270{
523224a3
DK		 6271 int i;
6272 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6273 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6274 int ramrod_flags = WAIT_RAMROD_COMMON;
6e30dd4e 6275 u8 offset = bnx2x_e1_cam_mc_offset(bp);
523224a3 6276
6e30dd4e 6277 for (i = 0; i < BNX2X_MAX_MULTICAST; i++)
523224a3
DK		 6278 SET_FLAG(config_cmd->config_table[i].flags,
6279 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6280 T_ETH_MAC_COMMAND_INVALIDATE);
6281
6e30dd4e
VZ		 6282 wmb();
6283
6284 config_cmd->hdr.length = BNX2X_MAX_MULTICAST;
6285 config_cmd->hdr.offset = offset;
6286 config_cmd->hdr.client_id = 0xff;
6287 /* We'll wait for a completion this time... */
6288 config_cmd->hdr.echo = 1;
6289
6290 bp->set_mac_pending = 1;
6291
6292 mb();
6293
523224a3
DK		 6294 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6295 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
e665bfda
MC		 6296
6297 /* Wait for a completion */
523224a3
DK		 6298 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
6299 ramrod_flags);
6300
e665bfda
MC		 6301}
6302
6e30dd4e
VZ		 6303/* Accept one or more multicasts */
6304static int bnx2x_set_e1h_mc_list(struct bnx2x *bp)
6305{
6306 struct net_device *dev = bp->dev;
6307 struct netdev_hw_addr *ha;
6308 u32 mc_filter[MC_HASH_SIZE];
6309 u32 crc, bit, regidx;
6310 int i;
6311
6312 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
6313
6314 netdev_for_each_mc_addr(ha, dev) {
6315 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
6316 bnx2x_mc_addr(ha));
6317
6318 crc = crc32c_le(0, bnx2x_mc_addr(ha),
6319 ETH_ALEN);
6320 bit = (crc >> 24) & 0xff;
6321 regidx = bit >> 5;
6322 bit &= 0x1f;
6323 mc_filter[regidx] |= (1 << bit);
6324 }
6325
6326 for (i = 0; i < MC_HASH_SIZE; i++)
6327 REG_WR(bp, MC_HASH_OFFSET(bp, i),
6328 mc_filter[i]);
6329
6330 return 0;
6331}
6332
6333void bnx2x_invalidate_e1h_mc_list(struct bnx2x *bp)
6334{
6335 int i;
6336
6337 for (i = 0; i < MC_HASH_SIZE; i++)
6338 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
6339}
6340
993ac7b5
MC		 6341#ifdef BCM_CNIC
6342/**
e8920674 6343 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
993ac7b5 6344 *
e8920674
DK		 6345 * @bp: driver handle
6346 * @set: set or clear the CAM entry
993ac7b5 6347 *
e8920674
DK		 6348 * This function will wait until the ramdord completion returns.
6349 * Return 0 if success, -ENODEV if ramrod doesn't return.
993ac7b5 6350 */
8d96286a 6351static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
993ac7b5 6352{
523224a3
DK		 6353 u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
6354 bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
ec6ba945
VZ		 6355 u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +
6356 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
523224a3 6357 u32 cl_bit_vec = (1 << iscsi_l2_cl_id);
2ba45142 6358 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
993ac7b5
MC		 6359
6360 /* Send a SET_MAC ramrod */
2ba45142 6361 bnx2x_set_mac_addr_gen(bp, set, iscsi_mac, cl_bit_vec,
523224a3 6362 cam_offset, 0);
0793f83f 6363
2ba45142 6364 bnx2x_set_mac_in_nig(bp, set, iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);
ec6ba945
VZ		 6365
6366 return 0;
6367}
6368
6369/**
e8920674 6370 * bnx2x_set_fip_eth_mac_addr - set FCoE L2 MAC(s)
ec6ba945 6371 *
e8920674
DK		 6372 * @bp: driver handle
6373 * @set: set or clear the CAM entry
ec6ba945 6374 *
e8920674
DK		 6375 * This function will wait until the ramrod completion returns.
6376 * Returns 0 if success, -ENODEV if ramrod doesn't return.
ec6ba945
VZ		 6377 */
6378int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)
6379{
6380 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6381 /**
6382 * CAM allocation for E1H
6383 * eth unicasts: by func number
6384 * iscsi: by func number
6385 * fip unicast: by func number
6386 * fip multicast: by func number
6387 */
6388 bnx2x_set_mac_addr_gen(bp, set, bp->fip_mac,
6389 cl_bit_vec, bnx2x_e1h_cam_offset(bp, CAM_FIP_ETH_LINE), 0);
6390
6391 return 0;
6392}
6393
6394int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set)
6395{
6396 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6397
6398 /**
6399 * CAM allocation for E1H
6400 * eth unicasts: by func number
6401 * iscsi: by func number
6402 * fip unicast: by func number
6403 * fip multicast: by func number
6404 */
6405 bnx2x_set_mac_addr_gen(bp, set, ALL_ENODE_MACS, cl_bit_vec,
6406 bnx2x_e1h_cam_offset(bp, CAM_FIP_MCAST_LINE), 0);
6407
993ac7b5
MC		 6408 return 0;
6409}
6410#endif
6411
523224a3
DK		 6412static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
6413 struct bnx2x_client_init_params *params,
6414 u8 activate,
6415 struct client_init_ramrod_data *data)
6416{
6417 /* Clear the buffer */
6418 memset(data, 0, sizeof(*data));
6419
6420 /* general */
6421 data->general.client_id = params->rxq_params.cl_id;
6422 data->general.statistics_counter_id = params->rxq_params.stat_id;
6423 data->general.statistics_en_flg =
6424 (params->rxq_params.flags & QUEUE_FLG_STATS) ? 1 : 0;
ec6ba945
VZ		 6425 data->general.is_fcoe_flg =
6426 (params->ramrod_params.flags & CLIENT_IS_FCOE) ? 1 : 0;
523224a3
DK		 6427 data->general.activate_flg = activate;
6428 data->general.sp_client_id = params->rxq_params.spcl_id;
6429
6430 /* Rx data */
6431 data->rx.tpa_en_flg =
6432 (params->rxq_params.flags & QUEUE_FLG_TPA) ? 1 : 0;
6433 data->rx.vmqueue_mode_en_flg = 0;
6434 data->rx.cache_line_alignment_log_size =
6435 params->rxq_params.cache_line_log;
6436 data->rx.enable_dynamic_hc =
6437 (params->rxq_params.flags & QUEUE_FLG_DHC) ? 1 : 0;
6438 data->rx.max_sges_for_packet = params->rxq_params.max_sges_pkt;
6439 data->rx.client_qzone_id = params->rxq_params.cl_qzone_id;
6440 data->rx.max_agg_size = params->rxq_params.tpa_agg_sz;
6441
6442 /* We don't set drop flags */
6443 data->rx.drop_ip_cs_err_flg = 0;
6444 data->rx.drop_tcp_cs_err_flg = 0;
6445 data->rx.drop_ttl0_flg = 0;
6446 data->rx.drop_udp_cs_err_flg = 0;
6447
6448 data->rx.inner_vlan_removal_enable_flg =
6449 (params->rxq_params.flags & QUEUE_FLG_VLAN) ? 1 : 0;
6450 data->rx.outer_vlan_removal_enable_flg =
6451 (params->rxq_params.flags & QUEUE_FLG_OV) ? 1 : 0;
6452 data->rx.status_block_id = params->rxq_params.fw_sb_id;
6453 data->rx.rx_sb_index_number = params->rxq_params.sb_cq_index;
6454 data->rx.bd_buff_size = cpu_to_le16(params->rxq_params.buf_sz);
6455 data->rx.sge_buff_size = cpu_to_le16(params->rxq_params.sge_buf_sz);
6456 data->rx.mtu = cpu_to_le16(params->rxq_params.mtu);
6457 data->rx.bd_page_base.lo =
6458 cpu_to_le32(U64_LO(params->rxq_params.dscr_map));
6459 data->rx.bd_page_base.hi =
6460 cpu_to_le32(U64_HI(params->rxq_params.dscr_map));
6461 data->rx.sge_page_base.lo =
6462 cpu_to_le32(U64_LO(params->rxq_params.sge_map));
6463 data->rx.sge_page_base.hi =
6464 cpu_to_le32(U64_HI(params->rxq_params.sge_map));
6465 data->rx.cqe_page_base.lo =
6466 cpu_to_le32(U64_LO(params->rxq_params.rcq_map));
6467 data->rx.cqe_page_base.hi =
6468 cpu_to_le32(U64_HI(params->rxq_params.rcq_map));
6469 data->rx.is_leading_rss =
6470 (params->ramrod_params.flags & CLIENT_IS_LEADING_RSS) ? 1 : 0;
6471 data->rx.is_approx_mcast = data->rx.is_leading_rss;
6472
6473 /* Tx data */
6474 data->tx.enforce_security_flg = 0; /* VF specific */
6475 data->tx.tx_status_block_id = params->txq_params.fw_sb_id;
6476 data->tx.tx_sb_index_number = params->txq_params.sb_cq_index;
6477 data->tx.mtu = 0; /* VF specific */
6478 data->tx.tx_bd_page_base.lo =
6479 cpu_to_le32(U64_LO(params->txq_params.dscr_map));
6480 data->tx.tx_bd_page_base.hi =
6481 cpu_to_le32(U64_HI(params->txq_params.dscr_map));
6482
6483 /* flow control data */
6484 data->fc.cqe_pause_thr_low = cpu_to_le16(params->pause.rcq_th_lo);
6485 data->fc.cqe_pause_thr_high = cpu_to_le16(params->pause.rcq_th_hi);
6486 data->fc.bd_pause_thr_low = cpu_to_le16(params->pause.bd_th_lo);
6487 data->fc.bd_pause_thr_high = cpu_to_le16(params->pause.bd_th_hi);
6488 data->fc.sge_pause_thr_low = cpu_to_le16(params->pause.sge_th_lo);
6489 data->fc.sge_pause_thr_high = cpu_to_le16(params->pause.sge_th_hi);
6490 data->fc.rx_cos_mask = cpu_to_le16(params->pause.pri_map);
6491
6492 data->fc.safc_group_num = params->txq_params.cos;
6493 data->fc.safc_group_en_flg =
6494 (params->txq_params.flags & QUEUE_FLG_COS) ? 1 : 0;
ec6ba945
VZ		 6495 data->fc.traffic_type =
6496 (params->ramrod_params.flags & CLIENT_IS_FCOE) ?
6497 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
523224a3
DK		 6498}
6499
6500static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
6501{
6502 /* ustorm cxt validation */
6503 cxt->ustorm_ag_context.cdu_usage =
6504 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_UCM_AG,
6505 ETH_CONNECTION_TYPE);
6506 /* xcontext validation */
6507 cxt->xstorm_ag_context.cdu_reserved =
6508 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_XCM_AG,
6509 ETH_CONNECTION_TYPE);
6510}
6511
8d96286a 6512static int bnx2x_setup_fw_client(struct bnx2x *bp,
6513 struct bnx2x_client_init_params *params,
6514 u8 activate,
6515 struct client_init_ramrod_data *data,
6516 dma_addr_t data_mapping)
523224a3
DK		 6517{
6518 u16 hc_usec;
6519 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
6520 int ramrod_flags = 0, rc;
6521
6522 /* HC and context validation values */
6523 hc_usec = params->txq_params.hc_rate ?
6524 1000000 / params->txq_params.hc_rate : 0;
6525 bnx2x_update_coalesce_sb_index(bp,
6526 params->txq_params.fw_sb_id,
6527 params->txq_params.sb_cq_index,
6528 !(params->txq_params.flags & QUEUE_FLG_HC),
6529 hc_usec);
6530
6531 *(params->ramrod_params.pstate) = BNX2X_FP_STATE_OPENING;
6532
6533 hc_usec = params->rxq_params.hc_rate ?
6534 1000000 / params->rxq_params.hc_rate : 0;
6535 bnx2x_update_coalesce_sb_index(bp,
6536 params->rxq_params.fw_sb_id,
6537 params->rxq_params.sb_cq_index,
6538 !(params->rxq_params.flags & QUEUE_FLG_HC),
6539 hc_usec);
6540
6541 bnx2x_set_ctx_validation(params->rxq_params.cxt,
6542 params->rxq_params.cid);
6543
6544 /* zero stats */
6545 if (params->txq_params.flags & QUEUE_FLG_STATS)
6546 storm_memset_xstats_zero(bp, BP_PORT(bp),
6547 params->txq_params.stat_id);
6548
6549 if (params->rxq_params.flags & QUEUE_FLG_STATS) {
6550 storm_memset_ustats_zero(bp, BP_PORT(bp),
6551 params->rxq_params.stat_id);
6552 storm_memset_tstats_zero(bp, BP_PORT(bp),
6553 params->rxq_params.stat_id);
6554 }
6555
6556 /* Fill the ramrod data */
6557 bnx2x_fill_cl_init_data(bp, params, activate, data);
6558
6559 /* SETUP ramrod.
6560 *
6561 * bnx2x_sp_post() takes a spin_lock thus no other explict memory
6562 * barrier except from mmiowb() is needed to impose a
6563 * proper ordering of memory operations.
6564 */
6565 mmiowb();
a2fbb9ea 6566
a2fbb9ea 6567
523224a3
DK		 6568 bnx2x_sp_post(bp, ramrod, params->ramrod_params.cid,
6569 U64_HI(data_mapping), U64_LO(data_mapping), 0);
a2fbb9ea 6570
34f80b04 6571 /* Wait for completion */
523224a3
DK		 6572 rc = bnx2x_wait_ramrod(bp, params->ramrod_params.state,
6573 params->ramrod_params.index,
6574 params->ramrod_params.pstate,
6575 ramrod_flags);
34f80b04 6576 return rc;
a2fbb9ea
ET		 6577}
6578
d6214d7a 6579/**
e8920674 6580 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 6581 *
e8920674 6582 * @bp: driver handle
d6214d7a 6583 *
e8920674 6584 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a
DK		 6585 */
6586static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 6587{
d6214d7a 6588 int rc = 0;
ca00392c 6589
d6214d7a
DK		 6590 switch (bp->int_mode) {
6591 case INT_MODE_MSI:
6592 bnx2x_enable_msi(bp);
6593 /* falling through... */
6594 case INT_MODE_INTx:
ec6ba945 6595 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
d6214d7a 6596 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
ca00392c 6597 break;
d6214d7a
DK		 6598 default:
6599 /* Set number of queues according to bp->multi_mode value */
6600 bnx2x_set_num_queues(bp);
ca00392c 6601
d6214d7a
DK		 6602 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6603 bp->num_queues);
ca00392c 6604
d6214d7a
DK		 6605 /* if we can't use MSI-X we only need one fp,
6606 * so try to enable MSI-X with the requested number of fp's
6607 * and fallback to MSI or legacy INTx with one fp
6608 */
6609 rc = bnx2x_enable_msix(bp);
6610 if (rc) {
6611 /* failed to enable MSI-X */
6612 if (bp->multi_mode)
6613 DP(NETIF_MSG_IFUP,
6614 "Multi requested but failed to "
6615 "enable MSI-X (%d), "
6616 "set number of queues to %d\n",
6617 bp->num_queues,
ec6ba945
VZ		 6618 1 + NONE_ETH_CONTEXT_USE);
6619 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
d6214d7a
DK		 6620
6621 if (!(bp->flags & DISABLE_MSI_FLAG))
6622 bnx2x_enable_msi(bp);
6623 }
ca00392c 6624
9f6c9258
DK		 6625 break;
6626 }
d6214d7a
DK		 6627
6628 return rc;
a2fbb9ea
ET		 6629}
6630
c2bff63f
DK		 6631/* must be called prioir to any HW initializations */
6632static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6633{
6634 return L2_ILT_LINES(bp);
6635}
6636
523224a3
DK		 6637void bnx2x_ilt_set_info(struct bnx2x *bp)
6638{
6639 struct ilt_client_info *ilt_client;
6640 struct bnx2x_ilt *ilt = BP_ILT(bp);
6641 u16 line = 0;
6642
6643 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6644 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6645
6646 /* CDU */
6647 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6648 ilt_client->client_num = ILT_CLIENT_CDU;
6649 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6650 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6651 ilt_client->start = line;
6652 line += L2_ILT_LINES(bp);
6653#ifdef BCM_CNIC
6654 line += CNIC_ILT_LINES;
6655#endif
6656 ilt_client->end = line - 1;
6657
6658 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6659 "flags 0x%x, hw psz %d\n",
6660 ilt_client->start,
6661 ilt_client->end,
6662 ilt_client->page_size,
6663 ilt_client->flags,
6664 ilog2(ilt_client->page_size >> 12));
6665
6666 /* QM */
6667 if (QM_INIT(bp->qm_cid_count)) {
6668 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6669 ilt_client->client_num = ILT_CLIENT_QM;
6670 ilt_client->page_size = QM_ILT_PAGE_SZ;
6671 ilt_client->flags = 0;
6672 ilt_client->start = line;
6673
6674 /* 4 bytes for each cid */
6675 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6676 QM_ILT_PAGE_SZ);
6677
6678 ilt_client->end = line - 1;
6679
6680 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6681 "flags 0x%x, hw psz %d\n",
6682 ilt_client->start,
6683 ilt_client->end,
6684 ilt_client->page_size,
6685 ilt_client->flags,
6686 ilog2(ilt_client->page_size >> 12));
6687
6688 }
6689 /* SRC */
6690 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6691#ifdef BCM_CNIC
6692 ilt_client->client_num = ILT_CLIENT_SRC;
6693 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6694 ilt_client->flags = 0;
6695 ilt_client->start = line;
6696 line += SRC_ILT_LINES;
6697 ilt_client->end = line - 1;
6698
6699 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6700 "flags 0x%x, hw psz %d\n",
6701 ilt_client->start,
6702 ilt_client->end,
6703 ilt_client->page_size,
6704 ilt_client->flags,
6705 ilog2(ilt_client->page_size >> 12));
6706
6707#else
6708 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6709#endif
9f6c9258 6710
523224a3
DK		 6711 /* TM */
6712 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6713#ifdef BCM_CNIC
6714 ilt_client->client_num = ILT_CLIENT_TM;
6715 ilt_client->page_size = TM_ILT_PAGE_SZ;
6716 ilt_client->flags = 0;
6717 ilt_client->start = line;
6718 line += TM_ILT_LINES;
6719 ilt_client->end = line - 1;
6720
6721 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6722 "flags 0x%x, hw psz %d\n",
6723 ilt_client->start,
6724 ilt_client->end,
6725 ilt_client->page_size,
6726 ilt_client->flags,
6727 ilog2(ilt_client->page_size >> 12));
9f6c9258 6728
523224a3
DK		 6729#else
6730 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6731#endif
6732}
f85582f8 6733
523224a3
DK		 6734int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6735 int is_leading)
a2fbb9ea 6736{
523224a3 6737 struct bnx2x_client_init_params params = { {0} };
a2fbb9ea
ET		 6738 int rc;
6739
ec6ba945
VZ		 6740 /* reset IGU state skip FCoE L2 queue */
6741 if (!IS_FCOE_FP(fp))
6742 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 6743 IGU_INT_ENABLE, 0);
a2fbb9ea 6744
523224a3
DK		 6745 params.ramrod_params.pstate = &fp->state;
6746 params.ramrod_params.state = BNX2X_FP_STATE_OPEN;
6747 params.ramrod_params.index = fp->index;
6748 params.ramrod_params.cid = fp->cid;
a2fbb9ea 6749
ec6ba945
VZ		 6750#ifdef BCM_CNIC
6751 if (IS_FCOE_FP(fp))
6752 params.ramrod_params.flags |= CLIENT_IS_FCOE;
6753
6754#endif
6755
523224a3
DK		 6756 if (is_leading)
6757 params.ramrod_params.flags |= CLIENT_IS_LEADING_RSS;
a2fbb9ea 6758
523224a3
DK		 6759 bnx2x_pf_rx_cl_prep(bp, fp, &params.pause, &params.rxq_params);
6760
6761 bnx2x_pf_tx_cl_prep(bp, fp, &params.txq_params);
6762
6763 rc = bnx2x_setup_fw_client(bp, &params, 1,
6764 bnx2x_sp(bp, client_init_data),
6765 bnx2x_sp_mapping(bp, client_init_data));
34f80b04 6766 return rc;
a2fbb9ea
ET		 6767}
6768
8d96286a 6769static int bnx2x_stop_fw_client(struct bnx2x *bp,
6770 struct bnx2x_client_ramrod_params *p)
a2fbb9ea 6771{
34f80b04 6772 int rc;
a2fbb9ea 6773
523224a3 6774 int poll_flag = p->poll ? WAIT_RAMROD_POLL : 0;
a2fbb9ea 6775
523224a3
DK		 6776 /* halt the connection */
6777 *p->pstate = BNX2X_FP_STATE_HALTING;
6778 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, p->cid, 0,
6779 p->cl_id, 0);
a2fbb9ea 6780
34f80b04 6781 /* Wait for completion */
523224a3
DK		 6782 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, p->index,
6783 p->pstate, poll_flag);
34f80b04 6784 if (rc) /* timeout */
da5a662a 6785 return rc;
a2fbb9ea 6786
523224a3
DK		 6787 *p->pstate = BNX2X_FP_STATE_TERMINATING;
6788 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, p->cid, 0,
6789 p->cl_id, 0);
6790 /* Wait for completion */
6791 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_TERMINATED, p->index,
6792 p->pstate, poll_flag);
6793 if (rc) /* timeout */
6794 return rc;
a2fbb9ea 6795
a2fbb9ea 6796
523224a3
DK		 6797 /* delete cfc entry */
6798 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, p->cid, 0, 0, 1);
da5a662a 6799
523224a3
DK		 6800 /* Wait for completion */
6801 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, p->index,
6802 p->pstate, WAIT_RAMROD_COMMON);
da5a662a 6803 return rc;
a2fbb9ea
ET		 6804}
6805
523224a3
DK		 6806static int bnx2x_stop_client(struct bnx2x *bp, int index)
6807{
6808 struct bnx2x_client_ramrod_params client_stop = {0};
6809 struct bnx2x_fastpath *fp = &bp->fp[index];
6810
6811 client_stop.index = index;
6812 client_stop.cid = fp->cid;
6813 client_stop.cl_id = fp->cl_id;
6814 client_stop.pstate = &(fp->state);
6815 client_stop.poll = 0;
6816
6817 return bnx2x_stop_fw_client(bp, &client_stop);
6818}
6819
6820
34f80b04
EG		 6821static void bnx2x_reset_func(struct bnx2x *bp)
6822{
6823 int port = BP_PORT(bp);
6824 int func = BP_FUNC(bp);
f2e0899f 6825 int i;
523224a3 6826 int pfunc_offset_fp = offsetof(struct hc_sb_data, p_func) +
f2e0899f
DK		 6827 (CHIP_IS_E2(bp) ?
6828 offsetof(struct hc_status_block_data_e2, common) :
6829 offsetof(struct hc_status_block_data_e1x, common));
523224a3
DK		 6830 int pfunc_offset_sp = offsetof(struct hc_sp_status_block_data, p_func);
6831 int pfid_offset = offsetof(struct pci_entity, pf_id);
6832
6833 /* Disable the function in the FW */
6834 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
6835 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
6836 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
6837 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
6838
6839 /* FP SBs */
ec6ba945 6840 for_each_eth_queue(bp, i) {
523224a3
DK		 6841 struct bnx2x_fastpath *fp = &bp->fp[i];
6842 REG_WR8(bp,
6843 BAR_CSTRORM_INTMEM +
6844 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id)
6845 + pfunc_offset_fp + pfid_offset,
6846 HC_FUNCTION_DISABLED);
6847 }
6848
6849 /* SP SB */
6850 REG_WR8(bp,
6851 BAR_CSTRORM_INTMEM +
6852 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
6853 pfunc_offset_sp + pfid_offset,
6854 HC_FUNCTION_DISABLED);
6855
6856
6857 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
6858 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
6859 0);
34f80b04
EG		 6860
6861 /* Configure IGU */
f2e0899f
DK		 6862 if (bp->common.int_block == INT_BLOCK_HC) {
6863 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6864 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6865 } else {
6866 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6867 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6868 }
34f80b04 6869
37b091ba
MC		 6870#ifdef BCM_CNIC
6871 /* Disable Timer scan */
6872 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
6873 /*
6874 * Wait for at least 10ms and up to 2 second for the timers scan to
6875 * complete
6876 */
6877 for (i = 0; i < 200; i++) {
6878 msleep(10);
6879 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
6880 break;
6881 }
6882#endif
34f80b04 6883 /* Clear ILT */
f2e0899f
DK		 6884 bnx2x_clear_func_ilt(bp, func);
6885
6886 /* Timers workaround bug for E2: if this is vnic-3,
6887 * we need to set the entire ilt range for this timers.
6888 */
6889 if (CHIP_IS_E2(bp) && BP_VN(bp) == 3) {
6890 struct ilt_client_info ilt_cli;
6891 /* use dummy TM client */
6892 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6893 ilt_cli.start = 0;
6894 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6895 ilt_cli.client_num = ILT_CLIENT_TM;
6896
6897 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
6898 }
6899
6900 /* this assumes that reset_port() called before reset_func()*/
6901 if (CHIP_IS_E2(bp))
6902 bnx2x_pf_disable(bp);
523224a3
DK		 6903
6904 bp->dmae_ready = 0;
34f80b04
EG		 6905}
6906
6907static void bnx2x_reset_port(struct bnx2x *bp)
6908{
6909 int port = BP_PORT(bp);
6910 u32 val;
6911
6912 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6913
6914 /* Do not rcv packets to BRB */
6915 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
6916 /* Do not direct rcv packets that are not for MCP to the BRB */
6917 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
6918 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
6919
6920 /* Configure AEU */
6921 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
6922
6923 msleep(100);
6924 /* Check for BRB port occupancy */
6925 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
6926 if (val)
6927 DP(NETIF_MSG_IFDOWN,
33471629 6928 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 6929
6930 /* TODO: Close Doorbell port? */
6931}
6932
34f80b04
EG		 6933static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
6934{
6935 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
f2e0899f 6936 BP_ABS_FUNC(bp), reset_code);
34f80b04
EG		 6937
6938 switch (reset_code) {
6939 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
6940 bnx2x_reset_port(bp);
6941 bnx2x_reset_func(bp);
6942 bnx2x_reset_common(bp);
6943 break;
6944
6945 case FW_MSG_CODE_DRV_UNLOAD_PORT:
6946 bnx2x_reset_port(bp);
6947 bnx2x_reset_func(bp);
6948 break;
6949
6950 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
6951 bnx2x_reset_func(bp);
6952 break;
49d66772 6953
34f80b04
EG		 6954 default:
6955 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
6956 break;
6957 }
6958}
6959
ec6ba945
VZ		 6960#ifdef BCM_CNIC
6961static inline void bnx2x_del_fcoe_eth_macs(struct bnx2x *bp)
6962{
6963 if (bp->flags & FCOE_MACS_SET) {
6964 if (!IS_MF_SD(bp))
6965 bnx2x_set_fip_eth_mac_addr(bp, 0);
6966
6967 bnx2x_set_all_enode_macs(bp, 0);
6968
6969 bp->flags &= ~FCOE_MACS_SET;
6970 }
6971}
6972#endif
6973
9f6c9258 6974void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
a2fbb9ea 6975{
da5a662a 6976 int port = BP_PORT(bp);
a2fbb9ea 6977 u32 reset_code = 0;
da5a662a 6978 int i, cnt, rc;
a2fbb9ea 6979
555f6c78 6980 /* Wait until tx fastpath tasks complete */
ec6ba945 6981 for_each_tx_queue(bp, i) {
228241eb
ET		 6982 struct bnx2x_fastpath *fp = &bp->fp[i];
6983
34f80b04 6984 cnt = 1000;
e8b5fc51 6985 while (bnx2x_has_tx_work_unload(fp)) {
da5a662a 6986
34f80b04
EG		 6987 if (!cnt) {
6988 BNX2X_ERR("timeout waiting for queue[%d]\n",
6989 i);
6990#ifdef BNX2X_STOP_ON_ERROR
6991 bnx2x_panic();
6992 return -EBUSY;
6993#else
6994 break;
6995#endif
6996 }
6997 cnt--;
da5a662a 6998 msleep(1);
34f80b04 6999 }
228241eb 7000 }
da5a662a
VZ		 7001 /* Give HW time to discard old tx messages */
7002 msleep(1);
a2fbb9ea 7003
6e30dd4e 7004 bnx2x_set_eth_mac(bp, 0);
65abd74d 7005
6e30dd4e 7006 bnx2x_invalidate_uc_list(bp);
3101c2bc 7007
6e30dd4e
VZ		 7008 if (CHIP_IS_E1(bp))
7009 bnx2x_invalidate_e1_mc_list(bp);
7010 else {
7011 bnx2x_invalidate_e1h_mc_list(bp);
7012 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3101c2bc 7013 }
523224a3 7014
993ac7b5 7015#ifdef BCM_CNIC
ec6ba945 7016 bnx2x_del_fcoe_eth_macs(bp);
993ac7b5 7017#endif
3101c2bc 7018
65abd74d
YG		 7019 if (unload_mode == UNLOAD_NORMAL)
7020 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7021
7d0446c2 7022 else if (bp->flags & NO_WOL_FLAG)
65abd74d 7023 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 7024
7d0446c2 7025 else if (bp->wol) {
65abd74d
YG		 7026 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7027 u8 *mac_addr = bp->dev->dev_addr;
7028 u32 val;
7029 /* The mac address is written to entries 1-4 to
7030 preserve entry 0 which is used by the PMF */
7031 u8 entry = (BP_E1HVN(bp) + 1)*8;
7032
7033 val = (mac_addr[0] << 8) | mac_addr[1];
7034 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7035
7036 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7037 (mac_addr[4] << 8) | mac_addr[5];
7038 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7039
7040 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7041
7042 } else
7043 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 7044
34f80b04
EG		 7045 /* Close multi and leading connections
7046 Completions for ramrods are collected in a synchronous way */
523224a3
DK		 7047 for_each_queue(bp, i)
7048
7049 if (bnx2x_stop_client(bp, i))
7050#ifdef BNX2X_STOP_ON_ERROR
7051 return;
7052#else
228241eb 7053 goto unload_error;
523224a3 7054#endif
a2fbb9ea 7055
523224a3 7056 rc = bnx2x_func_stop(bp);
da5a662a 7057 if (rc) {
523224a3 7058 BNX2X_ERR("Function stop failed!\n");
da5a662a 7059#ifdef BNX2X_STOP_ON_ERROR
523224a3 7060 return;
da5a662a
VZ		 7061#else
7062 goto unload_error;
34f80b04 7063#endif
228241eb 7064 }
523224a3 7065#ifndef BNX2X_STOP_ON_ERROR
228241eb 7066unload_error:
523224a3 7067#endif
34f80b04 7068 if (!BP_NOMCP(bp))
a22f0788 7069 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04 7070 else {
f2e0899f
DK		 7071 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7072 "%d, %d, %d\n", BP_PATH(bp),
7073 load_count[BP_PATH(bp)][0],
7074 load_count[BP_PATH(bp)][1],
7075 load_count[BP_PATH(bp)][2]);
7076 load_count[BP_PATH(bp)][0]--;
7077 load_count[BP_PATH(bp)][1 + port]--;
7078 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7079 "%d, %d, %d\n", BP_PATH(bp),
7080 load_count[BP_PATH(bp)][0], load_count[BP_PATH(bp)][1],
7081 load_count[BP_PATH(bp)][2]);
7082 if (load_count[BP_PATH(bp)][0] == 0)
34f80b04 7083 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
f2e0899f 7084 else if (load_count[BP_PATH(bp)][1 + port] == 0)
34f80b04
EG		 7085 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7086 else
7087 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7088 }
a2fbb9ea 7089
34f80b04
EG		 7090 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
7091 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
7092 bnx2x__link_reset(bp);
a2fbb9ea 7093
523224a3
DK		 7094 /* Disable HW interrupts, NAPI */
7095 bnx2x_netif_stop(bp, 1);
7096
7097 /* Release IRQs */
d6214d7a 7098 bnx2x_free_irq(bp);
523224a3 7099
a2fbb9ea 7100 /* Reset the chip */
228241eb 7101 bnx2x_reset_chip(bp, reset_code);
a2fbb9ea
ET		 7102
7103 /* Report UNLOAD_DONE to MCP */
34f80b04 7104 if (!BP_NOMCP(bp))
a22f0788 7105 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
356e2385 7106
72fd0718
VZ		 7107}
7108
9f6c9258 7109void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 7110{
7111 u32 val;
7112
7113 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7114
7115 if (CHIP_IS_E1(bp)) {
7116 int port = BP_PORT(bp);
7117 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7118 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7119
7120 val = REG_RD(bp, addr);
7121 val &= ~(0x300);
7122 REG_WR(bp, addr, val);
7123 } else if (CHIP_IS_E1H(bp)) {
7124 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7125 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7126 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7127 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7128 }
7129}
7130
72fd0718
VZ		 7131/* Close gates #2, #3 and #4: */
7132static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7133{
7134 u32 val, addr;
7135
7136 /* Gates #2 and #4a are closed/opened for "not E1" only */
7137 if (!CHIP_IS_E1(bp)) {
7138 /* #4 */
7139 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);
7140 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
7141 close ? (val | 0x1) : (val & (~(u32)1)));
7142 /* #2 */
7143 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);
7144 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
7145 close ? (val | 0x1) : (val & (~(u32)1)));
7146 }
7147
7148 /* #3 */
7149 addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
7150 val = REG_RD(bp, addr);
7151 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1)));
7152
7153 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7154 close ? "closing" : "opening");
7155 mmiowb();
7156}
7157
7158#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7159
7160static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7161{
7162 /* Do some magic... */
7163 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7164 *magic_val = val & SHARED_MF_CLP_MAGIC;
7165 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7166}
7167
e8920674
DK		 7168/**
7169 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 7170 *
e8920674
DK		 7171 * @bp: driver handle
7172 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 7173 */
7174static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7175{
7176 /* Restore the `magic' bit value... */
72fd0718
VZ		 7177 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7178 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7179 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7180}
7181
f85582f8 7182/**
e8920674 7183 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 7184 *
e8920674
DK		 7185 * @bp: driver handle
7186 * @magic_val: old value of 'magic' bit.
7187 *
7188 * Takes care of CLP configurations.
72fd0718
VZ		 7189 */
7190static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7191{
7192 u32 shmem;
7193 u32 validity_offset;
7194
7195 DP(NETIF_MSG_HW, "Starting\n");
7196
7197 /* Set `magic' bit in order to save MF config */
7198 if (!CHIP_IS_E1(bp))
7199 bnx2x_clp_reset_prep(bp, magic_val);
7200
7201 /* Get shmem offset */
7202 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7203 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7204
7205 /* Clear validity map flags */
7206 if (shmem > 0)
7207 REG_WR(bp, shmem + validity_offset, 0);
7208}
7209
7210#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7211#define MCP_ONE_TIMEOUT 100 /* 100 ms */
7212
e8920674
DK		 7213/**
7214 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 7215 *
e8920674 7216 * @bp: driver handle
72fd0718
VZ		 7217 */
7218static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7219{
7220 /* special handling for emulation and FPGA,
7221 wait 10 times longer */
7222 if (CHIP_REV_IS_SLOW(bp))
7223 msleep(MCP_ONE_TIMEOUT*10);
7224 else
7225 msleep(MCP_ONE_TIMEOUT);
7226}
7227
1b6e2ceb
DK		 7228/*
7229 * initializes bp->common.shmem_base and waits for validity signature to appear
7230 */
7231static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 7232{
1b6e2ceb
DK		 7233 int cnt = 0;
7234 u32 val = 0;
72fd0718 7235
1b6e2ceb
DK		 7236 do {
7237 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7238 if (bp->common.shmem_base) {
7239 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7240 if (val & SHR_MEM_VALIDITY_MB)
7241 return 0;
7242 }
72fd0718 7243
1b6e2ceb 7244 bnx2x_mcp_wait_one(bp);
72fd0718 7245
1b6e2ceb 7246 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 7247
1b6e2ceb 7248 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 7249
1b6e2ceb
DK		 7250 return -ENODEV;
7251}
72fd0718 7252
1b6e2ceb
DK		 7253static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7254{
7255 int rc = bnx2x_init_shmem(bp);
72fd0718 7256
72fd0718
VZ		 7257 /* Restore the `magic' bit value */
7258 if (!CHIP_IS_E1(bp))
7259 bnx2x_clp_reset_done(bp, magic_val);
7260
7261 return rc;
7262}
7263
7264static void bnx2x_pxp_prep(struct bnx2x *bp)
7265{
7266 if (!CHIP_IS_E1(bp)) {
7267 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7268 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7269 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
7270 mmiowb();
7271 }
7272}
7273
7274/*
7275 * Reset the whole chip except for:
7276 * - PCIE core
7277 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7278 * one reset bit)
7279 * - IGU
7280 * - MISC (including AEU)
7281 * - GRC
7282 * - RBCN, RBCP
7283 */
7284static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7285{
7286 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7287
7288 not_reset_mask1 =
7289 MISC_REGISTERS_RESET_REG_1_RST_HC |
7290 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7291 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7292
7293 not_reset_mask2 =
7294 MISC_REGISTERS_RESET_REG_2_RST_MDIO |
7295 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7296 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7297 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7298 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7299 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7300 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7301 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7302
7303 reset_mask1 = 0xffffffff;
7304
7305 if (CHIP_IS_E1(bp))
7306 reset_mask2 = 0xffff;
7307 else
7308 reset_mask2 = 0x1ffff;
7309
7310 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7311 reset_mask1 & (~not_reset_mask1));
7312 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7313 reset_mask2 & (~not_reset_mask2));
7314
7315 barrier();
7316 mmiowb();
7317
7318 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7319 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7320 mmiowb();
7321}
7322
7323static int bnx2x_process_kill(struct bnx2x *bp)
7324{
7325 int cnt = 1000;
7326 u32 val = 0;
7327 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7328
7329
7330 /* Empty the Tetris buffer, wait for 1s */
7331 do {
7332 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7333 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7334 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7335 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7336 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7337 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7338 ((port_is_idle_0 & 0x1) == 0x1) &&
7339 ((port_is_idle_1 & 0x1) == 0x1) &&
7340 (pgl_exp_rom2 == 0xffffffff))
7341 break;
7342 msleep(1);
7343 } while (cnt-- > 0);
7344
7345 if (cnt <= 0) {
7346 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7347 " are still"
7348 " outstanding read requests after 1s!\n");
7349 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7350 " port_is_idle_0=0x%08x,"
7351 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7352 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7353 pgl_exp_rom2);
7354 return -EAGAIN;
7355 }
7356
7357 barrier();
7358
7359 /* Close gates #2, #3 and #4 */
7360 bnx2x_set_234_gates(bp, true);
7361
7362 /* TBD: Indicate that "process kill" is in progress to MCP */
7363
7364 /* Clear "unprepared" bit */
7365 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7366 barrier();
7367
7368 /* Make sure all is written to the chip before the reset */
7369 mmiowb();
7370
7371 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7372 * PSWHST, GRC and PSWRD Tetris buffer.
7373 */
7374 msleep(1);
7375
7376 /* Prepare to chip reset: */
7377 /* MCP */
7378 bnx2x_reset_mcp_prep(bp, &val);
7379
7380 /* PXP */
7381 bnx2x_pxp_prep(bp);
7382 barrier();
7383
7384 /* reset the chip */
7385 bnx2x_process_kill_chip_reset(bp);
7386 barrier();
7387
7388 /* Recover after reset: */
7389 /* MCP */
7390 if (bnx2x_reset_mcp_comp(bp, val))
7391 return -EAGAIN;
7392
7393 /* PXP */
7394 bnx2x_pxp_prep(bp);
7395
7396 /* Open the gates #2, #3 and #4 */
7397 bnx2x_set_234_gates(bp, false);
7398
7399 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7400 * reset state, re-enable attentions. */
7401
a2fbb9ea
ET		 7402 return 0;
7403}
7404
72fd0718
VZ		 7405static int bnx2x_leader_reset(struct bnx2x *bp)
7406{
7407 int rc = 0;
7408 /* Try to recover after the failure */
7409 if (bnx2x_process_kill(bp)) {
7410 printk(KERN_ERR "%s: Something bad had happen! Aii!\n",
7411 bp->dev->name);
7412 rc = -EAGAIN;
7413 goto exit_leader_reset;
7414 }
7415
7416 /* Clear "reset is in progress" bit and update the driver state */
7417 bnx2x_set_reset_done(bp);
7418 bp->recovery_state = BNX2X_RECOVERY_DONE;
7419
7420exit_leader_reset:
7421 bp->is_leader = 0;
7422 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
7423 smp_wmb();
7424 return rc;
7425}
7426
72fd0718
VZ		 7427/* Assumption: runs under rtnl lock. This together with the fact
7428 * that it's called only from bnx2x_reset_task() ensure that it
7429 * will never be called when netif_running(bp->dev) is false.
7430 */
7431static void bnx2x_parity_recover(struct bnx2x *bp)
7432{
7433 DP(NETIF_MSG_HW, "Handling parity\n");
7434 while (1) {
7435 switch (bp->recovery_state) {
7436 case BNX2X_RECOVERY_INIT:
7437 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7438 /* Try to get a LEADER_LOCK HW lock */
7439 if (bnx2x_trylock_hw_lock(bp,
7440 HW_LOCK_RESOURCE_RESERVED_08))
7441 bp->is_leader = 1;
7442
7443 /* Stop the driver */
7444 /* If interface has been removed - break */
7445 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7446 return;
7447
7448 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7449 /* Ensure "is_leader" and "recovery_state"
7450 * update values are seen on other CPUs
7451 */
7452 smp_wmb();
7453 break;
7454
7455 case BNX2X_RECOVERY_WAIT:
7456 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7457 if (bp->is_leader) {
7458 u32 load_counter = bnx2x_get_load_cnt(bp);
7459 if (load_counter) {
7460 /* Wait until all other functions get
7461 * down.
7462 */
7463 schedule_delayed_work(&bp->reset_task,
7464 HZ/10);
7465 return;
7466 } else {
7467 /* If all other functions got down -
7468 * try to bring the chip back to
7469 * normal. In any case it's an exit
7470 * point for a leader.
7471 */
7472 if (bnx2x_leader_reset(bp) ||
7473 bnx2x_nic_load(bp, LOAD_NORMAL)) {
7474 printk(KERN_ERR"%s: Recovery "
7475 "has failed. Power cycle is "
7476 "needed.\n", bp->dev->name);
7477 /* Disconnect this device */
7478 netif_device_detach(bp->dev);
7479 /* Block ifup for all function
7480 * of this ASIC until
7481 * "process kill" or power
7482 * cycle.
7483 */
7484 bnx2x_set_reset_in_progress(bp);
7485 /* Shut down the power */
7486 bnx2x_set_power_state(bp,
7487 PCI_D3hot);
7488 return;
7489 }
7490
7491 return;
7492 }
7493 } else { /* non-leader */
7494 if (!bnx2x_reset_is_done(bp)) {
7495 /* Try to get a LEADER_LOCK HW lock as
7496 * long as a former leader may have
7497 * been unloaded by the user or
7498 * released a leadership by another
7499 * reason.
7500 */
7501 if (bnx2x_trylock_hw_lock(bp,
7502 HW_LOCK_RESOURCE_RESERVED_08)) {
7503 /* I'm a leader now! Restart a
7504 * switch case.
7505 */
7506 bp->is_leader = 1;
7507 break;
7508 }
7509
7510 schedule_delayed_work(&bp->reset_task,
7511 HZ/10);
7512 return;
7513
7514 } else { /* A leader has completed
7515 * the "process kill". It's an exit
7516 * point for a non-leader.
7517 */
7518 bnx2x_nic_load(bp, LOAD_NORMAL);
7519 bp->recovery_state =
7520 BNX2X_RECOVERY_DONE;
7521 smp_wmb();
7522 return;
7523 }
7524 }
7525 default:
7526 return;
7527 }
7528 }
7529}
7530
7531/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
7532 * scheduled on a general queue in order to prevent a dead lock.
7533 */
34f80b04
EG		 7534static void bnx2x_reset_task(struct work_struct *work)
7535{
72fd0718 7536 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
34f80b04
EG		 7537
7538#ifdef BNX2X_STOP_ON_ERROR
7539 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7540 " so reset not done to allow debug dump,\n"
72fd0718 7541 KERN_ERR " you will need to reboot when done\n");
34f80b04
EG		 7542 return;
7543#endif
7544
7545 rtnl_lock();
7546
7547 if (!netif_running(bp->dev))
7548 goto reset_task_exit;
7549
72fd0718
VZ		 7550 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
7551 bnx2x_parity_recover(bp);
7552 else {
7553 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7554 bnx2x_nic_load(bp, LOAD_NORMAL);
7555 }
34f80b04
EG		 7556
7557reset_task_exit:
7558 rtnl_unlock();
7559}
7560
a2fbb9ea
ET		 7561/* end of nic load/unload */
7562
a2fbb9ea
ET		 7563/*
7564 * Init service functions
7565 */
7566
8d96286a 7567static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 7568{
7569 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
7570 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
7571 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 7572}
7573
f2e0899f 7574static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 7575{
f2e0899f 7576 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 7577
7578 /* Flush all outstanding writes */
7579 mmiowb();
7580
7581 /* Pretend to be function 0 */
7582 REG_WR(bp, reg, 0);
f2e0899f 7583 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 7584
7585 /* From now we are in the "like-E1" mode */
7586 bnx2x_int_disable(bp);
7587
7588 /* Flush all outstanding writes */
7589 mmiowb();
7590
f2e0899f
DK		 7591 /* Restore the original function */
7592 REG_WR(bp, reg, BP_ABS_FUNC(bp));
7593 REG_RD(bp, reg);
f1ef27ef
EG		 7594}
7595
f2e0899f 7596static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 7597{
f2e0899f 7598 if (CHIP_IS_E1(bp))
f1ef27ef 7599 bnx2x_int_disable(bp);
f2e0899f
DK		 7600 else
7601 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 7602}
7603
34f80b04
EG		 7604static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
7605{
7606 u32 val;
7607
7608 /* Check if there is any driver already loaded */
7609 val = REG_RD(bp, MISC_REG_UNPREPARED);
7610 if (val == 0x1) {
7611 /* Check if it is the UNDI driver
7612 * UNDI driver initializes CID offset for normal bell to 0x7
7613 */
4a37fb66 7614 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 7615 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
7616 if (val == 0x7) {
7617 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
f2e0899f
DK		 7618 /* save our pf_num */
7619 int orig_pf_num = bp->pf_num;
da5a662a
VZ		 7620 u32 swap_en;
7621 u32 swap_val;
34f80b04 7622
b4661739
EG		 7623 /* clear the UNDI indication */
7624 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
7625
34f80b04
EG		 7626 BNX2X_DEV_INFO("UNDI is active! reset device\n");
7627
7628 /* try unload UNDI on port 0 */
f2e0899f 7629 bp->pf_num = 0;
da5a662a 7630 bp->fw_seq =
f2e0899f 7631 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 7632 DRV_MSG_SEQ_NUMBER_MASK);
a22f0788 7633 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 7634
7635 /* if UNDI is loaded on the other port */
7636 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7637
da5a662a 7638 /* send "DONE" for previous unload */
a22f0788
YR		 7639 bnx2x_fw_command(bp,
7640 DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 7641
7642 /* unload UNDI on port 1 */
f2e0899f 7643 bp->pf_num = 1;
da5a662a 7644 bp->fw_seq =
f2e0899f 7645 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a
VZ		 7646 DRV_MSG_SEQ_NUMBER_MASK);
7647 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7648
a22f0788 7649 bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 7650 }
7651
b4661739
EG		 7652 /* now it's safe to release the lock */
7653 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7654
f2e0899f 7655 bnx2x_undi_int_disable(bp);
da5a662a
VZ		 7656
7657 /* close input traffic and wait for it */
7658 /* Do not rcv packets to BRB */
7659 REG_WR(bp,
7660 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
7661 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
7662 /* Do not direct rcv packets that are not for MCP to
7663 * the BRB */
7664 REG_WR(bp,
7665 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
7666 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7667 /* clear AEU */
7668 REG_WR(bp,
7669 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7670 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
7671 msleep(10);
7672
7673 /* save NIG port swap info */
7674 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7675 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
34f80b04
EG		 7676 /* reset device */
7677 REG_WR(bp,
7678 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
da5a662a 7679 0xd3ffffff);
34f80b04
EG		 7680 REG_WR(bp,
7681 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7682 0x1403);
da5a662a
VZ		 7683 /* take the NIG out of reset and restore swap values */
7684 REG_WR(bp,
7685 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7686 MISC_REGISTERS_RESET_REG_1_RST_NIG);
7687 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
7688 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
7689
7690 /* send unload done to the MCP */
a22f0788 7691 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 7692
7693 /* restore our func and fw_seq */
f2e0899f 7694 bp->pf_num = orig_pf_num;
da5a662a 7695 bp->fw_seq =
f2e0899f 7696 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 7697 DRV_MSG_SEQ_NUMBER_MASK);
b4661739
EG		 7698 } else
7699 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 7700 }
7701}
7702
7703static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7704{
7705 u32 val, val2, val3, val4, id;
72ce58c3 7706 u16 pmc;
34f80b04
EG		 7707
7708 /* Get the chip revision id and number. */
7709 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7710 val = REG_RD(bp, MISC_REG_CHIP_NUM);
7711 id = ((val & 0xffff) << 16);
7712 val = REG_RD(bp, MISC_REG_CHIP_REV);
7713 id |= ((val & 0xf) << 12);
7714 val = REG_RD(bp, MISC_REG_CHIP_METAL);
7715 id |= ((val & 0xff) << 4);
5a40e08e 7716 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 7717 id |= (val & 0xf);
7718 bp->common.chip_id = id;
523224a3
DK		 7719
7720 /* Set doorbell size */
7721 bp->db_size = (1 << BNX2X_DB_SHIFT);
7722
f2e0899f
DK		 7723 if (CHIP_IS_E2(bp)) {
7724 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
7725 if ((val & 1) == 0)
7726 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
7727 else
7728 val = (val >> 1) & 1;
7729 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
7730 "2_PORT_MODE");
7731 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
7732 CHIP_2_PORT_MODE;
7733
7734 if (CHIP_MODE_IS_4_PORT(bp))
7735 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
7736 else
7737 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
7738 } else {
7739 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
7740 bp->pfid = bp->pf_num; /* 0..7 */
7741 }
7742
523224a3
DK		 7743 /*
7744 * set base FW non-default (fast path) status block id, this value is
7745 * used to initialize the fw_sb_id saved on the fp/queue structure to
7746 * determine the id used by the FW.
7747 */
f2e0899f
DK		 7748 if (CHIP_IS_E1x(bp))
7749 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x;
7750 else /* E2 */
7751 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E2;
7752
7753 bp->link_params.chip_id = bp->common.chip_id;
7754 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 7755
1c06328c
EG		 7756 val = (REG_RD(bp, 0x2874) & 0x55);
7757 if ((bp->common.chip_id & 0x1) ||
7758 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
7759 bp->flags |= ONE_PORT_FLAG;
7760 BNX2X_DEV_INFO("single port device\n");
7761 }
7762
34f80b04
EG		 7763 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7764 bp->common.flash_size = (NVRAM_1MB_SIZE <<
7765 (val & MCPR_NVM_CFG4_FLASH_SIZE));
7766 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7767 bp->common.flash_size, bp->common.flash_size);
7768
1b6e2ceb
DK		 7769 bnx2x_init_shmem(bp);
7770
f2e0899f
DK		 7771 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
7772 MISC_REG_GENERIC_CR_1 :
7773 MISC_REG_GENERIC_CR_0));
1b6e2ceb 7774
34f80b04 7775 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 7776 bp->link_params.shmem2_base = bp->common.shmem2_base;
2691d51d
EG		 7777 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
7778 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 7779
f2e0899f 7780 if (!bp->common.shmem_base) {
34f80b04
EG		 7781 BNX2X_DEV_INFO("MCP not active\n");
7782 bp->flags |= NO_MCP_FLAG;
7783 return;
7784 }
7785
34f80b04 7786 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 7787 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 7788
7789 bp->link_params.hw_led_mode = ((bp->common.hw_config &
7790 SHARED_HW_CFG_LED_MODE_MASK) >>
7791 SHARED_HW_CFG_LED_MODE_SHIFT);
7792
c2c8b03e
EG		 7793 bp->link_params.feature_config_flags = 0;
7794 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
7795 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
7796 bp->link_params.feature_config_flags |=
7797 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7798 else
7799 bp->link_params.feature_config_flags &=
7800 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7801
34f80b04
EG		 7802 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
7803 bp->common.bc_ver = val;
7804 BNX2X_DEV_INFO("bc_ver %X\n", val);
7805 if (val < BNX2X_BC_VER) {
7806 /* for now only warn
7807 * later we might need to enforce this */
f2e0899f
DK		 7808 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
7809 "please upgrade BC\n", BNX2X_BC_VER, val);
34f80b04 7810 }
4d295db0 7811 bp->link_params.feature_config_flags |=
a22f0788 7812 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 7813 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
7814
a22f0788
YR		 7815 bp->link_params.feature_config_flags |=
7816 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
7817 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
72ce58c3 7818
f9a3ebbe
DK		 7819 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
7820 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
7821
72ce58c3 7822 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 7823 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 7824
7825 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
7826 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
7827 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
7828 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
7829
cdaa7cb8
VZ		 7830 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
7831 val, val2, val3, val4);
34f80b04
EG		 7832}
7833
f2e0899f
DK		 7834#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
7835#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
7836
7837static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
7838{
7839 int pfid = BP_FUNC(bp);
7840 int vn = BP_E1HVN(bp);
7841 int igu_sb_id;
7842 u32 val;
7843 u8 fid;
7844
7845 bp->igu_base_sb = 0xff;
7846 bp->igu_sb_cnt = 0;
7847 if (CHIP_INT_MODE_IS_BC(bp)) {
7848 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
ec6ba945 7849 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 7850
7851 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
7852 FP_SB_MAX_E1x;
7853
7854 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
7855 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
7856
7857 return;
7858 }
7859
7860 /* IGU in normal mode - read CAM */
7861 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
7862 igu_sb_id++) {
7863 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
7864 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
7865 continue;
7866 fid = IGU_FID(val);
7867 if ((fid & IGU_FID_ENCODE_IS_PF)) {
7868 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
7869 continue;
7870 if (IGU_VEC(val) == 0)
7871 /* default status block */
7872 bp->igu_dsb_id = igu_sb_id;
7873 else {
7874 if (bp->igu_base_sb == 0xff)
7875 bp->igu_base_sb = igu_sb_id;
7876 bp->igu_sb_cnt++;
7877 }
7878 }
7879 }
ec6ba945
VZ		 7880 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
7881 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 7882 if (bp->igu_sb_cnt == 0)
7883 BNX2X_ERR("CAM configuration error\n");
7884}
7885
34f80b04
EG		 7886static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
7887 u32 switch_cfg)
a2fbb9ea 7888{
a22f0788
YR		 7889 int cfg_size = 0, idx, port = BP_PORT(bp);
7890
7891 /* Aggregation of supported attributes of all external phys */
7892 bp->port.supported[0] = 0;
7893 bp->port.supported[1] = 0;
b7737c9b
YR		 7894 switch (bp->link_params.num_phys) {
7895 case 1:
a22f0788
YR		 7896 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
7897 cfg_size = 1;
7898 break;
b7737c9b 7899 case 2:
a22f0788
YR		 7900 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
7901 cfg_size = 1;
7902 break;
7903 case 3:
7904 if (bp->link_params.multi_phy_config &
7905 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
7906 bp->port.supported[1] =
7907 bp->link_params.phy[EXT_PHY1].supported;
7908 bp->port.supported[0] =
7909 bp->link_params.phy[EXT_PHY2].supported;
7910 } else {
7911 bp->port.supported[0] =
7912 bp->link_params.phy[EXT_PHY1].supported;
7913 bp->port.supported[1] =
7914 bp->link_params.phy[EXT_PHY2].supported;
7915 }
7916 cfg_size = 2;
7917 break;
b7737c9b 7918 }
a2fbb9ea 7919
a22f0788 7920 if (!(bp->port.supported[0] || bp->port.supported[1])) {
b7737c9b 7921 BNX2X_ERR("NVRAM config error. BAD phy config."
a22f0788 7922 "PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 7923 SHMEM_RD(bp,
a22f0788
YR		 7924 dev_info.port_hw_config[port].external_phy_config),
7925 SHMEM_RD(bp,
7926 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 7927 return;
f85582f8 7928 }
a2fbb9ea 7929
b7737c9b
YR		 7930 switch (switch_cfg) {
7931 case SWITCH_CFG_1G:
34f80b04
EG		 7932 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
7933 port*0x10);
7934 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a2fbb9ea
ET		 7935 break;
7936
7937 case SWITCH_CFG_10G:
34f80b04
EG		 7938 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
7939 port*0x18);
7940 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a2fbb9ea
ET		 7941 break;
7942
7943 default:
7944 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
a22f0788 7945 bp->port.link_config[0]);
a2fbb9ea
ET		 7946 return;
7947 }
a22f0788
YR		 7948 /* mask what we support according to speed_cap_mask per configuration */
7949 for (idx = 0; idx < cfg_size; idx++) {
7950 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 7951 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 7952 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 7953
a22f0788 7954 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 7955 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 7956 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 7957
a22f0788 7958 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 7959 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 7960 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 7961
a22f0788 7962 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 7963 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 7964 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 7965
a22f0788 7966 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 7967 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 7968 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 7969 SUPPORTED_1000baseT_Full);
a2fbb9ea 7970
a22f0788 7971 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 7972 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 7973 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 7974
a22f0788 7975 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 7976 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 7977 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
7978
7979 }
a2fbb9ea 7980
a22f0788
YR		 7981 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
7982 bp->port.supported[1]);
a2fbb9ea
ET		 7983}
7984
34f80b04 7985static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 7986{
a22f0788
YR		 7987 u32 link_config, idx, cfg_size = 0;
7988 bp->port.advertising[0] = 0;
7989 bp->port.advertising[1] = 0;
7990 switch (bp->link_params.num_phys) {
7991 case 1:
7992 case 2:
7993 cfg_size = 1;
7994 break;
7995 case 3:
7996 cfg_size = 2;
7997 break;
7998 }
7999 for (idx = 0; idx < cfg_size; idx++) {
8000 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8001 link_config = bp->port.link_config[idx];
8002 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 8003 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 8004 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8005 bp->link_params.req_line_speed[idx] =
8006 SPEED_AUTO_NEG;
8007 bp->port.advertising[idx] |=
8008 bp->port.supported[idx];
f85582f8
DK		 8009 } else {
8010 /* force 10G, no AN */
a22f0788
YR		 8011 bp->link_params.req_line_speed[idx] =
8012 SPEED_10000;
8013 bp->port.advertising[idx] |=
8014 (ADVERTISED_10000baseT_Full |
f85582f8 8015 ADVERTISED_FIBRE);
a22f0788 8016 continue;
f85582f8
DK		 8017 }
8018 break;
a2fbb9ea 8019
f85582f8 8020 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 8021 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8022 bp->link_params.req_line_speed[idx] =
8023 SPEED_10;
8024 bp->port.advertising[idx] |=
8025 (ADVERTISED_10baseT_Full |
f85582f8
DK		 8026 ADVERTISED_TP);
8027 } else {
8028 BNX2X_ERROR("NVRAM config error. "
8029 "Invalid link_config 0x%x"
8030 " speed_cap_mask 0x%x\n",
8031 link_config,
a22f0788 8032 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8033 return;
8034 }
8035 break;
a2fbb9ea 8036
f85582f8 8037 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 8038 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8039 bp->link_params.req_line_speed[idx] =
8040 SPEED_10;
8041 bp->link_params.req_duplex[idx] =
8042 DUPLEX_HALF;
8043 bp->port.advertising[idx] |=
8044 (ADVERTISED_10baseT_Half |
f85582f8
DK		 8045 ADVERTISED_TP);
8046 } else {
8047 BNX2X_ERROR("NVRAM config error. "
8048 "Invalid link_config 0x%x"
8049 " speed_cap_mask 0x%x\n",
8050 link_config,
8051 bp->link_params.speed_cap_mask[idx]);
8052 return;
8053 }
8054 break;
a2fbb9ea 8055
f85582f8
DK		 8056 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8057 if (bp->port.supported[idx] &
8058 SUPPORTED_100baseT_Full) {
a22f0788
YR		 8059 bp->link_params.req_line_speed[idx] =
8060 SPEED_100;
8061 bp->port.advertising[idx] |=
8062 (ADVERTISED_100baseT_Full |
f85582f8
DK		 8063 ADVERTISED_TP);
8064 } else {
8065 BNX2X_ERROR("NVRAM config error. "
8066 "Invalid link_config 0x%x"
8067 " speed_cap_mask 0x%x\n",
8068 link_config,
8069 bp->link_params.speed_cap_mask[idx]);
8070 return;
8071 }
8072 break;
a2fbb9ea 8073
f85582f8
DK		 8074 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8075 if (bp->port.supported[idx] &
8076 SUPPORTED_100baseT_Half) {
8077 bp->link_params.req_line_speed[idx] =
8078 SPEED_100;
8079 bp->link_params.req_duplex[idx] =
8080 DUPLEX_HALF;
a22f0788
YR		 8081 bp->port.advertising[idx] |=
8082 (ADVERTISED_100baseT_Half |
f85582f8
DK		 8083 ADVERTISED_TP);
8084 } else {
8085 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8086 "Invalid link_config 0x%x"
8087 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8088 link_config,
8089 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8090 return;
8091 }
8092 break;
a2fbb9ea 8093
f85582f8 8094 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 8095 if (bp->port.supported[idx] &
8096 SUPPORTED_1000baseT_Full) {
8097 bp->link_params.req_line_speed[idx] =
8098 SPEED_1000;
8099 bp->port.advertising[idx] |=
8100 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 8101 ADVERTISED_TP);
8102 } else {
8103 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8104 "Invalid link_config 0x%x"
8105 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8106 link_config,
8107 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8108 return;
8109 }
8110 break;
a2fbb9ea 8111
f85582f8 8112 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 8113 if (bp->port.supported[idx] &
8114 SUPPORTED_2500baseX_Full) {
8115 bp->link_params.req_line_speed[idx] =
8116 SPEED_2500;
8117 bp->port.advertising[idx] |=
8118 (ADVERTISED_2500baseX_Full |
34f80b04 8119 ADVERTISED_TP);
f85582f8
DK		 8120 } else {
8121 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8122 "Invalid link_config 0x%x"
8123 " speed_cap_mask 0x%x\n",
a22f0788 8124 link_config,
f85582f8
DK		 8125 bp->link_params.speed_cap_mask[idx]);
8126 return;
8127 }
8128 break;
a2fbb9ea 8129
f85582f8
DK		 8130 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8131 case PORT_FEATURE_LINK_SPEED_10G_KX4:
8132 case PORT_FEATURE_LINK_SPEED_10G_KR:
a22f0788
YR		 8133 if (bp->port.supported[idx] &
8134 SUPPORTED_10000baseT_Full) {
8135 bp->link_params.req_line_speed[idx] =
8136 SPEED_10000;
8137 bp->port.advertising[idx] |=
8138 (ADVERTISED_10000baseT_Full |
34f80b04 8139 ADVERTISED_FIBRE);
f85582f8
DK		 8140 } else {
8141 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8142 "Invalid link_config 0x%x"
8143 " speed_cap_mask 0x%x\n",
a22f0788 8144 link_config,
f85582f8
DK		 8145 bp->link_params.speed_cap_mask[idx]);
8146 return;
8147 }
8148 break;
a2fbb9ea 8149
f85582f8
DK		 8150 default:
8151 BNX2X_ERROR("NVRAM config error. "
8152 "BAD link speed link_config 0x%x\n",
8153 link_config);
8154 bp->link_params.req_line_speed[idx] =
8155 SPEED_AUTO_NEG;
8156 bp->port.advertising[idx] =
8157 bp->port.supported[idx];
8158 break;
8159 }
a2fbb9ea 8160
a22f0788 8161 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 8162 PORT_FEATURE_FLOW_CONTROL_MASK);
a22f0788
YR		 8163 if ((bp->link_params.req_flow_ctrl[idx] ==
8164 BNX2X_FLOW_CTRL_AUTO) &&
8165 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8166 bp->link_params.req_flow_ctrl[idx] =
8167 BNX2X_FLOW_CTRL_NONE;
8168 }
a2fbb9ea 8169
a22f0788
YR		 8170 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8171 " 0x%x advertising 0x%x\n",
8172 bp->link_params.req_line_speed[idx],
8173 bp->link_params.req_duplex[idx],
8174 bp->link_params.req_flow_ctrl[idx],
8175 bp->port.advertising[idx]);
8176 }
a2fbb9ea
ET		 8177}
8178
e665bfda
MC		 8179static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8180{
8181 mac_hi = cpu_to_be16(mac_hi);
8182 mac_lo = cpu_to_be32(mac_lo);
8183 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8184 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8185}
8186
34f80b04 8187static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 8188{
34f80b04 8189 int port = BP_PORT(bp);
589abe3a 8190 u32 config;
6f38ad93 8191 u32 ext_phy_type, ext_phy_config;
a2fbb9ea 8192
c18487ee 8193 bp->link_params.bp = bp;
34f80b04 8194 bp->link_params.port = port;
c18487ee 8195
c18487ee 8196 bp->link_params.lane_config =
a2fbb9ea 8197 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 8198
a22f0788 8199 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 8200 SHMEM_RD(bp,
8201 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 8202 bp->link_params.speed_cap_mask[1] =
8203 SHMEM_RD(bp,
8204 dev_info.port_hw_config[port].speed_capability_mask2);
8205 bp->port.link_config[0] =
a2fbb9ea
ET		 8206 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8207
a22f0788
YR		 8208 bp->port.link_config[1] =
8209 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 8210
a22f0788
YR		 8211 bp->link_params.multi_phy_config =
8212 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 8213 /* If the device is capable of WoL, set the default state according
8214 * to the HW
8215 */
4d295db0 8216 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 8217 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8218 (config & PORT_FEATURE_WOL_ENABLED));
8219
f85582f8 8220 BNX2X_DEV_INFO("lane_config 0x%08x "
a22f0788 8221 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 8222 bp->link_params.lane_config,
a22f0788
YR		 8223 bp->link_params.speed_cap_mask[0],
8224 bp->port.link_config[0]);
a2fbb9ea 8225
a22f0788 8226 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 8227 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 8228 bnx2x_phy_probe(&bp->link_params);
c18487ee 8229 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 8230
8231 bnx2x_link_settings_requested(bp);
8232
01cd4528
EG		 8233 /*
8234 * If connected directly, work with the internal PHY, otherwise, work
8235 * with the external PHY
8236 */
b7737c9b
YR		 8237 ext_phy_config =
8238 SHMEM_RD(bp,
8239 dev_info.port_hw_config[port].external_phy_config);
8240 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 8241 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 8242 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 8243
8244 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8245 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8246 bp->mdio.prtad =
b7737c9b 8247 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d
YR		 8248
8249 /*
8250 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
8251 * In MF mode, it is set to cover self test cases
8252 */
8253 if (IS_MF(bp))
8254 bp->port.need_hw_lock = 1;
8255 else
8256 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
8257 bp->common.shmem_base,
8258 bp->common.shmem2_base);
0793f83f 8259}
01cd4528 8260
2ba45142
VZ		 8261#ifdef BCM_CNIC
8262static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
8263{
8264 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8265 drv_lic_key[BP_PORT(bp)].max_iscsi_conn);
8266 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8267 drv_lic_key[BP_PORT(bp)].max_fcoe_conn);
8268
8269 /* Get the number of maximum allowed iSCSI and FCoE connections */
8270 bp->cnic_eth_dev.max_iscsi_conn =
8271 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
8272 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
8273
8274 bp->cnic_eth_dev.max_fcoe_conn =
8275 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
8276 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
8277
8278 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
8279 bp->cnic_eth_dev.max_iscsi_conn,
8280 bp->cnic_eth_dev.max_fcoe_conn);
8281
8282 /* If mamimum allowed number of connections is zero -
8283 * disable the feature.
8284 */
8285 if (!bp->cnic_eth_dev.max_iscsi_conn)
8286 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8287
8288 if (!bp->cnic_eth_dev.max_fcoe_conn)
8289 bp->flags |= NO_FCOE_FLAG;
8290}
8291#endif
8292
0793f83f
DK		 8293static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8294{
8295 u32 val, val2;
8296 int func = BP_ABS_FUNC(bp);
8297 int port = BP_PORT(bp);
2ba45142
VZ		 8298#ifdef BCM_CNIC
8299 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
8300 u8 *fip_mac = bp->fip_mac;
8301#endif
0793f83f
DK		 8302
8303 if (BP_NOMCP(bp)) {
8304 BNX2X_ERROR("warning: random MAC workaround active\n");
8305 random_ether_addr(bp->dev->dev_addr);
8306 } else if (IS_MF(bp)) {
8307 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8308 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8309 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8310 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8311 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
37b091ba
MC		 8312
8313#ifdef BCM_CNIC
2ba45142
VZ		 8314 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
8315 * FCoE MAC then the appropriate feature should be disabled.
8316 */
0793f83f
DK		 8317 if (IS_MF_SI(bp)) {
8318 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8319 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8320 val2 = MF_CFG_RD(bp, func_ext_config[func].
8321 iscsi_mac_addr_upper);
8322 val = MF_CFG_RD(bp, func_ext_config[func].
8323 iscsi_mac_addr_lower);
2ba45142
VZ		 8324 BNX2X_DEV_INFO("Read iSCSI MAC: "
8325 "0x%x:0x%04x\n", val2, val);
8326 bnx2x_set_mac_buf(iscsi_mac, val, val2);
2ba45142
VZ		 8327 } else
8328 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8329
8330 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
8331 val2 = MF_CFG_RD(bp, func_ext_config[func].
8332 fcoe_mac_addr_upper);
8333 val = MF_CFG_RD(bp, func_ext_config[func].
8334 fcoe_mac_addr_lower);
8335 BNX2X_DEV_INFO("Read FCoE MAC to "
8336 "0x%x:0x%04x\n", val2, val);
8337 bnx2x_set_mac_buf(fip_mac, val, val2);
8338
2ba45142
VZ		 8339 } else
8340 bp->flags |= NO_FCOE_FLAG;
0793f83f 8341 }
37b091ba 8342#endif
0793f83f
DK		 8343 } else {
8344 /* in SF read MACs from port configuration */
8345 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8346 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8347 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8348
8349#ifdef BCM_CNIC
8350 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8351 iscsi_mac_upper);
8352 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8353 iscsi_mac_lower);
2ba45142 8354 bnx2x_set_mac_buf(iscsi_mac, val, val2);
0793f83f
DK		 8355#endif
8356 }
8357
8358 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8359 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8360
ec6ba945 8361#ifdef BCM_CNIC
2ba45142 8362 /* Set the FCoE MAC in modes other then MF_SI */
ec6ba945
VZ		 8363 if (!CHIP_IS_E1x(bp)) {
8364 if (IS_MF_SD(bp))
2ba45142
VZ		 8365 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
8366 else if (!IS_MF(bp))
8367 memcpy(fip_mac, iscsi_mac, ETH_ALEN);
ec6ba945 8368 }
426b9241
DK		 8369
8370 /* Disable iSCSI if MAC configuration is
8371 * invalid.
8372 */
8373 if (!is_valid_ether_addr(iscsi_mac)) {
8374 bp->flags |= NO_ISCSI_FLAG;
8375 memset(iscsi_mac, 0, ETH_ALEN);
8376 }
8377
8378 /* Disable FCoE if MAC configuration is
8379 * invalid.
8380 */
8381 if (!is_valid_ether_addr(fip_mac)) {
8382 bp->flags |= NO_FCOE_FLAG;
8383 memset(bp->fip_mac, 0, ETH_ALEN);
8384 }
ec6ba945 8385#endif
34f80b04
EG		 8386}
8387
8388static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8389{
0793f83f 8390 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 8391 int vn;
0793f83f 8392 u32 val = 0;
34f80b04 8393 int rc = 0;
a2fbb9ea 8394
34f80b04 8395 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 8396
f2e0899f
DK		 8397 if (CHIP_IS_E1x(bp)) {
8398 bp->common.int_block = INT_BLOCK_HC;
8399
8400 bp->igu_dsb_id = DEF_SB_IGU_ID;
8401 bp->igu_base_sb = 0;
ec6ba945
VZ		 8402 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8403 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 8404 } else {
8405 bp->common.int_block = INT_BLOCK_IGU;
8406 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8407 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8408 DP(NETIF_MSG_PROBE, "IGU Backward Compatible Mode\n");
8409 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8410 } else
8411 DP(NETIF_MSG_PROBE, "IGU Normal Mode\n");
523224a3 8412
f2e0899f
DK		 8413 bnx2x_get_igu_cam_info(bp);
8414
8415 }
8416 DP(NETIF_MSG_PROBE, "igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n",
8417 bp->igu_dsb_id, bp->igu_base_sb, bp->igu_sb_cnt);
8418
8419 /*
8420 * Initialize MF configuration
8421 */
523224a3 8422
fb3bff17
DK		 8423 bp->mf_ov = 0;
8424 bp->mf_mode = 0;
f2e0899f 8425 vn = BP_E1HVN(bp);
0793f83f 8426
f2e0899f 8427 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
0793f83f
DK		 8428 DP(NETIF_MSG_PROBE,
8429 "shmem2base 0x%x, size %d, mfcfg offset %d\n",
8430 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8431 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
f2e0899f
DK		 8432 if (SHMEM2_HAS(bp, mf_cfg_addr))
8433 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8434 else
8435 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 8436 offsetof(struct shmem_region, func_mb) +
8437 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 8438 /*
8439 * get mf configuration:
25985edc 8440 * 1. existence of MF configuration
0793f83f
DK		 8441 * 2. MAC address must be legal (check only upper bytes)
8442 * for Switch-Independent mode;
8443 * OVLAN must be legal for Switch-Dependent mode
8444 * 3. SF_MODE configures specific MF mode
8445 */
8446 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8447 /* get mf configuration */
8448 val = SHMEM_RD(bp,
8449 dev_info.shared_feature_config.config);
8450 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8451
8452 switch (val) {
8453 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8454 val = MF_CFG_RD(bp, func_mf_config[func].
8455 mac_upper);
8456 /* check for legal mac (upper bytes)*/
8457 if (val != 0xffff) {
8458 bp->mf_mode = MULTI_FUNCTION_SI;
8459 bp->mf_config[vn] = MF_CFG_RD(bp,
8460 func_mf_config[func].config);
8461 } else
8462 DP(NETIF_MSG_PROBE, "illegal MAC "
8463 "address for SI\n");
8464 break;
8465 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8466 /* get OV configuration */
8467 val = MF_CFG_RD(bp,
8468 func_mf_config[FUNC_0].e1hov_tag);
8469 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8470
8471 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8472 bp->mf_mode = MULTI_FUNCTION_SD;
8473 bp->mf_config[vn] = MF_CFG_RD(bp,
8474 func_mf_config[func].config);
8475 } else
8476 DP(NETIF_MSG_PROBE, "illegal OV for "
8477 "SD\n");
8478 break;
8479 default:
8480 /* Unknown configuration: reset mf_config */
8481 bp->mf_config[vn] = 0;
25985edc 8482 DP(NETIF_MSG_PROBE, "Unknown MF mode 0x%x\n",
0793f83f
DK		 8483 val);
8484 }
8485 }
a2fbb9ea 8486
2691d51d 8487 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 8488 IS_MF(bp) ? "multi" : "single");
2691d51d 8489
0793f83f
DK		 8490 switch (bp->mf_mode) {
8491 case MULTI_FUNCTION_SD:
8492 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
8493 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 8494 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 8495 bp->mf_ov = val;
0793f83f
DK		 8496 BNX2X_DEV_INFO("MF OV for func %d is %d"
8497 " (0x%04x)\n", func,
8498 bp->mf_ov, bp->mf_ov);
2691d51d 8499 } else {
0793f83f
DK		 8500 BNX2X_ERR("No valid MF OV for func %d,"
8501 " aborting\n", func);
34f80b04
EG		 8502 rc = -EPERM;
8503 }
0793f83f
DK		 8504 break;
8505 case MULTI_FUNCTION_SI:
8506 BNX2X_DEV_INFO("func %d is in MF "
8507 "switch-independent mode\n", func);
8508 break;
8509 default:
8510 if (vn) {
8511 BNX2X_ERR("VN %d in single function mode,"
8512 " aborting\n", vn);
2691d51d
EG		 8513 rc = -EPERM;
8514 }
0793f83f 8515 break;
34f80b04 8516 }
0793f83f 8517
34f80b04 8518 }
a2fbb9ea 8519
f2e0899f
DK		 8520 /* adjust igu_sb_cnt to MF for E1x */
8521 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 8522 bp->igu_sb_cnt /= E1HVN_MAX;
8523
f2e0899f
DK		 8524 /*
8525 * adjust E2 sb count: to be removed when FW will support
8526 * more then 16 L2 clients
8527 */
8528#define MAX_L2_CLIENTS 16
8529 if (CHIP_IS_E2(bp))
8530 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8531 MAX_L2_CLIENTS / (IS_MF(bp) ? 4 : 1));
8532
34f80b04
EG		 8533 if (!BP_NOMCP(bp)) {
8534 bnx2x_get_port_hwinfo(bp);
8535
f2e0899f
DK		 8536 bp->fw_seq =
8537 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
8538 DRV_MSG_SEQ_NUMBER_MASK);
34f80b04
EG		 8539 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
8540 }
8541
0793f83f
DK		 8542 /* Get MAC addresses */
8543 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 8544
2ba45142
VZ		 8545#ifdef BCM_CNIC
8546 bnx2x_get_cnic_info(bp);
8547#endif
8548
34f80b04
EG		 8549 return rc;
8550}
8551
34f24c7f
VZ		 8552static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
8553{
8554 int cnt, i, block_end, rodi;
8555 char vpd_data[BNX2X_VPD_LEN+1];
8556 char str_id_reg[VENDOR_ID_LEN+1];
8557 char str_id_cap[VENDOR_ID_LEN+1];
8558 u8 len;
8559
8560 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
8561 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
8562
8563 if (cnt < BNX2X_VPD_LEN)
8564 goto out_not_found;
8565
8566 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
8567 PCI_VPD_LRDT_RO_DATA);
8568 if (i < 0)
8569 goto out_not_found;
8570
8571
8572 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
8573 pci_vpd_lrdt_size(&vpd_data[i]);
8574
8575 i += PCI_VPD_LRDT_TAG_SIZE;
8576
8577 if (block_end > BNX2X_VPD_LEN)
8578 goto out_not_found;
8579
8580 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8581 PCI_VPD_RO_KEYWORD_MFR_ID);
8582 if (rodi < 0)
8583 goto out_not_found;
8584
8585 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8586
8587 if (len != VENDOR_ID_LEN)
8588 goto out_not_found;
8589
8590 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8591
8592 /* vendor specific info */
8593 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
8594 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
8595 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
8596 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
8597
8598 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8599 PCI_VPD_RO_KEYWORD_VENDOR0);
8600 if (rodi >= 0) {
8601 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8602
8603 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8604
8605 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
8606 memcpy(bp->fw_ver, &vpd_data[rodi], len);
8607 bp->fw_ver[len] = ' ';
8608 }
8609 }
8610 return;
8611 }
8612out_not_found:
8613 return;
8614}
8615
34f80b04
EG		 8616static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8617{
f2e0899f 8618 int func;
87942b46 8619 int timer_interval;
34f80b04
EG		 8620 int rc;
8621
34f80b04 8622 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 8623 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 8624 spin_lock_init(&bp->stats_lock);
993ac7b5
MC		 8625#ifdef BCM_CNIC
8626 mutex_init(&bp->cnic_mutex);
8627#endif
a2fbb9ea 8628
1cf167f2 8629 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
72fd0718 8630 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
34f80b04
EG		 8631
8632 rc = bnx2x_get_hwinfo(bp);
8633
523224a3
DK		 8634 if (!rc)
8635 rc = bnx2x_alloc_mem_bp(bp);
8636
34f24c7f 8637 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 8638
8639 func = BP_FUNC(bp);
8640
34f80b04
EG		 8641 /* need to reset chip if undi was active */
8642 if (!BP_NOMCP(bp))
8643 bnx2x_undi_unload(bp);
8644
8645 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 8646 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 8647
8648 if (BP_NOMCP(bp) && (func == 0))
cdaa7cb8
VZ		 8649 dev_err(&bp->pdev->dev, "MCP disabled, "
8650 "must load devices in order!\n");
34f80b04 8651
555f6c78 8652 bp->multi_mode = multi_mode;
5d7cd496 8653 bp->int_mode = int_mode;
555f6c78 8654
7a9b2557
VZ		 8655 /* Set TPA flags */
8656 if (disable_tpa) {
8657 bp->flags &= ~TPA_ENABLE_FLAG;
8658 bp->dev->features &= ~NETIF_F_LRO;
8659 } else {
8660 bp->flags |= TPA_ENABLE_FLAG;
8661 bp->dev->features |= NETIF_F_LRO;
8662 }
5d7cd496 8663 bp->disable_tpa = disable_tpa;
7a9b2557 8664
a18f5128
EG		 8665 if (CHIP_IS_E1(bp))
8666 bp->dropless_fc = 0;
8667 else
8668 bp->dropless_fc = dropless_fc;
8669
8d5726c4 8670 bp->mrrs = mrrs;
7a9b2557 8671
34f80b04 8672 bp->tx_ring_size = MAX_TX_AVAIL;
34f80b04 8673
7d323bfd 8674 /* make sure that the numbers are in the right granularity */
523224a3
DK		 8675 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
8676 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 8677
87942b46
EG		 8678 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
8679 bp->current_interval = (poll ? poll : timer_interval);
34f80b04
EG		 8680
8681 init_timer(&bp->timer);
8682 bp->timer.expires = jiffies + bp->current_interval;
8683 bp->timer.data = (unsigned long) bp;
8684 bp->timer.function = bnx2x_timer;
8685
785b9b1a 8686 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
e4901dde
VZ		 8687 bnx2x_dcbx_init_params(bp);
8688
34f80b04 8689 return rc;
a2fbb9ea
ET		 8690}
8691
a2fbb9ea 8692
de0c62db
DK		 8693/****************************************************************************
8694* General service functions
8695****************************************************************************/
a2fbb9ea 8696
bb2a0f7a 8697/* called with rtnl_lock */
a2fbb9ea
ET		 8698static int bnx2x_open(struct net_device *dev)
8699{
8700 struct bnx2x *bp = netdev_priv(dev);
8701
6eccabb3
EG		 8702 netif_carrier_off(dev);
8703
a2fbb9ea
ET		 8704 bnx2x_set_power_state(bp, PCI_D0);
8705
72fd0718
VZ		 8706 if (!bnx2x_reset_is_done(bp)) {
8707 do {
8708 /* Reset MCP mail box sequence if there is on going
8709 * recovery
8710 */
8711 bp->fw_seq = 0;
8712
8713 /* If it's the first function to load and reset done
8714 * is still not cleared it may mean that. We don't
8715 * check the attention state here because it may have
8716 * already been cleared by a "common" reset but we
8717 * shell proceed with "process kill" anyway.
8718 */
8719 if ((bnx2x_get_load_cnt(bp) == 0) &&
8720 bnx2x_trylock_hw_lock(bp,
8721 HW_LOCK_RESOURCE_RESERVED_08) &&
8722 (!bnx2x_leader_reset(bp))) {
8723 DP(NETIF_MSG_HW, "Recovered in open\n");
8724 break;
8725 }
8726
8727 bnx2x_set_power_state(bp, PCI_D3hot);
8728
8729 printk(KERN_ERR"%s: Recovery flow hasn't been properly"
8730 " completed yet. Try again later. If u still see this"
8731 " message after a few retries then power cycle is"
8732 " required.\n", bp->dev->name);
8733
8734 return -EAGAIN;
8735 } while (0);
8736 }
8737
8738 bp->recovery_state = BNX2X_RECOVERY_DONE;
8739
bb2a0f7a 8740 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 8741}
8742
bb2a0f7a 8743/* called with rtnl_lock */
a2fbb9ea
ET		 8744static int bnx2x_close(struct net_device *dev)
8745{
a2fbb9ea
ET		 8746 struct bnx2x *bp = netdev_priv(dev);
8747
8748 /* Unload the driver, release IRQs */
bb2a0f7a 8749 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
d3dbfee0 8750 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 8751
8752 return 0;
8753}
8754
6e30dd4e
VZ		 8755#define E1_MAX_UC_LIST 29
8756#define E1H_MAX_UC_LIST 30
8757#define E2_MAX_UC_LIST 14
8758static inline u8 bnx2x_max_uc_list(struct bnx2x *bp)
8759{
8760 if (CHIP_IS_E1(bp))
8761 return E1_MAX_UC_LIST;
8762 else if (CHIP_IS_E1H(bp))
8763 return E1H_MAX_UC_LIST;
8764 else
8765 return E2_MAX_UC_LIST;
8766}
8767
8768
8769static inline u8 bnx2x_uc_list_cam_offset(struct bnx2x *bp)
8770{
8771 if (CHIP_IS_E1(bp))
8772 /* CAM Entries for Port0:
8773 * 0 - prim ETH MAC
8774 * 1 - BCAST MAC
8775 * 2 - iSCSI L2 ring ETH MAC
8776 * 3-31 - UC MACs
8777 *
8778 * Port1 entries are allocated the same way starting from
8779 * entry 32.
8780 */
8781 return 3 + 32 * BP_PORT(bp);
8782 else if (CHIP_IS_E1H(bp)) {
8783 /* CAM Entries:
8784 * 0-7 - prim ETH MAC for each function
8785 * 8-15 - iSCSI L2 ring ETH MAC for each function
8786 * 16 till 255 UC MAC lists for each function
8787 *
8788 * Remark: There is no FCoE support for E1H, thus FCoE related
8789 * MACs are not considered.
8790 */
8791 return E1H_FUNC_MAX * (CAM_ISCSI_ETH_LINE + 1) +
8792 bnx2x_max_uc_list(bp) * BP_FUNC(bp);
8793 } else {
8794 /* CAM Entries (there is a separate CAM per engine):
8795 * 0-4 - prim ETH MAC for each function
8796 * 4-7 - iSCSI L2 ring ETH MAC for each function
8797 * 8-11 - FIP ucast L2 MAC for each function
8798 * 12-15 - ALL_ENODE_MACS mcast MAC for each function
8799 * 16 till 71 UC MAC lists for each function
8800 */
8801 u8 func_idx =
8802 (CHIP_MODE_IS_4_PORT(bp) ? BP_FUNC(bp) : BP_VN(bp));
8803
8804 return E2_FUNC_MAX * (CAM_MAX_PF_LINE + 1) +
8805 bnx2x_max_uc_list(bp) * func_idx;
8806 }
8807}
8808
8809/* set uc list, do not wait as wait implies sleep and
8810 * set_rx_mode can be invoked from non-sleepable context.
8811 *
8812 * Instead we use the same ramrod data buffer each time we need
8813 * to configure a list of addresses, and use the fact that the
8814 * list of MACs is changed in an incremental way and that the
8815 * function is called under the netif_addr_lock. A temporary
8816 * inconsistent CAM configuration (possible in case of very fast
8817 * sequence of add/del/add on the host side) will shortly be
8818 * restored by the handler of the last ramrod.
8819 */
8820static int bnx2x_set_uc_list(struct bnx2x *bp)
8821{
8822 int i = 0, old;
8823 struct net_device *dev = bp->dev;
8824 u8 offset = bnx2x_uc_list_cam_offset(bp);
8825 struct netdev_hw_addr *ha;
8826 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);
8827 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);
8828
8829 if (netdev_uc_count(dev) > bnx2x_max_uc_list(bp))
8830 return -EINVAL;
8831
8832 netdev_for_each_uc_addr(ha, dev) {
8833 /* copy mac */
8834 config_cmd->config_table[i].msb_mac_addr =
8835 swab16(*(u16 *)&bnx2x_uc_addr(ha)[0]);
8836 config_cmd->config_table[i].middle_mac_addr =
8837 swab16(*(u16 *)&bnx2x_uc_addr(ha)[2]);
8838 config_cmd->config_table[i].lsb_mac_addr =
8839 swab16(*(u16 *)&bnx2x_uc_addr(ha)[4]);
8840
8841 config_cmd->config_table[i].vlan_id = 0;
8842 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
8843 config_cmd->config_table[i].clients_bit_vector =
8844 cpu_to_le32(1 << BP_L_ID(bp));
8845
8846 SET_FLAG(config_cmd->config_table[i].flags,
8847 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8848 T_ETH_MAC_COMMAND_SET);
8849
8850 DP(NETIF_MSG_IFUP,
8851 "setting UCAST[%d] (%04x:%04x:%04x)\n", i,
8852 config_cmd->config_table[i].msb_mac_addr,
8853 config_cmd->config_table[i].middle_mac_addr,
8854 config_cmd->config_table[i].lsb_mac_addr);
8855
8856 i++;
8857
8858 /* Set uc MAC in NIG */
8859 bnx2x_set_mac_in_nig(bp, 1, bnx2x_uc_addr(ha),
8860 LLH_CAM_ETH_LINE + i);
8861 }
8862 old = config_cmd->hdr.length;
8863 if (old > i) {
8864 for (; i < old; i++) {
8865 if (CAM_IS_INVALID(config_cmd->
8866 config_table[i])) {
8867 /* already invalidated */
8868 break;
8869 }
8870 /* invalidate */
8871 SET_FLAG(config_cmd->config_table[i].flags,
8872 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8873 T_ETH_MAC_COMMAND_INVALIDATE);
8874 }
8875 }
8876
8877 wmb();
8878
8879 config_cmd->hdr.length = i;
8880 config_cmd->hdr.offset = offset;
8881 config_cmd->hdr.client_id = 0xff;
8882 /* Mark that this ramrod doesn't use bp->set_mac_pending for
8883 * synchronization.
8884 */
8885 config_cmd->hdr.echo = 0;
8886
8887 mb();
8888
8889 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
8890 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
8891
8892}
8893
8894void bnx2x_invalidate_uc_list(struct bnx2x *bp)
8895{
8896 int i;
8897 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);
8898 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);
8899 int ramrod_flags = WAIT_RAMROD_COMMON;
8900 u8 offset = bnx2x_uc_list_cam_offset(bp);
8901 u8 max_list_size = bnx2x_max_uc_list(bp);
8902
8903 for (i = 0; i < max_list_size; i++) {
8904 SET_FLAG(config_cmd->config_table[i].flags,
8905 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8906 T_ETH_MAC_COMMAND_INVALIDATE);
8907 bnx2x_set_mac_in_nig(bp, 0, NULL, LLH_CAM_ETH_LINE + 1 + i);
8908 }
8909
8910 wmb();
8911
8912 config_cmd->hdr.length = max_list_size;
8913 config_cmd->hdr.offset = offset;
8914 config_cmd->hdr.client_id = 0xff;
8915 /* We'll wait for a completion this time... */
8916 config_cmd->hdr.echo = 1;
8917
8918 bp->set_mac_pending = 1;
8919
8920 mb();
8921
8922 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
8923 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
8924
8925 /* Wait for a completion */
8926 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
8927 ramrod_flags);
8928
8929}
8930
8931static inline int bnx2x_set_mc_list(struct bnx2x *bp)
8932{
8933 /* some multicasts */
8934 if (CHIP_IS_E1(bp)) {
8935 return bnx2x_set_e1_mc_list(bp);
8936 } else { /* E1H and newer */
8937 return bnx2x_set_e1h_mc_list(bp);
8938 }
8939}
8940
f5372251 8941/* called with netif_tx_lock from dev_mcast.c */
9f6c9258 8942void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 8943{
8944 struct bnx2x *bp = netdev_priv(dev);
8945 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04
EG		 8946
8947 if (bp->state != BNX2X_STATE_OPEN) {
8948 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
8949 return;
8950 }
8951
8952 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
8953
8954 if (dev->flags & IFF_PROMISC)
8955 rx_mode = BNX2X_RX_MODE_PROMISC;
6e30dd4e 8956 else if (dev->flags & IFF_ALLMULTI)
34f80b04 8957 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6e30dd4e
VZ		 8958 else {
8959 /* some multicasts */
8960 if (bnx2x_set_mc_list(bp))
8961 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 8962
6e30dd4e
VZ		 8963 /* some unicasts */
8964 if (bnx2x_set_uc_list(bp))
8965 rx_mode = BNX2X_RX_MODE_PROMISC;
34f80b04
EG		 8966 }
8967
8968 bp->rx_mode = rx_mode;
8969 bnx2x_set_storm_rx_mode(bp);
8970}
8971
c18487ee 8972/* called with rtnl_lock */
01cd4528
EG		 8973static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
8974 int devad, u16 addr)
a2fbb9ea 8975{
01cd4528
EG		 8976 struct bnx2x *bp = netdev_priv(netdev);
8977 u16 value;
8978 int rc;
a2fbb9ea 8979
01cd4528
EG		 8980 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
8981 prtad, devad, addr);
a2fbb9ea 8982
01cd4528
EG		 8983 /* The HW expects different devad if CL22 is used */
8984 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 8985
01cd4528 8986 bnx2x_acquire_phy_lock(bp);
e10bc84d 8987 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 8988 bnx2x_release_phy_lock(bp);
8989 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 8990
01cd4528
EG		 8991 if (!rc)
8992 rc = value;
8993 return rc;
8994}
a2fbb9ea 8995
01cd4528
EG		 8996/* called with rtnl_lock */
8997static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
8998 u16 addr, u16 value)
8999{
9000 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 9001 int rc;
9002
9003 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
9004 " value 0x%x\n", prtad, devad, addr, value);
9005
01cd4528
EG		 9006 /* The HW expects different devad if CL22 is used */
9007 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 9008
01cd4528 9009 bnx2x_acquire_phy_lock(bp);
e10bc84d 9010 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 9011 bnx2x_release_phy_lock(bp);
9012 return rc;
9013}
c18487ee 9014
01cd4528
EG		 9015/* called with rtnl_lock */
9016static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9017{
9018 struct bnx2x *bp = netdev_priv(dev);
9019 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 9020
01cd4528
EG		 9021 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
9022 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 9023
01cd4528
EG		 9024 if (!netif_running(dev))
9025 return -EAGAIN;
9026
9027 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 9028}
9029
257ddbda 9030#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 9031static void poll_bnx2x(struct net_device *dev)
9032{
9033 struct bnx2x *bp = netdev_priv(dev);
9034
9035 disable_irq(bp->pdev->irq);
9036 bnx2x_interrupt(bp->pdev->irq, dev);
9037 enable_irq(bp->pdev->irq);
9038}
9039#endif
9040
c64213cd
SH		 9041static const struct net_device_ops bnx2x_netdev_ops = {
9042 .ndo_open = bnx2x_open,
9043 .ndo_stop = bnx2x_close,
9044 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 9045 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 9046 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd
SH		 9047 .ndo_set_mac_address = bnx2x_change_mac_addr,
9048 .ndo_validate_addr = eth_validate_addr,
9049 .ndo_do_ioctl = bnx2x_ioctl,
9050 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 9051 .ndo_fix_features = bnx2x_fix_features,
9052 .ndo_set_features = bnx2x_set_features,
c64213cd 9053 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 9054#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 9055 .ndo_poll_controller = poll_bnx2x,
9056#endif
9057};
9058
34f80b04
EG		 9059static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
9060 struct net_device *dev)
a2fbb9ea
ET		 9061{
9062 struct bnx2x *bp;
9063 int rc;
9064
9065 SET_NETDEV_DEV(dev, &pdev->dev);
9066 bp = netdev_priv(dev);
9067
34f80b04
EG		 9068 bp->dev = dev;
9069 bp->pdev = pdev;
a2fbb9ea 9070 bp->flags = 0;
f2e0899f 9071 bp->pf_num = PCI_FUNC(pdev->devfn);
a2fbb9ea
ET		 9072
9073 rc = pci_enable_device(pdev);
9074 if (rc) {
cdaa7cb8
VZ		 9075 dev_err(&bp->pdev->dev,
9076 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 9077 goto err_out;
9078 }
9079
9080 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 9081 dev_err(&bp->pdev->dev,
9082 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 9083 rc = -ENODEV;
9084 goto err_out_disable;
9085 }
9086
9087 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 9088 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
9089 " base address, aborting\n");
a2fbb9ea
ET		 9090 rc = -ENODEV;
9091 goto err_out_disable;
9092 }
9093
34f80b04
EG		 9094 if (atomic_read(&pdev->enable_cnt) == 1) {
9095 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9096 if (rc) {
cdaa7cb8
VZ		 9097 dev_err(&bp->pdev->dev,
9098 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 9099 goto err_out_disable;
9100 }
a2fbb9ea 9101
34f80b04
EG		 9102 pci_set_master(pdev);
9103 pci_save_state(pdev);
9104 }
a2fbb9ea
ET		 9105
9106 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9107 if (bp->pm_cap == 0) {
cdaa7cb8
VZ		 9108 dev_err(&bp->pdev->dev,
9109 "Cannot find power management capability, aborting\n");
a2fbb9ea
ET		 9110 rc = -EIO;
9111 goto err_out_release;
9112 }
9113
9114 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9115 if (bp->pcie_cap == 0) {
cdaa7cb8
VZ		 9116 dev_err(&bp->pdev->dev,
9117 "Cannot find PCI Express capability, aborting\n");
a2fbb9ea
ET		 9118 rc = -EIO;
9119 goto err_out_release;
9120 }
9121
1a983142 9122 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) == 0) {
a2fbb9ea 9123 bp->flags |= USING_DAC_FLAG;
1a983142 9124 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)) != 0) {
cdaa7cb8
VZ		 9125 dev_err(&bp->pdev->dev, "dma_set_coherent_mask"
9126 " failed, aborting\n");
a2fbb9ea
ET		 9127 rc = -EIO;
9128 goto err_out_release;
9129 }
9130
1a983142 9131 } else if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
cdaa7cb8
VZ		 9132 dev_err(&bp->pdev->dev,
9133 "System does not support DMA, aborting\n");
a2fbb9ea
ET		 9134 rc = -EIO;
9135 goto err_out_release;
9136 }
9137
34f80b04
EG		 9138 dev->mem_start = pci_resource_start(pdev, 0);
9139 dev->base_addr = dev->mem_start;
9140 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 9141
9142 dev->irq = pdev->irq;
9143
275f165f 9144 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 9145 if (!bp->regview) {
cdaa7cb8
VZ		 9146 dev_err(&bp->pdev->dev,
9147 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 9148 rc = -ENOMEM;
9149 goto err_out_release;
9150 }
9151
34f80b04 9152 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
523224a3 9153 min_t(u64, BNX2X_DB_SIZE(bp),
34f80b04 9154 pci_resource_len(pdev, 2)));
a2fbb9ea 9155 if (!bp->doorbells) {
cdaa7cb8
VZ		 9156 dev_err(&bp->pdev->dev,
9157 "Cannot map doorbell space, aborting\n");
a2fbb9ea
ET		 9158 rc = -ENOMEM;
9159 goto err_out_unmap;
9160 }
9161
9162 bnx2x_set_power_state(bp, PCI_D0);
9163
34f80b04
EG		 9164 /* clean indirect addresses */
9165 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9166 PCICFG_VENDOR_ID_OFFSET);
9167 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9168 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9169 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9170 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
a2fbb9ea 9171
72fd0718
VZ		 9172 /* Reset the load counter */
9173 bnx2x_clear_load_cnt(bp);
9174
34f80b04 9175 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 9176
c64213cd 9177 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 9178 bnx2x_set_ethtool_ops(dev);
5316bc0b 9179
66371c44
MM		 9180 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9181 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
9182 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
9183
9184 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9185 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
9186
9187 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
5316bc0b 9188 if (bp->flags & USING_DAC_FLAG)
66371c44 9189 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 9190
538dd2e3
MB		 9191 /* Add Loopback capability to the device */
9192 dev->hw_features |= NETIF_F_LOOPBACK;
9193
98507672 9194#ifdef BCM_DCBNL
785b9b1a
SR		 9195 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
9196#endif
9197
01cd4528
EG		 9198 /* get_port_hwinfo() will set prtad and mmds properly */
9199 bp->mdio.prtad = MDIO_PRTAD_NONE;
9200 bp->mdio.mmds = 0;
9201 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9202 bp->mdio.dev = dev;
9203 bp->mdio.mdio_read = bnx2x_mdio_read;
9204 bp->mdio.mdio_write = bnx2x_mdio_write;
9205
a2fbb9ea
ET		 9206 return 0;
9207
9208err_out_unmap:
9209 if (bp->regview) {
9210 iounmap(bp->regview);
9211 bp->regview = NULL;
9212 }
a2fbb9ea
ET		 9213 if (bp->doorbells) {
9214 iounmap(bp->doorbells);
9215 bp->doorbells = NULL;
9216 }
9217
9218err_out_release:
34f80b04
EG		 9219 if (atomic_read(&pdev->enable_cnt) == 1)
9220 pci_release_regions(pdev);
a2fbb9ea
ET		 9221
9222err_out_disable:
9223 pci_disable_device(pdev);
9224 pci_set_drvdata(pdev, NULL);
9225
9226err_out:
9227 return rc;
9228}
9229
37f9ce62
EG		 9230static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9231 int *width, int *speed)
25047950
ET		 9232{
9233 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9234
37f9ce62 9235 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 9236
37f9ce62
EG		 9237 /* return value of 1=2.5GHz 2=5GHz */
9238 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 9239}
37f9ce62 9240
6891dd25 9241static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 9242{
37f9ce62 9243 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 9244 struct bnx2x_fw_file_hdr *fw_hdr;
9245 struct bnx2x_fw_file_section *sections;
94a78b79 9246 u32 offset, len, num_ops;
37f9ce62 9247 u16 *ops_offsets;
94a78b79 9248 int i;
37f9ce62 9249 const u8 *fw_ver;
94a78b79
VZ		 9250
9251 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9252 return -EINVAL;
9253
9254 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9255 sections = (struct bnx2x_fw_file_section *)fw_hdr;
9256
9257 /* Make sure none of the offsets and sizes make us read beyond
9258 * the end of the firmware data */
9259 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9260 offset = be32_to_cpu(sections[i].offset);
9261 len = be32_to_cpu(sections[i].len);
9262 if (offset + len > firmware->size) {
cdaa7cb8
VZ		 9263 dev_err(&bp->pdev->dev,
9264 "Section %d length is out of bounds\n", i);
94a78b79
VZ		 9265 return -EINVAL;
9266 }
9267 }
9268
9269 /* Likewise for the init_ops offsets */
9270 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9271 ops_offsets = (u16 *)(firmware->data + offset);
9272 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9273
9274 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9275 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
cdaa7cb8
VZ		 9276 dev_err(&bp->pdev->dev,
9277 "Section offset %d is out of bounds\n", i);
94a78b79
VZ		 9278 return -EINVAL;
9279 }
9280 }
9281
9282 /* Check FW version */
9283 offset = be32_to_cpu(fw_hdr->fw_version.offset);
9284 fw_ver = firmware->data + offset;
9285 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9286 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9287 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9288 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
cdaa7cb8
VZ		 9289 dev_err(&bp->pdev->dev,
9290 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
94a78b79
VZ		 9291 fw_ver[0], fw_ver[1], fw_ver[2],
9292 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9293 BCM_5710_FW_MINOR_VERSION,
9294 BCM_5710_FW_REVISION_VERSION,
9295 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 9296 return -EINVAL;
94a78b79
VZ		 9297 }
9298
9299 return 0;
9300}
9301
ab6ad5a4 9302static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 9303{
ab6ad5a4
EG		 9304 const __be32 *source = (const __be32 *)_source;
9305 u32 *target = (u32 *)_target;
94a78b79 9306 u32 i;
94a78b79
VZ		 9307
9308 for (i = 0; i < n/4; i++)
9309 target[i] = be32_to_cpu(source[i]);
9310}
9311
9312/*
9313 Ops array is stored in the following format:
9314 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9315 */
ab6ad5a4 9316static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 9317{
ab6ad5a4
EG		 9318 const __be32 *source = (const __be32 *)_source;
9319 struct raw_op *target = (struct raw_op *)_target;
94a78b79 9320 u32 i, j, tmp;
94a78b79 9321
ab6ad5a4 9322 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 9323 tmp = be32_to_cpu(source[j]);
9324 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 9325 target[i].offset = tmp & 0xffffff;
9326 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 9327 }
9328}
ab6ad5a4 9329
523224a3
DK		 9330/**
9331 * IRO array is stored in the following format:
9332 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9333 */
9334static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9335{
9336 const __be32 *source = (const __be32 *)_source;
9337 struct iro *target = (struct iro *)_target;
9338 u32 i, j, tmp;
9339
9340 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9341 target[i].base = be32_to_cpu(source[j]);
9342 j++;
9343 tmp = be32_to_cpu(source[j]);
9344 target[i].m1 = (tmp >> 16) & 0xffff;
9345 target[i].m2 = tmp & 0xffff;
9346 j++;
9347 tmp = be32_to_cpu(source[j]);
9348 target[i].m3 = (tmp >> 16) & 0xffff;
9349 target[i].size = tmp & 0xffff;
9350 j++;
9351 }
9352}
9353
ab6ad5a4 9354static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 9355{
ab6ad5a4
EG		 9356 const __be16 *source = (const __be16 *)_source;
9357 u16 *target = (u16 *)_target;
94a78b79 9358 u32 i;
94a78b79
VZ		 9359
9360 for (i = 0; i < n/2; i++)
9361 target[i] = be16_to_cpu(source[i]);
9362}
9363
7995c64e
JP		 9364#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
9365do { \
9366 u32 len = be32_to_cpu(fw_hdr->arr.len); \
9367 bp->arr = kmalloc(len, GFP_KERNEL); \
9368 if (!bp->arr) { \
9369 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9370 goto lbl; \
9371 } \
9372 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
9373 (u8 *)bp->arr, len); \
9374} while (0)
94a78b79 9375
6891dd25 9376int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 9377{
45229b42 9378 const char *fw_file_name;
94a78b79 9379 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 9380 int rc;
94a78b79 9381
94a78b79 9382 if (CHIP_IS_E1(bp))
45229b42 9383 fw_file_name = FW_FILE_NAME_E1;
cdaa7cb8 9384 else if (CHIP_IS_E1H(bp))
45229b42 9385 fw_file_name = FW_FILE_NAME_E1H;
f2e0899f
DK		 9386 else if (CHIP_IS_E2(bp))
9387 fw_file_name = FW_FILE_NAME_E2;
cdaa7cb8 9388 else {
6891dd25 9389 BNX2X_ERR("Unsupported chip revision\n");
cdaa7cb8
VZ		 9390 return -EINVAL;
9391 }
94a78b79 9392
6891dd25 9393 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 9394
6891dd25 9395 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
94a78b79 9396 if (rc) {
6891dd25 9397 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
94a78b79
VZ		 9398 goto request_firmware_exit;
9399 }
9400
9401 rc = bnx2x_check_firmware(bp);
9402 if (rc) {
6891dd25 9403 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
94a78b79
VZ		 9404 goto request_firmware_exit;
9405 }
9406
9407 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
9408
9409 /* Initialize the pointers to the init arrays */
9410 /* Blob */
9411 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
9412
9413 /* Opcodes */
9414 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
9415
9416 /* Offsets */
ab6ad5a4
EG		 9417 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
9418 be16_to_cpu_n);
94a78b79
VZ		 9419
9420 /* STORMs firmware */
573f2035
EG		 9421 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9422 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
9423 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
9424 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
9425 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9426 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
9427 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
9428 be32_to_cpu(fw_hdr->usem_pram_data.offset);
9429 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9430 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
9431 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
9432 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
9433 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9434 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
9435 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
9436 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 9437 /* IRO */
9438 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 9439
9440 return 0;
ab6ad5a4 9441
523224a3
DK		 9442iro_alloc_err:
9443 kfree(bp->init_ops_offsets);
94a78b79
VZ		 9444init_offsets_alloc_err:
9445 kfree(bp->init_ops);
9446init_ops_alloc_err:
9447 kfree(bp->init_data);
9448request_firmware_exit:
9449 release_firmware(bp->firmware);
9450
9451 return rc;
9452}
9453
523224a3
DK		 9454static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
9455{
9456 int cid_count = L2_FP_COUNT(l2_cid_count);
94a78b79 9457
523224a3
DK		 9458#ifdef BCM_CNIC
9459 cid_count += CNIC_CID_MAX;
9460#endif
9461 return roundup(cid_count, QM_CID_ROUND);
9462}
f85582f8 9463
a2fbb9ea
ET		 9464static int __devinit bnx2x_init_one(struct pci_dev *pdev,
9465 const struct pci_device_id *ent)
9466{
a2fbb9ea
ET		 9467 struct net_device *dev = NULL;
9468 struct bnx2x *bp;
37f9ce62 9469 int pcie_width, pcie_speed;
523224a3
DK		 9470 int rc, cid_count;
9471
f2e0899f
DK		 9472 switch (ent->driver_data) {
9473 case BCM57710:
9474 case BCM57711:
9475 case BCM57711E:
9476 cid_count = FP_SB_MAX_E1x;
9477 break;
9478
9479 case BCM57712:
9480 case BCM57712E:
9481 cid_count = FP_SB_MAX_E2;
9482 break;
a2fbb9ea 9483
f2e0899f
DK		 9484 default:
9485 pr_err("Unknown board_type (%ld), aborting\n",
9486 ent->driver_data);
870634b0 9487 return -ENODEV;
f2e0899f
DK		 9488 }
9489
ec6ba945 9490 cid_count += NONE_ETH_CONTEXT_USE + CNIC_CONTEXT_USE;
f85582f8 9491
a2fbb9ea 9492 /* dev zeroed in init_etherdev */
523224a3 9493 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
34f80b04 9494 if (!dev) {
cdaa7cb8 9495 dev_err(&pdev->dev, "Cannot allocate net device\n");
a2fbb9ea 9496 return -ENOMEM;
34f80b04 9497 }
a2fbb9ea 9498
a2fbb9ea 9499 bp = netdev_priv(dev);
7995c64e 9500 bp->msg_enable = debug;
a2fbb9ea 9501
df4770de
EG		 9502 pci_set_drvdata(pdev, dev);
9503
523224a3
DK		 9504 bp->l2_cid_count = cid_count;
9505
34f80b04 9506 rc = bnx2x_init_dev(pdev, dev);
a2fbb9ea
ET		 9507 if (rc < 0) {
9508 free_netdev(dev);
9509 return rc;
9510 }
9511
34f80b04 9512 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 9513 if (rc)
9514 goto init_one_exit;
9515
523224a3
DK		 9516 /* calc qm_cid_count */
9517 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
9518
ec6ba945
VZ		 9519#ifdef BCM_CNIC
9520 /* disable FCOE L2 queue for E1x*/
9521 if (CHIP_IS_E1x(bp))
9522 bp->flags |= NO_FCOE_FLAG;
9523
9524#endif
9525
25985edc 9526 /* Configure interrupt mode: try to enable MSI-X/MSI if
d6214d7a
DK		 9527 * needed, set bp->num_queues appropriately.
9528 */
9529 bnx2x_set_int_mode(bp);
9530
9531 /* Add all NAPI objects */
9532 bnx2x_add_all_napi(bp);
9533
b340007f
VZ		 9534 rc = register_netdev(dev);
9535 if (rc) {
9536 dev_err(&pdev->dev, "Cannot register net device\n");
9537 goto init_one_exit;
9538 }
9539
ec6ba945
VZ		 9540#ifdef BCM_CNIC
9541 if (!NO_FCOE(bp)) {
9542 /* Add storage MAC address */
9543 rtnl_lock();
9544 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9545 rtnl_unlock();
9546 }
9547#endif
9548
37f9ce62 9549 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
d6214d7a 9550
cdaa7cb8
VZ		 9551 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
9552 " IRQ %d, ", board_info[ent->driver_data].name,
9553 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
f2e0899f
DK		 9554 pcie_width,
9555 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
9556 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
9557 "5GHz (Gen2)" : "2.5GHz",
cdaa7cb8
VZ		 9558 dev->base_addr, bp->pdev->irq);
9559 pr_cont("node addr %pM\n", dev->dev_addr);
c016201c 9560
a2fbb9ea 9561 return 0;
34f80b04
EG		 9562
9563init_one_exit:
9564 if (bp->regview)
9565 iounmap(bp->regview);
9566
9567 if (bp->doorbells)
9568 iounmap(bp->doorbells);
9569
9570 free_netdev(dev);
9571
9572 if (atomic_read(&pdev->enable_cnt) == 1)
9573 pci_release_regions(pdev);
9574
9575 pci_disable_device(pdev);
9576 pci_set_drvdata(pdev, NULL);
9577
9578 return rc;
a2fbb9ea
ET		 9579}
9580
9581static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
9582{
9583 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 9584 struct bnx2x *bp;
9585
9586 if (!dev) {
cdaa7cb8 9587 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 9588 return;
9589 }
228241eb 9590 bp = netdev_priv(dev);
a2fbb9ea 9591
ec6ba945
VZ		 9592#ifdef BCM_CNIC
9593 /* Delete storage MAC address */
9594 if (!NO_FCOE(bp)) {
9595 rtnl_lock();
9596 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9597 rtnl_unlock();
9598 }
9599#endif
9600
98507672
SR		 9601#ifdef BCM_DCBNL
9602 /* Delete app tlvs from dcbnl */
9603 bnx2x_dcbnl_update_applist(bp, true);
9604#endif
9605
a2fbb9ea
ET		 9606 unregister_netdev(dev);
9607
d6214d7a
DK		 9608 /* Delete all NAPI objects */
9609 bnx2x_del_all_napi(bp);
9610
084d6cbb
VZ		 9611 /* Power on: we can't let PCI layer write to us while we are in D3 */
9612 bnx2x_set_power_state(bp, PCI_D0);
9613
d6214d7a
DK		 9614 /* Disable MSI/MSI-X */
9615 bnx2x_disable_msi(bp);
f85582f8 9616
084d6cbb
VZ		 9617 /* Power off */
9618 bnx2x_set_power_state(bp, PCI_D3hot);
9619
72fd0718
VZ		 9620 /* Make sure RESET task is not scheduled before continuing */
9621 cancel_delayed_work_sync(&bp->reset_task);
9622
a2fbb9ea
ET		 9623 if (bp->regview)
9624 iounmap(bp->regview);
9625
9626 if (bp->doorbells)
9627 iounmap(bp->doorbells);
9628
523224a3
DK		 9629 bnx2x_free_mem_bp(bp);
9630
a2fbb9ea 9631 free_netdev(dev);
34f80b04
EG		 9632
9633 if (atomic_read(&pdev->enable_cnt) == 1)
9634 pci_release_regions(pdev);
9635
a2fbb9ea
ET		 9636 pci_disable_device(pdev);
9637 pci_set_drvdata(pdev, NULL);
9638}
9639
f8ef6e44
YG		 9640static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
9641{
9642 int i;
9643
9644 bp->state = BNX2X_STATE_ERROR;
9645
9646 bp->rx_mode = BNX2X_RX_MODE_NONE;
9647
9648 bnx2x_netif_stop(bp, 0);
c89af1a3 9649 netif_carrier_off(bp->dev);
f8ef6e44
YG		 9650
9651 del_timer_sync(&bp->timer);
9652 bp->stats_state = STATS_STATE_DISABLED;
9653 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
9654
9655 /* Release IRQs */
d6214d7a 9656 bnx2x_free_irq(bp);
f8ef6e44 9657
f8ef6e44
YG		 9658 /* Free SKBs, SGEs, TPA pool and driver internals */
9659 bnx2x_free_skbs(bp);
523224a3 9660
ec6ba945 9661 for_each_rx_queue(bp, i)
f8ef6e44 9662 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 9663
f8ef6e44
YG		 9664 bnx2x_free_mem(bp);
9665
9666 bp->state = BNX2X_STATE_CLOSED;
9667
f8ef6e44
YG		 9668 return 0;
9669}
9670
9671static void bnx2x_eeh_recover(struct bnx2x *bp)
9672{
9673 u32 val;
9674
9675 mutex_init(&bp->port.phy_mutex);
9676
9677 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9678 bp->link_params.shmem_base = bp->common.shmem_base;
9679 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
9680
9681 if (!bp->common.shmem_base ||
9682 (bp->common.shmem_base < 0xA0000) ||
9683 (bp->common.shmem_base >= 0xC0000)) {
9684 BNX2X_DEV_INFO("MCP not active\n");
9685 bp->flags |= NO_MCP_FLAG;
9686 return;
9687 }
9688
9689 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9690 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9691 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9692 BNX2X_ERR("BAD MCP validity signature\n");
9693
9694 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 9695 bp->fw_seq =
9696 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9697 DRV_MSG_SEQ_NUMBER_MASK);
f8ef6e44
YG		 9698 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9699 }
9700}
9701
493adb1f
WX		 9702/**
9703 * bnx2x_io_error_detected - called when PCI error is detected
9704 * @pdev: Pointer to PCI device
9705 * @state: The current pci connection state
9706 *
9707 * This function is called after a PCI bus error affecting
9708 * this device has been detected.
9709 */
9710static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
9711 pci_channel_state_t state)
9712{
9713 struct net_device *dev = pci_get_drvdata(pdev);
9714 struct bnx2x *bp = netdev_priv(dev);
9715
9716 rtnl_lock();
9717
9718 netif_device_detach(dev);
9719
07ce50e4
DN		 9720 if (state == pci_channel_io_perm_failure) {
9721 rtnl_unlock();
9722 return PCI_ERS_RESULT_DISCONNECT;
9723 }
9724
493adb1f 9725 if (netif_running(dev))
f8ef6e44 9726 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 9727
9728 pci_disable_device(pdev);
9729
9730 rtnl_unlock();
9731
9732 /* Request a slot reset */
9733 return PCI_ERS_RESULT_NEED_RESET;
9734}
9735
9736/**
9737 * bnx2x_io_slot_reset - called after the PCI bus has been reset
9738 * @pdev: Pointer to PCI device
9739 *
9740 * Restart the card from scratch, as if from a cold-boot.
9741 */
9742static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
9743{
9744 struct net_device *dev = pci_get_drvdata(pdev);
9745 struct bnx2x *bp = netdev_priv(dev);
9746
9747 rtnl_lock();
9748
9749 if (pci_enable_device(pdev)) {
9750 dev_err(&pdev->dev,
9751 "Cannot re-enable PCI device after reset\n");
9752 rtnl_unlock();
9753 return PCI_ERS_RESULT_DISCONNECT;
9754 }
9755
9756 pci_set_master(pdev);
9757 pci_restore_state(pdev);
9758
9759 if (netif_running(dev))
9760 bnx2x_set_power_state(bp, PCI_D0);
9761
9762 rtnl_unlock();
9763
9764 return PCI_ERS_RESULT_RECOVERED;
9765}
9766
9767/**
9768 * bnx2x_io_resume - called when traffic can start flowing again
9769 * @pdev: Pointer to PCI device
9770 *
9771 * This callback is called when the error recovery driver tells us that
9772 * its OK to resume normal operation.
9773 */
9774static void bnx2x_io_resume(struct pci_dev *pdev)
9775{
9776 struct net_device *dev = pci_get_drvdata(pdev);
9777 struct bnx2x *bp = netdev_priv(dev);
9778
72fd0718 9779 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
f2e0899f
DK		 9780 printk(KERN_ERR "Handling parity error recovery. "
9781 "Try again later\n");
72fd0718
VZ		 9782 return;
9783 }
9784
493adb1f
WX		 9785 rtnl_lock();
9786
f8ef6e44
YG		 9787 bnx2x_eeh_recover(bp);
9788
493adb1f 9789 if (netif_running(dev))
f8ef6e44 9790 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 9791
9792 netif_device_attach(dev);
9793
9794 rtnl_unlock();
9795}
9796
9797static struct pci_error_handlers bnx2x_err_handler = {
9798 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 9799 .slot_reset = bnx2x_io_slot_reset,
9800 .resume = bnx2x_io_resume,
493adb1f
WX		 9801};
9802
a2fbb9ea 9803static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 9804 .name = DRV_MODULE_NAME,
9805 .id_table = bnx2x_pci_tbl,
9806 .probe = bnx2x_init_one,
9807 .remove = __devexit_p(bnx2x_remove_one),
9808 .suspend = bnx2x_suspend,
9809 .resume = bnx2x_resume,
9810 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 9811};
9812
9813static int __init bnx2x_init(void)
9814{
dd21ca6d
SG		 9815 int ret;
9816
7995c64e 9817 pr_info("%s", version);
938cf541 9818
1cf167f2
EG		 9819 bnx2x_wq = create_singlethread_workqueue("bnx2x");
9820 if (bnx2x_wq == NULL) {
7995c64e 9821 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 9822 return -ENOMEM;
9823 }
9824
dd21ca6d
SG		 9825 ret = pci_register_driver(&bnx2x_pci_driver);
9826 if (ret) {
7995c64e 9827 pr_err("Cannot register driver\n");
dd21ca6d
SG		 9828 destroy_workqueue(bnx2x_wq);
9829 }
9830 return ret;
a2fbb9ea
ET		 9831}
9832
9833static void __exit bnx2x_cleanup(void)
9834{
9835 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 9836
9837 destroy_workqueue(bnx2x_wq);
a2fbb9ea
ET		 9838}
9839
9840module_init(bnx2x_init);
9841module_exit(bnx2x_cleanup);
9842
993ac7b5
MC		 9843#ifdef BCM_CNIC
9844
9845/* count denotes the number of new completions we have seen */
9846static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
9847{
9848 struct eth_spe *spe;
9849
9850#ifdef BNX2X_STOP_ON_ERROR
9851 if (unlikely(bp->panic))
9852 return;
9853#endif
9854
9855 spin_lock_bh(&bp->spq_lock);
c2bff63f 9856 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 9857 bp->cnic_spq_pending -= count;
9858
993ac7b5 9859
c2bff63f
DK		 9860 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
9861 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
9862 & SPE_HDR_CONN_TYPE) >>
9863 SPE_HDR_CONN_TYPE_SHIFT;
9864
9865 /* Set validation for iSCSI L2 client before sending SETUP
9866 * ramrod
9867 */
9868 if (type == ETH_CONNECTION_TYPE) {
9869 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->
9870 hdr.conn_and_cmd_data) >>
9871 SPE_HDR_CMD_ID_SHIFT) & 0xff;
9872
9873 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
9874 bnx2x_set_ctx_validation(&bp->context.
9875 vcxt[BNX2X_ISCSI_ETH_CID].eth,
9876 HW_CID(bp, BNX2X_ISCSI_ETH_CID));
9877 }
9878
6e30dd4e
VZ		 9879 /* There may be not more than 8 L2 and not more than 8 L5 SPEs
9880 * We also check that the number of outstanding
9881 * COMMON ramrods is not more than the EQ and SPQ can
9882 * accommodate.
c2bff63f 9883 */
6e30dd4e
VZ		 9884 if (type == ETH_CONNECTION_TYPE) {
9885 if (!atomic_read(&bp->cq_spq_left))
9886 break;
9887 else
9888 atomic_dec(&bp->cq_spq_left);
9889 } else if (type == NONE_CONNECTION_TYPE) {
9890 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 9891 break;
9892 else
6e30dd4e 9893 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 9894 } else if ((type == ISCSI_CONNECTION_TYPE) ||
9895 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 9896 if (bp->cnic_spq_pending >=
9897 bp->cnic_eth_dev.max_kwqe_pending)
9898 break;
9899 else
9900 bp->cnic_spq_pending++;
9901 } else {
9902 BNX2X_ERR("Unknown SPE type: %d\n", type);
9903 bnx2x_panic();
993ac7b5 9904 break;
c2bff63f 9905 }
993ac7b5
MC		 9906
9907 spe = bnx2x_sp_get_next(bp);
9908 *spe = *bp->cnic_kwq_cons;
9909
993ac7b5
MC		 9910 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
9911 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
9912
9913 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
9914 bp->cnic_kwq_cons = bp->cnic_kwq;
9915 else
9916 bp->cnic_kwq_cons++;
9917 }
9918 bnx2x_sp_prod_update(bp);
9919 spin_unlock_bh(&bp->spq_lock);
9920}
9921
9922static int bnx2x_cnic_sp_queue(struct net_device *dev,
9923 struct kwqe_16 *kwqes[], u32 count)
9924{
9925 struct bnx2x *bp = netdev_priv(dev);
9926 int i;
9927
9928#ifdef BNX2X_STOP_ON_ERROR
9929 if (unlikely(bp->panic))
9930 return -EIO;
9931#endif
9932
9933 spin_lock_bh(&bp->spq_lock);
9934
9935 for (i = 0; i < count; i++) {
9936 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
9937
9938 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
9939 break;
9940
9941 *bp->cnic_kwq_prod = *spe;
9942
9943 bp->cnic_kwq_pending++;
9944
9945 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
9946 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 9947 spe->data.update_data_addr.hi,
9948 spe->data.update_data_addr.lo,
993ac7b5
MC		 9949 bp->cnic_kwq_pending);
9950
9951 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
9952 bp->cnic_kwq_prod = bp->cnic_kwq;
9953 else
9954 bp->cnic_kwq_prod++;
9955 }
9956
9957 spin_unlock_bh(&bp->spq_lock);
9958
9959 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
9960 bnx2x_cnic_sp_post(bp, 0);
9961
9962 return i;
9963}
9964
9965static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
9966{
9967 struct cnic_ops *c_ops;
9968 int rc = 0;
9969
9970 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 9971 c_ops = rcu_dereference_protected(bp->cnic_ops,
9972 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 9973 if (c_ops)
9974 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
9975 mutex_unlock(&bp->cnic_mutex);
9976
9977 return rc;
9978}
9979
9980static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
9981{
9982 struct cnic_ops *c_ops;
9983 int rc = 0;
9984
9985 rcu_read_lock();
9986 c_ops = rcu_dereference(bp->cnic_ops);
9987 if (c_ops)
9988 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
9989 rcu_read_unlock();
9990
9991 return rc;
9992}
9993
9994/*
9995 * for commands that have no data
9996 */
9f6c9258 9997int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 9998{
9999 struct cnic_ctl_info ctl = {0};
10000
10001 ctl.cmd = cmd;
10002
10003 return bnx2x_cnic_ctl_send(bp, &ctl);
10004}
10005
10006static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
10007{
10008 struct cnic_ctl_info ctl;
10009
10010 /* first we tell CNIC and only then we count this as a completion */
10011 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
10012 ctl.data.comp.cid = cid;
10013
10014 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 10015 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 10016}
10017
10018static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
10019{
10020 struct bnx2x *bp = netdev_priv(dev);
10021 int rc = 0;
10022
10023 switch (ctl->cmd) {
10024 case DRV_CTL_CTXTBL_WR_CMD: {
10025 u32 index = ctl->data.io.offset;
10026 dma_addr_t addr = ctl->data.io.dma_addr;
10027
10028 bnx2x_ilt_wr(bp, index, addr);
10029 break;
10030 }
10031
c2bff63f
DK		 10032 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
10033 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 10034
10035 bnx2x_cnic_sp_post(bp, count);
10036 break;
10037 }
10038
10039 /* rtnl_lock is held. */
10040 case DRV_CTL_START_L2_CMD: {
10041 u32 cli = ctl->data.ring.client_id;
10042
ec6ba945
VZ		 10043 /* Clear FCoE FIP and ALL ENODE MACs addresses first */
10044 bnx2x_del_fcoe_eth_macs(bp);
10045
523224a3
DK		 10046 /* Set iSCSI MAC address */
10047 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
10048
10049 mmiowb();
10050 barrier();
10051
10052 /* Start accepting on iSCSI L2 ring. Accept all multicasts
10053 * because it's the only way for UIO Client to accept
10054 * multicasts (in non-promiscuous mode only one Client per
10055 * function will receive multicast packets (leading in our
10056 * case).
10057 */
10058 bnx2x_rxq_set_mac_filters(bp, cli,
10059 BNX2X_ACCEPT_UNICAST |
10060 BNX2X_ACCEPT_BROADCAST |
10061 BNX2X_ACCEPT_ALL_MULTICAST);
10062 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10063
993ac7b5
MC		 10064 break;
10065 }
10066
10067 /* rtnl_lock is held. */
10068 case DRV_CTL_STOP_L2_CMD: {
10069 u32 cli = ctl->data.ring.client_id;
10070
523224a3
DK		 10071 /* Stop accepting on iSCSI L2 ring */
10072 bnx2x_rxq_set_mac_filters(bp, cli, BNX2X_ACCEPT_NONE);
10073 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10074
10075 mmiowb();
10076 barrier();
10077
10078 /* Unset iSCSI L2 MAC */
10079 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
993ac7b5
MC		 10080 break;
10081 }
c2bff63f
DK		 10082 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
10083 int count = ctl->data.credit.credit_count;
10084
10085 smp_mb__before_atomic_inc();
6e30dd4e 10086 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 10087 smp_mb__after_atomic_inc();
10088 break;
10089 }
993ac7b5 10090
fab0dc89
DK		 10091 case DRV_CTL_ISCSI_STOPPED_CMD: {
10092 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_ISCSI_STOPPED);
10093 break;
10094 }
10095
993ac7b5
MC		 10096 default:
10097 BNX2X_ERR("unknown command %x\n", ctl->cmd);
10098 rc = -EINVAL;
10099 }
10100
10101 return rc;
10102}
10103
9f6c9258 10104void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 10105{
10106 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10107
10108 if (bp->flags & USING_MSIX_FLAG) {
10109 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
10110 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
10111 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10112 } else {
10113 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10114 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10115 }
f2e0899f
DK		 10116 if (CHIP_IS_E2(bp))
10117 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10118 else
10119 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10120
993ac7b5 10121 cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
523224a3 10122 cp->irq_arr[0].status_blk_num2 = CNIC_IGU_SB_ID(bp);
993ac7b5
MC		 10123 cp->irq_arr[1].status_blk = bp->def_status_blk;
10124 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 10125 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 10126
10127 cp->num_irq = 2;
10128}
10129
10130static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10131 void *data)
10132{
10133 struct bnx2x *bp = netdev_priv(dev);
10134 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10135
10136 if (ops == NULL)
10137 return -EINVAL;
10138
993ac7b5
MC		 10139 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10140 if (!bp->cnic_kwq)
10141 return -ENOMEM;
10142
10143 bp->cnic_kwq_cons = bp->cnic_kwq;
10144 bp->cnic_kwq_prod = bp->cnic_kwq;
10145 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10146
10147 bp->cnic_spq_pending = 0;
10148 bp->cnic_kwq_pending = 0;
10149
10150 bp->cnic_data = data;
10151
10152 cp->num_irq = 0;
10153 cp->drv_state = CNIC_DRV_STATE_REGD;
523224a3 10154 cp->iro_arr = bp->iro_arr;
993ac7b5 10155
993ac7b5 10156 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 10157
993ac7b5
MC		 10158 rcu_assign_pointer(bp->cnic_ops, ops);
10159
10160 return 0;
10161}
10162
10163static int bnx2x_unregister_cnic(struct net_device *dev)
10164{
10165 struct bnx2x *bp = netdev_priv(dev);
10166 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10167
10168 mutex_lock(&bp->cnic_mutex);
993ac7b5
MC		 10169 cp->drv_state = 0;
10170 rcu_assign_pointer(bp->cnic_ops, NULL);
10171 mutex_unlock(&bp->cnic_mutex);
10172 synchronize_rcu();
10173 kfree(bp->cnic_kwq);
10174 bp->cnic_kwq = NULL;
10175
10176 return 0;
10177}
10178
10179struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10180{
10181 struct bnx2x *bp = netdev_priv(dev);
10182 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10183
2ba45142
VZ		 10184 /* If both iSCSI and FCoE are disabled - return NULL in
10185 * order to indicate CNIC that it should not try to work
10186 * with this device.
10187 */
10188 if (NO_ISCSI(bp) && NO_FCOE(bp))
10189 return NULL;
10190
993ac7b5
MC		 10191 cp->drv_owner = THIS_MODULE;
10192 cp->chip_id = CHIP_ID(bp);
10193 cp->pdev = bp->pdev;
10194 cp->io_base = bp->regview;
10195 cp->io_base2 = bp->doorbells;
10196 cp->max_kwqe_pending = 8;
523224a3 10197 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 10198 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10199 bnx2x_cid_ilt_lines(bp);
993ac7b5 10200 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 10201 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 10202 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10203 cp->drv_ctl = bnx2x_drv_ctl;
10204 cp->drv_register_cnic = bnx2x_register_cnic;
10205 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
ec6ba945
VZ		 10206 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10207 cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID +
10208 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
c2bff63f
DK		 10209 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10210
2ba45142
VZ		 10211 if (NO_ISCSI_OOO(bp))
10212 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
10213
10214 if (NO_ISCSI(bp))
10215 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
10216
10217 if (NO_FCOE(bp))
10218 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
10219
c2bff63f
DK		 10220 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10221 "starting cid %d\n",
10222 cp->ctx_blk_size,
10223 cp->ctx_tbl_offset,
10224 cp->ctx_tbl_len,
10225 cp->starting_cid);
993ac7b5
MC		 10226 return cp;
10227}
10228EXPORT_SYMBOL(bnx2x_cnic_probe);
10229
10230#endif /* BCM_CNIC */
94a78b79 10231
Linux 6.x block layer and io_uring tree(s)