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cpmac: use resource_size()
[linux-2.6-block.git] / drivers / net / benet / be_main.c
CommitLineData
6b7c5b94 1/*
294aedcf 2 * Copyright (C) 2005 - 2010 ServerEngines
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18#include "be.h"
8788fdc2 19#include "be_cmds.h"
65f71b8b 20#include <asm/div64.h>
6b7c5b94
SP		 21
22MODULE_VERSION(DRV_VER);
23MODULE_DEVICE_TABLE(pci, be_dev_ids);
24MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
25MODULE_AUTHOR("ServerEngines Corporation");
26MODULE_LICENSE("GPL");
27
28static unsigned int rx_frag_size = 2048;
ba343c77 29static unsigned int num_vfs;
6b7c5b94 30module_param(rx_frag_size, uint, S_IRUGO);
ba343c77 31module_param(num_vfs, uint, S_IRUGO);
6b7c5b94 32MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
ba343c77 33MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
6b7c5b94 34
6b7c5b94 35static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
c4ca2374 36 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
59fd5d87 37 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
c4ca2374
AK		 38 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
39 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
6b7c5b94
SP		 40 { 0 }
41};
42MODULE_DEVICE_TABLE(pci, be_dev_ids);
43
44static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
45{
46 struct be_dma_mem *mem = &q->dma_mem;
47 if (mem->va)
48 pci_free_consistent(adapter->pdev, mem->size,
49 mem->va, mem->dma);
50}
51
52static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
53 u16 len, u16 entry_size)
54{
55 struct be_dma_mem *mem = &q->dma_mem;
56
57 memset(q, 0, sizeof(*q));
58 q->len = len;
59 q->entry_size = entry_size;
60 mem->size = len * entry_size;
61 mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
62 if (!mem->va)
63 return -1;
64 memset(mem->va, 0, mem->size);
65 return 0;
66}
67
8788fdc2 68static void be_intr_set(struct be_adapter *adapter, bool enable)
6b7c5b94 69{
8788fdc2 70 u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
6b7c5b94
SP		 71 u32 reg = ioread32(addr);
72 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 73
cf588477
SP		 74 if (adapter->eeh_err)
75 return;
76
5f0b849e 77 if (!enabled && enable)
6b7c5b94 78 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 79 else if (enabled && !enable)
6b7c5b94 80 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 81 else
6b7c5b94 82 return;
5f0b849e 83
6b7c5b94
SP		 84 iowrite32(reg, addr);
85}
86
8788fdc2 87static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 88{
89 u32 val = 0;
90 val |= qid & DB_RQ_RING_ID_MASK;
91 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
8788fdc2 92 iowrite32(val, adapter->db + DB_RQ_OFFSET);
6b7c5b94
SP		 93}
94
8788fdc2 95static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 96{
97 u32 val = 0;
98 val |= qid & DB_TXULP_RING_ID_MASK;
99 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
8788fdc2 100 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
6b7c5b94
SP		 101}
102
8788fdc2 103static void be_eq_notify(struct be_adapter *adapter, u16 qid,
6b7c5b94
SP		 104 bool arm, bool clear_int, u16 num_popped)
105{
106 u32 val = 0;
107 val |= qid & DB_EQ_RING_ID_MASK;
cf588477
SP		 108
109 if (adapter->eeh_err)
110 return;
111
6b7c5b94
SP		 112 if (arm)
113 val |= 1 << DB_EQ_REARM_SHIFT;
114 if (clear_int)
115 val |= 1 << DB_EQ_CLR_SHIFT;
116 val |= 1 << DB_EQ_EVNT_SHIFT;
117 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
8788fdc2 118 iowrite32(val, adapter->db + DB_EQ_OFFSET);
6b7c5b94
SP		 119}
120
8788fdc2 121void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
6b7c5b94
SP		 122{
123 u32 val = 0;
124 val |= qid & DB_CQ_RING_ID_MASK;
cf588477
SP		 125
126 if (adapter->eeh_err)
127 return;
128
6b7c5b94
SP		 129 if (arm)
130 val |= 1 << DB_CQ_REARM_SHIFT;
131 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
8788fdc2 132 iowrite32(val, adapter->db + DB_CQ_OFFSET);
6b7c5b94
SP		 133}
134
6b7c5b94
SP		 135static int be_mac_addr_set(struct net_device *netdev, void *p)
136{
137 struct be_adapter *adapter = netdev_priv(netdev);
138 struct sockaddr *addr = p;
139 int status = 0;
140
ca9e4988
AK		 141 if (!is_valid_ether_addr(addr->sa_data))
142 return -EADDRNOTAVAIL;
143
ba343c77
SB		 144 /* MAC addr configuration will be done in hardware for VFs
145 * by their corresponding PFs. Just copy to netdev addr here
146 */
147 if (!be_physfn(adapter))
148 goto netdev_addr;
149
a65027e4
SP		 150 status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
151 if (status)
152 return status;
6b7c5b94 153
a65027e4
SP		 154 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
155 adapter->if_handle, &adapter->pmac_id);
ba343c77 156netdev_addr:
6b7c5b94
SP		 157 if (!status)
158 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
159
160 return status;
161}
162
b31c50a7 163void netdev_stats_update(struct be_adapter *adapter)
6b7c5b94
SP		 164{
165 struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
166 struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
167 struct be_port_rxf_stats *port_stats =
168 &rxf_stats->port[adapter->port_num];
78122a52 169 struct net_device_stats *dev_stats = &adapter->netdev->stats;
68110868 170 struct be_erx_stats *erx_stats = &hw_stats->erx;
6b7c5b94 171
91992e44
AK		 172 dev_stats->rx_packets = drvr_stats(adapter)->be_rx_pkts;
173 dev_stats->tx_packets = drvr_stats(adapter)->be_tx_pkts;
174 dev_stats->rx_bytes = drvr_stats(adapter)->be_rx_bytes;
175 dev_stats->tx_bytes = drvr_stats(adapter)->be_tx_bytes;
6b7c5b94
SP		 176
177 /* bad pkts received */
178 dev_stats->rx_errors = port_stats->rx_crc_errors +
179 port_stats->rx_alignment_symbol_errors +
180 port_stats->rx_in_range_errors +
68110868
SP		 181 port_stats->rx_out_range_errors +
182 port_stats->rx_frame_too_long +
183 port_stats->rx_dropped_too_small +
184 port_stats->rx_dropped_too_short +
185 port_stats->rx_dropped_header_too_small +
186 port_stats->rx_dropped_tcp_length +
187 port_stats->rx_dropped_runt +
188 port_stats->rx_tcp_checksum_errs +
189 port_stats->rx_ip_checksum_errs +
190 port_stats->rx_udp_checksum_errs;
191
192 /* no space in linux buffers: best possible approximation */
01ed30da
SP		 193 dev_stats->rx_dropped =
194 erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
6b7c5b94
SP		 195
196 /* detailed rx errors */
197 dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
68110868
SP		 198 port_stats->rx_out_range_errors +
199 port_stats->rx_frame_too_long;
200
6b7c5b94
SP		 201 /* receive ring buffer overflow */
202 dev_stats->rx_over_errors = 0;
68110868 203
6b7c5b94
SP		 204 dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
205
206 /* frame alignment errors */
207 dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
68110868 208
6b7c5b94
SP		 209 /* receiver fifo overrun */
210 /* drops_no_pbuf is no per i/f, it's per BE card */
211 dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
212 port_stats->rx_input_fifo_overflow +
213 rxf_stats->rx_drops_no_pbuf;
214 /* receiver missed packetd */
215 dev_stats->rx_missed_errors = 0;
68110868
SP		 216
217 /* packet transmit problems */
218 dev_stats->tx_errors = 0;
219
220 /* no space available in linux */
221 dev_stats->tx_dropped = 0;
222
c5b9b92e 223 dev_stats->multicast = port_stats->rx_multicast_frames;
68110868
SP		 224 dev_stats->collisions = 0;
225
6b7c5b94
SP		 226 /* detailed tx_errors */
227 dev_stats->tx_aborted_errors = 0;
228 dev_stats->tx_carrier_errors = 0;
229 dev_stats->tx_fifo_errors = 0;
230 dev_stats->tx_heartbeat_errors = 0;
231 dev_stats->tx_window_errors = 0;
232}
233
8788fdc2 234void be_link_status_update(struct be_adapter *adapter, bool link_up)
6b7c5b94 235{
6b7c5b94
SP		 236 struct net_device *netdev = adapter->netdev;
237
6b7c5b94 238 /* If link came up or went down */
a8f447bd 239 if (adapter->link_up != link_up) {
0dffc83e 240 adapter->link_speed = -1;
a8f447bd 241 if (link_up) {
6b7c5b94
SP		 242 netif_start_queue(netdev);
243 netif_carrier_on(netdev);
244 printk(KERN_INFO "%s: Link up\n", netdev->name);
a8f447bd
SP		 245 } else {
246 netif_stop_queue(netdev);
247 netif_carrier_off(netdev);
248 printk(KERN_INFO "%s: Link down\n", netdev->name);
6b7c5b94 249 }
a8f447bd 250 adapter->link_up = link_up;
6b7c5b94 251 }
6b7c5b94
SP		 252}
253
254/* Update the EQ delay n BE based on the RX frags consumed / sec */
255static void be_rx_eqd_update(struct be_adapter *adapter)
256{
6b7c5b94
SP		 257 struct be_eq_obj *rx_eq = &adapter->rx_eq;
258 struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
4097f663
SP		 259 ulong now = jiffies;
260 u32 eqd;
261
262 if (!rx_eq->enable_aic)
263 return;
264
265 /* Wrapped around */
266 if (time_before(now, stats->rx_fps_jiffies)) {
267 stats->rx_fps_jiffies = now;
268 return;
269 }
6b7c5b94
SP		 270
271 /* Update once a second */
4097f663 272 if ((now - stats->rx_fps_jiffies) < HZ)
6b7c5b94
SP		 273 return;
274
275 stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
4097f663 276 ((now - stats->rx_fps_jiffies) / HZ);
6b7c5b94 277
4097f663 278 stats->rx_fps_jiffies = now;
6b7c5b94
SP		 279 stats->be_prev_rx_frags = stats->be_rx_frags;
280 eqd = stats->be_rx_fps / 110000;
281 eqd = eqd << 3;
282 if (eqd > rx_eq->max_eqd)
283 eqd = rx_eq->max_eqd;
284 if (eqd < rx_eq->min_eqd)
285 eqd = rx_eq->min_eqd;
286 if (eqd < 10)
287 eqd = 0;
288 if (eqd != rx_eq->cur_eqd)
8788fdc2 289 be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
6b7c5b94
SP		 290
291 rx_eq->cur_eqd = eqd;
292}
293
6b7c5b94
SP		 294static struct net_device_stats *be_get_stats(struct net_device *dev)
295{
78122a52 296 return &dev->stats;
6b7c5b94
SP		 297}
298
65f71b8b
SH		 299static u32 be_calc_rate(u64 bytes, unsigned long ticks)
300{
301 u64 rate = bytes;
302
303 do_div(rate, ticks / HZ);
304 rate <<= 3; /* bytes/sec -> bits/sec */
305 do_div(rate, 1000000ul); /* MB/Sec */
306
307 return rate;
308}
309
4097f663
SP		 310static void be_tx_rate_update(struct be_adapter *adapter)
311{
312 struct be_drvr_stats *stats = drvr_stats(adapter);
313 ulong now = jiffies;
314
315 /* Wrapped around? */
316 if (time_before(now, stats->be_tx_jiffies)) {
317 stats->be_tx_jiffies = now;
318 return;
319 }
320
321 /* Update tx rate once in two seconds */
322 if ((now - stats->be_tx_jiffies) > 2 * HZ) {
65f71b8b
SH		 323 stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
324 - stats->be_tx_bytes_prev,
325 now - stats->be_tx_jiffies);
4097f663
SP		 326 stats->be_tx_jiffies = now;
327 stats->be_tx_bytes_prev = stats->be_tx_bytes;
328 }
329}
330
6b7c5b94 331static void be_tx_stats_update(struct be_adapter *adapter,
91992e44 332 u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
6b7c5b94 333{
4097f663 334 struct be_drvr_stats *stats = drvr_stats(adapter);
6b7c5b94
SP		 335 stats->be_tx_reqs++;
336 stats->be_tx_wrbs += wrb_cnt;
337 stats->be_tx_bytes += copied;
91992e44 338 stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
6b7c5b94
SP		 339 if (stopped)
340 stats->be_tx_stops++;
6b7c5b94
SP		 341}
342
343/* Determine number of WRB entries needed to xmit data in an skb */
344static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
345{
ebc8d2ab
DM		 346 int cnt = (skb->len > skb->data_len);
347
348 cnt += skb_shinfo(skb)->nr_frags;
349
6b7c5b94
SP		 350 /* to account for hdr wrb */
351 cnt++;
352 if (cnt & 1) {
353 /* add a dummy to make it an even num */
354 cnt++;
355 *dummy = true;
356 } else
357 *dummy = false;
358 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
359 return cnt;
360}
361
362static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
363{
364 wrb->frag_pa_hi = upper_32_bits(addr);
365 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
366 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
367}
368
369static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
370 bool vlan, u32 wrb_cnt, u32 len)
371{
372 memset(hdr, 0, sizeof(*hdr));
373
374 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
375
49e4b847 376 if (skb_is_gso(skb)) {
6b7c5b94
SP		 377 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
378 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
379 hdr, skb_shinfo(skb)->gso_size);
49e4b847
AK		 380 if (skb_is_gso_v6(skb))
381 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
6b7c5b94
SP		 382 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
383 if (is_tcp_pkt(skb))
384 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
385 else if (is_udp_pkt(skb))
386 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
387 }
388
389 if (vlan && vlan_tx_tag_present(skb)) {
390 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
391 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
392 hdr, vlan_tx_tag_get(skb));
393 }
394
395 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
396 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
397 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
398 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
399}
400
7101e111
SP		 401static void unmap_tx_frag(struct pci_dev *pdev, struct be_eth_wrb *wrb,
402 bool unmap_single)
403{
404 dma_addr_t dma;
405
406 be_dws_le_to_cpu(wrb, sizeof(*wrb));
407
408 dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
b681ee77 409 if (wrb->frag_len) {
7101e111
SP		 410 if (unmap_single)
411 pci_unmap_single(pdev, dma, wrb->frag_len,
412 PCI_DMA_TODEVICE);
413 else
414 pci_unmap_page(pdev, dma, wrb->frag_len,
415 PCI_DMA_TODEVICE);
416 }
417}
6b7c5b94
SP		 418
419static int make_tx_wrbs(struct be_adapter *adapter,
420 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
421{
7101e111
SP		 422 dma_addr_t busaddr;
423 int i, copied = 0;
6b7c5b94
SP		 424 struct pci_dev *pdev = adapter->pdev;
425 struct sk_buff *first_skb = skb;
426 struct be_queue_info *txq = &adapter->tx_obj.q;
427 struct be_eth_wrb *wrb;
428 struct be_eth_hdr_wrb *hdr;
7101e111
SP		 429 bool map_single = false;
430 u16 map_head;
6b7c5b94 431
6b7c5b94
SP		 432 hdr = queue_head_node(txq);
433 queue_head_inc(txq);
7101e111 434 map_head = txq->head;
6b7c5b94 435
ebc8d2ab 436 if (skb->len > skb->data_len) {
e743d313 437 int len = skb_headlen(skb);
a73b796e
AD		 438 busaddr = pci_map_single(pdev, skb->data, len,
439 PCI_DMA_TODEVICE);
7101e111
SP		 440 if (pci_dma_mapping_error(pdev, busaddr))
441 goto dma_err;
442 map_single = true;
ebc8d2ab
DM		 443 wrb = queue_head_node(txq);
444 wrb_fill(wrb, busaddr, len);
445 be_dws_cpu_to_le(wrb, sizeof(*wrb));
446 queue_head_inc(txq);
447 copied += len;
448 }
6b7c5b94 449
ebc8d2ab
DM		 450 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
451 struct skb_frag_struct *frag =
452 &skb_shinfo(skb)->frags[i];
a73b796e
AD		 453 busaddr = pci_map_page(pdev, frag->page,
454 frag->page_offset,
455 frag->size, PCI_DMA_TODEVICE);
7101e111
SP		 456 if (pci_dma_mapping_error(pdev, busaddr))
457 goto dma_err;
ebc8d2ab
DM		 458 wrb = queue_head_node(txq);
459 wrb_fill(wrb, busaddr, frag->size);
460 be_dws_cpu_to_le(wrb, sizeof(*wrb));
461 queue_head_inc(txq);
462 copied += frag->size;
6b7c5b94
SP		 463 }
464
465 if (dummy_wrb) {
466 wrb = queue_head_node(txq);
467 wrb_fill(wrb, 0, 0);
468 be_dws_cpu_to_le(wrb, sizeof(*wrb));
469 queue_head_inc(txq);
470 }
471
472 wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
473 wrb_cnt, copied);
474 be_dws_cpu_to_le(hdr, sizeof(*hdr));
475
476 return copied;
7101e111
SP		 477dma_err:
478 txq->head = map_head;
479 while (copied) {
480 wrb = queue_head_node(txq);
481 unmap_tx_frag(pdev, wrb, map_single);
482 map_single = false;
483 copied -= wrb->frag_len;
484 queue_head_inc(txq);
485 }
486 return 0;
6b7c5b94
SP		 487}
488
61357325 489static netdev_tx_t be_xmit(struct sk_buff *skb,
b31c50a7 490 struct net_device *netdev)
6b7c5b94
SP		 491{
492 struct be_adapter *adapter = netdev_priv(netdev);
493 struct be_tx_obj *tx_obj = &adapter->tx_obj;
494 struct be_queue_info *txq = &tx_obj->q;
495 u32 wrb_cnt = 0, copied = 0;
496 u32 start = txq->head;
497 bool dummy_wrb, stopped = false;
498
499 wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
500
501 copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
c190e3c8
AK		 502 if (copied) {
503 /* record the sent skb in the sent_skb table */
504 BUG_ON(tx_obj->sent_skb_list[start]);
505 tx_obj->sent_skb_list[start] = skb;
506
507 /* Ensure txq has space for the next skb; Else stop the queue
508 * *BEFORE* ringing the tx doorbell, so that we serialze the
509 * tx compls of the current transmit which'll wake up the queue
510 */
7101e111 511 atomic_add(wrb_cnt, &txq->used);
c190e3c8
AK		 512 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
513 txq->len) {
514 netif_stop_queue(netdev);
515 stopped = true;
516 }
6b7c5b94 517
c190e3c8 518 be_txq_notify(adapter, txq->id, wrb_cnt);
6b7c5b94 519
91992e44
AK		 520 be_tx_stats_update(adapter, wrb_cnt, copied,
521 skb_shinfo(skb)->gso_segs, stopped);
c190e3c8
AK		 522 } else {
523 txq->head = start;
524 dev_kfree_skb_any(skb);
6b7c5b94 525 }
6b7c5b94
SP		 526 return NETDEV_TX_OK;
527}
528
529static int be_change_mtu(struct net_device *netdev, int new_mtu)
530{
531 struct be_adapter *adapter = netdev_priv(netdev);
532 if (new_mtu < BE_MIN_MTU ||
34a89b8c
AK		 533 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
534 (ETH_HLEN + ETH_FCS_LEN))) {
6b7c5b94
SP		 535 dev_info(&adapter->pdev->dev,
536 "MTU must be between %d and %d bytes\n",
34a89b8c
AK		 537 BE_MIN_MTU,
538 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
6b7c5b94
SP		 539 return -EINVAL;
540 }
541 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
542 netdev->mtu, new_mtu);
543 netdev->mtu = new_mtu;
544 return 0;
545}
546
547/*
82903e4b
AK		 548 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
549 * If the user configures more, place BE in vlan promiscuous mode.
6b7c5b94 550 */
b31c50a7 551static int be_vid_config(struct be_adapter *adapter)
6b7c5b94 552{
6b7c5b94
SP		 553 u16 vtag[BE_NUM_VLANS_SUPPORTED];
554 u16 ntags = 0, i;
82903e4b 555 int status = 0;
6b7c5b94 556
82903e4b 557 if (adapter->vlans_added <= adapter->max_vlans) {
6b7c5b94
SP		 558 /* Construct VLAN Table to give to HW */
559 for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
560 if (adapter->vlan_tag[i]) {
561 vtag[ntags] = cpu_to_le16(i);
562 ntags++;
563 }
564 }
b31c50a7
SP		 565 status = be_cmd_vlan_config(adapter, adapter->if_handle,
566 vtag, ntags, 1, 0);
6b7c5b94 567 } else {
b31c50a7
SP		 568 status = be_cmd_vlan_config(adapter, adapter->if_handle,
569 NULL, 0, 1, 1);
6b7c5b94 570 }
b31c50a7 571 return status;
6b7c5b94
SP		 572}
573
574static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
575{
576 struct be_adapter *adapter = netdev_priv(netdev);
577 struct be_eq_obj *rx_eq = &adapter->rx_eq;
578 struct be_eq_obj *tx_eq = &adapter->tx_eq;
6b7c5b94 579
8788fdc2
SP		 580 be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
581 be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
6b7c5b94 582 adapter->vlan_grp = grp;
8788fdc2
SP		 583 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
584 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
6b7c5b94
SP		 585}
586
587static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
588{
589 struct be_adapter *adapter = netdev_priv(netdev);
590
ba343c77
SB		 591 if (!be_physfn(adapter))
592 return;
593
6b7c5b94 594 adapter->vlan_tag[vid] = 1;
82903e4b
AK		 595 adapter->vlans_added++;
596 if (adapter->vlans_added <= (adapter->max_vlans + 1))
597 be_vid_config(adapter);
6b7c5b94
SP		 598}
599
600static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
601{
602 struct be_adapter *adapter = netdev_priv(netdev);
603
ba343c77
SB		 604 if (!be_physfn(adapter))
605 return;
606
6b7c5b94 607 adapter->vlan_tag[vid] = 0;
6b7c5b94 608 vlan_group_set_device(adapter->vlan_grp, vid, NULL);
82903e4b
AK		 609 adapter->vlans_added--;
610 if (adapter->vlans_added <= adapter->max_vlans)
611 be_vid_config(adapter);
6b7c5b94
SP		 612}
613
24307eef 614static void be_set_multicast_list(struct net_device *netdev)
6b7c5b94
SP		 615{
616 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 617
24307eef 618 if (netdev->flags & IFF_PROMISC) {
8788fdc2 619 be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
24307eef
SP		 620 adapter->promiscuous = true;
621 goto done;
6b7c5b94
SP		 622 }
623
24307eef
SP		 624 /* BE was previously in promiscous mode; disable it */
625 if (adapter->promiscuous) {
626 adapter->promiscuous = false;
8788fdc2 627 be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
6b7c5b94
SP		 628 }
629
e7b909a6 630 /* Enable multicast promisc if num configured exceeds what we support */
4cd24eaf
JP		 631 if (netdev->flags & IFF_ALLMULTI ||
632 netdev_mc_count(netdev) > BE_MAX_MC) {
0ddf477b 633 be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
e7b909a6 634 &adapter->mc_cmd_mem);
24307eef 635 goto done;
6b7c5b94 636 }
6b7c5b94 637
0ddf477b 638 be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
f31e50a8 639 &adapter->mc_cmd_mem);
24307eef
SP		 640done:
641 return;
6b7c5b94
SP		 642}
643
ba343c77
SB		 644static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
645{
646 struct be_adapter *adapter = netdev_priv(netdev);
647 int status;
648
649 if (!adapter->sriov_enabled)
650 return -EPERM;
651
652 if (!is_valid_ether_addr(mac) || (vf >= num_vfs))
653 return -EINVAL;
654
655 status = be_cmd_pmac_del(adapter, adapter->vf_if_handle[vf],
656 adapter->vf_pmac_id[vf]);
657
658 status = be_cmd_pmac_add(adapter, mac, adapter->vf_if_handle[vf],
659 &adapter->vf_pmac_id[vf]);
660 if (!status)
661 dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
662 mac, vf);
663 return status;
664}
665
4097f663 666static void be_rx_rate_update(struct be_adapter *adapter)
6b7c5b94 667{
4097f663
SP		 668 struct be_drvr_stats *stats = drvr_stats(adapter);
669 ulong now = jiffies;
6b7c5b94 670
4097f663
SP		 671 /* Wrapped around */
672 if (time_before(now, stats->be_rx_jiffies)) {
673 stats->be_rx_jiffies = now;
674 return;
675 }
6b7c5b94
SP		 676
677 /* Update the rate once in two seconds */
4097f663 678 if ((now - stats->be_rx_jiffies) < 2 * HZ)
6b7c5b94
SP		 679 return;
680
65f71b8b
SH		 681 stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
682 - stats->be_rx_bytes_prev,
683 now - stats->be_rx_jiffies);
4097f663 684 stats->be_rx_jiffies = now;
6b7c5b94
SP		 685 stats->be_rx_bytes_prev = stats->be_rx_bytes;
686}
687
4097f663
SP		 688static void be_rx_stats_update(struct be_adapter *adapter,
689 u32 pktsize, u16 numfrags)
690{
691 struct be_drvr_stats *stats = drvr_stats(adapter);
692
693 stats->be_rx_compl++;
694 stats->be_rx_frags += numfrags;
695 stats->be_rx_bytes += pktsize;
91992e44 696 stats->be_rx_pkts++;
4097f663
SP		 697}
698
728a9972
AK		 699static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
700{
701 u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
702
703 l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
704 ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
705 ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
706 if (ip_version) {
707 tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
708 udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
709 }
710 ipv6_chk = (ip_version && (tcpf || udpf));
711
712 return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
713}
714
6b7c5b94
SP		 715static struct be_rx_page_info *
716get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
717{
718 struct be_rx_page_info *rx_page_info;
719 struct be_queue_info *rxq = &adapter->rx_obj.q;
720
721 rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
722 BUG_ON(!rx_page_info->page);
723
205859a2 724 if (rx_page_info->last_page_user) {
fac6da5b 725 pci_unmap_page(adapter->pdev, dma_unmap_addr(rx_page_info, bus),
6b7c5b94 726 adapter->big_page_size, PCI_DMA_FROMDEVICE);
205859a2
AK		 727 rx_page_info->last_page_user = false;
728 }
6b7c5b94
SP		 729
730 atomic_dec(&rxq->used);
731 return rx_page_info;
732}
733
734/* Throwaway the data in the Rx completion */
735static void be_rx_compl_discard(struct be_adapter *adapter,
736 struct be_eth_rx_compl *rxcp)
737{
738 struct be_queue_info *rxq = &adapter->rx_obj.q;
739 struct be_rx_page_info *page_info;
740 u16 rxq_idx, i, num_rcvd;
741
742 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
743 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
744
745 for (i = 0; i < num_rcvd; i++) {
746 page_info = get_rx_page_info(adapter, rxq_idx);
747 put_page(page_info->page);
748 memset(page_info, 0, sizeof(*page_info));
749 index_inc(&rxq_idx, rxq->len);
750 }
751}
752
753/*
754 * skb_fill_rx_data forms a complete skb for an ether frame
755 * indicated by rxcp.
756 */
757static void skb_fill_rx_data(struct be_adapter *adapter,
89420424
SP		 758 struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
759 u16 num_rcvd)
6b7c5b94
SP		 760{
761 struct be_queue_info *rxq = &adapter->rx_obj.q;
762 struct be_rx_page_info *page_info;
89420424 763 u16 rxq_idx, i, j;
fa77406a 764 u32 pktsize, hdr_len, curr_frag_len, size;
6b7c5b94
SP		 765 u8 *start;
766
767 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
768 pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
6b7c5b94
SP		 769
770 page_info = get_rx_page_info(adapter, rxq_idx);
771
772 start = page_address(page_info->page) + page_info->page_offset;
773 prefetch(start);
774
775 /* Copy data in the first descriptor of this completion */
776 curr_frag_len = min(pktsize, rx_frag_size);
777
778 /* Copy the header portion into skb_data */
779 hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
780 memcpy(skb->data, start, hdr_len);
781 skb->len = curr_frag_len;
782 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
783 /* Complete packet has now been moved to data */
784 put_page(page_info->page);
785 skb->data_len = 0;
786 skb->tail += curr_frag_len;
787 } else {
788 skb_shinfo(skb)->nr_frags = 1;
789 skb_shinfo(skb)->frags[0].page = page_info->page;
790 skb_shinfo(skb)->frags[0].page_offset =
791 page_info->page_offset + hdr_len;
792 skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
793 skb->data_len = curr_frag_len - hdr_len;
794 skb->tail += hdr_len;
795 }
205859a2 796 page_info->page = NULL;
6b7c5b94
SP		 797
798 if (pktsize <= rx_frag_size) {
799 BUG_ON(num_rcvd != 1);
76fbb429 800 goto done;
6b7c5b94
SP		 801 }
802
803 /* More frags present for this completion */
fa77406a 804 size = pktsize;
bd46cb6c 805 for (i = 1, j = 0; i < num_rcvd; i++) {
fa77406a 806 size -= curr_frag_len;
6b7c5b94
SP		 807 index_inc(&rxq_idx, rxq->len);
808 page_info = get_rx_page_info(adapter, rxq_idx);
809
fa77406a 810 curr_frag_len = min(size, rx_frag_size);
6b7c5b94 811
bd46cb6c
AK		 812 /* Coalesce all frags from the same physical page in one slot */
813 if (page_info->page_offset == 0) {
814 /* Fresh page */
815 j++;
816 skb_shinfo(skb)->frags[j].page = page_info->page;
817 skb_shinfo(skb)->frags[j].page_offset =
818 page_info->page_offset;
819 skb_shinfo(skb)->frags[j].size = 0;
820 skb_shinfo(skb)->nr_frags++;
821 } else {
822 put_page(page_info->page);
823 }
824
825 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94
SP		 826 skb->len += curr_frag_len;
827 skb->data_len += curr_frag_len;
6b7c5b94 828
205859a2 829 page_info->page = NULL;
6b7c5b94 830 }
bd46cb6c 831 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 832
76fbb429 833done:
4097f663 834 be_rx_stats_update(adapter, pktsize, num_rcvd);
6b7c5b94
SP		 835}
836
5be93b9a 837/* Process the RX completion indicated by rxcp when GRO is disabled */
6b7c5b94
SP		 838static void be_rx_compl_process(struct be_adapter *adapter,
839 struct be_eth_rx_compl *rxcp)
840{
841 struct sk_buff *skb;
dcb9b564 842 u32 vlanf, vid;
89420424 843 u16 num_rcvd;
dcb9b564 844 u8 vtm;
6b7c5b94 845
89420424
SP		 846 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
847 /* Is it a flush compl that has no data */
848 if (unlikely(num_rcvd == 0))
849 return;
850
89d71a66 851 skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
a058a632 852 if (unlikely(!skb)) {
6b7c5b94
SP		 853 if (net_ratelimit())
854 dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
855 be_rx_compl_discard(adapter, rxcp);
856 return;
857 }
858
89420424 859 skb_fill_rx_data(adapter, skb, rxcp, num_rcvd);
6b7c5b94 860
728a9972 861 if (do_pkt_csum(rxcp, adapter->rx_csum))
6b7c5b94 862 skb->ip_summed = CHECKSUM_NONE;
728a9972
AK		 863 else
864 skb->ip_summed = CHECKSUM_UNNECESSARY;
6b7c5b94
SP		 865
866 skb->truesize = skb->len + sizeof(struct sk_buff);
867 skb->protocol = eth_type_trans(skb, adapter->netdev);
6b7c5b94 868
a058a632
SP		 869 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
870 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
871
872 /* vlanf could be wrongly set in some cards.
873 * ignore if vtm is not set */
874 if ((adapter->cap & 0x400) && !vtm)
875 vlanf = 0;
876
877 if (unlikely(vlanf)) {
82903e4b 878 if (!adapter->vlan_grp || adapter->vlans_added == 0) {
6b7c5b94
SP		 879 kfree_skb(skb);
880 return;
881 }
882 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
9cae9e4f 883 vid = swab16(vid);
6b7c5b94
SP		 884 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
885 } else {
886 netif_receive_skb(skb);
887 }
6b7c5b94
SP		 888}
889
5be93b9a
AK		 890/* Process the RX completion indicated by rxcp when GRO is enabled */
891static void be_rx_compl_process_gro(struct be_adapter *adapter,
6b7c5b94
SP		 892 struct be_eth_rx_compl *rxcp)
893{
894 struct be_rx_page_info *page_info;
5be93b9a 895 struct sk_buff *skb = NULL;
6b7c5b94 896 struct be_queue_info *rxq = &adapter->rx_obj.q;
5be93b9a 897 struct be_eq_obj *eq_obj = &adapter->rx_eq;
6b7c5b94 898 u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
bd46cb6c 899 u16 i, rxq_idx = 0, vid, j;
dcb9b564 900 u8 vtm;
6b7c5b94
SP		 901
902 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
89420424
SP		 903 /* Is it a flush compl that has no data */
904 if (unlikely(num_rcvd == 0))
905 return;
906
6b7c5b94
SP		 907 pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
908 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
909 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
dcb9b564
AK		 910 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
911
912 /* vlanf could be wrongly set in some cards.
913 * ignore if vtm is not set */
e1187b3b 914 if ((adapter->cap & 0x400) && !vtm)
dcb9b564 915 vlanf = 0;
6b7c5b94 916
5be93b9a
AK		 917 skb = napi_get_frags(&eq_obj->napi);
918 if (!skb) {
919 be_rx_compl_discard(adapter, rxcp);
920 return;
921 }
922
6b7c5b94 923 remaining = pkt_size;
bd46cb6c 924 for (i = 0, j = -1; i < num_rcvd; i++) {
6b7c5b94
SP		 925 page_info = get_rx_page_info(adapter, rxq_idx);
926
927 curr_frag_len = min(remaining, rx_frag_size);
928
bd46cb6c
AK		 929 /* Coalesce all frags from the same physical page in one slot */
930 if (i == 0 || page_info->page_offset == 0) {
931 /* First frag or Fresh page */
932 j++;
5be93b9a
AK		 933 skb_shinfo(skb)->frags[j].page = page_info->page;
934 skb_shinfo(skb)->frags[j].page_offset =
935 page_info->page_offset;
936 skb_shinfo(skb)->frags[j].size = 0;
bd46cb6c
AK		 937 } else {
938 put_page(page_info->page);
939 }
5be93b9a 940 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94 941
bd46cb6c 942 remaining -= curr_frag_len;
6b7c5b94 943 index_inc(&rxq_idx, rxq->len);
6b7c5b94
SP		 944 memset(page_info, 0, sizeof(*page_info));
945 }
bd46cb6c 946 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 947
5be93b9a
AK		 948 skb_shinfo(skb)->nr_frags = j + 1;
949 skb->len = pkt_size;
950 skb->data_len = pkt_size;
951 skb->truesize += pkt_size;
952 skb->ip_summed = CHECKSUM_UNNECESSARY;
953
6b7c5b94 954 if (likely(!vlanf)) {
5be93b9a 955 napi_gro_frags(&eq_obj->napi);
6b7c5b94
SP		 956 } else {
957 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
9cae9e4f 958 vid = swab16(vid);
6b7c5b94 959
82903e4b 960 if (!adapter->vlan_grp || adapter->vlans_added == 0)
6b7c5b94
SP		 961 return;
962
5be93b9a 963 vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
6b7c5b94
SP		 964 }
965
4097f663 966 be_rx_stats_update(adapter, pkt_size, num_rcvd);
6b7c5b94
SP		 967}
968
969static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
970{
971 struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
972
973 if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
974 return NULL;
975
976 be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
977
6b7c5b94
SP		 978 queue_tail_inc(&adapter->rx_obj.cq);
979 return rxcp;
980}
981
a7a0ef31
SP		 982/* To reset the valid bit, we need to reset the whole word as
983 * when walking the queue the valid entries are little-endian
984 * and invalid entries are host endian
985 */
986static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
987{
988 rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
989}
990
6b7c5b94
SP		 991static inline struct page *be_alloc_pages(u32 size)
992{
993 gfp_t alloc_flags = GFP_ATOMIC;
994 u32 order = get_order(size);
995 if (order > 0)
996 alloc_flags |= __GFP_COMP;
997 return alloc_pages(alloc_flags, order);
998}
999
1000/*
1001 * Allocate a page, split it to fragments of size rx_frag_size and post as
1002 * receive buffers to BE
1003 */
1004static void be_post_rx_frags(struct be_adapter *adapter)
1005{
1006 struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
26d92f92 1007 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
6b7c5b94
SP		 1008 struct be_queue_info *rxq = &adapter->rx_obj.q;
1009 struct page *pagep = NULL;
1010 struct be_eth_rx_d *rxd;
1011 u64 page_dmaaddr = 0, frag_dmaaddr;
1012 u32 posted, page_offset = 0;
1013
6b7c5b94
SP		 1014 page_info = &page_info_tbl[rxq->head];
1015 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
1016 if (!pagep) {
1017 pagep = be_alloc_pages(adapter->big_page_size);
1018 if (unlikely(!pagep)) {
1019 drvr_stats(adapter)->be_ethrx_post_fail++;
1020 break;
1021 }
1022 page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
1023 adapter->big_page_size,
1024 PCI_DMA_FROMDEVICE);
1025 page_info->page_offset = 0;
1026 } else {
1027 get_page(pagep);
1028 page_info->page_offset = page_offset + rx_frag_size;
1029 }
1030 page_offset = page_info->page_offset;
1031 page_info->page = pagep;
fac6da5b 1032 dma_unmap_addr_set(page_info, bus, page_dmaaddr);
6b7c5b94
SP		 1033 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
1034
1035 rxd = queue_head_node(rxq);
1036 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
1037 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
6b7c5b94
SP		 1038
1039 /* Any space left in the current big page for another frag? */
1040 if ((page_offset + rx_frag_size + rx_frag_size) >
1041 adapter->big_page_size) {
1042 pagep = NULL;
1043 page_info->last_page_user = true;
1044 }
26d92f92
SP		 1045
1046 prev_page_info = page_info;
1047 queue_head_inc(rxq);
6b7c5b94
SP		 1048 page_info = &page_info_tbl[rxq->head];
1049 }
1050 if (pagep)
26d92f92 1051 prev_page_info->last_page_user = true;
6b7c5b94
SP		 1052
1053 if (posted) {
6b7c5b94 1054 atomic_add(posted, &rxq->used);
8788fdc2 1055 be_rxq_notify(adapter, rxq->id, posted);
ea1dae11
SP		 1056 } else if (atomic_read(&rxq->used) == 0) {
1057 /* Let be_worker replenish when memory is available */
1058 adapter->rx_post_starved = true;
6b7c5b94 1059 }
6b7c5b94
SP		 1060}
1061
5fb379ee 1062static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
6b7c5b94 1063{
6b7c5b94
SP		 1064 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
1065
1066 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
1067 return NULL;
1068
1069 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1070
1071 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1072
1073 queue_tail_inc(tx_cq);
1074 return txcp;
1075}
1076
1077static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
1078{
1079 struct be_queue_info *txq = &adapter->tx_obj.q;
a73b796e 1080 struct be_eth_wrb *wrb;
6b7c5b94
SP		 1081 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1082 struct sk_buff *sent_skb;
ec43b1a6
SP		 1083 u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
1084 bool unmap_skb_hdr = true;
6b7c5b94 1085
ec43b1a6 1086 sent_skb = sent_skbs[txq->tail];
6b7c5b94 1087 BUG_ON(!sent_skb);
ec43b1a6
SP		 1088 sent_skbs[txq->tail] = NULL;
1089
1090 /* skip header wrb */
a73b796e 1091 queue_tail_inc(txq);
6b7c5b94 1092
ec43b1a6 1093 do {
6b7c5b94 1094 cur_index = txq->tail;
a73b796e 1095 wrb = queue_tail_node(txq);
ec43b1a6 1096 unmap_tx_frag(adapter->pdev, wrb, (unmap_skb_hdr &&
e743d313 1097 skb_headlen(sent_skb)));
ec43b1a6
SP		 1098 unmap_skb_hdr = false;
1099
6b7c5b94
SP		 1100 num_wrbs++;
1101 queue_tail_inc(txq);
ec43b1a6 1102 } while (cur_index != last_index);
6b7c5b94
SP		 1103
1104 atomic_sub(num_wrbs, &txq->used);
a73b796e 1105
6b7c5b94
SP		 1106 kfree_skb(sent_skb);
1107}
1108
859b1e4e
SP		 1109static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
1110{
1111 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1112
1113 if (!eqe->evt)
1114 return NULL;
1115
1116 eqe->evt = le32_to_cpu(eqe->evt);
1117 queue_tail_inc(&eq_obj->q);
1118 return eqe;
1119}
1120
1121static int event_handle(struct be_adapter *adapter,
1122 struct be_eq_obj *eq_obj)
1123{
1124 struct be_eq_entry *eqe;
1125 u16 num = 0;
1126
1127 while ((eqe = event_get(eq_obj)) != NULL) {
1128 eqe->evt = 0;
1129 num++;
1130 }
1131
1132 /* Deal with any spurious interrupts that come
1133 * without events
1134 */
1135 be_eq_notify(adapter, eq_obj->q.id, true, true, num);
1136 if (num)
1137 napi_schedule(&eq_obj->napi);
1138
1139 return num;
1140}
1141
1142/* Just read and notify events without processing them.
1143 * Used at the time of destroying event queues */
1144static void be_eq_clean(struct be_adapter *adapter,
1145 struct be_eq_obj *eq_obj)
1146{
1147 struct be_eq_entry *eqe;
1148 u16 num = 0;
1149
1150 while ((eqe = event_get(eq_obj)) != NULL) {
1151 eqe->evt = 0;
1152 num++;
1153 }
1154
1155 if (num)
1156 be_eq_notify(adapter, eq_obj->q.id, false, true, num);
1157}
1158
6b7c5b94
SP		 1159static void be_rx_q_clean(struct be_adapter *adapter)
1160{
1161 struct be_rx_page_info *page_info;
1162 struct be_queue_info *rxq = &adapter->rx_obj.q;
1163 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1164 struct be_eth_rx_compl *rxcp;
1165 u16 tail;
1166
1167 /* First cleanup pending rx completions */
1168 while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
1169 be_rx_compl_discard(adapter, rxcp);
a7a0ef31 1170 be_rx_compl_reset(rxcp);
8788fdc2 1171 be_cq_notify(adapter, rx_cq->id, true, 1);
6b7c5b94
SP		 1172 }
1173
1174 /* Then free posted rx buffer that were not used */
1175 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
cdab23b7 1176 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
6b7c5b94
SP		 1177 page_info = get_rx_page_info(adapter, tail);
1178 put_page(page_info->page);
1179 memset(page_info, 0, sizeof(*page_info));
1180 }
1181 BUG_ON(atomic_read(&rxq->used));
1182}
1183
a8e9179a 1184static void be_tx_compl_clean(struct be_adapter *adapter)
6b7c5b94 1185{
a8e9179a 1186 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1187 struct be_queue_info *txq = &adapter->tx_obj.q;
a8e9179a
SP		 1188 struct be_eth_tx_compl *txcp;
1189 u16 end_idx, cmpl = 0, timeo = 0;
b03388d6
SP		 1190 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1191 struct sk_buff *sent_skb;
1192 bool dummy_wrb;
a8e9179a
SP		 1193
1194 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1195 do {
1196 while ((txcp = be_tx_compl_get(tx_cq))) {
1197 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1198 wrb_index, txcp);
1199 be_tx_compl_process(adapter, end_idx);
1200 cmpl++;
1201 }
1202 if (cmpl) {
1203 be_cq_notify(adapter, tx_cq->id, false, cmpl);
1204 cmpl = 0;
1205 }
1206
1207 if (atomic_read(&txq->used) == 0 || ++timeo > 200)
1208 break;
1209
1210 mdelay(1);
1211 } while (true);
1212
1213 if (atomic_read(&txq->used))
1214 dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
1215 atomic_read(&txq->used));
b03388d6
SP		 1216
1217 /* free posted tx for which compls will never arrive */
1218 while (atomic_read(&txq->used)) {
1219 sent_skb = sent_skbs[txq->tail];
1220 end_idx = txq->tail;
1221 index_adv(&end_idx,
1222 wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
1223 be_tx_compl_process(adapter, end_idx);
1224 }
6b7c5b94
SP		 1225}
1226
5fb379ee
SP		 1227static void be_mcc_queues_destroy(struct be_adapter *adapter)
1228{
1229 struct be_queue_info *q;
5fb379ee 1230
8788fdc2 1231 q = &adapter->mcc_obj.q;
5fb379ee 1232 if (q->created)
8788fdc2 1233 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
5fb379ee
SP		 1234 be_queue_free(adapter, q);
1235
8788fdc2 1236 q = &adapter->mcc_obj.cq;
5fb379ee 1237 if (q->created)
8788fdc2 1238 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
5fb379ee
SP		 1239 be_queue_free(adapter, q);
1240}
1241
1242/* Must be called only after TX qs are created as MCC shares TX EQ */
1243static int be_mcc_queues_create(struct be_adapter *adapter)
1244{
1245 struct be_queue_info *q, *cq;
5fb379ee
SP		 1246
1247 /* Alloc MCC compl queue */
8788fdc2 1248 cq = &adapter->mcc_obj.cq;
5fb379ee 1249 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
efd2e40a 1250 sizeof(struct be_mcc_compl)))
5fb379ee
SP		 1251 goto err;
1252
1253 /* Ask BE to create MCC compl queue; share TX's eq */
8788fdc2 1254 if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
5fb379ee
SP		 1255 goto mcc_cq_free;
1256
1257 /* Alloc MCC queue */
8788fdc2 1258 q = &adapter->mcc_obj.q;
5fb379ee
SP		 1259 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1260 goto mcc_cq_destroy;
1261
1262 /* Ask BE to create MCC queue */
8788fdc2 1263 if (be_cmd_mccq_create(adapter, q, cq))
5fb379ee
SP		 1264 goto mcc_q_free;
1265
1266 return 0;
1267
1268mcc_q_free:
1269 be_queue_free(adapter, q);
1270mcc_cq_destroy:
8788fdc2 1271 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
5fb379ee
SP		 1272mcc_cq_free:
1273 be_queue_free(adapter, cq);
1274err:
1275 return -1;
1276}
1277
6b7c5b94
SP		 1278static void be_tx_queues_destroy(struct be_adapter *adapter)
1279{
1280 struct be_queue_info *q;
1281
1282 q = &adapter->tx_obj.q;
a8e9179a 1283 if (q->created)
8788fdc2 1284 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
6b7c5b94
SP		 1285 be_queue_free(adapter, q);
1286
1287 q = &adapter->tx_obj.cq;
1288 if (q->created)
8788fdc2 1289 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1290 be_queue_free(adapter, q);
1291
859b1e4e
SP		 1292 /* Clear any residual events */
1293 be_eq_clean(adapter, &adapter->tx_eq);
1294
6b7c5b94
SP		 1295 q = &adapter->tx_eq.q;
1296 if (q->created)
8788fdc2 1297 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1298 be_queue_free(adapter, q);
1299}
1300
1301static int be_tx_queues_create(struct be_adapter *adapter)
1302{
1303 struct be_queue_info *eq, *q, *cq;
1304
1305 adapter->tx_eq.max_eqd = 0;
1306 adapter->tx_eq.min_eqd = 0;
1307 adapter->tx_eq.cur_eqd = 96;
1308 adapter->tx_eq.enable_aic = false;
1309 /* Alloc Tx Event queue */
1310 eq = &adapter->tx_eq.q;
1311 if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
1312 return -1;
1313
1314 /* Ask BE to create Tx Event queue */
8788fdc2 1315 if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
6b7c5b94 1316 goto tx_eq_free;
ba343c77
SB		 1317 adapter->base_eq_id = adapter->tx_eq.q.id;
1318
6b7c5b94
SP		 1319 /* Alloc TX eth compl queue */
1320 cq = &adapter->tx_obj.cq;
1321 if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
1322 sizeof(struct be_eth_tx_compl)))
1323 goto tx_eq_destroy;
1324
1325 /* Ask BE to create Tx eth compl queue */
8788fdc2 1326 if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
6b7c5b94
SP		 1327 goto tx_cq_free;
1328
1329 /* Alloc TX eth queue */
1330 q = &adapter->tx_obj.q;
1331 if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
1332 goto tx_cq_destroy;
1333
1334 /* Ask BE to create Tx eth queue */
8788fdc2 1335 if (be_cmd_txq_create(adapter, q, cq))
6b7c5b94
SP		 1336 goto tx_q_free;
1337 return 0;
1338
1339tx_q_free:
1340 be_queue_free(adapter, q);
1341tx_cq_destroy:
8788fdc2 1342 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1343tx_cq_free:
1344 be_queue_free(adapter, cq);
1345tx_eq_destroy:
8788fdc2 1346 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1347tx_eq_free:
1348 be_queue_free(adapter, eq);
1349 return -1;
1350}
1351
1352static void be_rx_queues_destroy(struct be_adapter *adapter)
1353{
1354 struct be_queue_info *q;
1355
1356 q = &adapter->rx_obj.q;
1357 if (q->created) {
8788fdc2 1358 be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
89420424
SP		 1359
1360 /* After the rxq is invalidated, wait for a grace time
1361 * of 1ms for all dma to end and the flush compl to arrive
1362 */
1363 mdelay(1);
6b7c5b94
SP		 1364 be_rx_q_clean(adapter);
1365 }
1366 be_queue_free(adapter, q);
1367
1368 q = &adapter->rx_obj.cq;
1369 if (q->created)
8788fdc2 1370 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1371 be_queue_free(adapter, q);
1372
859b1e4e
SP		 1373 /* Clear any residual events */
1374 be_eq_clean(adapter, &adapter->rx_eq);
1375
6b7c5b94
SP		 1376 q = &adapter->rx_eq.q;
1377 if (q->created)
8788fdc2 1378 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1379 be_queue_free(adapter, q);
1380}
1381
1382static int be_rx_queues_create(struct be_adapter *adapter)
1383{
1384 struct be_queue_info *eq, *q, *cq;
1385 int rc;
1386
6b7c5b94
SP		 1387 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
1388 adapter->rx_eq.max_eqd = BE_MAX_EQD;
1389 adapter->rx_eq.min_eqd = 0;
1390 adapter->rx_eq.cur_eqd = 0;
1391 adapter->rx_eq.enable_aic = true;
1392
1393 /* Alloc Rx Event queue */
1394 eq = &adapter->rx_eq.q;
1395 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1396 sizeof(struct be_eq_entry));
1397 if (rc)
1398 return rc;
1399
1400 /* Ask BE to create Rx Event queue */
8788fdc2 1401 rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
6b7c5b94
SP		 1402 if (rc)
1403 goto rx_eq_free;
1404
1405 /* Alloc RX eth compl queue */
1406 cq = &adapter->rx_obj.cq;
1407 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1408 sizeof(struct be_eth_rx_compl));
1409 if (rc)
1410 goto rx_eq_destroy;
1411
1412 /* Ask BE to create Rx eth compl queue */
8788fdc2 1413 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
6b7c5b94
SP		 1414 if (rc)
1415 goto rx_cq_free;
1416
1417 /* Alloc RX eth queue */
1418 q = &adapter->rx_obj.q;
1419 rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
1420 if (rc)
1421 goto rx_cq_destroy;
1422
1423 /* Ask BE to create Rx eth queue */
8788fdc2 1424 rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
6b7c5b94
SP		 1425 BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
1426 if (rc)
1427 goto rx_q_free;
1428
1429 return 0;
1430rx_q_free:
1431 be_queue_free(adapter, q);
1432rx_cq_destroy:
8788fdc2 1433 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1434rx_cq_free:
1435 be_queue_free(adapter, cq);
1436rx_eq_destroy:
8788fdc2 1437 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1438rx_eq_free:
1439 be_queue_free(adapter, eq);
1440 return rc;
1441}
6b7c5b94 1442
b628bde2
SP		 1443/* There are 8 evt ids per func. Retruns the evt id's bit number */
1444static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
1445{
ba343c77 1446 return eq_id - adapter->base_eq_id;
b628bde2
SP		 1447}
1448
6b7c5b94
SP		 1449static irqreturn_t be_intx(int irq, void *dev)
1450{
1451 struct be_adapter *adapter = dev;
8788fdc2 1452 int isr;
6b7c5b94 1453
8788fdc2 1454 isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
55bdeed9 1455 (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
c001c213 1456 if (!isr)
8788fdc2 1457 return IRQ_NONE;
6b7c5b94 1458
8788fdc2
SP		 1459 event_handle(adapter, &adapter->tx_eq);
1460 event_handle(adapter, &adapter->rx_eq);
c001c213 1461
8788fdc2 1462 return IRQ_HANDLED;
6b7c5b94
SP		 1463}
1464
1465static irqreturn_t be_msix_rx(int irq, void *dev)
1466{
1467 struct be_adapter *adapter = dev;
1468
8788fdc2 1469 event_handle(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1470
1471 return IRQ_HANDLED;
1472}
1473
5fb379ee 1474static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
6b7c5b94
SP		 1475{
1476 struct be_adapter *adapter = dev;
1477
8788fdc2 1478 event_handle(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1479
1480 return IRQ_HANDLED;
1481}
1482
5be93b9a 1483static inline bool do_gro(struct be_adapter *adapter,
6b7c5b94
SP		 1484 struct be_eth_rx_compl *rxcp)
1485{
1486 int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
1487 int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
1488
1489 if (err)
1490 drvr_stats(adapter)->be_rxcp_err++;
1491
5be93b9a 1492 return (tcp_frame && !err) ? true : false;
6b7c5b94
SP		 1493}
1494
1495int be_poll_rx(struct napi_struct *napi, int budget)
1496{
1497 struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
1498 struct be_adapter *adapter =
1499 container_of(rx_eq, struct be_adapter, rx_eq);
1500 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1501 struct be_eth_rx_compl *rxcp;
1502 u32 work_done;
1503
b7b83ac3 1504 adapter->stats.drvr_stats.be_rx_polls++;
6b7c5b94
SP		 1505 for (work_done = 0; work_done < budget; work_done++) {
1506 rxcp = be_rx_compl_get(adapter);
1507 if (!rxcp)
1508 break;
1509
5be93b9a
AK		 1510 if (do_gro(adapter, rxcp))
1511 be_rx_compl_process_gro(adapter, rxcp);
6b7c5b94
SP		 1512 else
1513 be_rx_compl_process(adapter, rxcp);
a7a0ef31
SP		 1514
1515 be_rx_compl_reset(rxcp);
6b7c5b94
SP		 1516 }
1517
6b7c5b94
SP		 1518 /* Refill the queue */
1519 if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
1520 be_post_rx_frags(adapter);
1521
1522 /* All consumed */
1523 if (work_done < budget) {
1524 napi_complete(napi);
8788fdc2 1525 be_cq_notify(adapter, rx_cq->id, true, work_done);
6b7c5b94
SP		 1526 } else {
1527 /* More to be consumed; continue with interrupts disabled */
8788fdc2 1528 be_cq_notify(adapter, rx_cq->id, false, work_done);
6b7c5b94
SP		 1529 }
1530 return work_done;
1531}
1532
f31e50a8
SP		 1533/* As TX and MCC share the same EQ check for both TX and MCC completions.
1534 * For TX/MCC we don't honour budget; consume everything
1535 */
1536static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
6b7c5b94 1537{
f31e50a8
SP		 1538 struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
1539 struct be_adapter *adapter =
1540 container_of(tx_eq, struct be_adapter, tx_eq);
5fb379ee
SP		 1541 struct be_queue_info *txq = &adapter->tx_obj.q;
1542 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1543 struct be_eth_tx_compl *txcp;
f31e50a8 1544 int tx_compl = 0, mcc_compl, status = 0;
6b7c5b94
SP		 1545 u16 end_idx;
1546
5fb379ee 1547 while ((txcp = be_tx_compl_get(tx_cq))) {
6b7c5b94 1548 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
f31e50a8 1549 wrb_index, txcp);
6b7c5b94 1550 be_tx_compl_process(adapter, end_idx);
f31e50a8 1551 tx_compl++;
6b7c5b94
SP		 1552 }
1553
f31e50a8
SP		 1554 mcc_compl = be_process_mcc(adapter, &status);
1555
1556 napi_complete(napi);
1557
1558 if (mcc_compl) {
1559 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1560 be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
1561 }
1562
1563 if (tx_compl) {
1564 be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
5fb379ee
SP		 1565
1566 /* As Tx wrbs have been freed up, wake up netdev queue if
1567 * it was stopped due to lack of tx wrbs.
1568 */
1569 if (netif_queue_stopped(adapter->netdev) &&
6b7c5b94 1570 atomic_read(&txq->used) < txq->len / 2) {
5fb379ee
SP		 1571 netif_wake_queue(adapter->netdev);
1572 }
1573
1574 drvr_stats(adapter)->be_tx_events++;
f31e50a8 1575 drvr_stats(adapter)->be_tx_compl += tx_compl;
6b7c5b94 1576 }
6b7c5b94
SP		 1577
1578 return 1;
1579}
1580
ea1dae11
SP		 1581static void be_worker(struct work_struct *work)
1582{
1583 struct be_adapter *adapter =
1584 container_of(work, struct be_adapter, work.work);
ea1dae11 1585
b31c50a7 1586 be_cmd_get_stats(adapter, &adapter->stats.cmd);
ea1dae11
SP		 1587
1588 /* Set EQ delay */
1589 be_rx_eqd_update(adapter);
1590
4097f663
SP		 1591 be_tx_rate_update(adapter);
1592 be_rx_rate_update(adapter);
1593
ea1dae11
SP		 1594 if (adapter->rx_post_starved) {
1595 adapter->rx_post_starved = false;
1596 be_post_rx_frags(adapter);
1597 }
1598
1599 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
1600}
1601
8d56ff11
SP		 1602static void be_msix_disable(struct be_adapter *adapter)
1603{
1604 if (adapter->msix_enabled) {
1605 pci_disable_msix(adapter->pdev);
1606 adapter->msix_enabled = false;
1607 }
1608}
1609
6b7c5b94
SP		 1610static void be_msix_enable(struct be_adapter *adapter)
1611{
1612 int i, status;
1613
1614 for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
1615 adapter->msix_entries[i].entry = i;
1616
1617 status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1618 BE_NUM_MSIX_VECTORS);
1619 if (status == 0)
1620 adapter->msix_enabled = true;
6b7c5b94
SP		 1621}
1622
ba343c77
SB		 1623static void be_sriov_enable(struct be_adapter *adapter)
1624{
1625#ifdef CONFIG_PCI_IOV
1626 int status;
1627 if (be_physfn(adapter) && num_vfs) {
1628 status = pci_enable_sriov(adapter->pdev, num_vfs);
1629 adapter->sriov_enabled = status ? false : true;
1630 }
1631#endif
ba343c77
SB		 1632}
1633
1634static void be_sriov_disable(struct be_adapter *adapter)
1635{
1636#ifdef CONFIG_PCI_IOV
1637 if (adapter->sriov_enabled) {
1638 pci_disable_sriov(adapter->pdev);
1639 adapter->sriov_enabled = false;
1640 }
1641#endif
1642}
1643
6b7c5b94
SP		 1644static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
1645{
b628bde2
SP		 1646 return adapter->msix_entries[
1647 be_evt_bit_get(adapter, eq_id)].vector;
6b7c5b94
SP		 1648}
1649
b628bde2
SP		 1650static int be_request_irq(struct be_adapter *adapter,
1651 struct be_eq_obj *eq_obj,
1652 void *handler, char *desc)
6b7c5b94
SP		 1653{
1654 struct net_device *netdev = adapter->netdev;
b628bde2
SP		 1655 int vec;
1656
1657 sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
1658 vec = be_msix_vec_get(adapter, eq_obj->q.id);
1659 return request_irq(vec, handler, 0, eq_obj->desc, adapter);
1660}
1661
1662static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
1663{
1664 int vec = be_msix_vec_get(adapter, eq_obj->q.id);
1665 free_irq(vec, adapter);
1666}
6b7c5b94 1667
b628bde2
SP		 1668static int be_msix_register(struct be_adapter *adapter)
1669{
1670 int status;
1671
1672 status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
6b7c5b94
SP		 1673 if (status)
1674 goto err;
1675
b628bde2
SP		 1676 status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
1677 if (status)
1678 goto free_tx_irq;
1679
6b7c5b94 1680 return 0;
b628bde2
SP		 1681
1682free_tx_irq:
1683 be_free_irq(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1684err:
1685 dev_warn(&adapter->pdev->dev,
1686 "MSIX Request IRQ failed - err %d\n", status);
1687 pci_disable_msix(adapter->pdev);
1688 adapter->msix_enabled = false;
1689 return status;
1690}
1691
1692static int be_irq_register(struct be_adapter *adapter)
1693{
1694 struct net_device *netdev = adapter->netdev;
1695 int status;
1696
1697 if (adapter->msix_enabled) {
1698 status = be_msix_register(adapter);
1699 if (status == 0)
1700 goto done;
ba343c77
SB		 1701 /* INTx is not supported for VF */
1702 if (!be_physfn(adapter))
1703 return status;
6b7c5b94
SP		 1704 }
1705
1706 /* INTx */
1707 netdev->irq = adapter->pdev->irq;
1708 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
1709 adapter);
1710 if (status) {
1711 dev_err(&adapter->pdev->dev,
1712 "INTx request IRQ failed - err %d\n", status);
1713 return status;
1714 }
1715done:
1716 adapter->isr_registered = true;
1717 return 0;
1718}
1719
1720static void be_irq_unregister(struct be_adapter *adapter)
1721{
1722 struct net_device *netdev = adapter->netdev;
6b7c5b94
SP		 1723
1724 if (!adapter->isr_registered)
1725 return;
1726
1727 /* INTx */
1728 if (!adapter->msix_enabled) {
1729 free_irq(netdev->irq, adapter);
1730 goto done;
1731 }
1732
1733 /* MSIx */
b628bde2
SP		 1734 be_free_irq(adapter, &adapter->tx_eq);
1735 be_free_irq(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1736done:
1737 adapter->isr_registered = false;
6b7c5b94
SP		 1738}
1739
889cd4b2
SP		 1740static int be_close(struct net_device *netdev)
1741{
1742 struct be_adapter *adapter = netdev_priv(netdev);
1743 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1744 struct be_eq_obj *tx_eq = &adapter->tx_eq;
1745 int vec;
1746
1747 cancel_delayed_work_sync(&adapter->work);
1748
1749 be_async_mcc_disable(adapter);
1750
1751 netif_stop_queue(netdev);
1752 netif_carrier_off(netdev);
1753 adapter->link_up = false;
1754
1755 be_intr_set(adapter, false);
1756
1757 if (adapter->msix_enabled) {
1758 vec = be_msix_vec_get(adapter, tx_eq->q.id);
1759 synchronize_irq(vec);
1760 vec = be_msix_vec_get(adapter, rx_eq->q.id);
1761 synchronize_irq(vec);
1762 } else {
1763 synchronize_irq(netdev->irq);
1764 }
1765 be_irq_unregister(adapter);
1766
1767 napi_disable(&rx_eq->napi);
1768 napi_disable(&tx_eq->napi);
1769
1770 /* Wait for all pending tx completions to arrive so that
1771 * all tx skbs are freed.
1772 */
1773 be_tx_compl_clean(adapter);
1774
1775 return 0;
1776}
1777
6b7c5b94
SP		 1778static int be_open(struct net_device *netdev)
1779{
1780 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94
SP		 1781 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1782 struct be_eq_obj *tx_eq = &adapter->tx_eq;
a8f447bd
SP		 1783 bool link_up;
1784 int status;
0388f251
SB		 1785 u8 mac_speed;
1786 u16 link_speed;
5fb379ee
SP		 1787
1788 /* First time posting */
1789 be_post_rx_frags(adapter);
1790
1791 napi_enable(&rx_eq->napi);
1792 napi_enable(&tx_eq->napi);
1793
1794 be_irq_register(adapter);
1795
8788fdc2 1796 be_intr_set(adapter, true);
5fb379ee
SP		 1797
1798 /* The evt queues are created in unarmed state; arm them */
8788fdc2
SP		 1799 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
1800 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
5fb379ee
SP		 1801
1802 /* Rx compl queue may be in unarmed state; rearm it */
8788fdc2 1803 be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
5fb379ee 1804
7a1e9b20
SP		 1805 /* Now that interrupts are on we can process async mcc */
1806 be_async_mcc_enable(adapter);
1807
889cd4b2
SP		 1808 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
1809
0388f251
SB		 1810 status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
1811 &link_speed);
a8f447bd 1812 if (status)
889cd4b2 1813 goto err;
a8f447bd 1814 be_link_status_update(adapter, link_up);
5fb379ee 1815
889cd4b2 1816 if (be_physfn(adapter)) {
ba343c77 1817 status = be_vid_config(adapter);
889cd4b2
SP		 1818 if (status)
1819 goto err;
4f2aa89c 1820
ba343c77
SB		 1821 status = be_cmd_set_flow_control(adapter,
1822 adapter->tx_fc, adapter->rx_fc);
1823 if (status)
889cd4b2 1824 goto err;
ba343c77 1825 }
4f2aa89c 1826
889cd4b2
SP		 1827 return 0;
1828err:
1829 be_close(adapter->netdev);
1830 return -EIO;
5fb379ee
SP		 1831}
1832
71d8d1b5
AK		 1833static int be_setup_wol(struct be_adapter *adapter, bool enable)
1834{
1835 struct be_dma_mem cmd;
1836 int status = 0;
1837 u8 mac[ETH_ALEN];
1838
1839 memset(mac, 0, ETH_ALEN);
1840
1841 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
1842 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
1843 if (cmd.va == NULL)
1844 return -1;
1845 memset(cmd.va, 0, cmd.size);
1846
1847 if (enable) {
1848 status = pci_write_config_dword(adapter->pdev,
1849 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
1850 if (status) {
1851 dev_err(&adapter->pdev->dev,
2381a55c 1852 "Could not enable Wake-on-lan\n");
71d8d1b5
AK		 1853 pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
1854 cmd.dma);
1855 return status;
1856 }
1857 status = be_cmd_enable_magic_wol(adapter,
1858 adapter->netdev->dev_addr, &cmd);
1859 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
1860 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
1861 } else {
1862 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
1863 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
1864 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
1865 }
1866
1867 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
1868 return status;
1869}
1870
5fb379ee
SP		 1871static int be_setup(struct be_adapter *adapter)
1872{
5fb379ee 1873 struct net_device *netdev = adapter->netdev;
ba343c77 1874 u32 cap_flags, en_flags, vf = 0;
6b7c5b94 1875 int status;
ba343c77
SB		 1876 u8 mac[ETH_ALEN];
1877
1878 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST;
6b7c5b94 1879
ba343c77
SB		 1880 if (be_physfn(adapter)) {
1881 cap_flags |= BE_IF_FLAGS_MCAST_PROMISCUOUS |
1882 BE_IF_FLAGS_PROMISCUOUS |
1883 BE_IF_FLAGS_PASS_L3L4_ERRORS;
1884 en_flags |= BE_IF_FLAGS_PASS_L3L4_ERRORS;
1885 }
73d540f2
SP		 1886
1887 status = be_cmd_if_create(adapter, cap_flags, en_flags,
1888 netdev->dev_addr, false/* pmac_invalid */,
ba343c77 1889 &adapter->if_handle, &adapter->pmac_id, 0);
6b7c5b94
SP		 1890 if (status != 0)
1891 goto do_none;
1892
ba343c77
SB		 1893 if (be_physfn(adapter)) {
1894 while (vf < num_vfs) {
1895 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED
1896 | BE_IF_FLAGS_BROADCAST;
1897 status = be_cmd_if_create(adapter, cap_flags, en_flags,
1898 mac, true, &adapter->vf_if_handle[vf],
1899 NULL, vf+1);
1900 if (status) {
1901 dev_err(&adapter->pdev->dev,
1902 "Interface Create failed for VF %d\n", vf);
1903 goto if_destroy;
1904 }
1905 vf++;
84e5b9f7 1906 }
ba343c77
SB		 1907 } else if (!be_physfn(adapter)) {
1908 status = be_cmd_mac_addr_query(adapter, mac,
1909 MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
1910 if (!status) {
1911 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
1912 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
1913 }
1914 }
1915
6b7c5b94
SP		 1916 status = be_tx_queues_create(adapter);
1917 if (status != 0)
1918 goto if_destroy;
1919
1920 status = be_rx_queues_create(adapter);
1921 if (status != 0)
1922 goto tx_qs_destroy;
1923
5fb379ee
SP		 1924 status = be_mcc_queues_create(adapter);
1925 if (status != 0)
1926 goto rx_qs_destroy;
6b7c5b94 1927
0dffc83e
AK		 1928 adapter->link_speed = -1;
1929
6b7c5b94
SP		 1930 return 0;
1931
5fb379ee
SP		 1932rx_qs_destroy:
1933 be_rx_queues_destroy(adapter);
6b7c5b94
SP		 1934tx_qs_destroy:
1935 be_tx_queues_destroy(adapter);
1936if_destroy:
ba343c77
SB		 1937 for (vf = 0; vf < num_vfs; vf++)
1938 if (adapter->vf_if_handle[vf])
1939 be_cmd_if_destroy(adapter, adapter->vf_if_handle[vf]);
8788fdc2 1940 be_cmd_if_destroy(adapter, adapter->if_handle);
6b7c5b94
SP		 1941do_none:
1942 return status;
1943}
1944
5fb379ee
SP		 1945static int be_clear(struct be_adapter *adapter)
1946{
1a8887d8 1947 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 1948 be_rx_queues_destroy(adapter);
1949 be_tx_queues_destroy(adapter);
1950
8788fdc2 1951 be_cmd_if_destroy(adapter, adapter->if_handle);
5fb379ee 1952
2243e2e9
SP		 1953 /* tell fw we're done with firing cmds */
1954 be_cmd_fw_clean(adapter);
5fb379ee
SP		 1955 return 0;
1956}
1957
6b7c5b94 1958
84517482
AK		 1959#define FW_FILE_HDR_SIGN "ServerEngines Corp. "
1960char flash_cookie[2][16] = {"*** SE FLAS",
1961 "H DIRECTORY *** "};
fa9a6fed
SB		 1962
1963static bool be_flash_redboot(struct be_adapter *adapter,
3f0d4560
AK		 1964 const u8 *p, u32 img_start, int image_size,
1965 int hdr_size)
fa9a6fed
SB		 1966{
1967 u32 crc_offset;
1968 u8 flashed_crc[4];
1969 int status;
3f0d4560
AK		 1970
1971 crc_offset = hdr_size + img_start + image_size - 4;
1972
fa9a6fed 1973 p += crc_offset;
3f0d4560
AK		 1974
1975 status = be_cmd_get_flash_crc(adapter, flashed_crc,
f510fc64 1976 (image_size - 4));
fa9a6fed
SB		 1977 if (status) {
1978 dev_err(&adapter->pdev->dev,
1979 "could not get crc from flash, not flashing redboot\n");
1980 return false;
1981 }
1982
1983 /*update redboot only if crc does not match*/
1984 if (!memcmp(flashed_crc, p, 4))
1985 return false;
1986 else
1987 return true;
fa9a6fed
SB		 1988}
1989
3f0d4560 1990static int be_flash_data(struct be_adapter *adapter,
84517482 1991 const struct firmware *fw,
3f0d4560
AK		 1992 struct be_dma_mem *flash_cmd, int num_of_images)
1993
84517482 1994{
3f0d4560
AK		 1995 int status = 0, i, filehdr_size = 0;
1996 u32 total_bytes = 0, flash_op;
84517482
AK		 1997 int num_bytes;
1998 const u8 *p = fw->data;
1999 struct be_cmd_write_flashrom *req = flash_cmd->va;
3f0d4560 2000 struct flash_comp *pflashcomp;
9fe96934 2001 int num_comp;
3f0d4560 2002
9fe96934 2003 struct flash_comp gen3_flash_types[9] = {
3f0d4560
AK		 2004 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
2005 FLASH_IMAGE_MAX_SIZE_g3},
2006 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
2007 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
2008 { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
2009 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2010 { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
2011 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2012 { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
2013 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2014 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
2015 FLASH_IMAGE_MAX_SIZE_g3},
2016 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
2017 FLASH_IMAGE_MAX_SIZE_g3},
2018 { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
9fe96934
SB		 2019 FLASH_IMAGE_MAX_SIZE_g3},
2020 { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
2021 FLASH_NCSI_IMAGE_MAX_SIZE_g3}
3f0d4560
AK		 2022 };
2023 struct flash_comp gen2_flash_types[8] = {
2024 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
2025 FLASH_IMAGE_MAX_SIZE_g2},
2026 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
2027 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
2028 { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
2029 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2030 { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
2031 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2032 { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
2033 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2034 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
2035 FLASH_IMAGE_MAX_SIZE_g2},
2036 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
2037 FLASH_IMAGE_MAX_SIZE_g2},
2038 { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
2039 FLASH_IMAGE_MAX_SIZE_g2}
2040 };
2041
2042 if (adapter->generation == BE_GEN3) {
2043 pflashcomp = gen3_flash_types;
2044 filehdr_size = sizeof(struct flash_file_hdr_g3);
9fe96934 2045 num_comp = 9;
3f0d4560
AK		 2046 } else {
2047 pflashcomp = gen2_flash_types;
2048 filehdr_size = sizeof(struct flash_file_hdr_g2);
9fe96934 2049 num_comp = 8;
84517482 2050 }
9fe96934
SB		 2051 for (i = 0; i < num_comp; i++) {
2052 if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
2053 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2054 continue;
3f0d4560
AK		 2055 if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
2056 (!be_flash_redboot(adapter, fw->data,
2057 pflashcomp[i].offset, pflashcomp[i].size,
2058 filehdr_size)))
2059 continue;
2060 p = fw->data;
2061 p += filehdr_size + pflashcomp[i].offset
2062 + (num_of_images * sizeof(struct image_hdr));
2063 if (p + pflashcomp[i].size > fw->data + fw->size)
84517482 2064 return -1;
3f0d4560
AK		 2065 total_bytes = pflashcomp[i].size;
2066 while (total_bytes) {
2067 if (total_bytes > 32*1024)
2068 num_bytes = 32*1024;
2069 else
2070 num_bytes = total_bytes;
2071 total_bytes -= num_bytes;
2072
2073 if (!total_bytes)
2074 flash_op = FLASHROM_OPER_FLASH;
2075 else
2076 flash_op = FLASHROM_OPER_SAVE;
2077 memcpy(req->params.data_buf, p, num_bytes);
2078 p += num_bytes;
2079 status = be_cmd_write_flashrom(adapter, flash_cmd,
2080 pflashcomp[i].optype, flash_op, num_bytes);
2081 if (status) {
2082 dev_err(&adapter->pdev->dev,
2083 "cmd to write to flash rom failed.\n");
2084 return -1;
2085 }
2086 yield();
84517482 2087 }
84517482 2088 }
84517482
AK		 2089 return 0;
2090}
2091
3f0d4560
AK		 2092static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
2093{
2094 if (fhdr == NULL)
2095 return 0;
2096 if (fhdr->build[0] == '3')
2097 return BE_GEN3;
2098 else if (fhdr->build[0] == '2')
2099 return BE_GEN2;
2100 else
2101 return 0;
2102}
2103
84517482
AK		 2104int be_load_fw(struct be_adapter *adapter, u8 *func)
2105{
2106 char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
2107 const struct firmware *fw;
3f0d4560
AK		 2108 struct flash_file_hdr_g2 *fhdr;
2109 struct flash_file_hdr_g3 *fhdr3;
2110 struct image_hdr *img_hdr_ptr = NULL;
84517482 2111 struct be_dma_mem flash_cmd;
8b93b710 2112 int status, i = 0, num_imgs = 0;
84517482 2113 const u8 *p;
84517482 2114
84517482
AK		 2115 strcpy(fw_file, func);
2116
2117 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
2118 if (status)
2119 goto fw_exit;
2120
2121 p = fw->data;
3f0d4560 2122 fhdr = (struct flash_file_hdr_g2 *) p;
84517482
AK		 2123 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
2124
84517482
AK		 2125 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2126 flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
2127 &flash_cmd.dma);
2128 if (!flash_cmd.va) {
2129 status = -ENOMEM;
2130 dev_err(&adapter->pdev->dev,
2131 "Memory allocation failure while flashing\n");
2132 goto fw_exit;
2133 }
2134
3f0d4560
AK		 2135 if ((adapter->generation == BE_GEN3) &&
2136 (get_ufigen_type(fhdr) == BE_GEN3)) {
2137 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
8b93b710
AK		 2138 num_imgs = le32_to_cpu(fhdr3->num_imgs);
2139 for (i = 0; i < num_imgs; i++) {
3f0d4560
AK		 2140 img_hdr_ptr = (struct image_hdr *) (fw->data +
2141 (sizeof(struct flash_file_hdr_g3) +
8b93b710
AK		 2142 i * sizeof(struct image_hdr)));
2143 if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
2144 status = be_flash_data(adapter, fw, &flash_cmd,
2145 num_imgs);
3f0d4560
AK		 2146 }
2147 } else if ((adapter->generation == BE_GEN2) &&
2148 (get_ufigen_type(fhdr) == BE_GEN2)) {
2149 status = be_flash_data(adapter, fw, &flash_cmd, 0);
2150 } else {
2151 dev_err(&adapter->pdev->dev,
2152 "UFI and Interface are not compatible for flashing\n");
2153 status = -1;
84517482
AK		 2154 }
2155
2156 pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
2157 flash_cmd.dma);
2158 if (status) {
2159 dev_err(&adapter->pdev->dev, "Firmware load error\n");
2160 goto fw_exit;
2161 }
2162
af901ca1 2163 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
84517482
AK		 2164
2165fw_exit:
2166 release_firmware(fw);
2167 return status;
2168}
2169
6b7c5b94
SP		 2170static struct net_device_ops be_netdev_ops = {
2171 .ndo_open = be_open,
2172 .ndo_stop = be_close,
2173 .ndo_start_xmit = be_xmit,
2174 .ndo_get_stats = be_get_stats,
2175 .ndo_set_rx_mode = be_set_multicast_list,
2176 .ndo_set_mac_address = be_mac_addr_set,
2177 .ndo_change_mtu = be_change_mtu,
2178 .ndo_validate_addr = eth_validate_addr,
2179 .ndo_vlan_rx_register = be_vlan_register,
2180 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
2181 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
ba343c77 2182 .ndo_set_vf_mac = be_set_vf_mac
6b7c5b94
SP		 2183};
2184
2185static void be_netdev_init(struct net_device *netdev)
2186{
2187 struct be_adapter *adapter = netdev_priv(netdev);
2188
2189 netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
583e3f34 2190 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
49e4b847 2191 NETIF_F_GRO | NETIF_F_TSO6;
6b7c5b94 2192
51c59870
AK		 2193 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
2194
6b7c5b94
SP		 2195 netdev->flags |= IFF_MULTICAST;
2196
728a9972
AK		 2197 adapter->rx_csum = true;
2198
9e90c961
AK		 2199 /* Default settings for Rx and Tx flow control */
2200 adapter->rx_fc = true;
2201 adapter->tx_fc = true;
2202
c190e3c8
AK		 2203 netif_set_gso_max_size(netdev, 65535);
2204
6b7c5b94
SP		 2205 BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
2206
2207 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
2208
6b7c5b94
SP		 2209 netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
2210 BE_NAPI_WEIGHT);
5fb379ee 2211 netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
6b7c5b94
SP		 2212 BE_NAPI_WEIGHT);
2213
2214 netif_carrier_off(netdev);
2215 netif_stop_queue(netdev);
2216}
2217
2218static void be_unmap_pci_bars(struct be_adapter *adapter)
2219{
8788fdc2
SP		 2220 if (adapter->csr)
2221 iounmap(adapter->csr);
2222 if (adapter->db)
2223 iounmap(adapter->db);
ba343c77 2224 if (adapter->pcicfg && be_physfn(adapter))
8788fdc2 2225 iounmap(adapter->pcicfg);
6b7c5b94
SP		 2226}
2227
2228static int be_map_pci_bars(struct be_adapter *adapter)
2229{
2230 u8 __iomem *addr;
ba343c77 2231 int pcicfg_reg, db_reg;
6b7c5b94 2232
ba343c77
SB		 2233 if (be_physfn(adapter)) {
2234 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
2235 pci_resource_len(adapter->pdev, 2));
2236 if (addr == NULL)
2237 return -ENOMEM;
2238 adapter->csr = addr;
2239 }
6b7c5b94 2240
ba343c77 2241 if (adapter->generation == BE_GEN2) {
7b139c83 2242 pcicfg_reg = 1;
ba343c77
SB		 2243 db_reg = 4;
2244 } else {
7b139c83 2245 pcicfg_reg = 0;
ba343c77
SB		 2246 if (be_physfn(adapter))
2247 db_reg = 4;
2248 else
2249 db_reg = 0;
2250 }
2251 addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
2252 pci_resource_len(adapter->pdev, db_reg));
6b7c5b94
SP		 2253 if (addr == NULL)
2254 goto pci_map_err;
ba343c77
SB		 2255 adapter->db = addr;
2256
2257 if (be_physfn(adapter)) {
2258 addr = ioremap_nocache(
2259 pci_resource_start(adapter->pdev, pcicfg_reg),
2260 pci_resource_len(adapter->pdev, pcicfg_reg));
2261 if (addr == NULL)
2262 goto pci_map_err;
2263 adapter->pcicfg = addr;
2264 } else
2265 adapter->pcicfg = adapter->db + SRIOV_VF_PCICFG_OFFSET;
6b7c5b94
SP		 2266
2267 return 0;
2268pci_map_err:
2269 be_unmap_pci_bars(adapter);
2270 return -ENOMEM;
2271}
2272
2273
2274static void be_ctrl_cleanup(struct be_adapter *adapter)
2275{
8788fdc2 2276 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
6b7c5b94
SP		 2277
2278 be_unmap_pci_bars(adapter);
2279
2280 if (mem->va)
2281 pci_free_consistent(adapter->pdev, mem->size,
2282 mem->va, mem->dma);
e7b909a6
SP		 2283
2284 mem = &adapter->mc_cmd_mem;
2285 if (mem->va)
2286 pci_free_consistent(adapter->pdev, mem->size,
2287 mem->va, mem->dma);
6b7c5b94
SP		 2288}
2289
6b7c5b94
SP		 2290static int be_ctrl_init(struct be_adapter *adapter)
2291{
8788fdc2
SP		 2292 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
2293 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
e7b909a6 2294 struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
6b7c5b94 2295 int status;
6b7c5b94
SP		 2296
2297 status = be_map_pci_bars(adapter);
2298 if (status)
e7b909a6 2299 goto done;
6b7c5b94
SP		 2300
2301 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2302 mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
2303 mbox_mem_alloc->size, &mbox_mem_alloc->dma);
2304 if (!mbox_mem_alloc->va) {
e7b909a6
SP		 2305 status = -ENOMEM;
2306 goto unmap_pci_bars;
6b7c5b94 2307 }
e7b909a6 2308
6b7c5b94
SP		 2309 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
2310 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
2311 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
2312 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
e7b909a6
SP		 2313
2314 mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
2315 mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
2316 &mc_cmd_mem->dma);
2317 if (mc_cmd_mem->va == NULL) {
2318 status = -ENOMEM;
2319 goto free_mbox;
2320 }
2321 memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
2322
8788fdc2
SP		 2323 spin_lock_init(&adapter->mbox_lock);
2324 spin_lock_init(&adapter->mcc_lock);
2325 spin_lock_init(&adapter->mcc_cq_lock);
a8f447bd 2326
dd131e76 2327 init_completion(&adapter->flash_compl);
cf588477 2328 pci_save_state(adapter->pdev);
6b7c5b94 2329 return 0;
e7b909a6
SP		 2330
2331free_mbox:
2332 pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
2333 mbox_mem_alloc->va, mbox_mem_alloc->dma);
2334
2335unmap_pci_bars:
2336 be_unmap_pci_bars(adapter);
2337
2338done:
2339 return status;
6b7c5b94
SP		 2340}
2341
2342static void be_stats_cleanup(struct be_adapter *adapter)
2343{
2344 struct be_stats_obj *stats = &adapter->stats;
2345 struct be_dma_mem *cmd = &stats->cmd;
2346
2347 if (cmd->va)
2348 pci_free_consistent(adapter->pdev, cmd->size,
2349 cmd->va, cmd->dma);
2350}
2351
2352static int be_stats_init(struct be_adapter *adapter)
2353{
2354 struct be_stats_obj *stats = &adapter->stats;
2355 struct be_dma_mem *cmd = &stats->cmd;
2356
2357 cmd->size = sizeof(struct be_cmd_req_get_stats);
2358 cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
2359 if (cmd->va == NULL)
2360 return -1;
d291b9af 2361 memset(cmd->va, 0, cmd->size);
6b7c5b94
SP		 2362 return 0;
2363}
2364
2365static void __devexit be_remove(struct pci_dev *pdev)
2366{
2367 struct be_adapter *adapter = pci_get_drvdata(pdev);
8d56ff11 2368
6b7c5b94
SP		 2369 if (!adapter)
2370 return;
2371
2372 unregister_netdev(adapter->netdev);
2373
5fb379ee
SP		 2374 be_clear(adapter);
2375
6b7c5b94
SP		 2376 be_stats_cleanup(adapter);
2377
2378 be_ctrl_cleanup(adapter);
2379
ba343c77
SB		 2380 be_sriov_disable(adapter);
2381
8d56ff11 2382 be_msix_disable(adapter);
6b7c5b94
SP		 2383
2384 pci_set_drvdata(pdev, NULL);
2385 pci_release_regions(pdev);
2386 pci_disable_device(pdev);
2387
2388 free_netdev(adapter->netdev);
2389}
2390
2243e2e9 2391static int be_get_config(struct be_adapter *adapter)
6b7c5b94 2392{
6b7c5b94 2393 int status;
2243e2e9 2394 u8 mac[ETH_ALEN];
6b7c5b94 2395
2243e2e9 2396 status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
6b7c5b94
SP		 2397 if (status)
2398 return status;
2399
2243e2e9
SP		 2400 status = be_cmd_query_fw_cfg(adapter,
2401 &adapter->port_num, &adapter->cap);
43a04fdc
SP		 2402 if (status)
2403 return status;
2404
2243e2e9 2405 memset(mac, 0, ETH_ALEN);
ba343c77
SB		 2406
2407 if (be_physfn(adapter)) {
2408 status = be_cmd_mac_addr_query(adapter, mac,
2243e2e9 2409 MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
ca9e4988 2410
ba343c77
SB		 2411 if (status)
2412 return status;
ca9e4988 2413
ba343c77
SB		 2414 if (!is_valid_ether_addr(mac))
2415 return -EADDRNOTAVAIL;
2416
2417 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2418 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2419 }
6b7c5b94 2420
82903e4b
AK		 2421 if (adapter->cap & 0x400)
2422 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
2423 else
2424 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
2425
2243e2e9 2426 return 0;
6b7c5b94
SP		 2427}
2428
2429static int __devinit be_probe(struct pci_dev *pdev,
2430 const struct pci_device_id *pdev_id)
2431{
2432 int status = 0;
2433 struct be_adapter *adapter;
2434 struct net_device *netdev;
6b7c5b94 2435
ba343c77 2436
6b7c5b94
SP		 2437 status = pci_enable_device(pdev);
2438 if (status)
2439 goto do_none;
2440
2441 status = pci_request_regions(pdev, DRV_NAME);
2442 if (status)
2443 goto disable_dev;
2444 pci_set_master(pdev);
2445
2446 netdev = alloc_etherdev(sizeof(struct be_adapter));
2447 if (netdev == NULL) {
2448 status = -ENOMEM;
2449 goto rel_reg;
2450 }
2451 adapter = netdev_priv(netdev);
7b139c83
AK		 2452
2453 switch (pdev->device) {
2454 case BE_DEVICE_ID1:
2455 case OC_DEVICE_ID1:
2456 adapter->generation = BE_GEN2;
2457 break;
2458 case BE_DEVICE_ID2:
2459 case OC_DEVICE_ID2:
2460 adapter->generation = BE_GEN3;
2461 break;
2462 default:
2463 adapter->generation = 0;
2464 }
2465
6b7c5b94
SP		 2466 adapter->pdev = pdev;
2467 pci_set_drvdata(pdev, adapter);
2468 adapter->netdev = netdev;
2243e2e9
SP		 2469 be_netdev_init(netdev);
2470 SET_NETDEV_DEV(netdev, &pdev->dev);
6b7c5b94
SP		 2471
2472 be_msix_enable(adapter);
2473
e930438c 2474 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6b7c5b94
SP		 2475 if (!status) {
2476 netdev->features |= NETIF_F_HIGHDMA;
2477 } else {
e930438c 2478 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6b7c5b94
SP		 2479 if (status) {
2480 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
2481 goto free_netdev;
2482 }
2483 }
2484
ba343c77
SB		 2485 be_sriov_enable(adapter);
2486
6b7c5b94
SP		 2487 status = be_ctrl_init(adapter);
2488 if (status)
2489 goto free_netdev;
2490
2243e2e9 2491 /* sync up with fw's ready state */
ba343c77
SB		 2492 if (be_physfn(adapter)) {
2493 status = be_cmd_POST(adapter);
2494 if (status)
2495 goto ctrl_clean;
ba343c77 2496 }
6b7c5b94 2497
2243e2e9
SP		 2498 /* tell fw we're ready to fire cmds */
2499 status = be_cmd_fw_init(adapter);
6b7c5b94 2500 if (status)
2243e2e9
SP		 2501 goto ctrl_clean;
2502
556ae191
SB		 2503 if (be_physfn(adapter)) {
2504 status = be_cmd_reset_function(adapter);
2505 if (status)
2506 goto ctrl_clean;
2507 }
2508
2243e2e9
SP		 2509 status = be_stats_init(adapter);
2510 if (status)
2511 goto ctrl_clean;
2512
2513 status = be_get_config(adapter);
6b7c5b94
SP		 2514 if (status)
2515 goto stats_clean;
6b7c5b94
SP		 2516
2517 INIT_DELAYED_WORK(&adapter->work, be_worker);
6b7c5b94 2518
5fb379ee
SP		 2519 status = be_setup(adapter);
2520 if (status)
2521 goto stats_clean;
2243e2e9 2522
6b7c5b94
SP		 2523 status = register_netdev(netdev);
2524 if (status != 0)
5fb379ee 2525 goto unsetup;
6b7c5b94 2526
c4ca2374 2527 dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
6b7c5b94
SP		 2528 return 0;
2529
5fb379ee
SP		 2530unsetup:
2531 be_clear(adapter);
6b7c5b94
SP		 2532stats_clean:
2533 be_stats_cleanup(adapter);
2534ctrl_clean:
2535 be_ctrl_cleanup(adapter);
2536free_netdev:
8d56ff11 2537 be_msix_disable(adapter);
ba343c77 2538 be_sriov_disable(adapter);
6b7c5b94 2539 free_netdev(adapter->netdev);
8d56ff11 2540 pci_set_drvdata(pdev, NULL);
6b7c5b94
SP		 2541rel_reg:
2542 pci_release_regions(pdev);
2543disable_dev:
2544 pci_disable_device(pdev);
2545do_none:
c4ca2374 2546 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
6b7c5b94
SP		 2547 return status;
2548}
2549
2550static int be_suspend(struct pci_dev *pdev, pm_message_t state)
2551{
2552 struct be_adapter *adapter = pci_get_drvdata(pdev);
2553 struct net_device *netdev = adapter->netdev;
2554
71d8d1b5
AK		 2555 if (adapter->wol)
2556 be_setup_wol(adapter, true);
2557
6b7c5b94
SP		 2558 netif_device_detach(netdev);
2559 if (netif_running(netdev)) {
2560 rtnl_lock();
2561 be_close(netdev);
2562 rtnl_unlock();
2563 }
9e90c961 2564 be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
9b0365f1 2565 be_clear(adapter);
6b7c5b94
SP		 2566
2567 pci_save_state(pdev);
2568 pci_disable_device(pdev);
2569 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2570 return 0;
2571}
2572
2573static int be_resume(struct pci_dev *pdev)
2574{
2575 int status = 0;
2576 struct be_adapter *adapter = pci_get_drvdata(pdev);
2577 struct net_device *netdev = adapter->netdev;
2578
2579 netif_device_detach(netdev);
2580
2581 status = pci_enable_device(pdev);
2582 if (status)
2583 return status;
2584
2585 pci_set_power_state(pdev, 0);
2586 pci_restore_state(pdev);
2587
2243e2e9
SP		 2588 /* tell fw we're ready to fire cmds */
2589 status = be_cmd_fw_init(adapter);
2590 if (status)
2591 return status;
2592
9b0365f1 2593 be_setup(adapter);
6b7c5b94
SP		 2594 if (netif_running(netdev)) {
2595 rtnl_lock();
2596 be_open(netdev);
2597 rtnl_unlock();
2598 }
2599 netif_device_attach(netdev);
71d8d1b5
AK		 2600
2601 if (adapter->wol)
2602 be_setup_wol(adapter, false);
6b7c5b94
SP		 2603 return 0;
2604}
2605
82456b03
SP		 2606/*
2607 * An FLR will stop BE from DMAing any data.
2608 */
2609static void be_shutdown(struct pci_dev *pdev)
2610{
2611 struct be_adapter *adapter = pci_get_drvdata(pdev);
2612 struct net_device *netdev = adapter->netdev;
2613
2614 netif_device_detach(netdev);
2615
2616 be_cmd_reset_function(adapter);
2617
2618 if (adapter->wol)
2619 be_setup_wol(adapter, true);
2620
2621 pci_disable_device(pdev);
82456b03
SP		 2622}
2623
cf588477
SP		 2624static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
2625 pci_channel_state_t state)
2626{
2627 struct be_adapter *adapter = pci_get_drvdata(pdev);
2628 struct net_device *netdev = adapter->netdev;
2629
2630 dev_err(&adapter->pdev->dev, "EEH error detected\n");
2631
2632 adapter->eeh_err = true;
2633
2634 netif_device_detach(netdev);
2635
2636 if (netif_running(netdev)) {
2637 rtnl_lock();
2638 be_close(netdev);
2639 rtnl_unlock();
2640 }
2641 be_clear(adapter);
2642
2643 if (state == pci_channel_io_perm_failure)
2644 return PCI_ERS_RESULT_DISCONNECT;
2645
2646 pci_disable_device(pdev);
2647
2648 return PCI_ERS_RESULT_NEED_RESET;
2649}
2650
2651static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
2652{
2653 struct be_adapter *adapter = pci_get_drvdata(pdev);
2654 int status;
2655
2656 dev_info(&adapter->pdev->dev, "EEH reset\n");
2657 adapter->eeh_err = false;
2658
2659 status = pci_enable_device(pdev);
2660 if (status)
2661 return PCI_ERS_RESULT_DISCONNECT;
2662
2663 pci_set_master(pdev);
2664 pci_set_power_state(pdev, 0);
2665 pci_restore_state(pdev);
2666
2667 /* Check if card is ok and fw is ready */
2668 status = be_cmd_POST(adapter);
2669 if (status)
2670 return PCI_ERS_RESULT_DISCONNECT;
2671
2672 return PCI_ERS_RESULT_RECOVERED;
2673}
2674
2675static void be_eeh_resume(struct pci_dev *pdev)
2676{
2677 int status = 0;
2678 struct be_adapter *adapter = pci_get_drvdata(pdev);
2679 struct net_device *netdev = adapter->netdev;
2680
2681 dev_info(&adapter->pdev->dev, "EEH resume\n");
2682
2683 pci_save_state(pdev);
2684
2685 /* tell fw we're ready to fire cmds */
2686 status = be_cmd_fw_init(adapter);
2687 if (status)
2688 goto err;
2689
2690 status = be_setup(adapter);
2691 if (status)
2692 goto err;
2693
2694 if (netif_running(netdev)) {
2695 status = be_open(netdev);
2696 if (status)
2697 goto err;
2698 }
2699 netif_device_attach(netdev);
2700 return;
2701err:
2702 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
cf588477
SP		 2703}
2704
2705static struct pci_error_handlers be_eeh_handlers = {
2706 .error_detected = be_eeh_err_detected,
2707 .slot_reset = be_eeh_reset,
2708 .resume = be_eeh_resume,
2709};
2710
6b7c5b94
SP		 2711static struct pci_driver be_driver = {
2712 .name = DRV_NAME,
2713 .id_table = be_dev_ids,
2714 .probe = be_probe,
2715 .remove = be_remove,
2716 .suspend = be_suspend,
cf588477 2717 .resume = be_resume,
82456b03 2718 .shutdown = be_shutdown,
cf588477 2719 .err_handler = &be_eeh_handlers
6b7c5b94
SP		 2720};
2721
2722static int __init be_init_module(void)
2723{
8e95a202
JP		 2724 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
2725 rx_frag_size != 2048) {
6b7c5b94
SP		 2726 printk(KERN_WARNING DRV_NAME
2727 " : Module param rx_frag_size must be 2048/4096/8192."
2728 " Using 2048\n");
2729 rx_frag_size = 2048;
2730 }
6b7c5b94 2731
ba343c77
SB		 2732 if (num_vfs > 32) {
2733 printk(KERN_WARNING DRV_NAME
2734 " : Module param num_vfs must not be greater than 32."
2735 "Using 32\n");
2736 num_vfs = 32;
2737 }
2738
6b7c5b94
SP		 2739 return pci_register_driver(&be_driver);
2740}
2741module_init(be_init_module);
2742
2743static void __exit be_exit_module(void)
2744{
2745 pci_unregister_driver(&be_driver);
2746}
2747module_exit(be_exit_module);
Linux 6.x block layer and io_uring tree(s)