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firmware: convert acenic driver to request_firmware()
[linux-2.6-block.git] / drivers / net / acenic.c
CommitLineData
1da177e4
LT		 1/*
2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
3 * and other Tigon based cards.
4 *
5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
6 *
7 * Thanks to Alteon and 3Com for providing hardware and documentation
8 * enabling me to write this driver.
9 *
10 * A mailing list for discussing the use of this driver has been
11 * setup, please subscribe to the lists if you have any questions
12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
13 * see how to subscribe.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * Additional credits:
21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
22 * dump support. The trace dump support has not been
23 * integrated yet however.
24 * Troy Benjegerdes: Big Endian (PPC) patches.
25 * Nate Stahl: Better out of memory handling and stats support.
26 * Aman Singla: Nasty race between interrupt handler and tx code dealing
27 * with 'testing the tx_ret_csm and setting tx_full'
28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
29 * infrastructure and Sparc support
30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
31 * driver under Linux/Sparc64
32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
33 * ETHTOOL_GDRVINFO support
34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
35 * handler and close() cleanup.
36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
37 * memory mapped IO is enabled to
38 * make the driver work on RS/6000.
39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
40 * where the driver would disable
41 * bus master mode if it had to disable
42 * write and invalidate.
43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
44 * endian systems.
45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
46 * rx producer index when
47 * flushing the Jumbo ring.
48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
49 * driver init path.
50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
51 */
52
1da177e4
LT		 53#include <linux/module.h>
54#include <linux/moduleparam.h>
1da177e4
LT		 55#include <linux/types.h>
56#include <linux/errno.h>
57#include <linux/ioport.h>
58#include <linux/pci.h>
1e7f0bd8 59#include <linux/dma-mapping.h>
1da177e4
LT		 60#include <linux/kernel.h>
61#include <linux/netdevice.h>
62#include <linux/etherdevice.h>
63#include <linux/skbuff.h>
64#include <linux/init.h>
65#include <linux/delay.h>
66#include <linux/mm.h>
67#include <linux/highmem.h>
68#include <linux/sockios.h>
949b4254 69#include <linux/firmware.h>
1da177e4
LT		 70
71#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
72#include <linux/if_vlan.h>
73#endif
74
75#ifdef SIOCETHTOOL
76#include <linux/ethtool.h>
77#endif
78
79#include <net/sock.h>
80#include <net/ip.h>
81
82#include <asm/system.h>
83#include <asm/io.h>
84#include <asm/irq.h>
85#include <asm/byteorder.h>
86#include <asm/uaccess.h>
87
88
89#define DRV_NAME "acenic"
90
91#undef INDEX_DEBUG
92
93#ifdef CONFIG_ACENIC_OMIT_TIGON_I
94#define ACE_IS_TIGON_I(ap) 0
95#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
96#else
97#define ACE_IS_TIGON_I(ap) (ap->version == 1)
98#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
99#endif
100
101#ifndef PCI_VENDOR_ID_ALTEON
6aa20a22 102#define PCI_VENDOR_ID_ALTEON 0x12ae
1da177e4
LT		 103#endif
104#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
105#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
106#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
107#endif
108#ifndef PCI_DEVICE_ID_3COM_3C985
109#define PCI_DEVICE_ID_3COM_3C985 0x0001
110#endif
111#ifndef PCI_VENDOR_ID_NETGEAR
112#define PCI_VENDOR_ID_NETGEAR 0x1385
113#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
114#endif
115#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
116#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
117#endif
118
119
120/*
121 * Farallon used the DEC vendor ID by mistake and they seem not
122 * to care - stinky!
123 */
124#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
125#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
126#endif
127#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
128#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
129#endif
130#ifndef PCI_VENDOR_ID_SGI
131#define PCI_VENDOR_ID_SGI 0x10a9
132#endif
133#ifndef PCI_DEVICE_ID_SGI_ACENIC
134#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
135#endif
136
137static struct pci_device_id acenic_pci_tbl[] = {
138 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
139 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
140 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
141 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
142 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
143 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
144 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
145 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
146 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
147 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
148 /*
149 * Farallon used the DEC vendor ID on their cards incorrectly,
150 * then later Alteon's ID.
151 */
152 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
153 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
154 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
155 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
156 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
157 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
158 { }
159};
160MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
161
1da177e4 162#define ace_sync_irq(irq) synchronize_irq(irq)
1da177e4
LT		 163
164#ifndef offset_in_page
165#define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
166#endif
167
168#define ACE_MAX_MOD_PARMS 8
169#define BOARD_IDX_STATIC 0
170#define BOARD_IDX_OVERFLOW -1
171
172#if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
173 defined(NETIF_F_HW_VLAN_RX)
174#define ACENIC_DO_VLAN 1
175#define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
176#else
177#define ACENIC_DO_VLAN 0
178#define ACE_RCB_VLAN_FLAG 0
179#endif
180
181#include "acenic.h"
182
183/*
184 * These must be defined before the firmware is included.
185 */
186#define MAX_TEXT_LEN 96*1024
187#define MAX_RODATA_LEN 8*1024
188#define MAX_DATA_LEN 2*1024
189
1da177e4
LT		 190#ifndef tigon2FwReleaseLocal
191#define tigon2FwReleaseLocal 0
192#endif
193
194/*
195 * This driver currently supports Tigon I and Tigon II based cards
196 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
197 * GA620. The driver should also work on the SGI, DEC and Farallon
198 * versions of the card, however I have not been able to test that
199 * myself.
200 *
201 * This card is really neat, it supports receive hardware checksumming
202 * and jumbo frames (up to 9000 bytes) and does a lot of work in the
203 * firmware. Also the programming interface is quite neat, except for
204 * the parts dealing with the i2c eeprom on the card ;-)
205 *
206 * Using jumbo frames:
207 *
208 * To enable jumbo frames, simply specify an mtu between 1500 and 9000
209 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
210 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
211 * interface number and <MTU> being the MTU value.
212 *
213 * Module parameters:
214 *
215 * When compiled as a loadable module, the driver allows for a number
216 * of module parameters to be specified. The driver supports the
217 * following module parameters:
218 *
219 * trace=<val> - Firmware trace level. This requires special traced
220 * firmware to replace the firmware supplied with
221 * the driver - for debugging purposes only.
222 *
223 * link=<val> - Link state. Normally you want to use the default link
224 * parameters set by the driver. This can be used to
225 * override these in case your switch doesn't negotiate
226 * the link properly. Valid values are:
227 * 0x0001 - Force half duplex link.
228 * 0x0002 - Do not negotiate line speed with the other end.
229 * 0x0010 - 10Mbit/sec link.
230 * 0x0020 - 100Mbit/sec link.
231 * 0x0040 - 1000Mbit/sec link.
232 * 0x0100 - Do not negotiate flow control.
233 * 0x0200 - Enable RX flow control Y
234 * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
235 * Default value is 0x0270, ie. enable link+flow
236 * control negotiation. Negotiating the highest
237 * possible link speed with RX flow control enabled.
238 *
239 * When disabling link speed negotiation, only one link
240 * speed is allowed to be specified!
241 *
242 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
243 * to wait for more packets to arive before
244 * interrupting the host, from the time the first
245 * packet arrives.
246 *
247 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
248 * to wait for more packets to arive in the transmit ring,
249 * before interrupting the host, after transmitting the
250 * first packet in the ring.
251 *
252 * max_tx_desc=<val> - maximum number of transmit descriptors
253 * (packets) transmitted before interrupting the host.
254 *
255 * max_rx_desc=<val> - maximum number of receive descriptors
256 * (packets) received before interrupting the host.
257 *
258 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
259 * increments of the NIC's on board memory to be used for
260 * transmit and receive buffers. For the 1MB NIC app. 800KB
261 * is available, on the 1/2MB NIC app. 300KB is available.
262 * 68KB will always be available as a minimum for both
263 * directions. The default value is a 50/50 split.
264 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
265 * operations, default (1) is to always disable this as
266 * that is what Alteon does on NT. I have not been able
267 * to measure any real performance differences with
268 * this on my systems. Set <val>=0 if you want to
269 * enable these operations.
270 *
271 * If you use more than one NIC, specify the parameters for the
272 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
273 * run tracing on NIC #2 but not on NIC #1 and #3.
274 *
275 * TODO:
276 *
277 * - Proper multicast support.
278 * - NIC dump support.
279 * - More tuning parameters.
280 *
281 * The mini ring is not used under Linux and I am not sure it makes sense
282 * to actually use it.
283 *
284 * New interrupt handler strategy:
285 *
286 * The old interrupt handler worked using the traditional method of
287 * replacing an skbuff with a new one when a packet arrives. However
288 * the rx rings do not need to contain a static number of buffer
289 * descriptors, thus it makes sense to move the memory allocation out
290 * of the main interrupt handler and do it in a bottom half handler
291 * and only allocate new buffers when the number of buffers in the
292 * ring is below a certain threshold. In order to avoid starving the
293 * NIC under heavy load it is however necessary to force allocation
294 * when hitting a minimum threshold. The strategy for alloction is as
295 * follows:
296 *
297 * RX_LOW_BUF_THRES - allocate buffers in the bottom half
298 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
299 * the buffers in the interrupt handler
300 * RX_RING_THRES - maximum number of buffers in the rx ring
301 * RX_MINI_THRES - maximum number of buffers in the mini ring
302 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
303 *
304 * One advantagous side effect of this allocation approach is that the
305 * entire rx processing can be done without holding any spin lock
306 * since the rx rings and registers are totally independent of the tx
307 * ring and its registers. This of course includes the kmalloc's of
308 * new skb's. Thus start_xmit can run in parallel with rx processing
309 * and the memory allocation on SMP systems.
310 *
311 * Note that running the skb reallocation in a bottom half opens up
312 * another can of races which needs to be handled properly. In
313 * particular it can happen that the interrupt handler tries to run
314 * the reallocation while the bottom half is either running on another
315 * CPU or was interrupted on the same CPU. To get around this the
316 * driver uses bitops to prevent the reallocation routines from being
317 * reentered.
318 *
319 * TX handling can also be done without holding any spin lock, wheee
320 * this is fun! since tx_ret_csm is only written to by the interrupt
321 * handler. The case to be aware of is when shutting down the device
322 * and cleaning up where it is necessary to make sure that
323 * start_xmit() is not running while this is happening. Well DaveM
324 * informs me that this case is already protected against ... bye bye
325 * Mr. Spin Lock, it was nice to know you.
326 *
327 * TX interrupts are now partly disabled so the NIC will only generate
328 * TX interrupts for the number of coal ticks, not for the number of
329 * TX packets in the queue. This should reduce the number of TX only,
330 * ie. when no RX processing is done, interrupts seen.
331 */
332
333/*
334 * Threshold values for RX buffer allocation - the low water marks for
335 * when to start refilling the rings are set to 75% of the ring
336 * sizes. It seems to make sense to refill the rings entirely from the
337 * intrrupt handler once it gets below the panic threshold, that way
338 * we don't risk that the refilling is moved to another CPU when the
339 * one running the interrupt handler just got the slab code hot in its
340 * cache.
341 */
342#define RX_RING_SIZE 72
343#define RX_MINI_SIZE 64
344#define RX_JUMBO_SIZE 48
345
346#define RX_PANIC_STD_THRES 16
347#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
348#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
349#define RX_PANIC_MINI_THRES 12
350#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
351#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
352#define RX_PANIC_JUMBO_THRES 6
353#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
354#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
355
356
357/*
358 * Size of the mini ring entries, basically these just should be big
359 * enough to take TCP ACKs
360 */
361#define ACE_MINI_SIZE 100
362
363#define ACE_MINI_BUFSIZE ACE_MINI_SIZE
364#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
365#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
366
367/*
368 * There seems to be a magic difference in the effect between 995 and 996
369 * but little difference between 900 and 995 ... no idea why.
370 *
371 * There is now a default set of tuning parameters which is set, depending
372 * on whether or not the user enables Jumbo frames. It's assumed that if
373 * Jumbo frames are enabled, the user wants optimal tuning for that case.
374 */
375#define DEF_TX_COAL 400 /* 996 */
376#define DEF_TX_MAX_DESC 60 /* was 40 */
377#define DEF_RX_COAL 120 /* 1000 */
378#define DEF_RX_MAX_DESC 25
379#define DEF_TX_RATIO 21 /* 24 */
380
381#define DEF_JUMBO_TX_COAL 20
382#define DEF_JUMBO_TX_MAX_DESC 60
383#define DEF_JUMBO_RX_COAL 30
384#define DEF_JUMBO_RX_MAX_DESC 6
385#define DEF_JUMBO_TX_RATIO 21
386
387#if tigon2FwReleaseLocal < 20001118
388/*
389 * Standard firmware and early modifications duplicate
390 * IRQ load without this flag (coal timer is never reset).
391 * Note that with this flag tx_coal should be less than
392 * time to xmit full tx ring.
393 * 400usec is not so bad for tx ring size of 128.
394 */
395#define TX_COAL_INTS_ONLY 1 /* worth it */
396#else
397/*
398 * With modified firmware, this is not necessary, but still useful.
399 */
400#define TX_COAL_INTS_ONLY 1
401#endif
402
403#define DEF_TRACE 0
404#define DEF_STAT (2 * TICKS_PER_SEC)
405
406
ddfce6bb 407static int link_state[ACE_MAX_MOD_PARMS];
1da177e4
LT		 408static int trace[ACE_MAX_MOD_PARMS];
409static int tx_coal_tick[ACE_MAX_MOD_PARMS];
410static int rx_coal_tick[ACE_MAX_MOD_PARMS];
411static int max_tx_desc[ACE_MAX_MOD_PARMS];
412static int max_rx_desc[ACE_MAX_MOD_PARMS];
413static int tx_ratio[ACE_MAX_MOD_PARMS];
414static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
415
416MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
417MODULE_LICENSE("GPL");
418MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
949b4254
JS		 419#ifndef CONFIG_ACENIC_OMIT_TIGON_I
420MODULE_FIRMWARE("acenic/tg1.bin");
421#endif
422MODULE_FIRMWARE("acenic/tg2.bin");
1da177e4 423
ddfce6bb 424module_param_array_named(link, link_state, int, NULL, 0);
1da177e4
LT		 425module_param_array(trace, int, NULL, 0);
426module_param_array(tx_coal_tick, int, NULL, 0);
427module_param_array(max_tx_desc, int, NULL, 0);
428module_param_array(rx_coal_tick, int, NULL, 0);
429module_param_array(max_rx_desc, int, NULL, 0);
430module_param_array(tx_ratio, int, NULL, 0);
431MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
432MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
433MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
434MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
435MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
436MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
437MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
438
439
6aa20a22 440static char version[] __devinitdata =
1da177e4
LT		 441 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
442 " http://home.cern.ch/~jes/gige/acenic.html\n";
443
444static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
445static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
446static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
447
7282d491 448static const struct ethtool_ops ace_ethtool_ops = {
1da177e4
LT		 449 .get_settings = ace_get_settings,
450 .set_settings = ace_set_settings,
451 .get_drvinfo = ace_get_drvinfo,
452};
453
454static void ace_watchdog(struct net_device *dev);
455
d8b83c57
SH		 456static const struct net_device_ops ace_netdev_ops = {
457 .ndo_open = ace_open,
458 .ndo_stop = ace_close,
459 .ndo_tx_timeout = ace_watchdog,
460 .ndo_get_stats = ace_get_stats,
00829823 461 .ndo_start_xmit = ace_start_xmit,
d8b83c57
SH		 462 .ndo_set_multicast_list = ace_set_multicast_list,
463 .ndo_set_mac_address = ace_set_mac_addr,
464 .ndo_change_mtu = ace_change_mtu,
00829823 465#if ACENIC_DO_VLAN
d8b83c57 466 .ndo_vlan_rx_register = ace_vlan_rx_register,
00829823 467#endif
d8b83c57
SH		 468};
469
1da177e4
LT		 470static int __devinit acenic_probe_one(struct pci_dev *pdev,
471 const struct pci_device_id *id)
472{
473 struct net_device *dev;
474 struct ace_private *ap;
475 static int boards_found;
476
477 dev = alloc_etherdev(sizeof(struct ace_private));
478 if (dev == NULL) {
479 printk(KERN_ERR "acenic: Unable to allocate "
480 "net_device structure!\n");
481 return -ENOMEM;
482 }
483
1da177e4
LT		 484 SET_NETDEV_DEV(dev, &pdev->dev);
485
454d7c9b 486 ap = netdev_priv(dev);
1da177e4
LT		 487 ap->pdev = pdev;
488 ap->name = pci_name(pdev);
489
490 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
491#if ACENIC_DO_VLAN
492 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 493#endif
25805dcf 494
25805dcf 495 dev->watchdog_timeo = 5*HZ;
1da177e4 496
d8b83c57 497 dev->netdev_ops = &ace_netdev_ops;
1da177e4 498 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
1da177e4
LT		 499
500 /* we only display this string ONCE */
501 if (!boards_found)
502 printk(version);
503
504 if (pci_enable_device(pdev))
505 goto fail_free_netdev;
506
507 /*
508 * Enable master mode before we start playing with the
509 * pci_command word since pci_set_master() will modify
510 * it.
511 */
512 pci_set_master(pdev);
513
514 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
515
6aa20a22 516 /* OpenFirmware on Mac's does not set this - DOH.. */
1da177e4
LT		 517 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
518 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
519 "access - was not enabled by BIOS/Firmware\n",
520 ap->name);
521 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
522 pci_write_config_word(ap->pdev, PCI_COMMAND,
523 ap->pci_command);
524 wmb();
525 }
526
527 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
528 if (ap->pci_latency <= 0x40) {
529 ap->pci_latency = 0x40;
530 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
531 }
532
533 /*
534 * Remap the regs into kernel space - this is abuse of
535 * dev->base_addr since it was means for I/O port
536 * addresses but who gives a damn.
537 */
538 dev->base_addr = pci_resource_start(pdev, 0);
539 ap->regs = ioremap(dev->base_addr, 0x4000);
540 if (!ap->regs) {
541 printk(KERN_ERR "%s: Unable to map I/O register, "
542 "AceNIC %i will be disabled.\n",
543 ap->name, boards_found);
544 goto fail_free_netdev;
545 }
546
547 switch(pdev->vendor) {
548 case PCI_VENDOR_ID_ALTEON:
549 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
550 printk(KERN_INFO "%s: Farallon PN9100-T ",
551 ap->name);
552 } else {
553 printk(KERN_INFO "%s: Alteon AceNIC ",
554 ap->name);
555 }
556 break;
557 case PCI_VENDOR_ID_3COM:
558 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
559 break;
560 case PCI_VENDOR_ID_NETGEAR:
561 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
562 break;
563 case PCI_VENDOR_ID_DEC:
564 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
565 printk(KERN_INFO "%s: Farallon PN9000-SX ",
566 ap->name);
567 break;
568 }
569 case PCI_VENDOR_ID_SGI:
570 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
571 break;
572 default:
573 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
574 break;
575 }
576
577 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
c6387a48 578 printk("irq %d\n", pdev->irq);
1da177e4
LT		 579
580#ifdef CONFIG_ACENIC_OMIT_TIGON_I
581 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
582 printk(KERN_ERR "%s: Driver compiled without Tigon I"
583 " support - NIC disabled\n", dev->name);
584 goto fail_uninit;
585 }
586#endif
587
588 if (ace_allocate_descriptors(dev))
589 goto fail_free_netdev;
590
591#ifdef MODULE
592 if (boards_found >= ACE_MAX_MOD_PARMS)
593 ap->board_idx = BOARD_IDX_OVERFLOW;
594 else
595 ap->board_idx = boards_found;
596#else
597 ap->board_idx = BOARD_IDX_STATIC;
598#endif
599
600 if (ace_init(dev))
601 goto fail_free_netdev;
602
603 if (register_netdev(dev)) {
604 printk(KERN_ERR "acenic: device registration failed\n");
605 goto fail_uninit;
606 }
607 ap->name = dev->name;
608
609 if (ap->pci_using_dac)
610 dev->features |= NETIF_F_HIGHDMA;
611
612 pci_set_drvdata(pdev, dev);
613
614 boards_found++;
615 return 0;
616
617 fail_uninit:
618 ace_init_cleanup(dev);
619 fail_free_netdev:
620 free_netdev(dev);
621 return -ENODEV;
622}
623
624static void __devexit acenic_remove_one(struct pci_dev *pdev)
625{
626 struct net_device *dev = pci_get_drvdata(pdev);
627 struct ace_private *ap = netdev_priv(dev);
628 struct ace_regs __iomem *regs = ap->regs;
629 short i;
630
631 unregister_netdev(dev);
632
633 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
634 if (ap->version >= 2)
635 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
6aa20a22 636
1da177e4
LT		 637 /*
638 * This clears any pending interrupts
639 */
640 writel(1, &regs->Mb0Lo);
641 readl(&regs->CpuCtrl); /* flush */
642
643 /*
644 * Make sure no other CPUs are processing interrupts
645 * on the card before the buffers are being released.
646 * Otherwise one might experience some `interesting'
647 * effects.
648 *
649 * Then release the RX buffers - jumbo buffers were
650 * already released in ace_close().
651 */
652 ace_sync_irq(dev->irq);
653
654 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
655 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
656
657 if (skb) {
658 struct ring_info *ringp;
659 dma_addr_t mapping;
660
661 ringp = &ap->skb->rx_std_skbuff[i];
662 mapping = pci_unmap_addr(ringp, mapping);
663 pci_unmap_page(ap->pdev, mapping,
664 ACE_STD_BUFSIZE,
665 PCI_DMA_FROMDEVICE);
666
667 ap->rx_std_ring[i].size = 0;
668 ap->skb->rx_std_skbuff[i].skb = NULL;
669 dev_kfree_skb(skb);
670 }
671 }
672
673 if (ap->version >= 2) {
674 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
675 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
676
677 if (skb) {
678 struct ring_info *ringp;
679 dma_addr_t mapping;
680
681 ringp = &ap->skb->rx_mini_skbuff[i];
682 mapping = pci_unmap_addr(ringp,mapping);
683 pci_unmap_page(ap->pdev, mapping,
684 ACE_MINI_BUFSIZE,
685 PCI_DMA_FROMDEVICE);
686
687 ap->rx_mini_ring[i].size = 0;
688 ap->skb->rx_mini_skbuff[i].skb = NULL;
689 dev_kfree_skb(skb);
690 }
691 }
692 }
693
694 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
695 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
696 if (skb) {
697 struct ring_info *ringp;
698 dma_addr_t mapping;
699
700 ringp = &ap->skb->rx_jumbo_skbuff[i];
701 mapping = pci_unmap_addr(ringp, mapping);
702 pci_unmap_page(ap->pdev, mapping,
703 ACE_JUMBO_BUFSIZE,
704 PCI_DMA_FROMDEVICE);
705
706 ap->rx_jumbo_ring[i].size = 0;
707 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
708 dev_kfree_skb(skb);
709 }
710 }
711
712 ace_init_cleanup(dev);
713 free_netdev(dev);
714}
715
716static struct pci_driver acenic_pci_driver = {
717 .name = "acenic",
718 .id_table = acenic_pci_tbl,
719 .probe = acenic_probe_one,
720 .remove = __devexit_p(acenic_remove_one),
721};
722
723static int __init acenic_init(void)
724{
29917620 725 return pci_register_driver(&acenic_pci_driver);
1da177e4
LT		 726}
727
728static void __exit acenic_exit(void)
729{
730 pci_unregister_driver(&acenic_pci_driver);
731}
732
733module_init(acenic_init);
734module_exit(acenic_exit);
735
736static void ace_free_descriptors(struct net_device *dev)
737{
738 struct ace_private *ap = netdev_priv(dev);
739 int size;
740
741 if (ap->rx_std_ring != NULL) {
742 size = (sizeof(struct rx_desc) *
743 (RX_STD_RING_ENTRIES +
744 RX_JUMBO_RING_ENTRIES +
745 RX_MINI_RING_ENTRIES +
746 RX_RETURN_RING_ENTRIES));
747 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
748 ap->rx_ring_base_dma);
749 ap->rx_std_ring = NULL;
750 ap->rx_jumbo_ring = NULL;
751 ap->rx_mini_ring = NULL;
752 ap->rx_return_ring = NULL;
753 }
754 if (ap->evt_ring != NULL) {
755 size = (sizeof(struct event) * EVT_RING_ENTRIES);
756 pci_free_consistent(ap->pdev, size, ap->evt_ring,
757 ap->evt_ring_dma);
758 ap->evt_ring = NULL;
759 }
760 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
761 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
762 pci_free_consistent(ap->pdev, size, ap->tx_ring,
763 ap->tx_ring_dma);
764 }
765 ap->tx_ring = NULL;
766
767 if (ap->evt_prd != NULL) {
768 pci_free_consistent(ap->pdev, sizeof(u32),
769 (void *)ap->evt_prd, ap->evt_prd_dma);
770 ap->evt_prd = NULL;
771 }
772 if (ap->rx_ret_prd != NULL) {
773 pci_free_consistent(ap->pdev, sizeof(u32),
774 (void *)ap->rx_ret_prd,
775 ap->rx_ret_prd_dma);
776 ap->rx_ret_prd = NULL;
777 }
778 if (ap->tx_csm != NULL) {
779 pci_free_consistent(ap->pdev, sizeof(u32),
780 (void *)ap->tx_csm, ap->tx_csm_dma);
781 ap->tx_csm = NULL;
782 }
783}
784
785
786static int ace_allocate_descriptors(struct net_device *dev)
787{
788 struct ace_private *ap = netdev_priv(dev);
789 int size;
790
791 size = (sizeof(struct rx_desc) *
792 (RX_STD_RING_ENTRIES +
793 RX_JUMBO_RING_ENTRIES +
794 RX_MINI_RING_ENTRIES +
795 RX_RETURN_RING_ENTRIES));
796
797 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
798 &ap->rx_ring_base_dma);
799 if (ap->rx_std_ring == NULL)
800 goto fail;
801
802 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
803 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
804 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
805
806 size = (sizeof(struct event) * EVT_RING_ENTRIES);
807
808 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
809
810 if (ap->evt_ring == NULL)
811 goto fail;
812
813 /*
814 * Only allocate a host TX ring for the Tigon II, the Tigon I
815 * has to use PCI registers for this ;-(
816 */
817 if (!ACE_IS_TIGON_I(ap)) {
818 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
819
820 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
821 &ap->tx_ring_dma);
822
823 if (ap->tx_ring == NULL)
824 goto fail;
825 }
826
827 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
828 &ap->evt_prd_dma);
829 if (ap->evt_prd == NULL)
830 goto fail;
831
832 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
833 &ap->rx_ret_prd_dma);
834 if (ap->rx_ret_prd == NULL)
835 goto fail;
836
837 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
838 &ap->tx_csm_dma);
839 if (ap->tx_csm == NULL)
840 goto fail;
841
842 return 0;
843
844fail:
845 /* Clean up. */
846 ace_init_cleanup(dev);
847 return 1;
848}
849
850
851/*
852 * Generic cleanup handling data allocated during init. Used when the
853 * module is unloaded or if an error occurs during initialization
854 */
855static void ace_init_cleanup(struct net_device *dev)
856{
857 struct ace_private *ap;
858
859 ap = netdev_priv(dev);
860
861 ace_free_descriptors(dev);
862
863 if (ap->info)
864 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
865 ap->info, ap->info_dma);
b4558ea9
JJ		 866 kfree(ap->skb);
867 kfree(ap->trace_buf);
1da177e4
LT		 868
869 if (dev->irq)
870 free_irq(dev->irq, dev);
871
872 iounmap(ap->regs);
873}
874
875
876/*
877 * Commands are considered to be slow.
878 */
879static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
880{
881 u32 idx;
882
883 idx = readl(&regs->CmdPrd);
884
885 writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
886 idx = (idx + 1) % CMD_RING_ENTRIES;
887
888 writel(idx, &regs->CmdPrd);
889}
890
891
892static int __devinit ace_init(struct net_device *dev)
893{
894 struct ace_private *ap;
895 struct ace_regs __iomem *regs;
896 struct ace_info *info = NULL;
897 struct pci_dev *pdev;
898 unsigned long myjif;
899 u64 tmp_ptr;
900 u32 tig_ver, mac1, mac2, tmp, pci_state;
901 int board_idx, ecode = 0;
902 short i;
903 unsigned char cache_size;
904
905 ap = netdev_priv(dev);
906 regs = ap->regs;
907
908 board_idx = ap->board_idx;
909
910 /*
911 * aman@sgi.com - its useful to do a NIC reset here to
912 * address the `Firmware not running' problem subsequent
913 * to any crashes involving the NIC
914 */
915 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
916 readl(&regs->HostCtrl); /* PCI write posting */
917 udelay(5);
918
919 /*
920 * Don't access any other registers before this point!
921 */
922#ifdef __BIG_ENDIAN
923 /*
924 * This will most likely need BYTE_SWAP once we switch
925 * to using __raw_writel()
926 */
927 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
928 &regs->HostCtrl);
929#else
930 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
931 &regs->HostCtrl);
932#endif
933 readl(&regs->HostCtrl); /* PCI write posting */
934
935 /*
936 * Stop the NIC CPU and clear pending interrupts
937 */
938 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
939 readl(&regs->CpuCtrl); /* PCI write posting */
940 writel(0, &regs->Mb0Lo);
941
942 tig_ver = readl(&regs->HostCtrl) >> 28;
943
944 switch(tig_ver){
945#ifndef CONFIG_ACENIC_OMIT_TIGON_I
946 case 4:
947 case 5:
948 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
949b4254
JS		 949 tig_ver, ap->firmware_major, ap->firmware_minor,
950 ap->firmware_fix);
1da177e4
LT		 951 writel(0, &regs->LocalCtrl);
952 ap->version = 1;
953 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
954 break;
955#endif
956 case 6:
957 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
949b4254
JS		 958 tig_ver, ap->firmware_major, ap->firmware_minor,
959 ap->firmware_fix);
1da177e4
LT		 960 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
961 readl(&regs->CpuBCtrl); /* PCI write posting */
962 /*
963 * The SRAM bank size does _not_ indicate the amount
964 * of memory on the card, it controls the _bank_ size!
965 * Ie. a 1MB AceNIC will have two banks of 512KB.
966 */
967 writel(SRAM_BANK_512K, &regs->LocalCtrl);
968 writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
969 ap->version = 2;
970 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
971 break;
972 default:
973 printk(KERN_WARNING " Unsupported Tigon version detected "
974 "(%i)\n", tig_ver);
975 ecode = -ENODEV;
976 goto init_error;
977 }
978
979 /*
980 * ModeStat _must_ be set after the SRAM settings as this change
981 * seems to corrupt the ModeStat and possible other registers.
982 * The SRAM settings survive resets and setting it to the same
983 * value a second time works as well. This is what caused the
984 * `Firmware not running' problem on the Tigon II.
985 */
986#ifdef __BIG_ENDIAN
987 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
988 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
989#else
990 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
991 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
992#endif
993 readl(&regs->ModeStat); /* PCI write posting */
994
995 mac1 = 0;
996 for(i = 0; i < 4; i++) {
ddfce6bb 997 int t;
6f9d4722 998
1da177e4 999 mac1 = mac1 << 8;
ddfce6bb
SH		 1000 t = read_eeprom_byte(dev, 0x8c+i);
1001 if (t < 0) {
1da177e4
LT		 1002 ecode = -EIO;
1003 goto init_error;
1004 } else
ddfce6bb 1005 mac1 |= (t & 0xff);
1da177e4
LT		 1006 }
1007 mac2 = 0;
1008 for(i = 4; i < 8; i++) {
ddfce6bb 1009 int t;
6f9d4722 1010
1da177e4 1011 mac2 = mac2 << 8;
ddfce6bb
SH		 1012 t = read_eeprom_byte(dev, 0x8c+i);
1013 if (t < 0) {
1da177e4
LT		 1014 ecode = -EIO;
1015 goto init_error;
1016 } else
ddfce6bb 1017 mac2 |= (t & 0xff);
1da177e4
LT		 1018 }
1019
1020 writel(mac1, &regs->MacAddrHi);
1021 writel(mac2, &regs->MacAddrLo);
1022
1da177e4
LT		 1023 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1024 dev->dev_addr[1] = mac1 & 0xff;
1025 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1026 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1027 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1028 dev->dev_addr[5] = mac2 & 0xff;
1029
e174961c 1030 printk("MAC: %pM\n", dev->dev_addr);
0795af57 1031
1da177e4
LT		 1032 /*
1033 * Looks like this is necessary to deal with on all architectures,
1034 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1035 * Ie. having two NICs in the machine, one will have the cache
1036 * line set at boot time, the other will not.
1037 */
1038 pdev = ap->pdev;
1039 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1040 cache_size <<= 2;
1041 if (cache_size != SMP_CACHE_BYTES) {
1042 printk(KERN_INFO " PCI cache line size set incorrectly "
1043 "(%i bytes) by BIOS/FW, ", cache_size);
1044 if (cache_size > SMP_CACHE_BYTES)
1045 printk("expecting %i\n", SMP_CACHE_BYTES);
1046 else {
1047 printk("correcting to %i\n", SMP_CACHE_BYTES);
1048 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1049 SMP_CACHE_BYTES >> 2);
1050 }
1051 }
1052
1053 pci_state = readl(&regs->PciState);
1054 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1055 "latency: %i clks\n",
1056 (pci_state & PCI_32BIT) ? 32 : 64,
6aa20a22 1057 (pci_state & PCI_66MHZ) ? 66 : 33,
1da177e4
LT		 1058 ap->pci_latency);
1059
1060 /*
1061 * Set the max DMA transfer size. Seems that for most systems
1062 * the performance is better when no MAX parameter is
1063 * set. However for systems enabling PCI write and invalidate,
1064 * DMA writes must be set to the L1 cache line size to get
1065 * optimal performance.
1066 *
1067 * The default is now to turn the PCI write and invalidate off
1068 * - that is what Alteon does for NT.
1069 */
1070 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1071 if (ap->version >= 2) {
1072 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1073 /*
1074 * Tuning parameters only supported for 8 cards
1075 */
1076 if (board_idx == BOARD_IDX_OVERFLOW ||
1077 dis_pci_mem_inval[board_idx]) {
1078 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1079 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1080 pci_write_config_word(pdev, PCI_COMMAND,
1081 ap->pci_command);
1082 printk(KERN_INFO " Disabling PCI memory "
1083 "write and invalidate\n");
1084 }
1085 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1086 printk(KERN_INFO " PCI memory write & invalidate "
1087 "enabled by BIOS, enabling counter measures\n");
1088
1089 switch(SMP_CACHE_BYTES) {
1090 case 16:
1091 tmp |= DMA_WRITE_MAX_16;
1092 break;
1093 case 32:
1094 tmp |= DMA_WRITE_MAX_32;
1095 break;
1096 case 64:
1097 tmp |= DMA_WRITE_MAX_64;
1098 break;
1099 case 128:
1100 tmp |= DMA_WRITE_MAX_128;
1101 break;
1102 default:
1103 printk(KERN_INFO " Cache line size %i not "
1104 "supported, PCI write and invalidate "
1105 "disabled\n", SMP_CACHE_BYTES);
1106 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1107 pci_write_config_word(pdev, PCI_COMMAND,
1108 ap->pci_command);
1109 }
1110 }
1111 }
1112
1113#ifdef __sparc__
1114 /*
1115 * On this platform, we know what the best dma settings
1116 * are. We use 64-byte maximum bursts, because if we
1117 * burst larger than the cache line size (or even cross
1118 * a 64byte boundary in a single burst) the UltraSparc
1119 * PCI controller will disconnect at 64-byte multiples.
1120 *
1121 * Read-multiple will be properly enabled above, and when
1122 * set will give the PCI controller proper hints about
1123 * prefetching.
1124 */
1125 tmp &= ~DMA_READ_WRITE_MASK;
1126 tmp |= DMA_READ_MAX_64;
1127 tmp |= DMA_WRITE_MAX_64;
1128#endif
1129#ifdef __alpha__
1130 tmp &= ~DMA_READ_WRITE_MASK;
1131 tmp |= DMA_READ_MAX_128;
1132 /*
1133 * All the docs say MUST NOT. Well, I did.
1134 * Nothing terrible happens, if we load wrong size.
1135 * Bit w&i still works better!
1136 */
1137 tmp |= DMA_WRITE_MAX_128;
1138#endif
1139 writel(tmp, &regs->PciState);
1140
1141#if 0
1142 /*
1143 * The Host PCI bus controller driver has to set FBB.
1144 * If all devices on that PCI bus support FBB, then the controller
1145 * can enable FBB support in the Host PCI Bus controller (or on
1146 * the PCI-PCI bridge if that applies).
1147 * -ggg
1148 */
1149 /*
1150 * I have received reports from people having problems when this
1151 * bit is enabled.
1152 */
1153 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1154 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1155 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1156 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1157 }
1158#endif
6aa20a22 1159
1da177e4
LT		 1160 /*
1161 * Configure DMA attributes.
1162 */
1e7f0bd8 1163 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4 1164 ap->pci_using_dac = 1;
1e7f0bd8 1165 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 1166 ap->pci_using_dac = 0;
1167 } else {
1168 ecode = -ENODEV;
1169 goto init_error;
1170 }
1171
1172 /*
1173 * Initialize the generic info block and the command+event rings
1174 * and the control blocks for the transmit and receive rings
1175 * as they need to be setup once and for all.
1176 */
1177 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1178 &ap->info_dma))) {
1179 ecode = -EAGAIN;
1180 goto init_error;
1181 }
1182 ap->info = info;
1183
1184 /*
1185 * Get the memory for the skb rings.
1186 */
1187 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1188 ecode = -EAGAIN;
1189 goto init_error;
1190 }
1191
1fb9df5d 1192 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1da177e4
LT		 1193 DRV_NAME, dev);
1194 if (ecode) {
1195 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1196 DRV_NAME, pdev->irq);
1197 goto init_error;
1198 } else
1199 dev->irq = pdev->irq;
1200
1201#ifdef INDEX_DEBUG
1202 spin_lock_init(&ap->debug_lock);
1203 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1204 ap->last_std_rx = 0;
1205 ap->last_mini_rx = 0;
1206#endif
1207
1208 memset(ap->info, 0, sizeof(struct ace_info));
1209 memset(ap->skb, 0, sizeof(struct ace_skb));
1210
949b4254
JS		 1211 if (ace_load_firmware(dev))
1212 goto init_error;
1213
1da177e4
LT		 1214 ap->fw_running = 0;
1215
1216 tmp_ptr = ap->info_dma;
1217 writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1218 writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1219
1220 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1221
1222 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1223 info->evt_ctrl.flags = 0;
1224
1225 *(ap->evt_prd) = 0;
1226 wmb();
1227 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1228 writel(0, &regs->EvtCsm);
1229
1230 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1231 info->cmd_ctrl.flags = 0;
1232 info->cmd_ctrl.max_len = 0;
1233
1234 for (i = 0; i < CMD_RING_ENTRIES; i++)
1235 writel(0, &regs->CmdRng[i]);
1236
1237 writel(0, &regs->CmdPrd);
1238 writel(0, &regs->CmdCsm);
1239
1240 tmp_ptr = ap->info_dma;
1241 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1242 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1243
1244 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1245 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1246 info->rx_std_ctrl.flags =
1247 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1248
1249 memset(ap->rx_std_ring, 0,
1250 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1251
1252 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1253 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1254
1255 ap->rx_std_skbprd = 0;
1256 atomic_set(&ap->cur_rx_bufs, 0);
1257
1258 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1259 (ap->rx_ring_base_dma +
1260 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1261 info->rx_jumbo_ctrl.max_len = 0;
1262 info->rx_jumbo_ctrl.flags =
1263 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1264
1265 memset(ap->rx_jumbo_ring, 0,
1266 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1267
1268 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1269 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1270
1271 ap->rx_jumbo_skbprd = 0;
1272 atomic_set(&ap->cur_jumbo_bufs, 0);
1273
1274 memset(ap->rx_mini_ring, 0,
1275 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1276
1277 if (ap->version >= 2) {
1278 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1279 (ap->rx_ring_base_dma +
1280 (sizeof(struct rx_desc) *
1281 (RX_STD_RING_ENTRIES +
1282 RX_JUMBO_RING_ENTRIES))));
1283 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
6aa20a22 1284 info->rx_mini_ctrl.flags =
1da177e4
LT		 1285 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
1286
1287 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1288 ap->rx_mini_ring[i].flags =
1289 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1290 } else {
1291 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1292 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1293 info->rx_mini_ctrl.max_len = 0;
1294 }
1295
1296 ap->rx_mini_skbprd = 0;
1297 atomic_set(&ap->cur_mini_bufs, 0);
1298
1299 set_aceaddr(&info->rx_return_ctrl.rngptr,
1300 (ap->rx_ring_base_dma +
1301 (sizeof(struct rx_desc) *
1302 (RX_STD_RING_ENTRIES +
1303 RX_JUMBO_RING_ENTRIES +
1304 RX_MINI_RING_ENTRIES))));
1305 info->rx_return_ctrl.flags = 0;
1306 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1307
1308 memset(ap->rx_return_ring, 0,
1309 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1310
1311 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1312 *(ap->rx_ret_prd) = 0;
1313
1314 writel(TX_RING_BASE, &regs->WinBase);
1315
1316 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 1317 ap->tx_ring = (__force struct tx_desc *) regs->Window;
6aa20a22 1318 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1da177e4 1319 * sizeof(struct tx_desc)) / sizeof(u32); i++)
ddfce6bb 1320 writel(0, (__force void __iomem *)ap->tx_ring + i * 4);
1da177e4
LT		 1321
1322 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1323 } else {
1324 memset(ap->tx_ring, 0,
1325 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1326
1327 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1328 }
1329
1330 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1331 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1332
1333 /*
1334 * The Tigon I does not like having the TX ring in host memory ;-(
1335 */
1336 if (!ACE_IS_TIGON_I(ap))
1337 tmp |= RCB_FLG_TX_HOST_RING;
1338#if TX_COAL_INTS_ONLY
1339 tmp |= RCB_FLG_COAL_INT_ONLY;
1340#endif
1341 info->tx_ctrl.flags = tmp;
1342
1343 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1344
1345 /*
1346 * Potential item for tuning parameter
1347 */
1348#if 0 /* NO */
1349 writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1350 writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1351#else
1352 writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1353 writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1354#endif
1355
1356 writel(0, &regs->MaskInt);
1357 writel(1, &regs->IfIdx);
1358#if 0
1359 /*
1360 * McKinley boxes do not like us fiddling with AssistState
1361 * this early
1362 */
1363 writel(1, &regs->AssistState);
1364#endif
1365
1366 writel(DEF_STAT, &regs->TuneStatTicks);
1367 writel(DEF_TRACE, &regs->TuneTrace);
1368
1369 ace_set_rxtx_parms(dev, 0);
1370
1371 if (board_idx == BOARD_IDX_OVERFLOW) {
1372 printk(KERN_WARNING "%s: more than %i NICs detected, "
1373 "ignoring module parameters!\n",
1374 ap->name, ACE_MAX_MOD_PARMS);
1375 } else if (board_idx >= 0) {
1376 if (tx_coal_tick[board_idx])
1377 writel(tx_coal_tick[board_idx],
1378 &regs->TuneTxCoalTicks);
1379 if (max_tx_desc[board_idx])
1380 writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1381
1382 if (rx_coal_tick[board_idx])
1383 writel(rx_coal_tick[board_idx],
1384 &regs->TuneRxCoalTicks);
1385 if (max_rx_desc[board_idx])
1386 writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1387
1388 if (trace[board_idx])
1389 writel(trace[board_idx], &regs->TuneTrace);
1390
1391 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1392 writel(tx_ratio[board_idx], &regs->TxBufRat);
1393 }
1394
1395 /*
1396 * Default link parameters
1397 */
1398 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1399 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1400 if(ap->version >= 2)
1401 tmp |= LNK_TX_FLOW_CTL_Y;
1402
1403 /*
1404 * Override link default parameters
1405 */
ddfce6bb
SH		 1406 if ((board_idx >= 0) && link_state[board_idx]) {
1407 int option = link_state[board_idx];
1da177e4
LT		 1408
1409 tmp = LNK_ENABLE;
1410
1411 if (option & 0x01) {
1412 printk(KERN_INFO "%s: Setting half duplex link\n",
1413 ap->name);
1414 tmp &= ~LNK_FULL_DUPLEX;
1415 }
1416 if (option & 0x02)
1417 tmp &= ~LNK_NEGOTIATE;
1418 if (option & 0x10)
1419 tmp |= LNK_10MB;
1420 if (option & 0x20)
1421 tmp |= LNK_100MB;
1422 if (option & 0x40)
1423 tmp |= LNK_1000MB;
1424 if ((option & 0x70) == 0) {
1425 printk(KERN_WARNING "%s: No media speed specified, "
1426 "forcing auto negotiation\n", ap->name);
1427 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1428 LNK_100MB | LNK_10MB;
1429 }
1430 if ((option & 0x100) == 0)
1431 tmp |= LNK_NEG_FCTL;
1432 else
1433 printk(KERN_INFO "%s: Disabling flow control "
1434 "negotiation\n", ap->name);
1435 if (option & 0x200)
1436 tmp |= LNK_RX_FLOW_CTL_Y;
1437 if ((option & 0x400) && (ap->version >= 2)) {
1438 printk(KERN_INFO "%s: Enabling TX flow control\n",
1439 ap->name);
1440 tmp |= LNK_TX_FLOW_CTL_Y;
1441 }
1442 }
1443
1444 ap->link = tmp;
1445 writel(tmp, &regs->TuneLink);
1446 if (ap->version >= 2)
1447 writel(tmp, &regs->TuneFastLink);
1448
949b4254 1449 writel(ap->firmware_start, &regs->Pc);
1da177e4
LT		 1450
1451 writel(0, &regs->Mb0Lo);
1452
1453 /*
1454 * Set tx_csm before we start receiving interrupts, otherwise
1455 * the interrupt handler might think it is supposed to process
1456 * tx ints before we are up and running, which may cause a null
1457 * pointer access in the int handler.
1458 */
1459 ap->cur_rx = 0;
1460 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1461
1462 wmb();
1463 ace_set_txprd(regs, ap, 0);
1464 writel(0, &regs->RxRetCsm);
1465
1da177e4
LT		 1466 /*
1467 * Enable DMA engine now.
1468 * If we do this sooner, Mckinley box pukes.
1469 * I assume it's because Tigon II DMA engine wants to check
1470 * *something* even before the CPU is started.
1471 */
1472 writel(1, &regs->AssistState); /* enable DMA */
1473
1474 /*
1475 * Start the NIC CPU
1476 */
1477 writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1478 readl(&regs->CpuCtrl);
1479
1480 /*
1481 * Wait for the firmware to spin up - max 3 seconds.
1482 */
1483 myjif = jiffies + 3 * HZ;
1484 while (time_before(jiffies, myjif) && !ap->fw_running)
1485 cpu_relax();
1486
1487 if (!ap->fw_running) {
1488 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1489
1490 ace_dump_trace(ap);
1491 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1492 readl(&regs->CpuCtrl);
1493
1494 /* aman@sgi.com - account for badly behaving firmware/NIC:
1495 * - have observed that the NIC may continue to generate
1496 * interrupts for some reason; attempt to stop it - halt
1497 * second CPU for Tigon II cards, and also clear Mb0
1498 * - if we're a module, we'll fail to load if this was
1499 * the only GbE card in the system => if the kernel does
1500 * see an interrupt from the NIC, code to handle it is
1501 * gone and OOps! - so free_irq also
1502 */
1503 if (ap->version >= 2)
1504 writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1505 &regs->CpuBCtrl);
1506 writel(0, &regs->Mb0Lo);
1507 readl(&regs->Mb0Lo);
1508
1509 ecode = -EBUSY;
1510 goto init_error;
1511 }
1512
1513 /*
1514 * We load the ring here as there seem to be no way to tell the
1515 * firmware to wipe the ring without re-initializing it.
1516 */
1517 if (!test_and_set_bit(0, &ap->std_refill_busy))
1518 ace_load_std_rx_ring(ap, RX_RING_SIZE);
1519 else
1520 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1521 ap->name);
1522 if (ap->version >= 2) {
1523 if (!test_and_set_bit(0, &ap->mini_refill_busy))
1524 ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
1525 else
1526 printk(KERN_ERR "%s: Someone is busy refilling "
1527 "the RX mini ring\n", ap->name);
1528 }
1529 return 0;
1530
1531 init_error:
1532 ace_init_cleanup(dev);
1533 return ecode;
1534}
1535
1536
1537static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1538{
1539 struct ace_private *ap = netdev_priv(dev);
1540 struct ace_regs __iomem *regs = ap->regs;
1541 int board_idx = ap->board_idx;
1542
1543 if (board_idx >= 0) {
1544 if (!jumbo) {
1545 if (!tx_coal_tick[board_idx])
1546 writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1547 if (!max_tx_desc[board_idx])
1548 writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1549 if (!rx_coal_tick[board_idx])
1550 writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1551 if (!max_rx_desc[board_idx])
1552 writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1553 if (!tx_ratio[board_idx])
1554 writel(DEF_TX_RATIO, &regs->TxBufRat);
1555 } else {
1556 if (!tx_coal_tick[board_idx])
1557 writel(DEF_JUMBO_TX_COAL,
1558 &regs->TuneTxCoalTicks);
1559 if (!max_tx_desc[board_idx])
1560 writel(DEF_JUMBO_TX_MAX_DESC,
1561 &regs->TuneMaxTxDesc);
1562 if (!rx_coal_tick[board_idx])
1563 writel(DEF_JUMBO_RX_COAL,
1564 &regs->TuneRxCoalTicks);
1565 if (!max_rx_desc[board_idx])
1566 writel(DEF_JUMBO_RX_MAX_DESC,
1567 &regs->TuneMaxRxDesc);
1568 if (!tx_ratio[board_idx])
1569 writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1570 }
1571 }
1572}
1573
1574
1575static void ace_watchdog(struct net_device *data)
1576{
1577 struct net_device *dev = data;
1578 struct ace_private *ap = netdev_priv(dev);
1579 struct ace_regs __iomem *regs = ap->regs;
1580
1581 /*
1582 * We haven't received a stats update event for more than 2.5
1583 * seconds and there is data in the transmit queue, thus we
1584 * asume the card is stuck.
1585 */
1586 if (*ap->tx_csm != ap->tx_ret_csm) {
1587 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1588 dev->name, (unsigned int)readl(&regs->HostCtrl));
1589 /* This can happen due to ieee flow control. */
1590 } else {
1591 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1592 dev->name);
1593#if 0
1594 netif_wake_queue(dev);
1595#endif
1596 }
1597}
1598
1599
1600static void ace_tasklet(unsigned long dev)
1601{
1602 struct ace_private *ap = netdev_priv((struct net_device *)dev);
1603 int cur_size;
1604
1605 cur_size = atomic_read(&ap->cur_rx_bufs);
1606 if ((cur_size < RX_LOW_STD_THRES) &&
1607 !test_and_set_bit(0, &ap->std_refill_busy)) {
1608#ifdef DEBUG
1609 printk("refilling buffers (current %i)\n", cur_size);
1610#endif
1611 ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
1612 }
1613
1614 if (ap->version >= 2) {
1615 cur_size = atomic_read(&ap->cur_mini_bufs);
1616 if ((cur_size < RX_LOW_MINI_THRES) &&
1617 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1618#ifdef DEBUG
1619 printk("refilling mini buffers (current %i)\n",
1620 cur_size);
1621#endif
1622 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
1623 }
1624 }
1625
1626 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1627 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1628 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1629#ifdef DEBUG
1630 printk("refilling jumbo buffers (current %i)\n", cur_size);
1631#endif
1632 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
1633 }
1634 ap->tasklet_pending = 0;
1635}
1636
1637
1638/*
1639 * Copy the contents of the NIC's trace buffer to kernel memory.
1640 */
1641static void ace_dump_trace(struct ace_private *ap)
1642{
1643#if 0
1644 if (!ap->trace_buf)
1645 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1646 return;
1647#endif
1648}
1649
1650
1651/*
1652 * Load the standard rx ring.
1653 *
1654 * Loading rings is safe without holding the spin lock since this is
1655 * done only before the device is enabled, thus no interrupts are
1656 * generated and by the interrupt handler/tasklet handler.
1657 */
1658static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
1659{
1660 struct ace_regs __iomem *regs = ap->regs;
1661 short i, idx;
6aa20a22 1662
1da177e4
LT		 1663
1664 prefetchw(&ap->cur_rx_bufs);
1665
1666 idx = ap->rx_std_skbprd;
1667
1668 for (i = 0; i < nr_bufs; i++) {
1669 struct sk_buff *skb;
1670 struct rx_desc *rd;
1671 dma_addr_t mapping;
1672
1673 skb = alloc_skb(ACE_STD_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1674 if (!skb)
1675 break;
1676
1677 skb_reserve(skb, NET_IP_ALIGN);
1678 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1679 offset_in_page(skb->data),
1680 ACE_STD_BUFSIZE,
1681 PCI_DMA_FROMDEVICE);
1682 ap->skb->rx_std_skbuff[idx].skb = skb;
1683 pci_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1684 mapping, mapping);
1685
1686 rd = &ap->rx_std_ring[idx];
1687 set_aceaddr(&rd->addr, mapping);
1688 rd->size = ACE_STD_BUFSIZE;
1689 rd->idx = idx;
1690 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1691 }
1692
1693 if (!i)
1694 goto error_out;
1695
1696 atomic_add(i, &ap->cur_rx_bufs);
1697 ap->rx_std_skbprd = idx;
1698
1699 if (ACE_IS_TIGON_I(ap)) {
1700 struct cmd cmd;
1701 cmd.evt = C_SET_RX_PRD_IDX;
1702 cmd.code = 0;
1703 cmd.idx = ap->rx_std_skbprd;
1704 ace_issue_cmd(regs, &cmd);
1705 } else {
1706 writel(idx, &regs->RxStdPrd);
1707 wmb();
1708 }
1709
1710 out:
1711 clear_bit(0, &ap->std_refill_busy);
1712 return;
1713
1714 error_out:
1715 printk(KERN_INFO "Out of memory when allocating "
1716 "standard receive buffers\n");
1717 goto out;
1718}
1719
1720
1721static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
1722{
1723 struct ace_regs __iomem *regs = ap->regs;
1724 short i, idx;
1725
1726 prefetchw(&ap->cur_mini_bufs);
1727
1728 idx = ap->rx_mini_skbprd;
1729 for (i = 0; i < nr_bufs; i++) {
1730 struct sk_buff *skb;
1731 struct rx_desc *rd;
1732 dma_addr_t mapping;
1733
1734 skb = alloc_skb(ACE_MINI_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1735 if (!skb)
1736 break;
1737
1738 skb_reserve(skb, NET_IP_ALIGN);
1739 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1740 offset_in_page(skb->data),
1741 ACE_MINI_BUFSIZE,
1742 PCI_DMA_FROMDEVICE);
1743 ap->skb->rx_mini_skbuff[idx].skb = skb;
1744 pci_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1745 mapping, mapping);
1746
1747 rd = &ap->rx_mini_ring[idx];
1748 set_aceaddr(&rd->addr, mapping);
1749 rd->size = ACE_MINI_BUFSIZE;
1750 rd->idx = idx;
1751 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1752 }
1753
1754 if (!i)
1755 goto error_out;
1756
1757 atomic_add(i, &ap->cur_mini_bufs);
1758
1759 ap->rx_mini_skbprd = idx;
1760
1761 writel(idx, &regs->RxMiniPrd);
1762 wmb();
1763
1764 out:
1765 clear_bit(0, &ap->mini_refill_busy);
1766 return;
1767 error_out:
1768 printk(KERN_INFO "Out of memory when allocating "
1769 "mini receive buffers\n");
1770 goto out;
1771}
1772
1773
1774/*
1775 * Load the jumbo rx ring, this may happen at any time if the MTU
1776 * is changed to a value > 1500.
1777 */
1778static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
1779{
1780 struct ace_regs __iomem *regs = ap->regs;
1781 short i, idx;
1782
1783 idx = ap->rx_jumbo_skbprd;
1784
1785 for (i = 0; i < nr_bufs; i++) {
1786 struct sk_buff *skb;
1787 struct rx_desc *rd;
1788 dma_addr_t mapping;
1789
1790 skb = alloc_skb(ACE_JUMBO_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1791 if (!skb)
1792 break;
1793
1794 skb_reserve(skb, NET_IP_ALIGN);
1795 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1796 offset_in_page(skb->data),
1797 ACE_JUMBO_BUFSIZE,
1798 PCI_DMA_FROMDEVICE);
1799 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
1800 pci_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1801 mapping, mapping);
1802
1803 rd = &ap->rx_jumbo_ring[idx];
1804 set_aceaddr(&rd->addr, mapping);
1805 rd->size = ACE_JUMBO_BUFSIZE;
1806 rd->idx = idx;
1807 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1808 }
1809
1810 if (!i)
1811 goto error_out;
1812
1813 atomic_add(i, &ap->cur_jumbo_bufs);
1814 ap->rx_jumbo_skbprd = idx;
1815
1816 if (ACE_IS_TIGON_I(ap)) {
1817 struct cmd cmd;
1818 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1819 cmd.code = 0;
1820 cmd.idx = ap->rx_jumbo_skbprd;
1821 ace_issue_cmd(regs, &cmd);
1822 } else {
1823 writel(idx, &regs->RxJumboPrd);
1824 wmb();
1825 }
1826
1827 out:
1828 clear_bit(0, &ap->jumbo_refill_busy);
1829 return;
1830 error_out:
1831 if (net_ratelimit())
1832 printk(KERN_INFO "Out of memory when allocating "
1833 "jumbo receive buffers\n");
1834 goto out;
1835}
1836
1837
1838/*
1839 * All events are considered to be slow (RX/TX ints do not generate
1840 * events) and are handled here, outside the main interrupt handler,
1841 * to reduce the size of the handler.
1842 */
1843static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1844{
1845 struct ace_private *ap;
1846
1847 ap = netdev_priv(dev);
1848
1849 while (evtcsm != evtprd) {
1850 switch (ap->evt_ring[evtcsm].evt) {
1851 case E_FW_RUNNING:
1852 printk(KERN_INFO "%s: Firmware up and running\n",
1853 ap->name);
1854 ap->fw_running = 1;
1855 wmb();
1856 break;
1857 case E_STATS_UPDATED:
1858 break;
1859 case E_LNK_STATE:
1860 {
1861 u16 code = ap->evt_ring[evtcsm].code;
1862 switch (code) {
1863 case E_C_LINK_UP:
1864 {
1865 u32 state = readl(&ap->regs->GigLnkState);
1866 printk(KERN_WARNING "%s: Optical link UP "
1867 "(%s Duplex, Flow Control: %s%s)\n",
1868 ap->name,
1869 state & LNK_FULL_DUPLEX ? "Full":"Half",
1870 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1871 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1872 break;
1873 }
1874 case E_C_LINK_DOWN:
1875 printk(KERN_WARNING "%s: Optical link DOWN\n",
1876 ap->name);
1877 break;
1878 case E_C_LINK_10_100:
1879 printk(KERN_WARNING "%s: 10/100BaseT link "
1880 "UP\n", ap->name);
1881 break;
1882 default:
1883 printk(KERN_ERR "%s: Unknown optical link "
1884 "state %02x\n", ap->name, code);
1885 }
1886 break;
1887 }
1888 case E_ERROR:
1889 switch(ap->evt_ring[evtcsm].code) {
1890 case E_C_ERR_INVAL_CMD:
1891 printk(KERN_ERR "%s: invalid command error\n",
1892 ap->name);
1893 break;
1894 case E_C_ERR_UNIMP_CMD:
1895 printk(KERN_ERR "%s: unimplemented command "
1896 "error\n", ap->name);
1897 break;
1898 case E_C_ERR_BAD_CFG:
1899 printk(KERN_ERR "%s: bad config error\n",
1900 ap->name);
1901 break;
1902 default:
1903 printk(KERN_ERR "%s: unknown error %02x\n",
1904 ap->name, ap->evt_ring[evtcsm].code);
1905 }
1906 break;
1907 case E_RESET_JUMBO_RNG:
1908 {
1909 int i;
1910 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1911 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1912 ap->rx_jumbo_ring[i].size = 0;
1913 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1914 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1915 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1916 }
1917 }
1918
1919 if (ACE_IS_TIGON_I(ap)) {
1920 struct cmd cmd;
1921 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1922 cmd.code = 0;
1923 cmd.idx = 0;
1924 ace_issue_cmd(ap->regs, &cmd);
1925 } else {
1926 writel(0, &((ap->regs)->RxJumboPrd));
1927 wmb();
1928 }
1929
1930 ap->jumbo = 0;
1931 ap->rx_jumbo_skbprd = 0;
1932 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1933 ap->name);
1934 clear_bit(0, &ap->jumbo_refill_busy);
1935 break;
1936 }
1937 default:
1938 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1939 ap->name, ap->evt_ring[evtcsm].evt);
1940 }
1941 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1942 }
1943
1944 return evtcsm;
1945}
1946
1947
1948static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1949{
1950 struct ace_private *ap = netdev_priv(dev);
1951 u32 idx;
1952 int mini_count = 0, std_count = 0;
1953
1954 idx = rxretcsm;
1955
1956 prefetchw(&ap->cur_rx_bufs);
1957 prefetchw(&ap->cur_mini_bufs);
6aa20a22 1958
1da177e4
LT		 1959 while (idx != rxretprd) {
1960 struct ring_info *rip;
1961 struct sk_buff *skb;
1962 struct rx_desc *rxdesc, *retdesc;
1963 u32 skbidx;
1964 int bd_flags, desc_type, mapsize;
1965 u16 csum;
1966
1967
1968 /* make sure the rx descriptor isn't read before rxretprd */
6aa20a22 1969 if (idx == rxretcsm)
1da177e4
LT		 1970 rmb();
1971
1972 retdesc = &ap->rx_return_ring[idx];
1973 skbidx = retdesc->idx;
1974 bd_flags = retdesc->flags;
1975 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1976
1977 switch(desc_type) {
1978 /*
1979 * Normal frames do not have any flags set
1980 *
1981 * Mini and normal frames arrive frequently,
1982 * so use a local counter to avoid doing
1983 * atomic operations for each packet arriving.
1984 */
1985 case 0:
1986 rip = &ap->skb->rx_std_skbuff[skbidx];
1987 mapsize = ACE_STD_BUFSIZE;
1988 rxdesc = &ap->rx_std_ring[skbidx];
1989 std_count++;
1990 break;
1991 case BD_FLG_JUMBO:
1992 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
1993 mapsize = ACE_JUMBO_BUFSIZE;
1994 rxdesc = &ap->rx_jumbo_ring[skbidx];
1995 atomic_dec(&ap->cur_jumbo_bufs);
1996 break;
1997 case BD_FLG_MINI:
1998 rip = &ap->skb->rx_mini_skbuff[skbidx];
1999 mapsize = ACE_MINI_BUFSIZE;
2000 rxdesc = &ap->rx_mini_ring[skbidx];
6aa20a22 2001 mini_count++;
1da177e4
LT		 2002 break;
2003 default:
2004 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
2005 "returned by NIC\n", dev->name,
2006 retdesc->flags);
2007 goto error;
2008 }
2009
2010 skb = rip->skb;
2011 rip->skb = NULL;
2012 pci_unmap_page(ap->pdev,
2013 pci_unmap_addr(rip, mapping),
2014 mapsize,
2015 PCI_DMA_FROMDEVICE);
2016 skb_put(skb, retdesc->size);
2017
2018 /*
2019 * Fly baby, fly!
2020 */
2021 csum = retdesc->tcp_udp_csum;
2022
1da177e4
LT		 2023 skb->protocol = eth_type_trans(skb, dev);
2024
2025 /*
2026 * Instead of forcing the poor tigon mips cpu to calculate
2027 * pseudo hdr checksum, we do this ourselves.
2028 */
2029 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2030 skb->csum = htons(csum);
84fa7933 2031 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 2032 } else {
2033 skb->ip_summed = CHECKSUM_NONE;
2034 }
2035
2036 /* send it up */
2037#if ACENIC_DO_VLAN
2038 if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
2039 vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
2040 } else
2041#endif
2042 netif_rx(skb);
2043
966e37bc
PZ		 2044 dev->stats.rx_packets++;
2045 dev->stats.rx_bytes += retdesc->size;
1da177e4
LT		 2046
2047 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2048 }
2049
2050 atomic_sub(std_count, &ap->cur_rx_bufs);
2051 if (!ACE_IS_TIGON_I(ap))
2052 atomic_sub(mini_count, &ap->cur_mini_bufs);
2053
2054 out:
2055 /*
2056 * According to the documentation RxRetCsm is obsolete with
2057 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2058 */
2059 if (ACE_IS_TIGON_I(ap)) {
2060 writel(idx, &ap->regs->RxRetCsm);
2061 }
2062 ap->cur_rx = idx;
2063
2064 return;
2065 error:
2066 idx = rxretprd;
2067 goto out;
2068}
2069
2070
2071static inline void ace_tx_int(struct net_device *dev,
2072 u32 txcsm, u32 idx)
2073{
2074 struct ace_private *ap = netdev_priv(dev);
2075
2076 do {
2077 struct sk_buff *skb;
2078 dma_addr_t mapping;
2079 struct tx_ring_info *info;
2080
2081 info = ap->skb->tx_skbuff + idx;
2082 skb = info->skb;
2083 mapping = pci_unmap_addr(info, mapping);
2084
2085 if (mapping) {
2086 pci_unmap_page(ap->pdev, mapping,
2087 pci_unmap_len(info, maplen),
2088 PCI_DMA_TODEVICE);
2089 pci_unmap_addr_set(info, mapping, 0);
2090 }
2091
2092 if (skb) {
966e37bc
PZ		 2093 dev->stats.tx_packets++;
2094 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 2095 dev_kfree_skb_irq(skb);
2096 info->skb = NULL;
2097 }
2098
2099 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2100 } while (idx != txcsm);
2101
2102 if (netif_queue_stopped(dev))
2103 netif_wake_queue(dev);
2104
2105 wmb();
2106 ap->tx_ret_csm = txcsm;
2107
2108 /* So... tx_ret_csm is advanced _after_ check for device wakeup.
2109 *
2110 * We could try to make it before. In this case we would get
2111 * the following race condition: hard_start_xmit on other cpu
2112 * enters after we advanced tx_ret_csm and fills space,
2113 * which we have just freed, so that we make illegal device wakeup.
2114 * There is no good way to workaround this (at entry
2115 * to ace_start_xmit detects this condition and prevents
2116 * ring corruption, but it is not a good workaround.)
2117 *
2118 * When tx_ret_csm is advanced after, we wake up device _only_
2119 * if we really have some space in ring (though the core doing
2120 * hard_start_xmit can see full ring for some period and has to
2121 * synchronize.) Superb.
2122 * BUT! We get another subtle race condition. hard_start_xmit
2123 * may think that ring is full between wakeup and advancing
2124 * tx_ret_csm and will stop device instantly! It is not so bad.
2125 * We are guaranteed that there is something in ring, so that
2126 * the next irq will resume transmission. To speedup this we could
2127 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2128 * (see ace_start_xmit).
2129 *
2130 * Well, this dilemma exists in all lock-free devices.
2131 * We, following scheme used in drivers by Donald Becker,
2132 * select the least dangerous.
2133 * --ANK
2134 */
2135}
2136
2137
7d12e780 2138static irqreturn_t ace_interrupt(int irq, void *dev_id)
1da177e4
LT		 2139{
2140 struct net_device *dev = (struct net_device *)dev_id;
2141 struct ace_private *ap = netdev_priv(dev);
2142 struct ace_regs __iomem *regs = ap->regs;
2143 u32 idx;
2144 u32 txcsm, rxretcsm, rxretprd;
2145 u32 evtcsm, evtprd;
2146
2147 /*
2148 * In case of PCI shared interrupts or spurious interrupts,
2149 * we want to make sure it is actually our interrupt before
2150 * spending any time in here.
2151 */
2152 if (!(readl(&regs->HostCtrl) & IN_INT))
2153 return IRQ_NONE;
2154
2155 /*
2156 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2157 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2158 * writel(0, &regs->Mb0Lo).
2159 *
2160 * "IRQ avoidance" recommended in docs applies to IRQs served
2161 * threads and it is wrong even for that case.
2162 */
2163 writel(0, &regs->Mb0Lo);
2164 readl(&regs->Mb0Lo);
2165
2166 /*
2167 * There is no conflict between transmit handling in
2168 * start_xmit and receive processing, thus there is no reason
2169 * to take a spin lock for RX handling. Wait until we start
2170 * working on the other stuff - hey we don't need a spin lock
2171 * anymore.
2172 */
2173 rxretprd = *ap->rx_ret_prd;
2174 rxretcsm = ap->cur_rx;
2175
2176 if (rxretprd != rxretcsm)
2177 ace_rx_int(dev, rxretprd, rxretcsm);
2178
2179 txcsm = *ap->tx_csm;
2180 idx = ap->tx_ret_csm;
2181
2182 if (txcsm != idx) {
2183 /*
2184 * If each skb takes only one descriptor this check degenerates
2185 * to identity, because new space has just been opened.
2186 * But if skbs are fragmented we must check that this index
2187 * update releases enough of space, otherwise we just
2188 * wait for device to make more work.
2189 */
2190 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2191 ace_tx_int(dev, txcsm, idx);
2192 }
2193
2194 evtcsm = readl(&regs->EvtCsm);
2195 evtprd = *ap->evt_prd;
2196
2197 if (evtcsm != evtprd) {
2198 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2199 writel(evtcsm, &regs->EvtCsm);
2200 }
2201
2202 /*
2203 * This has to go last in the interrupt handler and run with
2204 * the spin lock released ... what lock?
2205 */
2206 if (netif_running(dev)) {
2207 int cur_size;
2208 int run_tasklet = 0;
2209
2210 cur_size = atomic_read(&ap->cur_rx_bufs);
2211 if (cur_size < RX_LOW_STD_THRES) {
2212 if ((cur_size < RX_PANIC_STD_THRES) &&
2213 !test_and_set_bit(0, &ap->std_refill_busy)) {
2214#ifdef DEBUG
2215 printk("low on std buffers %i\n", cur_size);
2216#endif
2217 ace_load_std_rx_ring(ap,
2218 RX_RING_SIZE - cur_size);
2219 } else
2220 run_tasklet = 1;
2221 }
2222
2223 if (!ACE_IS_TIGON_I(ap)) {
2224 cur_size = atomic_read(&ap->cur_mini_bufs);
2225 if (cur_size < RX_LOW_MINI_THRES) {
2226 if ((cur_size < RX_PANIC_MINI_THRES) &&
2227 !test_and_set_bit(0,
2228 &ap->mini_refill_busy)) {
2229#ifdef DEBUG
2230 printk("low on mini buffers %i\n",
2231 cur_size);
2232#endif
2233 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
2234 } else
2235 run_tasklet = 1;
2236 }
2237 }
2238
2239 if (ap->jumbo) {
2240 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2241 if (cur_size < RX_LOW_JUMBO_THRES) {
2242 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2243 !test_and_set_bit(0,
2244 &ap->jumbo_refill_busy)){
2245#ifdef DEBUG
2246 printk("low on jumbo buffers %i\n",
2247 cur_size);
2248#endif
2249 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
2250 } else
2251 run_tasklet = 1;
2252 }
2253 }
2254 if (run_tasklet && !ap->tasklet_pending) {
2255 ap->tasklet_pending = 1;
2256 tasklet_schedule(&ap->ace_tasklet);
2257 }
2258 }
2259
2260 return IRQ_HANDLED;
2261}
2262
2263
2264#if ACENIC_DO_VLAN
2265static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2266{
2267 struct ace_private *ap = netdev_priv(dev);
2268 unsigned long flags;
2269
2270 local_irq_save(flags);
2271 ace_mask_irq(dev);
2272
2273 ap->vlgrp = grp;
2274
2275 ace_unmask_irq(dev);
2276 local_irq_restore(flags);
2277}
1da177e4
LT		 2278#endif /* ACENIC_DO_VLAN */
2279
2280
2281static int ace_open(struct net_device *dev)
2282{
2283 struct ace_private *ap = netdev_priv(dev);
2284 struct ace_regs __iomem *regs = ap->regs;
2285 struct cmd cmd;
2286
2287 if (!(ap->fw_running)) {
2288 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2289 return -EBUSY;
2290 }
2291
2292 writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2293
2294 cmd.evt = C_CLEAR_STATS;
2295 cmd.code = 0;
2296 cmd.idx = 0;
2297 ace_issue_cmd(regs, &cmd);
2298
2299 cmd.evt = C_HOST_STATE;
2300 cmd.code = C_C_STACK_UP;
2301 cmd.idx = 0;
2302 ace_issue_cmd(regs, &cmd);
2303
2304 if (ap->jumbo &&
2305 !test_and_set_bit(0, &ap->jumbo_refill_busy))
2306 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2307
2308 if (dev->flags & IFF_PROMISC) {
2309 cmd.evt = C_SET_PROMISC_MODE;
2310 cmd.code = C_C_PROMISC_ENABLE;
2311 cmd.idx = 0;
2312 ace_issue_cmd(regs, &cmd);
2313
2314 ap->promisc = 1;
2315 }else
2316 ap->promisc = 0;
2317 ap->mcast_all = 0;
2318
2319#if 0
2320 cmd.evt = C_LNK_NEGOTIATION;
2321 cmd.code = 0;
2322 cmd.idx = 0;
2323 ace_issue_cmd(regs, &cmd);
2324#endif
2325
2326 netif_start_queue(dev);
2327
2328 /*
2329 * Setup the bottom half rx ring refill handler
2330 */
2331 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2332 return 0;
2333}
2334
2335
2336static int ace_close(struct net_device *dev)
2337{
2338 struct ace_private *ap = netdev_priv(dev);
2339 struct ace_regs __iomem *regs = ap->regs;
2340 struct cmd cmd;
2341 unsigned long flags;
2342 short i;
2343
2344 /*
2345 * Without (or before) releasing irq and stopping hardware, this
2346 * is an absolute non-sense, by the way. It will be reset instantly
2347 * by the first irq.
2348 */
2349 netif_stop_queue(dev);
2350
6aa20a22 2351
1da177e4
LT		 2352 if (ap->promisc) {
2353 cmd.evt = C_SET_PROMISC_MODE;
2354 cmd.code = C_C_PROMISC_DISABLE;
2355 cmd.idx = 0;
2356 ace_issue_cmd(regs, &cmd);
2357 ap->promisc = 0;
2358 }
2359
2360 cmd.evt = C_HOST_STATE;
2361 cmd.code = C_C_STACK_DOWN;
2362 cmd.idx = 0;
2363 ace_issue_cmd(regs, &cmd);
2364
2365 tasklet_kill(&ap->ace_tasklet);
2366
2367 /*
2368 * Make sure one CPU is not processing packets while
2369 * buffers are being released by another.
2370 */
2371
2372 local_irq_save(flags);
2373 ace_mask_irq(dev);
2374
2375 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2376 struct sk_buff *skb;
2377 dma_addr_t mapping;
2378 struct tx_ring_info *info;
2379
2380 info = ap->skb->tx_skbuff + i;
2381 skb = info->skb;
2382 mapping = pci_unmap_addr(info, mapping);
2383
2384 if (mapping) {
2385 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb
SH		 2386 /* NB: TIGON_1 is special, tx_ring is in io space */
2387 struct tx_desc __iomem *tx;
2388 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
1da177e4
LT		 2389 writel(0, &tx->addr.addrhi);
2390 writel(0, &tx->addr.addrlo);
2391 writel(0, &tx->flagsize);
2392 } else
2393 memset(ap->tx_ring + i, 0,
2394 sizeof(struct tx_desc));
2395 pci_unmap_page(ap->pdev, mapping,
2396 pci_unmap_len(info, maplen),
2397 PCI_DMA_TODEVICE);
2398 pci_unmap_addr_set(info, mapping, 0);
2399 }
2400 if (skb) {
2401 dev_kfree_skb(skb);
2402 info->skb = NULL;
2403 }
2404 }
2405
2406 if (ap->jumbo) {
2407 cmd.evt = C_RESET_JUMBO_RNG;
2408 cmd.code = 0;
2409 cmd.idx = 0;
2410 ace_issue_cmd(regs, &cmd);
2411 }
2412
2413 ace_unmask_irq(dev);
2414 local_irq_restore(flags);
2415
2416 return 0;
2417}
2418
2419
2420static inline dma_addr_t
2421ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2422 struct sk_buff *tail, u32 idx)
2423{
2424 dma_addr_t mapping;
2425 struct tx_ring_info *info;
2426
2427 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2428 offset_in_page(skb->data),
2429 skb->len, PCI_DMA_TODEVICE);
2430
2431 info = ap->skb->tx_skbuff + idx;
2432 info->skb = tail;
2433 pci_unmap_addr_set(info, mapping, mapping);
2434 pci_unmap_len_set(info, maplen, skb->len);
2435 return mapping;
2436}
2437
2438
2439static inline void
2440ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2441 u32 flagsize, u32 vlan_tag)
2442{
2443#if !USE_TX_COAL_NOW
2444 flagsize &= ~BD_FLG_COAL_NOW;
2445#endif
2446
2447 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 2448 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
1da177e4
LT		 2449 writel(addr >> 32, &io->addr.addrhi);
2450 writel(addr & 0xffffffff, &io->addr.addrlo);
2451 writel(flagsize, &io->flagsize);
2452#if ACENIC_DO_VLAN
2453 writel(vlan_tag, &io->vlanres);
2454#endif
2455 } else {
2456 desc->addr.addrhi = addr >> 32;
2457 desc->addr.addrlo = addr;
2458 desc->flagsize = flagsize;
2459#if ACENIC_DO_VLAN
2460 desc->vlanres = vlan_tag;
2461#endif
2462 }
2463}
2464
2465
2466static int ace_start_xmit(struct sk_buff *skb, struct net_device *dev)
2467{
2468 struct ace_private *ap = netdev_priv(dev);
2469 struct ace_regs __iomem *regs = ap->regs;
2470 struct tx_desc *desc;
2471 u32 idx, flagsize;
2472 unsigned long maxjiff = jiffies + 3*HZ;
2473
2474restart:
2475 idx = ap->tx_prd;
2476
2477 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2478 goto overflow;
2479
2480 if (!skb_shinfo(skb)->nr_frags) {
2481 dma_addr_t mapping;
2482 u32 vlan_tag = 0;
2483
2484 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2485 flagsize = (skb->len << 16) | (BD_FLG_END);
84fa7933 2486 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2487 flagsize |= BD_FLG_TCP_UDP_SUM;
2488#if ACENIC_DO_VLAN
2489 if (vlan_tx_tag_present(skb)) {
2490 flagsize |= BD_FLG_VLAN_TAG;
2491 vlan_tag = vlan_tx_tag_get(skb);
2492 }
2493#endif
2494 desc = ap->tx_ring + idx;
2495 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2496
2497 /* Look at ace_tx_int for explanations. */
2498 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2499 flagsize |= BD_FLG_COAL_NOW;
2500
2501 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2502 } else {
2503 dma_addr_t mapping;
2504 u32 vlan_tag = 0;
2505 int i, len = 0;
2506
2507 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2508 flagsize = (skb_headlen(skb) << 16);
84fa7933 2509 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2510 flagsize |= BD_FLG_TCP_UDP_SUM;
2511#if ACENIC_DO_VLAN
2512 if (vlan_tx_tag_present(skb)) {
2513 flagsize |= BD_FLG_VLAN_TAG;
2514 vlan_tag = vlan_tx_tag_get(skb);
2515 }
2516#endif
2517
2518 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2519
2520 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2521
2522 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2523 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2524 struct tx_ring_info *info;
2525
2526 len += frag->size;
2527 info = ap->skb->tx_skbuff + idx;
2528 desc = ap->tx_ring + idx;
2529
2530 mapping = pci_map_page(ap->pdev, frag->page,
2531 frag->page_offset, frag->size,
2532 PCI_DMA_TODEVICE);
2533
2534 flagsize = (frag->size << 16);
84fa7933 2535 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2536 flagsize |= BD_FLG_TCP_UDP_SUM;
2537 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2538
2539 if (i == skb_shinfo(skb)->nr_frags - 1) {
2540 flagsize |= BD_FLG_END;
2541 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2542 flagsize |= BD_FLG_COAL_NOW;
2543
2544 /*
2545 * Only the last fragment frees
2546 * the skb!
2547 */
2548 info->skb = skb;
2549 } else {
2550 info->skb = NULL;
2551 }
2552 pci_unmap_addr_set(info, mapping, mapping);
2553 pci_unmap_len_set(info, maplen, frag->size);
2554 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2555 }
2556 }
2557
2558 wmb();
2559 ap->tx_prd = idx;
2560 ace_set_txprd(regs, ap, idx);
2561
2562 if (flagsize & BD_FLG_COAL_NOW) {
2563 netif_stop_queue(dev);
2564
2565 /*
2566 * A TX-descriptor producer (an IRQ) might have gotten
2567 * inbetween, making the ring free again. Since xmit is
2568 * serialized, this is the only situation we have to
2569 * re-test.
2570 */
2571 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2572 netif_wake_queue(dev);
2573 }
2574
2575 dev->trans_start = jiffies;
2576 return NETDEV_TX_OK;
2577
2578overflow:
2579 /*
2580 * This race condition is unavoidable with lock-free drivers.
2581 * We wake up the queue _before_ tx_prd is advanced, so that we can
2582 * enter hard_start_xmit too early, while tx ring still looks closed.
2583 * This happens ~1-4 times per 100000 packets, so that we can allow
2584 * to loop syncing to other CPU. Probably, we need an additional
2585 * wmb() in ace_tx_intr as well.
2586 *
2587 * Note that this race is relieved by reserving one more entry
2588 * in tx ring than it is necessary (see original non-SG driver).
2589 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2590 * is already overkill.
2591 *
2592 * Alternative is to return with 1 not throttling queue. In this
2593 * case loop becomes longer, no more useful effects.
2594 */
2595 if (time_before(jiffies, maxjiff)) {
2596 barrier();
2597 cpu_relax();
2598 goto restart;
2599 }
6aa20a22 2600
1da177e4
LT		 2601 /* The ring is stuck full. */
2602 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2603 return NETDEV_TX_BUSY;
2604}
2605
2606
2607static int ace_change_mtu(struct net_device *dev, int new_mtu)
2608{
2609 struct ace_private *ap = netdev_priv(dev);
2610 struct ace_regs __iomem *regs = ap->regs;
2611
2612 if (new_mtu > ACE_JUMBO_MTU)
2613 return -EINVAL;
2614
2615 writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2616 dev->mtu = new_mtu;
2617
2618 if (new_mtu > ACE_STD_MTU) {
2619 if (!(ap->jumbo)) {
2620 printk(KERN_INFO "%s: Enabling Jumbo frame "
2621 "support\n", dev->name);
2622 ap->jumbo = 1;
2623 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2624 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2625 ace_set_rxtx_parms(dev, 1);
2626 }
2627 } else {
2628 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2629 ace_sync_irq(dev->irq);
2630 ace_set_rxtx_parms(dev, 0);
2631 if (ap->jumbo) {
2632 struct cmd cmd;
2633
2634 cmd.evt = C_RESET_JUMBO_RNG;
2635 cmd.code = 0;
2636 cmd.idx = 0;
2637 ace_issue_cmd(regs, &cmd);
2638 }
2639 }
2640
2641 return 0;
2642}
2643
2644static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2645{
2646 struct ace_private *ap = netdev_priv(dev);
2647 struct ace_regs __iomem *regs = ap->regs;
2648 u32 link;
2649
2650 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2651 ecmd->supported =
2652 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2653 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2654 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2655 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2656
2657 ecmd->port = PORT_FIBRE;
2658 ecmd->transceiver = XCVR_INTERNAL;
2659
2660 link = readl(&regs->GigLnkState);
2661 if (link & LNK_1000MB)
2662 ecmd->speed = SPEED_1000;
2663 else {
2664 link = readl(&regs->FastLnkState);
2665 if (link & LNK_100MB)
2666 ecmd->speed = SPEED_100;
2667 else if (link & LNK_10MB)
2668 ecmd->speed = SPEED_10;
2669 else
2670 ecmd->speed = 0;
2671 }
2672 if (link & LNK_FULL_DUPLEX)
2673 ecmd->duplex = DUPLEX_FULL;
2674 else
2675 ecmd->duplex = DUPLEX_HALF;
2676
2677 if (link & LNK_NEGOTIATE)
2678 ecmd->autoneg = AUTONEG_ENABLE;
2679 else
2680 ecmd->autoneg = AUTONEG_DISABLE;
2681
2682#if 0
2683 /*
2684 * Current struct ethtool_cmd is insufficient
2685 */
2686 ecmd->trace = readl(&regs->TuneTrace);
2687
2688 ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2689 ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2690#endif
2691 ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
2692 ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
2693
2694 return 0;
2695}
2696
2697static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2698{
2699 struct ace_private *ap = netdev_priv(dev);
2700 struct ace_regs __iomem *regs = ap->regs;
2701 u32 link, speed;
2702
2703 link = readl(&regs->GigLnkState);
2704 if (link & LNK_1000MB)
2705 speed = SPEED_1000;
2706 else {
2707 link = readl(&regs->FastLnkState);
2708 if (link & LNK_100MB)
2709 speed = SPEED_100;
2710 else if (link & LNK_10MB)
2711 speed = SPEED_10;
2712 else
2713 speed = SPEED_100;
2714 }
2715
2716 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2717 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2718 if (!ACE_IS_TIGON_I(ap))
2719 link |= LNK_TX_FLOW_CTL_Y;
2720 if (ecmd->autoneg == AUTONEG_ENABLE)
2721 link |= LNK_NEGOTIATE;
2722 if (ecmd->speed != speed) {
2723 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
2724 switch (speed) {
2725 case SPEED_1000:
2726 link |= LNK_1000MB;
2727 break;
2728 case SPEED_100:
2729 link |= LNK_100MB;
2730 break;
2731 case SPEED_10:
2732 link |= LNK_10MB;
2733 break;
2734 }
2735 }
2736
2737 if (ecmd->duplex == DUPLEX_FULL)
2738 link |= LNK_FULL_DUPLEX;
2739
2740 if (link != ap->link) {
2741 struct cmd cmd;
2742 printk(KERN_INFO "%s: Renegotiating link state\n",
2743 dev->name);
2744
2745 ap->link = link;
2746 writel(link, &regs->TuneLink);
2747 if (!ACE_IS_TIGON_I(ap))
2748 writel(link, &regs->TuneFastLink);
2749 wmb();
2750
2751 cmd.evt = C_LNK_NEGOTIATION;
2752 cmd.code = 0;
2753 cmd.idx = 0;
2754 ace_issue_cmd(regs, &cmd);
2755 }
2756 return 0;
2757}
2758
6aa20a22 2759static void ace_get_drvinfo(struct net_device *dev,
1da177e4
LT		 2760 struct ethtool_drvinfo *info)
2761{
2762 struct ace_private *ap = netdev_priv(dev);
2763
2764 strlcpy(info->driver, "acenic", sizeof(info->driver));
6aa20a22 2765 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
949b4254
JS		 2766 ap->firmware_major, ap->firmware_minor,
2767 ap->firmware_fix);
1da177e4
LT		 2768
2769 if (ap->pdev)
6aa20a22 2770 strlcpy(info->bus_info, pci_name(ap->pdev),
1da177e4
LT		 2771 sizeof(info->bus_info));
2772
2773}
2774
2775/*
2776 * Set the hardware MAC address.
2777 */
2778static int ace_set_mac_addr(struct net_device *dev, void *p)
2779{
2780 struct ace_private *ap = netdev_priv(dev);
2781 struct ace_regs __iomem *regs = ap->regs;
2782 struct sockaddr *addr=p;
2783 u8 *da;
2784 struct cmd cmd;
2785
2786 if(netif_running(dev))
2787 return -EBUSY;
2788
2789 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2790
2791 da = (u8 *)dev->dev_addr;
2792
2793 writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2794 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2795 &regs->MacAddrLo);
2796
2797 cmd.evt = C_SET_MAC_ADDR;
2798 cmd.code = 0;
2799 cmd.idx = 0;
2800 ace_issue_cmd(regs, &cmd);
2801
2802 return 0;
2803}
2804
2805
2806static void ace_set_multicast_list(struct net_device *dev)
2807{
2808 struct ace_private *ap = netdev_priv(dev);
2809 struct ace_regs __iomem *regs = ap->regs;
2810 struct cmd cmd;
2811
2812 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2813 cmd.evt = C_SET_MULTICAST_MODE;
2814 cmd.code = C_C_MCAST_ENABLE;
2815 cmd.idx = 0;
2816 ace_issue_cmd(regs, &cmd);
2817 ap->mcast_all = 1;
2818 } else if (ap->mcast_all) {
2819 cmd.evt = C_SET_MULTICAST_MODE;
2820 cmd.code = C_C_MCAST_DISABLE;
2821 cmd.idx = 0;
2822 ace_issue_cmd(regs, &cmd);
2823 ap->mcast_all = 0;
2824 }
2825
2826 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2827 cmd.evt = C_SET_PROMISC_MODE;
2828 cmd.code = C_C_PROMISC_ENABLE;
2829 cmd.idx = 0;
2830 ace_issue_cmd(regs, &cmd);
2831 ap->promisc = 1;
2832 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2833 cmd.evt = C_SET_PROMISC_MODE;
2834 cmd.code = C_C_PROMISC_DISABLE;
2835 cmd.idx = 0;
2836 ace_issue_cmd(regs, &cmd);
2837 ap->promisc = 0;
2838 }
2839
2840 /*
2841 * For the time being multicast relies on the upper layers
2842 * filtering it properly. The Firmware does not allow one to
2843 * set the entire multicast list at a time and keeping track of
2844 * it here is going to be messy.
2845 */
2846 if ((dev->mc_count) && !(ap->mcast_all)) {
2847 cmd.evt = C_SET_MULTICAST_MODE;
2848 cmd.code = C_C_MCAST_ENABLE;
2849 cmd.idx = 0;
2850 ace_issue_cmd(regs, &cmd);
2851 }else if (!ap->mcast_all) {
2852 cmd.evt = C_SET_MULTICAST_MODE;
2853 cmd.code = C_C_MCAST_DISABLE;
2854 cmd.idx = 0;
2855 ace_issue_cmd(regs, &cmd);
2856 }
2857}
2858
2859
2860static struct net_device_stats *ace_get_stats(struct net_device *dev)
2861{
2862 struct ace_private *ap = netdev_priv(dev);
2863 struct ace_mac_stats __iomem *mac_stats =
2864 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2865
966e37bc
PZ		 2866 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2867 dev->stats.multicast = readl(&mac_stats->kept_mc);
2868 dev->stats.collisions = readl(&mac_stats->coll);
1da177e4 2869
966e37bc 2870 return &dev->stats;
1da177e4
LT		 2871}
2872
2873
949b4254
JS		 2874static void __devinit ace_copy(struct ace_regs __iomem *regs, const __be32 *src,
2875 u32 dest, int size)
1da177e4
LT		 2876{
2877 void __iomem *tdest;
1da177e4
LT		 2878 short tsize, i;
2879
2880 if (size <= 0)
2881 return;
2882
2883 while (size > 0) {
2884 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2885 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2886 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2887 (dest & (ACE_WINDOW_SIZE - 1));
2888 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
1da177e4 2889 for (i = 0; i < (tsize / 4); i++) {
949b4254
JS		 2890 /* Firmware is big-endian */
2891 writel(be32_to_cpup(src), tdest);
2892 src++;
2893 tdest += 4;
2894 dest += 4;
2895 size -= 4;
1da177e4 2896 }
1da177e4 2897 }
1da177e4
LT		 2898}
2899
2900
2901static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2902{
2903 void __iomem *tdest;
2904 short tsize = 0, i;
2905
2906 if (size <= 0)
2907 return;
2908
2909 while (size > 0) {
2910 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2911 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2912 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2913 (dest & (ACE_WINDOW_SIZE - 1));
2914 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2915
2916 for (i = 0; i < (tsize / 4); i++) {
2917 writel(0, tdest + i*4);
2918 }
2919
2920 dest += tsize;
2921 size -= tsize;
2922 }
2923
2924 return;
2925}
2926
2927
2928/*
2929 * Download the firmware into the SRAM on the NIC
2930 *
2931 * This operation requires the NIC to be halted and is performed with
2932 * interrupts disabled and with the spinlock hold.
2933 */
ddfce6bb 2934static int __devinit ace_load_firmware(struct net_device *dev)
1da177e4 2935{
949b4254
JS		 2936 const struct firmware *fw;
2937 const char *fw_name = "acenic/tg2.bin";
1da177e4
LT		 2938 struct ace_private *ap = netdev_priv(dev);
2939 struct ace_regs __iomem *regs = ap->regs;
949b4254
JS		 2940 const __be32 *fw_data;
2941 u32 load_addr;
2942 int ret;
1da177e4
LT		 2943
2944 if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2945 printk(KERN_ERR "%s: trying to download firmware while the "
2946 "CPU is running!\n", ap->name);
2947 return -EFAULT;
2948 }
2949
949b4254
JS		 2950 if (ACE_IS_TIGON_I(ap))
2951 fw_name = "acenic/tg1.bin";
2952
2953 ret = request_firmware(&fw, fw_name, &ap->pdev->dev);
2954 if (ret) {
2955 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
2956 ap->name, fw_name);
2957 return ret;
2958 }
2959
2960 fw_data = (void *)fw->data;
2961
2962 /* Firmware blob starts with version numbers, followed by
2963 load and start address. Remainder is the blob to be loaded
2964 contiguously from load address. We don't bother to represent
2965 the BSS/SBSS sections any more, since we were clearing the
2966 whole thing anyway. */
2967 ap->firmware_major = fw->data[0];
2968 ap->firmware_minor = fw->data[1];
2969 ap->firmware_fix = fw->data[2];
2970
2971 ap->firmware_start = be32_to_cpu(fw_data[1]);
2972 if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) {
2973 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2974 ap->name, ap->firmware_start, fw_name);
2975 ret = -EINVAL;
2976 goto out;
2977 }
2978
2979 load_addr = be32_to_cpu(fw_data[2]);
2980 if (load_addr < 0x4000 || load_addr >= 0x80000) {
2981 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2982 ap->name, load_addr, fw_name);
2983 ret = -EINVAL;
2984 goto out;
2985 }
2986
1da177e4 2987 /*
949b4254
JS		 2988 * Do not try to clear more than 512KiB or we end up seeing
2989 * funny things on NICs with only 512KiB SRAM
1da177e4
LT		 2990 */
2991 ace_clear(regs, 0x2000, 0x80000-0x2000);
949b4254
JS		 2992 ace_copy(regs, &fw_data[3], load_addr, fw->size-12);
2993 out:
2994 release_firmware(fw);
2995 return ret;
1da177e4
LT		 2996}
2997
2998
2999/*
3000 * The eeprom on the AceNIC is an Atmel i2c EEPROM.
3001 *
3002 * Accessing the EEPROM is `interesting' to say the least - don't read
3003 * this code right after dinner.
3004 *
3005 * This is all about black magic and bit-banging the device .... I
3006 * wonder in what hospital they have put the guy who designed the i2c
3007 * specs.
3008 *
3009 * Oh yes, this is only the beginning!
3010 *
3011 * Thanks to Stevarino Webinski for helping tracking down the bugs in the
3012 * code i2c readout code by beta testing all my hacks.
3013 */
3014static void __devinit eeprom_start(struct ace_regs __iomem *regs)
3015{
3016 u32 local;
3017
3018 readl(&regs->LocalCtrl);
3019 udelay(ACE_SHORT_DELAY);
3020 local = readl(&regs->LocalCtrl);
3021 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
3022 writel(local, &regs->LocalCtrl);
3023 readl(&regs->LocalCtrl);
3024 mb();
3025 udelay(ACE_SHORT_DELAY);
3026 local |= EEPROM_CLK_OUT;
3027 writel(local, &regs->LocalCtrl);
3028 readl(&regs->LocalCtrl);
3029 mb();
3030 udelay(ACE_SHORT_DELAY);
3031 local &= ~EEPROM_DATA_OUT;
3032 writel(local, &regs->LocalCtrl);
3033 readl(&regs->LocalCtrl);
3034 mb();
3035 udelay(ACE_SHORT_DELAY);
3036 local &= ~EEPROM_CLK_OUT;
3037 writel(local, &regs->LocalCtrl);
3038 readl(&regs->LocalCtrl);
3039 mb();
3040}
3041
3042
3043static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
3044{
3045 short i;
3046 u32 local;
3047
3048 udelay(ACE_SHORT_DELAY);
3049 local = readl(&regs->LocalCtrl);
3050 local &= ~EEPROM_DATA_OUT;
3051 local |= EEPROM_WRITE_ENABLE;
3052 writel(local, &regs->LocalCtrl);
3053 readl(&regs->LocalCtrl);
3054 mb();
3055
3056 for (i = 0; i < 8; i++, magic <<= 1) {
3057 udelay(ACE_SHORT_DELAY);
6aa20a22 3058 if (magic & 0x80)
1da177e4
LT		 3059 local |= EEPROM_DATA_OUT;
3060 else
3061 local &= ~EEPROM_DATA_OUT;
3062 writel(local, &regs->LocalCtrl);
3063 readl(&regs->LocalCtrl);
3064 mb();
3065
3066 udelay(ACE_SHORT_DELAY);
3067 local |= EEPROM_CLK_OUT;
3068 writel(local, &regs->LocalCtrl);
3069 readl(&regs->LocalCtrl);
3070 mb();
3071 udelay(ACE_SHORT_DELAY);
3072 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3073 writel(local, &regs->LocalCtrl);
3074 readl(&regs->LocalCtrl);
3075 mb();
3076 }
3077}
3078
3079
3080static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
3081{
3082 int state;
3083 u32 local;
3084
3085 local = readl(&regs->LocalCtrl);
3086 local &= ~EEPROM_WRITE_ENABLE;
3087 writel(local, &regs->LocalCtrl);
3088 readl(&regs->LocalCtrl);
3089 mb();
3090 udelay(ACE_LONG_DELAY);
3091 local |= EEPROM_CLK_OUT;
3092 writel(local, &regs->LocalCtrl);
3093 readl(&regs->LocalCtrl);
3094 mb();
3095 udelay(ACE_SHORT_DELAY);
3096 /* sample data in middle of high clk */
3097 state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3098 udelay(ACE_SHORT_DELAY);
3099 mb();
3100 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3101 readl(&regs->LocalCtrl);
3102 mb();
3103
3104 return state;
3105}
3106
3107
3108static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
3109{
3110 u32 local;
3111
3112 udelay(ACE_SHORT_DELAY);
3113 local = readl(&regs->LocalCtrl);
3114 local |= EEPROM_WRITE_ENABLE;
3115 writel(local, &regs->LocalCtrl);
3116 readl(&regs->LocalCtrl);
3117 mb();
3118 udelay(ACE_SHORT_DELAY);
3119 local &= ~EEPROM_DATA_OUT;
3120 writel(local, &regs->LocalCtrl);
3121 readl(&regs->LocalCtrl);
3122 mb();
3123 udelay(ACE_SHORT_DELAY);
3124 local |= EEPROM_CLK_OUT;
3125 writel(local, &regs->LocalCtrl);
3126 readl(&regs->LocalCtrl);
3127 mb();
3128 udelay(ACE_SHORT_DELAY);
3129 local |= EEPROM_DATA_OUT;
3130 writel(local, &regs->LocalCtrl);
3131 readl(&regs->LocalCtrl);
3132 mb();
3133 udelay(ACE_LONG_DELAY);
3134 local &= ~EEPROM_CLK_OUT;
3135 writel(local, &regs->LocalCtrl);
3136 mb();
3137}
3138
3139
3140/*
3141 * Read a whole byte from the EEPROM.
3142 */
3143static int __devinit read_eeprom_byte(struct net_device *dev,
3144 unsigned long offset)
3145{
3146 struct ace_private *ap = netdev_priv(dev);
3147 struct ace_regs __iomem *regs = ap->regs;
3148 unsigned long flags;
3149 u32 local;
3150 int result = 0;
3151 short i;
3152
1da177e4
LT		 3153 /*
3154 * Don't take interrupts on this CPU will bit banging
3155 * the %#%#@$ I2C device
3156 */
3157 local_irq_save(flags);
3158
3159 eeprom_start(regs);
3160
3161 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3162 if (eeprom_check_ack(regs)) {
3163 local_irq_restore(flags);
3164 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3165 result = -EIO;
3166 goto eeprom_read_error;
3167 }
3168
3169 eeprom_prep(regs, (offset >> 8) & 0xff);
3170 if (eeprom_check_ack(regs)) {
3171 local_irq_restore(flags);
3172 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3173 ap->name);
3174 result = -EIO;
3175 goto eeprom_read_error;
3176 }
3177
3178 eeprom_prep(regs, offset & 0xff);
3179 if (eeprom_check_ack(regs)) {
3180 local_irq_restore(flags);
3181 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3182 ap->name);
3183 result = -EIO;
3184 goto eeprom_read_error;
3185 }
3186
3187 eeprom_start(regs);
3188 eeprom_prep(regs, EEPROM_READ_SELECT);
3189 if (eeprom_check_ack(regs)) {
3190 local_irq_restore(flags);
3191 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3192 ap->name);
3193 result = -EIO;
3194 goto eeprom_read_error;
3195 }
3196
3197 for (i = 0; i < 8; i++) {
3198 local = readl(&regs->LocalCtrl);
3199 local &= ~EEPROM_WRITE_ENABLE;
3200 writel(local, &regs->LocalCtrl);
3201 readl(&regs->LocalCtrl);
3202 udelay(ACE_LONG_DELAY);
3203 mb();
3204 local |= EEPROM_CLK_OUT;
3205 writel(local, &regs->LocalCtrl);
3206 readl(&regs->LocalCtrl);
3207 mb();
3208 udelay(ACE_SHORT_DELAY);
3209 /* sample data mid high clk */
3210 result = (result << 1) |
3211 ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3212 udelay(ACE_SHORT_DELAY);
3213 mb();
3214 local = readl(&regs->LocalCtrl);
3215 local &= ~EEPROM_CLK_OUT;
3216 writel(local, &regs->LocalCtrl);
3217 readl(&regs->LocalCtrl);
3218 udelay(ACE_SHORT_DELAY);
3219 mb();
3220 if (i == 7) {
3221 local |= EEPROM_WRITE_ENABLE;
3222 writel(local, &regs->LocalCtrl);
3223 readl(&regs->LocalCtrl);
3224 mb();
3225 udelay(ACE_SHORT_DELAY);
3226 }
3227 }
3228
3229 local |= EEPROM_DATA_OUT;
3230 writel(local, &regs->LocalCtrl);
3231 readl(&regs->LocalCtrl);
3232 mb();
3233 udelay(ACE_SHORT_DELAY);
3234 writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3235 readl(&regs->LocalCtrl);
3236 udelay(ACE_LONG_DELAY);
3237 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3238 readl(&regs->LocalCtrl);
3239 mb();
3240 udelay(ACE_SHORT_DELAY);
3241 eeprom_stop(regs);
3242
3243 local_irq_restore(flags);
3244 out:
3245 return result;
3246
3247 eeprom_read_error:
3248 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3249 ap->name, offset);
3250 goto out;
3251}
Linux 6.x block layer and io_uring tree(s)