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ARM: S5PC100: gpio.h cleanup
[linux-2.6-block.git] / drivers / net / acenic.c
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1da177e4
LT		 1/*
2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
3 * and other Tigon based cards.
4 *
5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
6 *
7 * Thanks to Alteon and 3Com for providing hardware and documentation
8 * enabling me to write this driver.
9 *
10 * A mailing list for discussing the use of this driver has been
11 * setup, please subscribe to the lists if you have any questions
12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
13 * see how to subscribe.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * Additional credits:
21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
22 * dump support. The trace dump support has not been
23 * integrated yet however.
24 * Troy Benjegerdes: Big Endian (PPC) patches.
25 * Nate Stahl: Better out of memory handling and stats support.
26 * Aman Singla: Nasty race between interrupt handler and tx code dealing
27 * with 'testing the tx_ret_csm and setting tx_full'
28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
29 * infrastructure and Sparc support
30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
31 * driver under Linux/Sparc64
32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
33 * ETHTOOL_GDRVINFO support
34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
35 * handler and close() cleanup.
36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
37 * memory mapped IO is enabled to
38 * make the driver work on RS/6000.
39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
40 * where the driver would disable
41 * bus master mode if it had to disable
42 * write and invalidate.
43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
44 * endian systems.
45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
46 * rx producer index when
47 * flushing the Jumbo ring.
48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
49 * driver init path.
50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
51 */
52
1da177e4
LT		 53#include <linux/module.h>
54#include <linux/moduleparam.h>
1da177e4
LT		 55#include <linux/types.h>
56#include <linux/errno.h>
57#include <linux/ioport.h>
58#include <linux/pci.h>
1e7f0bd8 59#include <linux/dma-mapping.h>
1da177e4
LT		 60#include <linux/kernel.h>
61#include <linux/netdevice.h>
62#include <linux/etherdevice.h>
63#include <linux/skbuff.h>
64#include <linux/init.h>
65#include <linux/delay.h>
66#include <linux/mm.h>
67#include <linux/highmem.h>
68#include <linux/sockios.h>
949b4254 69#include <linux/firmware.h>
5a0e3ad6 70#include <linux/slab.h>
1da177e4
LT		 71
72#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
73#include <linux/if_vlan.h>
74#endif
75
76#ifdef SIOCETHTOOL
77#include <linux/ethtool.h>
78#endif
79
80#include <net/sock.h>
81#include <net/ip.h>
82
83#include <asm/system.h>
84#include <asm/io.h>
85#include <asm/irq.h>
86#include <asm/byteorder.h>
87#include <asm/uaccess.h>
88
89
90#define DRV_NAME "acenic"
91
92#undef INDEX_DEBUG
93
94#ifdef CONFIG_ACENIC_OMIT_TIGON_I
95#define ACE_IS_TIGON_I(ap) 0
96#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
97#else
98#define ACE_IS_TIGON_I(ap) (ap->version == 1)
99#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
100#endif
101
102#ifndef PCI_VENDOR_ID_ALTEON
6aa20a22 103#define PCI_VENDOR_ID_ALTEON 0x12ae
1da177e4
LT		 104#endif
105#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
106#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
107#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
108#endif
109#ifndef PCI_DEVICE_ID_3COM_3C985
110#define PCI_DEVICE_ID_3COM_3C985 0x0001
111#endif
112#ifndef PCI_VENDOR_ID_NETGEAR
113#define PCI_VENDOR_ID_NETGEAR 0x1385
114#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
115#endif
116#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
117#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
118#endif
119
120
121/*
122 * Farallon used the DEC vendor ID by mistake and they seem not
123 * to care - stinky!
124 */
125#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
126#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
127#endif
128#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
129#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
130#endif
131#ifndef PCI_VENDOR_ID_SGI
132#define PCI_VENDOR_ID_SGI 0x10a9
133#endif
134#ifndef PCI_DEVICE_ID_SGI_ACENIC
135#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
136#endif
137
a3aa1884 138static DEFINE_PCI_DEVICE_TABLE(acenic_pci_tbl) = {
1da177e4
LT		 139 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
140 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
141 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
142 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
143 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
144 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
145 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
146 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
147 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
148 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
149 /*
150 * Farallon used the DEC vendor ID on their cards incorrectly,
151 * then later Alteon's ID.
152 */
153 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
154 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
155 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
156 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
157 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
158 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
159 { }
160};
161MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
162
1da177e4 163#define ace_sync_irq(irq) synchronize_irq(irq)
1da177e4
LT		 164
165#ifndef offset_in_page
166#define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
167#endif
168
169#define ACE_MAX_MOD_PARMS 8
170#define BOARD_IDX_STATIC 0
171#define BOARD_IDX_OVERFLOW -1
172
173#if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
174 defined(NETIF_F_HW_VLAN_RX)
175#define ACENIC_DO_VLAN 1
176#define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
177#else
178#define ACENIC_DO_VLAN 0
179#define ACE_RCB_VLAN_FLAG 0
180#endif
181
182#include "acenic.h"
183
184/*
185 * These must be defined before the firmware is included.
186 */
187#define MAX_TEXT_LEN 96*1024
188#define MAX_RODATA_LEN 8*1024
189#define MAX_DATA_LEN 2*1024
190
1da177e4
LT		 191#ifndef tigon2FwReleaseLocal
192#define tigon2FwReleaseLocal 0
193#endif
194
195/*
196 * This driver currently supports Tigon I and Tigon II based cards
197 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
198 * GA620. The driver should also work on the SGI, DEC and Farallon
199 * versions of the card, however I have not been able to test that
200 * myself.
201 *
202 * This card is really neat, it supports receive hardware checksumming
203 * and jumbo frames (up to 9000 bytes) and does a lot of work in the
204 * firmware. Also the programming interface is quite neat, except for
205 * the parts dealing with the i2c eeprom on the card ;-)
206 *
207 * Using jumbo frames:
208 *
209 * To enable jumbo frames, simply specify an mtu between 1500 and 9000
210 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
211 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
212 * interface number and <MTU> being the MTU value.
213 *
214 * Module parameters:
215 *
216 * When compiled as a loadable module, the driver allows for a number
217 * of module parameters to be specified. The driver supports the
218 * following module parameters:
219 *
220 * trace=<val> - Firmware trace level. This requires special traced
221 * firmware to replace the firmware supplied with
222 * the driver - for debugging purposes only.
223 *
224 * link=<val> - Link state. Normally you want to use the default link
225 * parameters set by the driver. This can be used to
226 * override these in case your switch doesn't negotiate
227 * the link properly. Valid values are:
228 * 0x0001 - Force half duplex link.
229 * 0x0002 - Do not negotiate line speed with the other end.
230 * 0x0010 - 10Mbit/sec link.
231 * 0x0020 - 100Mbit/sec link.
232 * 0x0040 - 1000Mbit/sec link.
233 * 0x0100 - Do not negotiate flow control.
234 * 0x0200 - Enable RX flow control Y
235 * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
236 * Default value is 0x0270, ie. enable link+flow
237 * control negotiation. Negotiating the highest
238 * possible link speed with RX flow control enabled.
239 *
240 * When disabling link speed negotiation, only one link
241 * speed is allowed to be specified!
242 *
243 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
244 * to wait for more packets to arive before
245 * interrupting the host, from the time the first
246 * packet arrives.
247 *
248 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
249 * to wait for more packets to arive in the transmit ring,
250 * before interrupting the host, after transmitting the
251 * first packet in the ring.
252 *
253 * max_tx_desc=<val> - maximum number of transmit descriptors
254 * (packets) transmitted before interrupting the host.
255 *
256 * max_rx_desc=<val> - maximum number of receive descriptors
257 * (packets) received before interrupting the host.
258 *
259 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
260 * increments of the NIC's on board memory to be used for
261 * transmit and receive buffers. For the 1MB NIC app. 800KB
262 * is available, on the 1/2MB NIC app. 300KB is available.
263 * 68KB will always be available as a minimum for both
264 * directions. The default value is a 50/50 split.
265 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
266 * operations, default (1) is to always disable this as
267 * that is what Alteon does on NT. I have not been able
268 * to measure any real performance differences with
269 * this on my systems. Set <val>=0 if you want to
270 * enable these operations.
271 *
272 * If you use more than one NIC, specify the parameters for the
273 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
274 * run tracing on NIC #2 but not on NIC #1 and #3.
275 *
276 * TODO:
277 *
278 * - Proper multicast support.
279 * - NIC dump support.
280 * - More tuning parameters.
281 *
282 * The mini ring is not used under Linux and I am not sure it makes sense
283 * to actually use it.
284 *
285 * New interrupt handler strategy:
286 *
287 * The old interrupt handler worked using the traditional method of
288 * replacing an skbuff with a new one when a packet arrives. However
289 * the rx rings do not need to contain a static number of buffer
290 * descriptors, thus it makes sense to move the memory allocation out
291 * of the main interrupt handler and do it in a bottom half handler
292 * and only allocate new buffers when the number of buffers in the
293 * ring is below a certain threshold. In order to avoid starving the
294 * NIC under heavy load it is however necessary to force allocation
295 * when hitting a minimum threshold. The strategy for alloction is as
296 * follows:
297 *
298 * RX_LOW_BUF_THRES - allocate buffers in the bottom half
299 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
300 * the buffers in the interrupt handler
301 * RX_RING_THRES - maximum number of buffers in the rx ring
302 * RX_MINI_THRES - maximum number of buffers in the mini ring
303 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
304 *
305 * One advantagous side effect of this allocation approach is that the
306 * entire rx processing can be done without holding any spin lock
307 * since the rx rings and registers are totally independent of the tx
308 * ring and its registers. This of course includes the kmalloc's of
309 * new skb's. Thus start_xmit can run in parallel with rx processing
310 * and the memory allocation on SMP systems.
311 *
312 * Note that running the skb reallocation in a bottom half opens up
313 * another can of races which needs to be handled properly. In
314 * particular it can happen that the interrupt handler tries to run
315 * the reallocation while the bottom half is either running on another
316 * CPU or was interrupted on the same CPU. To get around this the
317 * driver uses bitops to prevent the reallocation routines from being
318 * reentered.
319 *
320 * TX handling can also be done without holding any spin lock, wheee
321 * this is fun! since tx_ret_csm is only written to by the interrupt
322 * handler. The case to be aware of is when shutting down the device
323 * and cleaning up where it is necessary to make sure that
324 * start_xmit() is not running while this is happening. Well DaveM
325 * informs me that this case is already protected against ... bye bye
326 * Mr. Spin Lock, it was nice to know you.
327 *
328 * TX interrupts are now partly disabled so the NIC will only generate
329 * TX interrupts for the number of coal ticks, not for the number of
330 * TX packets in the queue. This should reduce the number of TX only,
331 * ie. when no RX processing is done, interrupts seen.
332 */
333
334/*
335 * Threshold values for RX buffer allocation - the low water marks for
336 * when to start refilling the rings are set to 75% of the ring
337 * sizes. It seems to make sense to refill the rings entirely from the
338 * intrrupt handler once it gets below the panic threshold, that way
339 * we don't risk that the refilling is moved to another CPU when the
340 * one running the interrupt handler just got the slab code hot in its
341 * cache.
342 */
343#define RX_RING_SIZE 72
344#define RX_MINI_SIZE 64
345#define RX_JUMBO_SIZE 48
346
347#define RX_PANIC_STD_THRES 16
348#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
349#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
350#define RX_PANIC_MINI_THRES 12
351#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
352#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
353#define RX_PANIC_JUMBO_THRES 6
354#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
355#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
356
357
358/*
359 * Size of the mini ring entries, basically these just should be big
360 * enough to take TCP ACKs
361 */
362#define ACE_MINI_SIZE 100
363
364#define ACE_MINI_BUFSIZE ACE_MINI_SIZE
365#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
366#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
367
368/*
369 * There seems to be a magic difference in the effect between 995 and 996
370 * but little difference between 900 and 995 ... no idea why.
371 *
372 * There is now a default set of tuning parameters which is set, depending
373 * on whether or not the user enables Jumbo frames. It's assumed that if
374 * Jumbo frames are enabled, the user wants optimal tuning for that case.
375 */
376#define DEF_TX_COAL 400 /* 996 */
377#define DEF_TX_MAX_DESC 60 /* was 40 */
378#define DEF_RX_COAL 120 /* 1000 */
379#define DEF_RX_MAX_DESC 25
380#define DEF_TX_RATIO 21 /* 24 */
381
382#define DEF_JUMBO_TX_COAL 20
383#define DEF_JUMBO_TX_MAX_DESC 60
384#define DEF_JUMBO_RX_COAL 30
385#define DEF_JUMBO_RX_MAX_DESC 6
386#define DEF_JUMBO_TX_RATIO 21
387
388#if tigon2FwReleaseLocal < 20001118
389/*
390 * Standard firmware and early modifications duplicate
391 * IRQ load without this flag (coal timer is never reset).
392 * Note that with this flag tx_coal should be less than
393 * time to xmit full tx ring.
394 * 400usec is not so bad for tx ring size of 128.
395 */
396#define TX_COAL_INTS_ONLY 1 /* worth it */
397#else
398/*
399 * With modified firmware, this is not necessary, but still useful.
400 */
401#define TX_COAL_INTS_ONLY 1
402#endif
403
404#define DEF_TRACE 0
405#define DEF_STAT (2 * TICKS_PER_SEC)
406
407
ddfce6bb 408static int link_state[ACE_MAX_MOD_PARMS];
1da177e4
LT		 409static int trace[ACE_MAX_MOD_PARMS];
410static int tx_coal_tick[ACE_MAX_MOD_PARMS];
411static int rx_coal_tick[ACE_MAX_MOD_PARMS];
412static int max_tx_desc[ACE_MAX_MOD_PARMS];
413static int max_rx_desc[ACE_MAX_MOD_PARMS];
414static int tx_ratio[ACE_MAX_MOD_PARMS];
415static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
416
417MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
418MODULE_LICENSE("GPL");
419MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
949b4254
JS		 420#ifndef CONFIG_ACENIC_OMIT_TIGON_I
421MODULE_FIRMWARE("acenic/tg1.bin");
422#endif
423MODULE_FIRMWARE("acenic/tg2.bin");
1da177e4 424
ddfce6bb 425module_param_array_named(link, link_state, int, NULL, 0);
1da177e4
LT		 426module_param_array(trace, int, NULL, 0);
427module_param_array(tx_coal_tick, int, NULL, 0);
428module_param_array(max_tx_desc, int, NULL, 0);
429module_param_array(rx_coal_tick, int, NULL, 0);
430module_param_array(max_rx_desc, int, NULL, 0);
431module_param_array(tx_ratio, int, NULL, 0);
432MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
433MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
434MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
435MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
436MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
437MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
438MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
439
440
da38075c 441static const char version[] __devinitconst =
1da177e4
LT		 442 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
443 " http://home.cern.ch/~jes/gige/acenic.html\n";
444
445static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
446static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
447static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
448
7282d491 449static const struct ethtool_ops ace_ethtool_ops = {
1da177e4
LT		 450 .get_settings = ace_get_settings,
451 .set_settings = ace_set_settings,
452 .get_drvinfo = ace_get_drvinfo,
453};
454
455static void ace_watchdog(struct net_device *dev);
456
d8b83c57
SH		 457static const struct net_device_ops ace_netdev_ops = {
458 .ndo_open = ace_open,
459 .ndo_stop = ace_close,
460 .ndo_tx_timeout = ace_watchdog,
461 .ndo_get_stats = ace_get_stats,
00829823 462 .ndo_start_xmit = ace_start_xmit,
d8b83c57 463 .ndo_set_multicast_list = ace_set_multicast_list,
52255bbe 464 .ndo_validate_addr = eth_validate_addr,
d8b83c57
SH		 465 .ndo_set_mac_address = ace_set_mac_addr,
466 .ndo_change_mtu = ace_change_mtu,
00829823 467#if ACENIC_DO_VLAN
d8b83c57 468 .ndo_vlan_rx_register = ace_vlan_rx_register,
00829823 469#endif
d8b83c57
SH		 470};
471
1da177e4
LT		 472static int __devinit acenic_probe_one(struct pci_dev *pdev,
473 const struct pci_device_id *id)
474{
475 struct net_device *dev;
476 struct ace_private *ap;
477 static int boards_found;
478
479 dev = alloc_etherdev(sizeof(struct ace_private));
480 if (dev == NULL) {
481 printk(KERN_ERR "acenic: Unable to allocate "
482 "net_device structure!\n");
483 return -ENOMEM;
484 }
485
1da177e4
LT		 486 SET_NETDEV_DEV(dev, &pdev->dev);
487
454d7c9b 488 ap = netdev_priv(dev);
1da177e4
LT		 489 ap->pdev = pdev;
490 ap->name = pci_name(pdev);
491
492 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
493#if ACENIC_DO_VLAN
494 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 495#endif
25805dcf 496
25805dcf 497 dev->watchdog_timeo = 5*HZ;
1da177e4 498
d8b83c57 499 dev->netdev_ops = &ace_netdev_ops;
1da177e4 500 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
1da177e4
LT		 501
502 /* we only display this string ONCE */
503 if (!boards_found)
504 printk(version);
505
506 if (pci_enable_device(pdev))
507 goto fail_free_netdev;
508
509 /*
510 * Enable master mode before we start playing with the
511 * pci_command word since pci_set_master() will modify
512 * it.
513 */
514 pci_set_master(pdev);
515
516 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
517
6aa20a22 518 /* OpenFirmware on Mac's does not set this - DOH.. */
1da177e4
LT		 519 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
520 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
521 "access - was not enabled by BIOS/Firmware\n",
522 ap->name);
523 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
524 pci_write_config_word(ap->pdev, PCI_COMMAND,
525 ap->pci_command);
526 wmb();
527 }
528
529 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
530 if (ap->pci_latency <= 0x40) {
531 ap->pci_latency = 0x40;
532 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
533 }
534
535 /*
536 * Remap the regs into kernel space - this is abuse of
537 * dev->base_addr since it was means for I/O port
538 * addresses but who gives a damn.
539 */
540 dev->base_addr = pci_resource_start(pdev, 0);
541 ap->regs = ioremap(dev->base_addr, 0x4000);
542 if (!ap->regs) {
543 printk(KERN_ERR "%s: Unable to map I/O register, "
544 "AceNIC %i will be disabled.\n",
545 ap->name, boards_found);
546 goto fail_free_netdev;
547 }
548
549 switch(pdev->vendor) {
550 case PCI_VENDOR_ID_ALTEON:
551 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
552 printk(KERN_INFO "%s: Farallon PN9100-T ",
553 ap->name);
554 } else {
555 printk(KERN_INFO "%s: Alteon AceNIC ",
556 ap->name);
557 }
558 break;
559 case PCI_VENDOR_ID_3COM:
560 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
561 break;
562 case PCI_VENDOR_ID_NETGEAR:
563 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
564 break;
565 case PCI_VENDOR_ID_DEC:
566 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
567 printk(KERN_INFO "%s: Farallon PN9000-SX ",
568 ap->name);
569 break;
570 }
571 case PCI_VENDOR_ID_SGI:
572 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
573 break;
574 default:
575 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
576 break;
577 }
578
579 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
c6387a48 580 printk("irq %d\n", pdev->irq);
1da177e4
LT		 581
582#ifdef CONFIG_ACENIC_OMIT_TIGON_I
583 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
584 printk(KERN_ERR "%s: Driver compiled without Tigon I"
585 " support - NIC disabled\n", dev->name);
586 goto fail_uninit;
587 }
588#endif
589
590 if (ace_allocate_descriptors(dev))
591 goto fail_free_netdev;
592
593#ifdef MODULE
594 if (boards_found >= ACE_MAX_MOD_PARMS)
595 ap->board_idx = BOARD_IDX_OVERFLOW;
596 else
597 ap->board_idx = boards_found;
598#else
599 ap->board_idx = BOARD_IDX_STATIC;
600#endif
601
602 if (ace_init(dev))
603 goto fail_free_netdev;
604
605 if (register_netdev(dev)) {
606 printk(KERN_ERR "acenic: device registration failed\n");
607 goto fail_uninit;
608 }
609 ap->name = dev->name;
610
611 if (ap->pci_using_dac)
612 dev->features |= NETIF_F_HIGHDMA;
613
614 pci_set_drvdata(pdev, dev);
615
616 boards_found++;
617 return 0;
618
619 fail_uninit:
620 ace_init_cleanup(dev);
621 fail_free_netdev:
622 free_netdev(dev);
623 return -ENODEV;
624}
625
626static void __devexit acenic_remove_one(struct pci_dev *pdev)
627{
628 struct net_device *dev = pci_get_drvdata(pdev);
629 struct ace_private *ap = netdev_priv(dev);
630 struct ace_regs __iomem *regs = ap->regs;
631 short i;
632
633 unregister_netdev(dev);
634
635 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
636 if (ap->version >= 2)
637 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
6aa20a22 638
1da177e4
LT		 639 /*
640 * This clears any pending interrupts
641 */
642 writel(1, &regs->Mb0Lo);
643 readl(&regs->CpuCtrl); /* flush */
644
645 /*
646 * Make sure no other CPUs are processing interrupts
647 * on the card before the buffers are being released.
648 * Otherwise one might experience some `interesting'
649 * effects.
650 *
651 * Then release the RX buffers - jumbo buffers were
652 * already released in ace_close().
653 */
654 ace_sync_irq(dev->irq);
655
656 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
657 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
658
659 if (skb) {
660 struct ring_info *ringp;
661 dma_addr_t mapping;
662
663 ringp = &ap->skb->rx_std_skbuff[i];
664 mapping = pci_unmap_addr(ringp, mapping);
665 pci_unmap_page(ap->pdev, mapping,
666 ACE_STD_BUFSIZE,
667 PCI_DMA_FROMDEVICE);
668
669 ap->rx_std_ring[i].size = 0;
670 ap->skb->rx_std_skbuff[i].skb = NULL;
671 dev_kfree_skb(skb);
672 }
673 }
674
675 if (ap->version >= 2) {
676 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
677 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
678
679 if (skb) {
680 struct ring_info *ringp;
681 dma_addr_t mapping;
682
683 ringp = &ap->skb->rx_mini_skbuff[i];
684 mapping = pci_unmap_addr(ringp,mapping);
685 pci_unmap_page(ap->pdev, mapping,
686 ACE_MINI_BUFSIZE,
687 PCI_DMA_FROMDEVICE);
688
689 ap->rx_mini_ring[i].size = 0;
690 ap->skb->rx_mini_skbuff[i].skb = NULL;
691 dev_kfree_skb(skb);
692 }
693 }
694 }
695
696 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
697 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
698 if (skb) {
699 struct ring_info *ringp;
700 dma_addr_t mapping;
701
702 ringp = &ap->skb->rx_jumbo_skbuff[i];
703 mapping = pci_unmap_addr(ringp, mapping);
704 pci_unmap_page(ap->pdev, mapping,
705 ACE_JUMBO_BUFSIZE,
706 PCI_DMA_FROMDEVICE);
707
708 ap->rx_jumbo_ring[i].size = 0;
709 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
710 dev_kfree_skb(skb);
711 }
712 }
713
714 ace_init_cleanup(dev);
715 free_netdev(dev);
716}
717
718static struct pci_driver acenic_pci_driver = {
719 .name = "acenic",
720 .id_table = acenic_pci_tbl,
721 .probe = acenic_probe_one,
722 .remove = __devexit_p(acenic_remove_one),
723};
724
725static int __init acenic_init(void)
726{
29917620 727 return pci_register_driver(&acenic_pci_driver);
1da177e4
LT		 728}
729
730static void __exit acenic_exit(void)
731{
732 pci_unregister_driver(&acenic_pci_driver);
733}
734
735module_init(acenic_init);
736module_exit(acenic_exit);
737
738static void ace_free_descriptors(struct net_device *dev)
739{
740 struct ace_private *ap = netdev_priv(dev);
741 int size;
742
743 if (ap->rx_std_ring != NULL) {
744 size = (sizeof(struct rx_desc) *
745 (RX_STD_RING_ENTRIES +
746 RX_JUMBO_RING_ENTRIES +
747 RX_MINI_RING_ENTRIES +
748 RX_RETURN_RING_ENTRIES));
749 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
750 ap->rx_ring_base_dma);
751 ap->rx_std_ring = NULL;
752 ap->rx_jumbo_ring = NULL;
753 ap->rx_mini_ring = NULL;
754 ap->rx_return_ring = NULL;
755 }
756 if (ap->evt_ring != NULL) {
757 size = (sizeof(struct event) * EVT_RING_ENTRIES);
758 pci_free_consistent(ap->pdev, size, ap->evt_ring,
759 ap->evt_ring_dma);
760 ap->evt_ring = NULL;
761 }
762 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
763 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
764 pci_free_consistent(ap->pdev, size, ap->tx_ring,
765 ap->tx_ring_dma);
766 }
767 ap->tx_ring = NULL;
768
769 if (ap->evt_prd != NULL) {
770 pci_free_consistent(ap->pdev, sizeof(u32),
771 (void *)ap->evt_prd, ap->evt_prd_dma);
772 ap->evt_prd = NULL;
773 }
774 if (ap->rx_ret_prd != NULL) {
775 pci_free_consistent(ap->pdev, sizeof(u32),
776 (void *)ap->rx_ret_prd,
777 ap->rx_ret_prd_dma);
778 ap->rx_ret_prd = NULL;
779 }
780 if (ap->tx_csm != NULL) {
781 pci_free_consistent(ap->pdev, sizeof(u32),
782 (void *)ap->tx_csm, ap->tx_csm_dma);
783 ap->tx_csm = NULL;
784 }
785}
786
787
788static int ace_allocate_descriptors(struct net_device *dev)
789{
790 struct ace_private *ap = netdev_priv(dev);
791 int size;
792
793 size = (sizeof(struct rx_desc) *
794 (RX_STD_RING_ENTRIES +
795 RX_JUMBO_RING_ENTRIES +
796 RX_MINI_RING_ENTRIES +
797 RX_RETURN_RING_ENTRIES));
798
799 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
800 &ap->rx_ring_base_dma);
801 if (ap->rx_std_ring == NULL)
802 goto fail;
803
804 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
805 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
806 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
807
808 size = (sizeof(struct event) * EVT_RING_ENTRIES);
809
810 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
811
812 if (ap->evt_ring == NULL)
813 goto fail;
814
815 /*
816 * Only allocate a host TX ring for the Tigon II, the Tigon I
817 * has to use PCI registers for this ;-(
818 */
819 if (!ACE_IS_TIGON_I(ap)) {
820 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
821
822 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
823 &ap->tx_ring_dma);
824
825 if (ap->tx_ring == NULL)
826 goto fail;
827 }
828
829 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
830 &ap->evt_prd_dma);
831 if (ap->evt_prd == NULL)
832 goto fail;
833
834 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
835 &ap->rx_ret_prd_dma);
836 if (ap->rx_ret_prd == NULL)
837 goto fail;
838
839 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
840 &ap->tx_csm_dma);
841 if (ap->tx_csm == NULL)
842 goto fail;
843
844 return 0;
845
846fail:
847 /* Clean up. */
848 ace_init_cleanup(dev);
849 return 1;
850}
851
852
853/*
854 * Generic cleanup handling data allocated during init. Used when the
855 * module is unloaded or if an error occurs during initialization
856 */
857static void ace_init_cleanup(struct net_device *dev)
858{
859 struct ace_private *ap;
860
861 ap = netdev_priv(dev);
862
863 ace_free_descriptors(dev);
864
865 if (ap->info)
866 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
867 ap->info, ap->info_dma);
b4558ea9
JJ		 868 kfree(ap->skb);
869 kfree(ap->trace_buf);
1da177e4
LT		 870
871 if (dev->irq)
872 free_irq(dev->irq, dev);
873
874 iounmap(ap->regs);
875}
876
877
878/*
879 * Commands are considered to be slow.
880 */
881static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
882{
883 u32 idx;
884
885 idx = readl(&regs->CmdPrd);
886
887 writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
888 idx = (idx + 1) % CMD_RING_ENTRIES;
889
890 writel(idx, &regs->CmdPrd);
891}
892
893
894static int __devinit ace_init(struct net_device *dev)
895{
896 struct ace_private *ap;
897 struct ace_regs __iomem *regs;
898 struct ace_info *info = NULL;
899 struct pci_dev *pdev;
900 unsigned long myjif;
901 u64 tmp_ptr;
902 u32 tig_ver, mac1, mac2, tmp, pci_state;
903 int board_idx, ecode = 0;
904 short i;
905 unsigned char cache_size;
906
907 ap = netdev_priv(dev);
908 regs = ap->regs;
909
910 board_idx = ap->board_idx;
911
912 /*
913 * aman@sgi.com - its useful to do a NIC reset here to
914 * address the `Firmware not running' problem subsequent
915 * to any crashes involving the NIC
916 */
917 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
918 readl(&regs->HostCtrl); /* PCI write posting */
919 udelay(5);
920
921 /*
922 * Don't access any other registers before this point!
923 */
924#ifdef __BIG_ENDIAN
925 /*
926 * This will most likely need BYTE_SWAP once we switch
927 * to using __raw_writel()
928 */
929 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
930 &regs->HostCtrl);
931#else
932 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
933 &regs->HostCtrl);
934#endif
935 readl(&regs->HostCtrl); /* PCI write posting */
936
937 /*
938 * Stop the NIC CPU and clear pending interrupts
939 */
940 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
941 readl(&regs->CpuCtrl); /* PCI write posting */
942 writel(0, &regs->Mb0Lo);
943
944 tig_ver = readl(&regs->HostCtrl) >> 28;
945
946 switch(tig_ver){
947#ifndef CONFIG_ACENIC_OMIT_TIGON_I
948 case 4:
949 case 5:
950 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
949b4254
JS		 951 tig_ver, ap->firmware_major, ap->firmware_minor,
952 ap->firmware_fix);
1da177e4
LT		 953 writel(0, &regs->LocalCtrl);
954 ap->version = 1;
955 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
956 break;
957#endif
958 case 6:
959 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
949b4254
JS		 960 tig_ver, ap->firmware_major, ap->firmware_minor,
961 ap->firmware_fix);
1da177e4
LT		 962 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
963 readl(&regs->CpuBCtrl); /* PCI write posting */
964 /*
965 * The SRAM bank size does _not_ indicate the amount
966 * of memory on the card, it controls the _bank_ size!
967 * Ie. a 1MB AceNIC will have two banks of 512KB.
968 */
969 writel(SRAM_BANK_512K, &regs->LocalCtrl);
970 writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
971 ap->version = 2;
972 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
973 break;
974 default:
975 printk(KERN_WARNING " Unsupported Tigon version detected "
976 "(%i)\n", tig_ver);
977 ecode = -ENODEV;
978 goto init_error;
979 }
980
981 /*
982 * ModeStat _must_ be set after the SRAM settings as this change
983 * seems to corrupt the ModeStat and possible other registers.
984 * The SRAM settings survive resets and setting it to the same
985 * value a second time works as well. This is what caused the
986 * `Firmware not running' problem on the Tigon II.
987 */
988#ifdef __BIG_ENDIAN
989 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
990 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
991#else
992 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
993 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
994#endif
995 readl(&regs->ModeStat); /* PCI write posting */
996
997 mac1 = 0;
998 for(i = 0; i < 4; i++) {
ddfce6bb 999 int t;
6f9d4722 1000
1da177e4 1001 mac1 = mac1 << 8;
ddfce6bb
SH		 1002 t = read_eeprom_byte(dev, 0x8c+i);
1003 if (t < 0) {
1da177e4
LT		 1004 ecode = -EIO;
1005 goto init_error;
1006 } else
ddfce6bb 1007 mac1 |= (t & 0xff);
1da177e4
LT		 1008 }
1009 mac2 = 0;
1010 for(i = 4; i < 8; i++) {
ddfce6bb 1011 int t;
6f9d4722 1012
1da177e4 1013 mac2 = mac2 << 8;
ddfce6bb
SH		 1014 t = read_eeprom_byte(dev, 0x8c+i);
1015 if (t < 0) {
1da177e4
LT		 1016 ecode = -EIO;
1017 goto init_error;
1018 } else
ddfce6bb 1019 mac2 |= (t & 0xff);
1da177e4
LT		 1020 }
1021
1022 writel(mac1, &regs->MacAddrHi);
1023 writel(mac2, &regs->MacAddrLo);
1024
1da177e4
LT		 1025 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1026 dev->dev_addr[1] = mac1 & 0xff;
1027 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1028 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1029 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1030 dev->dev_addr[5] = mac2 & 0xff;
1031
e174961c 1032 printk("MAC: %pM\n", dev->dev_addr);
0795af57 1033
1da177e4
LT		 1034 /*
1035 * Looks like this is necessary to deal with on all architectures,
1036 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1037 * Ie. having two NICs in the machine, one will have the cache
1038 * line set at boot time, the other will not.
1039 */
1040 pdev = ap->pdev;
1041 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1042 cache_size <<= 2;
1043 if (cache_size != SMP_CACHE_BYTES) {
1044 printk(KERN_INFO " PCI cache line size set incorrectly "
1045 "(%i bytes) by BIOS/FW, ", cache_size);
1046 if (cache_size > SMP_CACHE_BYTES)
1047 printk("expecting %i\n", SMP_CACHE_BYTES);
1048 else {
1049 printk("correcting to %i\n", SMP_CACHE_BYTES);
1050 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1051 SMP_CACHE_BYTES >> 2);
1052 }
1053 }
1054
1055 pci_state = readl(&regs->PciState);
1056 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1057 "latency: %i clks\n",
1058 (pci_state & PCI_32BIT) ? 32 : 64,
6aa20a22 1059 (pci_state & PCI_66MHZ) ? 66 : 33,
1da177e4
LT		 1060 ap->pci_latency);
1061
1062 /*
1063 * Set the max DMA transfer size. Seems that for most systems
1064 * the performance is better when no MAX parameter is
1065 * set. However for systems enabling PCI write and invalidate,
1066 * DMA writes must be set to the L1 cache line size to get
1067 * optimal performance.
1068 *
1069 * The default is now to turn the PCI write and invalidate off
1070 * - that is what Alteon does for NT.
1071 */
1072 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1073 if (ap->version >= 2) {
1074 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1075 /*
1076 * Tuning parameters only supported for 8 cards
1077 */
1078 if (board_idx == BOARD_IDX_OVERFLOW ||
1079 dis_pci_mem_inval[board_idx]) {
1080 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1081 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1082 pci_write_config_word(pdev, PCI_COMMAND,
1083 ap->pci_command);
1084 printk(KERN_INFO " Disabling PCI memory "
1085 "write and invalidate\n");
1086 }
1087 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1088 printk(KERN_INFO " PCI memory write & invalidate "
1089 "enabled by BIOS, enabling counter measures\n");
1090
1091 switch(SMP_CACHE_BYTES) {
1092 case 16:
1093 tmp |= DMA_WRITE_MAX_16;
1094 break;
1095 case 32:
1096 tmp |= DMA_WRITE_MAX_32;
1097 break;
1098 case 64:
1099 tmp |= DMA_WRITE_MAX_64;
1100 break;
1101 case 128:
1102 tmp |= DMA_WRITE_MAX_128;
1103 break;
1104 default:
1105 printk(KERN_INFO " Cache line size %i not "
1106 "supported, PCI write and invalidate "
1107 "disabled\n", SMP_CACHE_BYTES);
1108 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1109 pci_write_config_word(pdev, PCI_COMMAND,
1110 ap->pci_command);
1111 }
1112 }
1113 }
1114
1115#ifdef __sparc__
1116 /*
1117 * On this platform, we know what the best dma settings
1118 * are. We use 64-byte maximum bursts, because if we
1119 * burst larger than the cache line size (or even cross
1120 * a 64byte boundary in a single burst) the UltraSparc
1121 * PCI controller will disconnect at 64-byte multiples.
1122 *
1123 * Read-multiple will be properly enabled above, and when
1124 * set will give the PCI controller proper hints about
1125 * prefetching.
1126 */
1127 tmp &= ~DMA_READ_WRITE_MASK;
1128 tmp |= DMA_READ_MAX_64;
1129 tmp |= DMA_WRITE_MAX_64;
1130#endif
1131#ifdef __alpha__
1132 tmp &= ~DMA_READ_WRITE_MASK;
1133 tmp |= DMA_READ_MAX_128;
1134 /*
1135 * All the docs say MUST NOT. Well, I did.
1136 * Nothing terrible happens, if we load wrong size.
1137 * Bit w&i still works better!
1138 */
1139 tmp |= DMA_WRITE_MAX_128;
1140#endif
1141 writel(tmp, &regs->PciState);
1142
1143#if 0
1144 /*
1145 * The Host PCI bus controller driver has to set FBB.
1146 * If all devices on that PCI bus support FBB, then the controller
1147 * can enable FBB support in the Host PCI Bus controller (or on
1148 * the PCI-PCI bridge if that applies).
1149 * -ggg
1150 */
1151 /*
1152 * I have received reports from people having problems when this
1153 * bit is enabled.
1154 */
1155 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1156 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1157 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1158 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1159 }
1160#endif
6aa20a22 1161
1da177e4
LT		 1162 /*
1163 * Configure DMA attributes.
1164 */
6a35528a 1165 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 1166 ap->pci_using_dac = 1;
284901a9 1167 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 1168 ap->pci_using_dac = 0;
1169 } else {
1170 ecode = -ENODEV;
1171 goto init_error;
1172 }
1173
1174 /*
1175 * Initialize the generic info block and the command+event rings
1176 * and the control blocks for the transmit and receive rings
1177 * as they need to be setup once and for all.
1178 */
1179 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1180 &ap->info_dma))) {
1181 ecode = -EAGAIN;
1182 goto init_error;
1183 }
1184 ap->info = info;
1185
1186 /*
1187 * Get the memory for the skb rings.
1188 */
1189 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1190 ecode = -EAGAIN;
1191 goto init_error;
1192 }
1193
1fb9df5d 1194 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1da177e4
LT		 1195 DRV_NAME, dev);
1196 if (ecode) {
1197 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1198 DRV_NAME, pdev->irq);
1199 goto init_error;
1200 } else
1201 dev->irq = pdev->irq;
1202
1203#ifdef INDEX_DEBUG
1204 spin_lock_init(&ap->debug_lock);
1205 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1206 ap->last_std_rx = 0;
1207 ap->last_mini_rx = 0;
1208#endif
1209
1210 memset(ap->info, 0, sizeof(struct ace_info));
1211 memset(ap->skb, 0, sizeof(struct ace_skb));
1212
6c60e0c3
BH		 1213 ecode = ace_load_firmware(dev);
1214 if (ecode)
949b4254
JS		 1215 goto init_error;
1216
1da177e4
LT		 1217 ap->fw_running = 0;
1218
1219 tmp_ptr = ap->info_dma;
1220 writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1221 writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1222
1223 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1224
1225 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1226 info->evt_ctrl.flags = 0;
1227
1228 *(ap->evt_prd) = 0;
1229 wmb();
1230 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1231 writel(0, &regs->EvtCsm);
1232
1233 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1234 info->cmd_ctrl.flags = 0;
1235 info->cmd_ctrl.max_len = 0;
1236
1237 for (i = 0; i < CMD_RING_ENTRIES; i++)
1238 writel(0, &regs->CmdRng[i]);
1239
1240 writel(0, &regs->CmdPrd);
1241 writel(0, &regs->CmdCsm);
1242
1243 tmp_ptr = ap->info_dma;
1244 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1245 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1246
1247 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1248 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1249 info->rx_std_ctrl.flags =
1250 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1251
1252 memset(ap->rx_std_ring, 0,
1253 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1254
1255 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1256 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1257
1258 ap->rx_std_skbprd = 0;
1259 atomic_set(&ap->cur_rx_bufs, 0);
1260
1261 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1262 (ap->rx_ring_base_dma +
1263 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1264 info->rx_jumbo_ctrl.max_len = 0;
1265 info->rx_jumbo_ctrl.flags =
1266 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1267
1268 memset(ap->rx_jumbo_ring, 0,
1269 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1270
1271 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1272 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1273
1274 ap->rx_jumbo_skbprd = 0;
1275 atomic_set(&ap->cur_jumbo_bufs, 0);
1276
1277 memset(ap->rx_mini_ring, 0,
1278 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1279
1280 if (ap->version >= 2) {
1281 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1282 (ap->rx_ring_base_dma +
1283 (sizeof(struct rx_desc) *
1284 (RX_STD_RING_ENTRIES +
1285 RX_JUMBO_RING_ENTRIES))));
1286 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
6aa20a22 1287 info->rx_mini_ctrl.flags =
1da177e4
LT		 1288 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
1289
1290 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1291 ap->rx_mini_ring[i].flags =
1292 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1293 } else {
1294 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1295 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1296 info->rx_mini_ctrl.max_len = 0;
1297 }
1298
1299 ap->rx_mini_skbprd = 0;
1300 atomic_set(&ap->cur_mini_bufs, 0);
1301
1302 set_aceaddr(&info->rx_return_ctrl.rngptr,
1303 (ap->rx_ring_base_dma +
1304 (sizeof(struct rx_desc) *
1305 (RX_STD_RING_ENTRIES +
1306 RX_JUMBO_RING_ENTRIES +
1307 RX_MINI_RING_ENTRIES))));
1308 info->rx_return_ctrl.flags = 0;
1309 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1310
1311 memset(ap->rx_return_ring, 0,
1312 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1313
1314 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1315 *(ap->rx_ret_prd) = 0;
1316
1317 writel(TX_RING_BASE, &regs->WinBase);
1318
1319 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 1320 ap->tx_ring = (__force struct tx_desc *) regs->Window;
6aa20a22 1321 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1da177e4 1322 * sizeof(struct tx_desc)) / sizeof(u32); i++)
ddfce6bb 1323 writel(0, (__force void __iomem *)ap->tx_ring + i * 4);
1da177e4
LT		 1324
1325 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1326 } else {
1327 memset(ap->tx_ring, 0,
1328 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1329
1330 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1331 }
1332
1333 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1334 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1335
1336 /*
1337 * The Tigon I does not like having the TX ring in host memory ;-(
1338 */
1339 if (!ACE_IS_TIGON_I(ap))
1340 tmp |= RCB_FLG_TX_HOST_RING;
1341#if TX_COAL_INTS_ONLY
1342 tmp |= RCB_FLG_COAL_INT_ONLY;
1343#endif
1344 info->tx_ctrl.flags = tmp;
1345
1346 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1347
1348 /*
1349 * Potential item for tuning parameter
1350 */
1351#if 0 /* NO */
1352 writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1353 writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1354#else
1355 writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1356 writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1357#endif
1358
1359 writel(0, &regs->MaskInt);
1360 writel(1, &regs->IfIdx);
1361#if 0
1362 /*
1363 * McKinley boxes do not like us fiddling with AssistState
1364 * this early
1365 */
1366 writel(1, &regs->AssistState);
1367#endif
1368
1369 writel(DEF_STAT, &regs->TuneStatTicks);
1370 writel(DEF_TRACE, &regs->TuneTrace);
1371
1372 ace_set_rxtx_parms(dev, 0);
1373
1374 if (board_idx == BOARD_IDX_OVERFLOW) {
1375 printk(KERN_WARNING "%s: more than %i NICs detected, "
1376 "ignoring module parameters!\n",
1377 ap->name, ACE_MAX_MOD_PARMS);
1378 } else if (board_idx >= 0) {
1379 if (tx_coal_tick[board_idx])
1380 writel(tx_coal_tick[board_idx],
1381 &regs->TuneTxCoalTicks);
1382 if (max_tx_desc[board_idx])
1383 writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1384
1385 if (rx_coal_tick[board_idx])
1386 writel(rx_coal_tick[board_idx],
1387 &regs->TuneRxCoalTicks);
1388 if (max_rx_desc[board_idx])
1389 writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1390
1391 if (trace[board_idx])
1392 writel(trace[board_idx], &regs->TuneTrace);
1393
1394 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1395 writel(tx_ratio[board_idx], &regs->TxBufRat);
1396 }
1397
1398 /*
1399 * Default link parameters
1400 */
1401 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1402 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1403 if(ap->version >= 2)
1404 tmp |= LNK_TX_FLOW_CTL_Y;
1405
1406 /*
1407 * Override link default parameters
1408 */
ddfce6bb
SH		 1409 if ((board_idx >= 0) && link_state[board_idx]) {
1410 int option = link_state[board_idx];
1da177e4
LT		 1411
1412 tmp = LNK_ENABLE;
1413
1414 if (option & 0x01) {
1415 printk(KERN_INFO "%s: Setting half duplex link\n",
1416 ap->name);
1417 tmp &= ~LNK_FULL_DUPLEX;
1418 }
1419 if (option & 0x02)
1420 tmp &= ~LNK_NEGOTIATE;
1421 if (option & 0x10)
1422 tmp |= LNK_10MB;
1423 if (option & 0x20)
1424 tmp |= LNK_100MB;
1425 if (option & 0x40)
1426 tmp |= LNK_1000MB;
1427 if ((option & 0x70) == 0) {
1428 printk(KERN_WARNING "%s: No media speed specified, "
1429 "forcing auto negotiation\n", ap->name);
1430 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1431 LNK_100MB | LNK_10MB;
1432 }
1433 if ((option & 0x100) == 0)
1434 tmp |= LNK_NEG_FCTL;
1435 else
1436 printk(KERN_INFO "%s: Disabling flow control "
1437 "negotiation\n", ap->name);
1438 if (option & 0x200)
1439 tmp |= LNK_RX_FLOW_CTL_Y;
1440 if ((option & 0x400) && (ap->version >= 2)) {
1441 printk(KERN_INFO "%s: Enabling TX flow control\n",
1442 ap->name);
1443 tmp |= LNK_TX_FLOW_CTL_Y;
1444 }
1445 }
1446
1447 ap->link = tmp;
1448 writel(tmp, &regs->TuneLink);
1449 if (ap->version >= 2)
1450 writel(tmp, &regs->TuneFastLink);
1451
949b4254 1452 writel(ap->firmware_start, &regs->Pc);
1da177e4
LT		 1453
1454 writel(0, &regs->Mb0Lo);
1455
1456 /*
1457 * Set tx_csm before we start receiving interrupts, otherwise
1458 * the interrupt handler might think it is supposed to process
1459 * tx ints before we are up and running, which may cause a null
1460 * pointer access in the int handler.
1461 */
1462 ap->cur_rx = 0;
1463 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1464
1465 wmb();
1466 ace_set_txprd(regs, ap, 0);
1467 writel(0, &regs->RxRetCsm);
1468
1da177e4
LT		 1469 /*
1470 * Enable DMA engine now.
1471 * If we do this sooner, Mckinley box pukes.
1472 * I assume it's because Tigon II DMA engine wants to check
1473 * *something* even before the CPU is started.
1474 */
1475 writel(1, &regs->AssistState); /* enable DMA */
1476
1477 /*
1478 * Start the NIC CPU
1479 */
1480 writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1481 readl(&regs->CpuCtrl);
1482
1483 /*
1484 * Wait for the firmware to spin up - max 3 seconds.
1485 */
1486 myjif = jiffies + 3 * HZ;
1487 while (time_before(jiffies, myjif) && !ap->fw_running)
1488 cpu_relax();
1489
1490 if (!ap->fw_running) {
1491 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1492
1493 ace_dump_trace(ap);
1494 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1495 readl(&regs->CpuCtrl);
1496
1497 /* aman@sgi.com - account for badly behaving firmware/NIC:
1498 * - have observed that the NIC may continue to generate
1499 * interrupts for some reason; attempt to stop it - halt
1500 * second CPU for Tigon II cards, and also clear Mb0
1501 * - if we're a module, we'll fail to load if this was
1502 * the only GbE card in the system => if the kernel does
1503 * see an interrupt from the NIC, code to handle it is
1504 * gone and OOps! - so free_irq also
1505 */
1506 if (ap->version >= 2)
1507 writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1508 &regs->CpuBCtrl);
1509 writel(0, &regs->Mb0Lo);
1510 readl(&regs->Mb0Lo);
1511
1512 ecode = -EBUSY;
1513 goto init_error;
1514 }
1515
1516 /*
1517 * We load the ring here as there seem to be no way to tell the
1518 * firmware to wipe the ring without re-initializing it.
1519 */
1520 if (!test_and_set_bit(0, &ap->std_refill_busy))
1521 ace_load_std_rx_ring(ap, RX_RING_SIZE);
1522 else
1523 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1524 ap->name);
1525 if (ap->version >= 2) {
1526 if (!test_and_set_bit(0, &ap->mini_refill_busy))
1527 ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
1528 else
1529 printk(KERN_ERR "%s: Someone is busy refilling "
1530 "the RX mini ring\n", ap->name);
1531 }
1532 return 0;
1533
1534 init_error:
1535 ace_init_cleanup(dev);
1536 return ecode;
1537}
1538
1539
1540static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1541{
1542 struct ace_private *ap = netdev_priv(dev);
1543 struct ace_regs __iomem *regs = ap->regs;
1544 int board_idx = ap->board_idx;
1545
1546 if (board_idx >= 0) {
1547 if (!jumbo) {
1548 if (!tx_coal_tick[board_idx])
1549 writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1550 if (!max_tx_desc[board_idx])
1551 writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1552 if (!rx_coal_tick[board_idx])
1553 writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1554 if (!max_rx_desc[board_idx])
1555 writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1556 if (!tx_ratio[board_idx])
1557 writel(DEF_TX_RATIO, &regs->TxBufRat);
1558 } else {
1559 if (!tx_coal_tick[board_idx])
1560 writel(DEF_JUMBO_TX_COAL,
1561 &regs->TuneTxCoalTicks);
1562 if (!max_tx_desc[board_idx])
1563 writel(DEF_JUMBO_TX_MAX_DESC,
1564 &regs->TuneMaxTxDesc);
1565 if (!rx_coal_tick[board_idx])
1566 writel(DEF_JUMBO_RX_COAL,
1567 &regs->TuneRxCoalTicks);
1568 if (!max_rx_desc[board_idx])
1569 writel(DEF_JUMBO_RX_MAX_DESC,
1570 &regs->TuneMaxRxDesc);
1571 if (!tx_ratio[board_idx])
1572 writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1573 }
1574 }
1575}
1576
1577
1578static void ace_watchdog(struct net_device *data)
1579{
1580 struct net_device *dev = data;
1581 struct ace_private *ap = netdev_priv(dev);
1582 struct ace_regs __iomem *regs = ap->regs;
1583
1584 /*
1585 * We haven't received a stats update event for more than 2.5
1586 * seconds and there is data in the transmit queue, thus we
1587 * asume the card is stuck.
1588 */
1589 if (*ap->tx_csm != ap->tx_ret_csm) {
1590 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1591 dev->name, (unsigned int)readl(&regs->HostCtrl));
1592 /* This can happen due to ieee flow control. */
1593 } else {
1594 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1595 dev->name);
1596#if 0
1597 netif_wake_queue(dev);
1598#endif
1599 }
1600}
1601
1602
1603static void ace_tasklet(unsigned long dev)
1604{
1605 struct ace_private *ap = netdev_priv((struct net_device *)dev);
1606 int cur_size;
1607
1608 cur_size = atomic_read(&ap->cur_rx_bufs);
1609 if ((cur_size < RX_LOW_STD_THRES) &&
1610 !test_and_set_bit(0, &ap->std_refill_busy)) {
1611#ifdef DEBUG
1612 printk("refilling buffers (current %i)\n", cur_size);
1613#endif
1614 ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
1615 }
1616
1617 if (ap->version >= 2) {
1618 cur_size = atomic_read(&ap->cur_mini_bufs);
1619 if ((cur_size < RX_LOW_MINI_THRES) &&
1620 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1621#ifdef DEBUG
1622 printk("refilling mini buffers (current %i)\n",
1623 cur_size);
1624#endif
1625 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
1626 }
1627 }
1628
1629 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1630 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1631 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1632#ifdef DEBUG
1633 printk("refilling jumbo buffers (current %i)\n", cur_size);
1634#endif
1635 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
1636 }
1637 ap->tasklet_pending = 0;
1638}
1639
1640
1641/*
1642 * Copy the contents of the NIC's trace buffer to kernel memory.
1643 */
1644static void ace_dump_trace(struct ace_private *ap)
1645{
1646#if 0
1647 if (!ap->trace_buf)
1648 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1649 return;
1650#endif
1651}
1652
1653
1654/*
1655 * Load the standard rx ring.
1656 *
1657 * Loading rings is safe without holding the spin lock since this is
1658 * done only before the device is enabled, thus no interrupts are
1659 * generated and by the interrupt handler/tasklet handler.
1660 */
1661static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
1662{
1663 struct ace_regs __iomem *regs = ap->regs;
1664 short i, idx;
6aa20a22 1665
1da177e4
LT		 1666
1667 prefetchw(&ap->cur_rx_bufs);
1668
1669 idx = ap->rx_std_skbprd;
1670
1671 for (i = 0; i < nr_bufs; i++) {
1672 struct sk_buff *skb;
1673 struct rx_desc *rd;
1674 dma_addr_t mapping;
1675
1676 skb = alloc_skb(ACE_STD_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1677 if (!skb)
1678 break;
1679
1680 skb_reserve(skb, NET_IP_ALIGN);
1681 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1682 offset_in_page(skb->data),
1683 ACE_STD_BUFSIZE,
1684 PCI_DMA_FROMDEVICE);
1685 ap->skb->rx_std_skbuff[idx].skb = skb;
1686 pci_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1687 mapping, mapping);
1688
1689 rd = &ap->rx_std_ring[idx];
1690 set_aceaddr(&rd->addr, mapping);
1691 rd->size = ACE_STD_BUFSIZE;
1692 rd->idx = idx;
1693 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1694 }
1695
1696 if (!i)
1697 goto error_out;
1698
1699 atomic_add(i, &ap->cur_rx_bufs);
1700 ap->rx_std_skbprd = idx;
1701
1702 if (ACE_IS_TIGON_I(ap)) {
1703 struct cmd cmd;
1704 cmd.evt = C_SET_RX_PRD_IDX;
1705 cmd.code = 0;
1706 cmd.idx = ap->rx_std_skbprd;
1707 ace_issue_cmd(regs, &cmd);
1708 } else {
1709 writel(idx, &regs->RxStdPrd);
1710 wmb();
1711 }
1712
1713 out:
1714 clear_bit(0, &ap->std_refill_busy);
1715 return;
1716
1717 error_out:
1718 printk(KERN_INFO "Out of memory when allocating "
1719 "standard receive buffers\n");
1720 goto out;
1721}
1722
1723
1724static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
1725{
1726 struct ace_regs __iomem *regs = ap->regs;
1727 short i, idx;
1728
1729 prefetchw(&ap->cur_mini_bufs);
1730
1731 idx = ap->rx_mini_skbprd;
1732 for (i = 0; i < nr_bufs; i++) {
1733 struct sk_buff *skb;
1734 struct rx_desc *rd;
1735 dma_addr_t mapping;
1736
1737 skb = alloc_skb(ACE_MINI_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1738 if (!skb)
1739 break;
1740
1741 skb_reserve(skb, NET_IP_ALIGN);
1742 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1743 offset_in_page(skb->data),
1744 ACE_MINI_BUFSIZE,
1745 PCI_DMA_FROMDEVICE);
1746 ap->skb->rx_mini_skbuff[idx].skb = skb;
1747 pci_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1748 mapping, mapping);
1749
1750 rd = &ap->rx_mini_ring[idx];
1751 set_aceaddr(&rd->addr, mapping);
1752 rd->size = ACE_MINI_BUFSIZE;
1753 rd->idx = idx;
1754 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1755 }
1756
1757 if (!i)
1758 goto error_out;
1759
1760 atomic_add(i, &ap->cur_mini_bufs);
1761
1762 ap->rx_mini_skbprd = idx;
1763
1764 writel(idx, &regs->RxMiniPrd);
1765 wmb();
1766
1767 out:
1768 clear_bit(0, &ap->mini_refill_busy);
1769 return;
1770 error_out:
1771 printk(KERN_INFO "Out of memory when allocating "
1772 "mini receive buffers\n");
1773 goto out;
1774}
1775
1776
1777/*
1778 * Load the jumbo rx ring, this may happen at any time if the MTU
1779 * is changed to a value > 1500.
1780 */
1781static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
1782{
1783 struct ace_regs __iomem *regs = ap->regs;
1784 short i, idx;
1785
1786 idx = ap->rx_jumbo_skbprd;
1787
1788 for (i = 0; i < nr_bufs; i++) {
1789 struct sk_buff *skb;
1790 struct rx_desc *rd;
1791 dma_addr_t mapping;
1792
1793 skb = alloc_skb(ACE_JUMBO_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1794 if (!skb)
1795 break;
1796
1797 skb_reserve(skb, NET_IP_ALIGN);
1798 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1799 offset_in_page(skb->data),
1800 ACE_JUMBO_BUFSIZE,
1801 PCI_DMA_FROMDEVICE);
1802 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
1803 pci_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1804 mapping, mapping);
1805
1806 rd = &ap->rx_jumbo_ring[idx];
1807 set_aceaddr(&rd->addr, mapping);
1808 rd->size = ACE_JUMBO_BUFSIZE;
1809 rd->idx = idx;
1810 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1811 }
1812
1813 if (!i)
1814 goto error_out;
1815
1816 atomic_add(i, &ap->cur_jumbo_bufs);
1817 ap->rx_jumbo_skbprd = idx;
1818
1819 if (ACE_IS_TIGON_I(ap)) {
1820 struct cmd cmd;
1821 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1822 cmd.code = 0;
1823 cmd.idx = ap->rx_jumbo_skbprd;
1824 ace_issue_cmd(regs, &cmd);
1825 } else {
1826 writel(idx, &regs->RxJumboPrd);
1827 wmb();
1828 }
1829
1830 out:
1831 clear_bit(0, &ap->jumbo_refill_busy);
1832 return;
1833 error_out:
1834 if (net_ratelimit())
1835 printk(KERN_INFO "Out of memory when allocating "
1836 "jumbo receive buffers\n");
1837 goto out;
1838}
1839
1840
1841/*
1842 * All events are considered to be slow (RX/TX ints do not generate
1843 * events) and are handled here, outside the main interrupt handler,
1844 * to reduce the size of the handler.
1845 */
1846static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1847{
1848 struct ace_private *ap;
1849
1850 ap = netdev_priv(dev);
1851
1852 while (evtcsm != evtprd) {
1853 switch (ap->evt_ring[evtcsm].evt) {
1854 case E_FW_RUNNING:
1855 printk(KERN_INFO "%s: Firmware up and running\n",
1856 ap->name);
1857 ap->fw_running = 1;
1858 wmb();
1859 break;
1860 case E_STATS_UPDATED:
1861 break;
1862 case E_LNK_STATE:
1863 {
1864 u16 code = ap->evt_ring[evtcsm].code;
1865 switch (code) {
1866 case E_C_LINK_UP:
1867 {
1868 u32 state = readl(&ap->regs->GigLnkState);
1869 printk(KERN_WARNING "%s: Optical link UP "
1870 "(%s Duplex, Flow Control: %s%s)\n",
1871 ap->name,
1872 state & LNK_FULL_DUPLEX ? "Full":"Half",
1873 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1874 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1875 break;
1876 }
1877 case E_C_LINK_DOWN:
1878 printk(KERN_WARNING "%s: Optical link DOWN\n",
1879 ap->name);
1880 break;
1881 case E_C_LINK_10_100:
1882 printk(KERN_WARNING "%s: 10/100BaseT link "
1883 "UP\n", ap->name);
1884 break;
1885 default:
1886 printk(KERN_ERR "%s: Unknown optical link "
1887 "state %02x\n", ap->name, code);
1888 }
1889 break;
1890 }
1891 case E_ERROR:
1892 switch(ap->evt_ring[evtcsm].code) {
1893 case E_C_ERR_INVAL_CMD:
1894 printk(KERN_ERR "%s: invalid command error\n",
1895 ap->name);
1896 break;
1897 case E_C_ERR_UNIMP_CMD:
1898 printk(KERN_ERR "%s: unimplemented command "
1899 "error\n", ap->name);
1900 break;
1901 case E_C_ERR_BAD_CFG:
1902 printk(KERN_ERR "%s: bad config error\n",
1903 ap->name);
1904 break;
1905 default:
1906 printk(KERN_ERR "%s: unknown error %02x\n",
1907 ap->name, ap->evt_ring[evtcsm].code);
1908 }
1909 break;
1910 case E_RESET_JUMBO_RNG:
1911 {
1912 int i;
1913 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1914 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1915 ap->rx_jumbo_ring[i].size = 0;
1916 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1917 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1918 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1919 }
1920 }
1921
1922 if (ACE_IS_TIGON_I(ap)) {
1923 struct cmd cmd;
1924 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1925 cmd.code = 0;
1926 cmd.idx = 0;
1927 ace_issue_cmd(ap->regs, &cmd);
1928 } else {
1929 writel(0, &((ap->regs)->RxJumboPrd));
1930 wmb();
1931 }
1932
1933 ap->jumbo = 0;
1934 ap->rx_jumbo_skbprd = 0;
1935 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1936 ap->name);
1937 clear_bit(0, &ap->jumbo_refill_busy);
1938 break;
1939 }
1940 default:
1941 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1942 ap->name, ap->evt_ring[evtcsm].evt);
1943 }
1944 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1945 }
1946
1947 return evtcsm;
1948}
1949
1950
1951static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1952{
1953 struct ace_private *ap = netdev_priv(dev);
1954 u32 idx;
1955 int mini_count = 0, std_count = 0;
1956
1957 idx = rxretcsm;
1958
1959 prefetchw(&ap->cur_rx_bufs);
1960 prefetchw(&ap->cur_mini_bufs);
6aa20a22 1961
1da177e4
LT		 1962 while (idx != rxretprd) {
1963 struct ring_info *rip;
1964 struct sk_buff *skb;
1965 struct rx_desc *rxdesc, *retdesc;
1966 u32 skbidx;
1967 int bd_flags, desc_type, mapsize;
1968 u16 csum;
1969
1970
1971 /* make sure the rx descriptor isn't read before rxretprd */
6aa20a22 1972 if (idx == rxretcsm)
1da177e4
LT		 1973 rmb();
1974
1975 retdesc = &ap->rx_return_ring[idx];
1976 skbidx = retdesc->idx;
1977 bd_flags = retdesc->flags;
1978 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1979
1980 switch(desc_type) {
1981 /*
1982 * Normal frames do not have any flags set
1983 *
1984 * Mini and normal frames arrive frequently,
1985 * so use a local counter to avoid doing
1986 * atomic operations for each packet arriving.
1987 */
1988 case 0:
1989 rip = &ap->skb->rx_std_skbuff[skbidx];
1990 mapsize = ACE_STD_BUFSIZE;
1991 rxdesc = &ap->rx_std_ring[skbidx];
1992 std_count++;
1993 break;
1994 case BD_FLG_JUMBO:
1995 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
1996 mapsize = ACE_JUMBO_BUFSIZE;
1997 rxdesc = &ap->rx_jumbo_ring[skbidx];
1998 atomic_dec(&ap->cur_jumbo_bufs);
1999 break;
2000 case BD_FLG_MINI:
2001 rip = &ap->skb->rx_mini_skbuff[skbidx];
2002 mapsize = ACE_MINI_BUFSIZE;
2003 rxdesc = &ap->rx_mini_ring[skbidx];
6aa20a22 2004 mini_count++;
1da177e4
LT		 2005 break;
2006 default:
2007 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
2008 "returned by NIC\n", dev->name,
2009 retdesc->flags);
2010 goto error;
2011 }
2012
2013 skb = rip->skb;
2014 rip->skb = NULL;
2015 pci_unmap_page(ap->pdev,
2016 pci_unmap_addr(rip, mapping),
2017 mapsize,
2018 PCI_DMA_FROMDEVICE);
2019 skb_put(skb, retdesc->size);
2020
2021 /*
2022 * Fly baby, fly!
2023 */
2024 csum = retdesc->tcp_udp_csum;
2025
1da177e4
LT		 2026 skb->protocol = eth_type_trans(skb, dev);
2027
2028 /*
2029 * Instead of forcing the poor tigon mips cpu to calculate
2030 * pseudo hdr checksum, we do this ourselves.
2031 */
2032 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2033 skb->csum = htons(csum);
84fa7933 2034 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 2035 } else {
2036 skb->ip_summed = CHECKSUM_NONE;
2037 }
2038
2039 /* send it up */
2040#if ACENIC_DO_VLAN
2041 if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
2042 vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
2043 } else
2044#endif
2045 netif_rx(skb);
2046
966e37bc
PZ		 2047 dev->stats.rx_packets++;
2048 dev->stats.rx_bytes += retdesc->size;
1da177e4
LT		 2049
2050 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2051 }
2052
2053 atomic_sub(std_count, &ap->cur_rx_bufs);
2054 if (!ACE_IS_TIGON_I(ap))
2055 atomic_sub(mini_count, &ap->cur_mini_bufs);
2056
2057 out:
2058 /*
2059 * According to the documentation RxRetCsm is obsolete with
2060 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2061 */
2062 if (ACE_IS_TIGON_I(ap)) {
2063 writel(idx, &ap->regs->RxRetCsm);
2064 }
2065 ap->cur_rx = idx;
2066
2067 return;
2068 error:
2069 idx = rxretprd;
2070 goto out;
2071}
2072
2073
2074static inline void ace_tx_int(struct net_device *dev,
2075 u32 txcsm, u32 idx)
2076{
2077 struct ace_private *ap = netdev_priv(dev);
2078
2079 do {
2080 struct sk_buff *skb;
2081 dma_addr_t mapping;
2082 struct tx_ring_info *info;
2083
2084 info = ap->skb->tx_skbuff + idx;
2085 skb = info->skb;
2086 mapping = pci_unmap_addr(info, mapping);
2087
2088 if (mapping) {
2089 pci_unmap_page(ap->pdev, mapping,
2090 pci_unmap_len(info, maplen),
2091 PCI_DMA_TODEVICE);
2092 pci_unmap_addr_set(info, mapping, 0);
2093 }
2094
2095 if (skb) {
966e37bc
PZ		 2096 dev->stats.tx_packets++;
2097 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 2098 dev_kfree_skb_irq(skb);
2099 info->skb = NULL;
2100 }
2101
2102 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2103 } while (idx != txcsm);
2104
2105 if (netif_queue_stopped(dev))
2106 netif_wake_queue(dev);
2107
2108 wmb();
2109 ap->tx_ret_csm = txcsm;
2110
2111 /* So... tx_ret_csm is advanced _after_ check for device wakeup.
2112 *
2113 * We could try to make it before. In this case we would get
2114 * the following race condition: hard_start_xmit on other cpu
2115 * enters after we advanced tx_ret_csm and fills space,
2116 * which we have just freed, so that we make illegal device wakeup.
2117 * There is no good way to workaround this (at entry
2118 * to ace_start_xmit detects this condition and prevents
2119 * ring corruption, but it is not a good workaround.)
2120 *
2121 * When tx_ret_csm is advanced after, we wake up device _only_
2122 * if we really have some space in ring (though the core doing
2123 * hard_start_xmit can see full ring for some period and has to
2124 * synchronize.) Superb.
2125 * BUT! We get another subtle race condition. hard_start_xmit
2126 * may think that ring is full between wakeup and advancing
2127 * tx_ret_csm and will stop device instantly! It is not so bad.
2128 * We are guaranteed that there is something in ring, so that
2129 * the next irq will resume transmission. To speedup this we could
2130 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2131 * (see ace_start_xmit).
2132 *
2133 * Well, this dilemma exists in all lock-free devices.
2134 * We, following scheme used in drivers by Donald Becker,
2135 * select the least dangerous.
2136 * --ANK
2137 */
2138}
2139
2140
7d12e780 2141static irqreturn_t ace_interrupt(int irq, void *dev_id)
1da177e4
LT		 2142{
2143 struct net_device *dev = (struct net_device *)dev_id;
2144 struct ace_private *ap = netdev_priv(dev);
2145 struct ace_regs __iomem *regs = ap->regs;
2146 u32 idx;
2147 u32 txcsm, rxretcsm, rxretprd;
2148 u32 evtcsm, evtprd;
2149
2150 /*
2151 * In case of PCI shared interrupts or spurious interrupts,
2152 * we want to make sure it is actually our interrupt before
2153 * spending any time in here.
2154 */
2155 if (!(readl(&regs->HostCtrl) & IN_INT))
2156 return IRQ_NONE;
2157
2158 /*
2159 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2160 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2161 * writel(0, &regs->Mb0Lo).
2162 *
2163 * "IRQ avoidance" recommended in docs applies to IRQs served
2164 * threads and it is wrong even for that case.
2165 */
2166 writel(0, &regs->Mb0Lo);
2167 readl(&regs->Mb0Lo);
2168
2169 /*
2170 * There is no conflict between transmit handling in
2171 * start_xmit and receive processing, thus there is no reason
2172 * to take a spin lock for RX handling. Wait until we start
2173 * working on the other stuff - hey we don't need a spin lock
2174 * anymore.
2175 */
2176 rxretprd = *ap->rx_ret_prd;
2177 rxretcsm = ap->cur_rx;
2178
2179 if (rxretprd != rxretcsm)
2180 ace_rx_int(dev, rxretprd, rxretcsm);
2181
2182 txcsm = *ap->tx_csm;
2183 idx = ap->tx_ret_csm;
2184
2185 if (txcsm != idx) {
2186 /*
2187 * If each skb takes only one descriptor this check degenerates
2188 * to identity, because new space has just been opened.
2189 * But if skbs are fragmented we must check that this index
2190 * update releases enough of space, otherwise we just
2191 * wait for device to make more work.
2192 */
2193 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2194 ace_tx_int(dev, txcsm, idx);
2195 }
2196
2197 evtcsm = readl(&regs->EvtCsm);
2198 evtprd = *ap->evt_prd;
2199
2200 if (evtcsm != evtprd) {
2201 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2202 writel(evtcsm, &regs->EvtCsm);
2203 }
2204
2205 /*
2206 * This has to go last in the interrupt handler and run with
2207 * the spin lock released ... what lock?
2208 */
2209 if (netif_running(dev)) {
2210 int cur_size;
2211 int run_tasklet = 0;
2212
2213 cur_size = atomic_read(&ap->cur_rx_bufs);
2214 if (cur_size < RX_LOW_STD_THRES) {
2215 if ((cur_size < RX_PANIC_STD_THRES) &&
2216 !test_and_set_bit(0, &ap->std_refill_busy)) {
2217#ifdef DEBUG
2218 printk("low on std buffers %i\n", cur_size);
2219#endif
2220 ace_load_std_rx_ring(ap,
2221 RX_RING_SIZE - cur_size);
2222 } else
2223 run_tasklet = 1;
2224 }
2225
2226 if (!ACE_IS_TIGON_I(ap)) {
2227 cur_size = atomic_read(&ap->cur_mini_bufs);
2228 if (cur_size < RX_LOW_MINI_THRES) {
2229 if ((cur_size < RX_PANIC_MINI_THRES) &&
2230 !test_and_set_bit(0,
2231 &ap->mini_refill_busy)) {
2232#ifdef DEBUG
2233 printk("low on mini buffers %i\n",
2234 cur_size);
2235#endif
2236 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
2237 } else
2238 run_tasklet = 1;
2239 }
2240 }
2241
2242 if (ap->jumbo) {
2243 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2244 if (cur_size < RX_LOW_JUMBO_THRES) {
2245 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2246 !test_and_set_bit(0,
2247 &ap->jumbo_refill_busy)){
2248#ifdef DEBUG
2249 printk("low on jumbo buffers %i\n",
2250 cur_size);
2251#endif
2252 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
2253 } else
2254 run_tasklet = 1;
2255 }
2256 }
2257 if (run_tasklet && !ap->tasklet_pending) {
2258 ap->tasklet_pending = 1;
2259 tasklet_schedule(&ap->ace_tasklet);
2260 }
2261 }
2262
2263 return IRQ_HANDLED;
2264}
2265
2266
2267#if ACENIC_DO_VLAN
2268static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2269{
2270 struct ace_private *ap = netdev_priv(dev);
2271 unsigned long flags;
2272
2273 local_irq_save(flags);
2274 ace_mask_irq(dev);
2275
2276 ap->vlgrp = grp;
2277
2278 ace_unmask_irq(dev);
2279 local_irq_restore(flags);
2280}
1da177e4
LT		 2281#endif /* ACENIC_DO_VLAN */
2282
2283
2284static int ace_open(struct net_device *dev)
2285{
2286 struct ace_private *ap = netdev_priv(dev);
2287 struct ace_regs __iomem *regs = ap->regs;
2288 struct cmd cmd;
2289
2290 if (!(ap->fw_running)) {
2291 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2292 return -EBUSY;
2293 }
2294
2295 writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2296
2297 cmd.evt = C_CLEAR_STATS;
2298 cmd.code = 0;
2299 cmd.idx = 0;
2300 ace_issue_cmd(regs, &cmd);
2301
2302 cmd.evt = C_HOST_STATE;
2303 cmd.code = C_C_STACK_UP;
2304 cmd.idx = 0;
2305 ace_issue_cmd(regs, &cmd);
2306
2307 if (ap->jumbo &&
2308 !test_and_set_bit(0, &ap->jumbo_refill_busy))
2309 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2310
2311 if (dev->flags & IFF_PROMISC) {
2312 cmd.evt = C_SET_PROMISC_MODE;
2313 cmd.code = C_C_PROMISC_ENABLE;
2314 cmd.idx = 0;
2315 ace_issue_cmd(regs, &cmd);
2316
2317 ap->promisc = 1;
2318 }else
2319 ap->promisc = 0;
2320 ap->mcast_all = 0;
2321
2322#if 0
2323 cmd.evt = C_LNK_NEGOTIATION;
2324 cmd.code = 0;
2325 cmd.idx = 0;
2326 ace_issue_cmd(regs, &cmd);
2327#endif
2328
2329 netif_start_queue(dev);
2330
2331 /*
2332 * Setup the bottom half rx ring refill handler
2333 */
2334 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2335 return 0;
2336}
2337
2338
2339static int ace_close(struct net_device *dev)
2340{
2341 struct ace_private *ap = netdev_priv(dev);
2342 struct ace_regs __iomem *regs = ap->regs;
2343 struct cmd cmd;
2344 unsigned long flags;
2345 short i;
2346
2347 /*
2348 * Without (or before) releasing irq and stopping hardware, this
2349 * is an absolute non-sense, by the way. It will be reset instantly
2350 * by the first irq.
2351 */
2352 netif_stop_queue(dev);
2353
6aa20a22 2354
1da177e4
LT		 2355 if (ap->promisc) {
2356 cmd.evt = C_SET_PROMISC_MODE;
2357 cmd.code = C_C_PROMISC_DISABLE;
2358 cmd.idx = 0;
2359 ace_issue_cmd(regs, &cmd);
2360 ap->promisc = 0;
2361 }
2362
2363 cmd.evt = C_HOST_STATE;
2364 cmd.code = C_C_STACK_DOWN;
2365 cmd.idx = 0;
2366 ace_issue_cmd(regs, &cmd);
2367
2368 tasklet_kill(&ap->ace_tasklet);
2369
2370 /*
2371 * Make sure one CPU is not processing packets while
2372 * buffers are being released by another.
2373 */
2374
2375 local_irq_save(flags);
2376 ace_mask_irq(dev);
2377
2378 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2379 struct sk_buff *skb;
2380 dma_addr_t mapping;
2381 struct tx_ring_info *info;
2382
2383 info = ap->skb->tx_skbuff + i;
2384 skb = info->skb;
2385 mapping = pci_unmap_addr(info, mapping);
2386
2387 if (mapping) {
2388 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb
SH		 2389 /* NB: TIGON_1 is special, tx_ring is in io space */
2390 struct tx_desc __iomem *tx;
2391 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
1da177e4
LT		 2392 writel(0, &tx->addr.addrhi);
2393 writel(0, &tx->addr.addrlo);
2394 writel(0, &tx->flagsize);
2395 } else
2396 memset(ap->tx_ring + i, 0,
2397 sizeof(struct tx_desc));
2398 pci_unmap_page(ap->pdev, mapping,
2399 pci_unmap_len(info, maplen),
2400 PCI_DMA_TODEVICE);
2401 pci_unmap_addr_set(info, mapping, 0);
2402 }
2403 if (skb) {
2404 dev_kfree_skb(skb);
2405 info->skb = NULL;
2406 }
2407 }
2408
2409 if (ap->jumbo) {
2410 cmd.evt = C_RESET_JUMBO_RNG;
2411 cmd.code = 0;
2412 cmd.idx = 0;
2413 ace_issue_cmd(regs, &cmd);
2414 }
2415
2416 ace_unmask_irq(dev);
2417 local_irq_restore(flags);
2418
2419 return 0;
2420}
2421
2422
2423static inline dma_addr_t
2424ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2425 struct sk_buff *tail, u32 idx)
2426{
2427 dma_addr_t mapping;
2428 struct tx_ring_info *info;
2429
2430 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2431 offset_in_page(skb->data),
2432 skb->len, PCI_DMA_TODEVICE);
2433
2434 info = ap->skb->tx_skbuff + idx;
2435 info->skb = tail;
2436 pci_unmap_addr_set(info, mapping, mapping);
2437 pci_unmap_len_set(info, maplen, skb->len);
2438 return mapping;
2439}
2440
2441
2442static inline void
2443ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2444 u32 flagsize, u32 vlan_tag)
2445{
2446#if !USE_TX_COAL_NOW
2447 flagsize &= ~BD_FLG_COAL_NOW;
2448#endif
2449
2450 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 2451 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
1da177e4
LT		 2452 writel(addr >> 32, &io->addr.addrhi);
2453 writel(addr & 0xffffffff, &io->addr.addrlo);
2454 writel(flagsize, &io->flagsize);
2455#if ACENIC_DO_VLAN
2456 writel(vlan_tag, &io->vlanres);
2457#endif
2458 } else {
2459 desc->addr.addrhi = addr >> 32;
2460 desc->addr.addrlo = addr;
2461 desc->flagsize = flagsize;
2462#if ACENIC_DO_VLAN
2463 desc->vlanres = vlan_tag;
2464#endif
2465 }
2466}
2467
2468
61357325
SH		 2469static netdev_tx_t ace_start_xmit(struct sk_buff *skb,
2470 struct net_device *dev)
1da177e4
LT		 2471{
2472 struct ace_private *ap = netdev_priv(dev);
2473 struct ace_regs __iomem *regs = ap->regs;
2474 struct tx_desc *desc;
2475 u32 idx, flagsize;
2476 unsigned long maxjiff = jiffies + 3*HZ;
2477
2478restart:
2479 idx = ap->tx_prd;
2480
2481 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2482 goto overflow;
2483
2484 if (!skb_shinfo(skb)->nr_frags) {
2485 dma_addr_t mapping;
2486 u32 vlan_tag = 0;
2487
2488 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2489 flagsize = (skb->len << 16) | (BD_FLG_END);
84fa7933 2490 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2491 flagsize |= BD_FLG_TCP_UDP_SUM;
2492#if ACENIC_DO_VLAN
2493 if (vlan_tx_tag_present(skb)) {
2494 flagsize |= BD_FLG_VLAN_TAG;
2495 vlan_tag = vlan_tx_tag_get(skb);
2496 }
2497#endif
2498 desc = ap->tx_ring + idx;
2499 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2500
2501 /* Look at ace_tx_int for explanations. */
2502 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2503 flagsize |= BD_FLG_COAL_NOW;
2504
2505 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2506 } else {
2507 dma_addr_t mapping;
2508 u32 vlan_tag = 0;
2509 int i, len = 0;
2510
2511 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2512 flagsize = (skb_headlen(skb) << 16);
84fa7933 2513 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2514 flagsize |= BD_FLG_TCP_UDP_SUM;
2515#if ACENIC_DO_VLAN
2516 if (vlan_tx_tag_present(skb)) {
2517 flagsize |= BD_FLG_VLAN_TAG;
2518 vlan_tag = vlan_tx_tag_get(skb);
2519 }
2520#endif
2521
2522 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2523
2524 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2525
2526 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2527 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2528 struct tx_ring_info *info;
2529
2530 len += frag->size;
2531 info = ap->skb->tx_skbuff + idx;
2532 desc = ap->tx_ring + idx;
2533
2534 mapping = pci_map_page(ap->pdev, frag->page,
2535 frag->page_offset, frag->size,
2536 PCI_DMA_TODEVICE);
2537
2538 flagsize = (frag->size << 16);
84fa7933 2539 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2540 flagsize |= BD_FLG_TCP_UDP_SUM;
2541 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2542
2543 if (i == skb_shinfo(skb)->nr_frags - 1) {
2544 flagsize |= BD_FLG_END;
2545 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2546 flagsize |= BD_FLG_COAL_NOW;
2547
2548 /*
2549 * Only the last fragment frees
2550 * the skb!
2551 */
2552 info->skb = skb;
2553 } else {
2554 info->skb = NULL;
2555 }
2556 pci_unmap_addr_set(info, mapping, mapping);
2557 pci_unmap_len_set(info, maplen, frag->size);
2558 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2559 }
2560 }
2561
2562 wmb();
2563 ap->tx_prd = idx;
2564 ace_set_txprd(regs, ap, idx);
2565
2566 if (flagsize & BD_FLG_COAL_NOW) {
2567 netif_stop_queue(dev);
2568
2569 /*
2570 * A TX-descriptor producer (an IRQ) might have gotten
2571 * inbetween, making the ring free again. Since xmit is
2572 * serialized, this is the only situation we have to
2573 * re-test.
2574 */
2575 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2576 netif_wake_queue(dev);
2577 }
2578
1da177e4
LT		 2579 return NETDEV_TX_OK;
2580
2581overflow:
2582 /*
2583 * This race condition is unavoidable with lock-free drivers.
2584 * We wake up the queue _before_ tx_prd is advanced, so that we can
2585 * enter hard_start_xmit too early, while tx ring still looks closed.
2586 * This happens ~1-4 times per 100000 packets, so that we can allow
2587 * to loop syncing to other CPU. Probably, we need an additional
2588 * wmb() in ace_tx_intr as well.
2589 *
2590 * Note that this race is relieved by reserving one more entry
2591 * in tx ring than it is necessary (see original non-SG driver).
2592 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2593 * is already overkill.
2594 *
2595 * Alternative is to return with 1 not throttling queue. In this
2596 * case loop becomes longer, no more useful effects.
2597 */
2598 if (time_before(jiffies, maxjiff)) {
2599 barrier();
2600 cpu_relax();
2601 goto restart;
2602 }
6aa20a22 2603
1da177e4
LT		 2604 /* The ring is stuck full. */
2605 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2606 return NETDEV_TX_BUSY;
2607}
2608
2609
2610static int ace_change_mtu(struct net_device *dev, int new_mtu)
2611{
2612 struct ace_private *ap = netdev_priv(dev);
2613 struct ace_regs __iomem *regs = ap->regs;
2614
2615 if (new_mtu > ACE_JUMBO_MTU)
2616 return -EINVAL;
2617
2618 writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2619 dev->mtu = new_mtu;
2620
2621 if (new_mtu > ACE_STD_MTU) {
2622 if (!(ap->jumbo)) {
2623 printk(KERN_INFO "%s: Enabling Jumbo frame "
2624 "support\n", dev->name);
2625 ap->jumbo = 1;
2626 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2627 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2628 ace_set_rxtx_parms(dev, 1);
2629 }
2630 } else {
2631 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2632 ace_sync_irq(dev->irq);
2633 ace_set_rxtx_parms(dev, 0);
2634 if (ap->jumbo) {
2635 struct cmd cmd;
2636
2637 cmd.evt = C_RESET_JUMBO_RNG;
2638 cmd.code = 0;
2639 cmd.idx = 0;
2640 ace_issue_cmd(regs, &cmd);
2641 }
2642 }
2643
2644 return 0;
2645}
2646
2647static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2648{
2649 struct ace_private *ap = netdev_priv(dev);
2650 struct ace_regs __iomem *regs = ap->regs;
2651 u32 link;
2652
2653 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2654 ecmd->supported =
2655 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2656 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2657 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2658 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2659
2660 ecmd->port = PORT_FIBRE;
2661 ecmd->transceiver = XCVR_INTERNAL;
2662
2663 link = readl(&regs->GigLnkState);
2664 if (link & LNK_1000MB)
2665 ecmd->speed = SPEED_1000;
2666 else {
2667 link = readl(&regs->FastLnkState);
2668 if (link & LNK_100MB)
2669 ecmd->speed = SPEED_100;
2670 else if (link & LNK_10MB)
2671 ecmd->speed = SPEED_10;
2672 else
2673 ecmd->speed = 0;
2674 }
2675 if (link & LNK_FULL_DUPLEX)
2676 ecmd->duplex = DUPLEX_FULL;
2677 else
2678 ecmd->duplex = DUPLEX_HALF;
2679
2680 if (link & LNK_NEGOTIATE)
2681 ecmd->autoneg = AUTONEG_ENABLE;
2682 else
2683 ecmd->autoneg = AUTONEG_DISABLE;
2684
2685#if 0
2686 /*
2687 * Current struct ethtool_cmd is insufficient
2688 */
2689 ecmd->trace = readl(&regs->TuneTrace);
2690
2691 ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2692 ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2693#endif
2694 ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
2695 ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
2696
2697 return 0;
2698}
2699
2700static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2701{
2702 struct ace_private *ap = netdev_priv(dev);
2703 struct ace_regs __iomem *regs = ap->regs;
2704 u32 link, speed;
2705
2706 link = readl(&regs->GigLnkState);
2707 if (link & LNK_1000MB)
2708 speed = SPEED_1000;
2709 else {
2710 link = readl(&regs->FastLnkState);
2711 if (link & LNK_100MB)
2712 speed = SPEED_100;
2713 else if (link & LNK_10MB)
2714 speed = SPEED_10;
2715 else
2716 speed = SPEED_100;
2717 }
2718
2719 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2720 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2721 if (!ACE_IS_TIGON_I(ap))
2722 link |= LNK_TX_FLOW_CTL_Y;
2723 if (ecmd->autoneg == AUTONEG_ENABLE)
2724 link |= LNK_NEGOTIATE;
2725 if (ecmd->speed != speed) {
2726 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
2727 switch (speed) {
2728 case SPEED_1000:
2729 link |= LNK_1000MB;
2730 break;
2731 case SPEED_100:
2732 link |= LNK_100MB;
2733 break;
2734 case SPEED_10:
2735 link |= LNK_10MB;
2736 break;
2737 }
2738 }
2739
2740 if (ecmd->duplex == DUPLEX_FULL)
2741 link |= LNK_FULL_DUPLEX;
2742
2743 if (link != ap->link) {
2744 struct cmd cmd;
2745 printk(KERN_INFO "%s: Renegotiating link state\n",
2746 dev->name);
2747
2748 ap->link = link;
2749 writel(link, &regs->TuneLink);
2750 if (!ACE_IS_TIGON_I(ap))
2751 writel(link, &regs->TuneFastLink);
2752 wmb();
2753
2754 cmd.evt = C_LNK_NEGOTIATION;
2755 cmd.code = 0;
2756 cmd.idx = 0;
2757 ace_issue_cmd(regs, &cmd);
2758 }
2759 return 0;
2760}
2761
6aa20a22 2762static void ace_get_drvinfo(struct net_device *dev,
1da177e4
LT		 2763 struct ethtool_drvinfo *info)
2764{
2765 struct ace_private *ap = netdev_priv(dev);
2766
2767 strlcpy(info->driver, "acenic", sizeof(info->driver));
6aa20a22 2768 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
949b4254
JS		 2769 ap->firmware_major, ap->firmware_minor,
2770 ap->firmware_fix);
1da177e4
LT		 2771
2772 if (ap->pdev)
6aa20a22 2773 strlcpy(info->bus_info, pci_name(ap->pdev),
1da177e4
LT		 2774 sizeof(info->bus_info));
2775
2776}
2777
2778/*
2779 * Set the hardware MAC address.
2780 */
2781static int ace_set_mac_addr(struct net_device *dev, void *p)
2782{
2783 struct ace_private *ap = netdev_priv(dev);
2784 struct ace_regs __iomem *regs = ap->regs;
2785 struct sockaddr *addr=p;
2786 u8 *da;
2787 struct cmd cmd;
2788
2789 if(netif_running(dev))
2790 return -EBUSY;
2791
2792 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2793
2794 da = (u8 *)dev->dev_addr;
2795
2796 writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2797 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2798 &regs->MacAddrLo);
2799
2800 cmd.evt = C_SET_MAC_ADDR;
2801 cmd.code = 0;
2802 cmd.idx = 0;
2803 ace_issue_cmd(regs, &cmd);
2804
2805 return 0;
2806}
2807
2808
2809static void ace_set_multicast_list(struct net_device *dev)
2810{
2811 struct ace_private *ap = netdev_priv(dev);
2812 struct ace_regs __iomem *regs = ap->regs;
2813 struct cmd cmd;
2814
2815 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2816 cmd.evt = C_SET_MULTICAST_MODE;
2817 cmd.code = C_C_MCAST_ENABLE;
2818 cmd.idx = 0;
2819 ace_issue_cmd(regs, &cmd);
2820 ap->mcast_all = 1;
2821 } else if (ap->mcast_all) {
2822 cmd.evt = C_SET_MULTICAST_MODE;
2823 cmd.code = C_C_MCAST_DISABLE;
2824 cmd.idx = 0;
2825 ace_issue_cmd(regs, &cmd);
2826 ap->mcast_all = 0;
2827 }
2828
2829 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2830 cmd.evt = C_SET_PROMISC_MODE;
2831 cmd.code = C_C_PROMISC_ENABLE;
2832 cmd.idx = 0;
2833 ace_issue_cmd(regs, &cmd);
2834 ap->promisc = 1;
2835 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2836 cmd.evt = C_SET_PROMISC_MODE;
2837 cmd.code = C_C_PROMISC_DISABLE;
2838 cmd.idx = 0;
2839 ace_issue_cmd(regs, &cmd);
2840 ap->promisc = 0;
2841 }
2842
2843 /*
2844 * For the time being multicast relies on the upper layers
2845 * filtering it properly. The Firmware does not allow one to
2846 * set the entire multicast list at a time and keeping track of
2847 * it here is going to be messy.
2848 */
4cd24eaf 2849 if (!netdev_mc_empty(dev) && !ap->mcast_all) {
1da177e4
LT		 2850 cmd.evt = C_SET_MULTICAST_MODE;
2851 cmd.code = C_C_MCAST_ENABLE;
2852 cmd.idx = 0;
2853 ace_issue_cmd(regs, &cmd);
2854 }else if (!ap->mcast_all) {
2855 cmd.evt = C_SET_MULTICAST_MODE;
2856 cmd.code = C_C_MCAST_DISABLE;
2857 cmd.idx = 0;
2858 ace_issue_cmd(regs, &cmd);
2859 }
2860}
2861
2862
2863static struct net_device_stats *ace_get_stats(struct net_device *dev)
2864{
2865 struct ace_private *ap = netdev_priv(dev);
2866 struct ace_mac_stats __iomem *mac_stats =
2867 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2868
966e37bc
PZ		 2869 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2870 dev->stats.multicast = readl(&mac_stats->kept_mc);
2871 dev->stats.collisions = readl(&mac_stats->coll);
1da177e4 2872
966e37bc 2873 return &dev->stats;
1da177e4
LT		 2874}
2875
2876
949b4254
JS		 2877static void __devinit ace_copy(struct ace_regs __iomem *regs, const __be32 *src,
2878 u32 dest, int size)
1da177e4
LT		 2879{
2880 void __iomem *tdest;
1da177e4
LT		 2881 short tsize, i;
2882
2883 if (size <= 0)
2884 return;
2885
2886 while (size > 0) {
2887 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2888 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2889 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2890 (dest & (ACE_WINDOW_SIZE - 1));
2891 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
1da177e4 2892 for (i = 0; i < (tsize / 4); i++) {
949b4254
JS		 2893 /* Firmware is big-endian */
2894 writel(be32_to_cpup(src), tdest);
2895 src++;
2896 tdest += 4;
2897 dest += 4;
2898 size -= 4;
1da177e4 2899 }
1da177e4 2900 }
1da177e4
LT		 2901}
2902
2903
2904static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2905{
2906 void __iomem *tdest;
2907 short tsize = 0, i;
2908
2909 if (size <= 0)
2910 return;
2911
2912 while (size > 0) {
2913 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2914 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2915 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2916 (dest & (ACE_WINDOW_SIZE - 1));
2917 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2918
2919 for (i = 0; i < (tsize / 4); i++) {
2920 writel(0, tdest + i*4);
2921 }
2922
2923 dest += tsize;
2924 size -= tsize;
2925 }
2926
2927 return;
2928}
2929
2930
2931/*
2932 * Download the firmware into the SRAM on the NIC
2933 *
2934 * This operation requires the NIC to be halted and is performed with
2935 * interrupts disabled and with the spinlock hold.
2936 */
ddfce6bb 2937static int __devinit ace_load_firmware(struct net_device *dev)
1da177e4 2938{
949b4254
JS		 2939 const struct firmware *fw;
2940 const char *fw_name = "acenic/tg2.bin";
1da177e4
LT		 2941 struct ace_private *ap = netdev_priv(dev);
2942 struct ace_regs __iomem *regs = ap->regs;
949b4254
JS		 2943 const __be32 *fw_data;
2944 u32 load_addr;
2945 int ret;
1da177e4
LT		 2946
2947 if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2948 printk(KERN_ERR "%s: trying to download firmware while the "
2949 "CPU is running!\n", ap->name);
2950 return -EFAULT;
2951 }
2952
949b4254
JS		 2953 if (ACE_IS_TIGON_I(ap))
2954 fw_name = "acenic/tg1.bin";
2955
2956 ret = request_firmware(&fw, fw_name, &ap->pdev->dev);
2957 if (ret) {
2958 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
2959 ap->name, fw_name);
2960 return ret;
2961 }
2962
2963 fw_data = (void *)fw->data;
2964
2965 /* Firmware blob starts with version numbers, followed by
2966 load and start address. Remainder is the blob to be loaded
2967 contiguously from load address. We don't bother to represent
2968 the BSS/SBSS sections any more, since we were clearing the
2969 whole thing anyway. */
2970 ap->firmware_major = fw->data[0];
2971 ap->firmware_minor = fw->data[1];
2972 ap->firmware_fix = fw->data[2];
2973
2974 ap->firmware_start = be32_to_cpu(fw_data[1]);
2975 if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) {
2976 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2977 ap->name, ap->firmware_start, fw_name);
2978 ret = -EINVAL;
2979 goto out;
2980 }
2981
2982 load_addr = be32_to_cpu(fw_data[2]);
2983 if (load_addr < 0x4000 || load_addr >= 0x80000) {
2984 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2985 ap->name, load_addr, fw_name);
2986 ret = -EINVAL;
2987 goto out;
2988 }
2989
1da177e4 2990 /*
949b4254
JS		 2991 * Do not try to clear more than 512KiB or we end up seeing
2992 * funny things on NICs with only 512KiB SRAM
1da177e4
LT		 2993 */
2994 ace_clear(regs, 0x2000, 0x80000-0x2000);
949b4254
JS		 2995 ace_copy(regs, &fw_data[3], load_addr, fw->size-12);
2996 out:
2997 release_firmware(fw);
2998 return ret;
1da177e4
LT		 2999}
3000
3001
3002/*
3003 * The eeprom on the AceNIC is an Atmel i2c EEPROM.
3004 *
3005 * Accessing the EEPROM is `interesting' to say the least - don't read
3006 * this code right after dinner.
3007 *
3008 * This is all about black magic and bit-banging the device .... I
3009 * wonder in what hospital they have put the guy who designed the i2c
3010 * specs.
3011 *
3012 * Oh yes, this is only the beginning!
3013 *
3014 * Thanks to Stevarino Webinski for helping tracking down the bugs in the
3015 * code i2c readout code by beta testing all my hacks.
3016 */
3017static void __devinit eeprom_start(struct ace_regs __iomem *regs)
3018{
3019 u32 local;
3020
3021 readl(&regs->LocalCtrl);
3022 udelay(ACE_SHORT_DELAY);
3023 local = readl(&regs->LocalCtrl);
3024 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
3025 writel(local, &regs->LocalCtrl);
3026 readl(&regs->LocalCtrl);
3027 mb();
3028 udelay(ACE_SHORT_DELAY);
3029 local |= EEPROM_CLK_OUT;
3030 writel(local, &regs->LocalCtrl);
3031 readl(&regs->LocalCtrl);
3032 mb();
3033 udelay(ACE_SHORT_DELAY);
3034 local &= ~EEPROM_DATA_OUT;
3035 writel(local, &regs->LocalCtrl);
3036 readl(&regs->LocalCtrl);
3037 mb();
3038 udelay(ACE_SHORT_DELAY);
3039 local &= ~EEPROM_CLK_OUT;
3040 writel(local, &regs->LocalCtrl);
3041 readl(&regs->LocalCtrl);
3042 mb();
3043}
3044
3045
3046static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
3047{
3048 short i;
3049 u32 local;
3050
3051 udelay(ACE_SHORT_DELAY);
3052 local = readl(&regs->LocalCtrl);
3053 local &= ~EEPROM_DATA_OUT;
3054 local |= EEPROM_WRITE_ENABLE;
3055 writel(local, &regs->LocalCtrl);
3056 readl(&regs->LocalCtrl);
3057 mb();
3058
3059 for (i = 0; i < 8; i++, magic <<= 1) {
3060 udelay(ACE_SHORT_DELAY);
6aa20a22 3061 if (magic & 0x80)
1da177e4
LT		 3062 local |= EEPROM_DATA_OUT;
3063 else
3064 local &= ~EEPROM_DATA_OUT;
3065 writel(local, &regs->LocalCtrl);
3066 readl(&regs->LocalCtrl);
3067 mb();
3068
3069 udelay(ACE_SHORT_DELAY);
3070 local |= EEPROM_CLK_OUT;
3071 writel(local, &regs->LocalCtrl);
3072 readl(&regs->LocalCtrl);
3073 mb();
3074 udelay(ACE_SHORT_DELAY);
3075 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3076 writel(local, &regs->LocalCtrl);
3077 readl(&regs->LocalCtrl);
3078 mb();
3079 }
3080}
3081
3082
3083static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
3084{
3085 int state;
3086 u32 local;
3087
3088 local = readl(&regs->LocalCtrl);
3089 local &= ~EEPROM_WRITE_ENABLE;
3090 writel(local, &regs->LocalCtrl);
3091 readl(&regs->LocalCtrl);
3092 mb();
3093 udelay(ACE_LONG_DELAY);
3094 local |= EEPROM_CLK_OUT;
3095 writel(local, &regs->LocalCtrl);
3096 readl(&regs->LocalCtrl);
3097 mb();
3098 udelay(ACE_SHORT_DELAY);
3099 /* sample data in middle of high clk */
3100 state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3101 udelay(ACE_SHORT_DELAY);
3102 mb();
3103 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3104 readl(&regs->LocalCtrl);
3105 mb();
3106
3107 return state;
3108}
3109
3110
3111static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
3112{
3113 u32 local;
3114
3115 udelay(ACE_SHORT_DELAY);
3116 local = readl(&regs->LocalCtrl);
3117 local |= EEPROM_WRITE_ENABLE;
3118 writel(local, &regs->LocalCtrl);
3119 readl(&regs->LocalCtrl);
3120 mb();
3121 udelay(ACE_SHORT_DELAY);
3122 local &= ~EEPROM_DATA_OUT;
3123 writel(local, &regs->LocalCtrl);
3124 readl(&regs->LocalCtrl);
3125 mb();
3126 udelay(ACE_SHORT_DELAY);
3127 local |= EEPROM_CLK_OUT;
3128 writel(local, &regs->LocalCtrl);
3129 readl(&regs->LocalCtrl);
3130 mb();
3131 udelay(ACE_SHORT_DELAY);
3132 local |= EEPROM_DATA_OUT;
3133 writel(local, &regs->LocalCtrl);
3134 readl(&regs->LocalCtrl);
3135 mb();
3136 udelay(ACE_LONG_DELAY);
3137 local &= ~EEPROM_CLK_OUT;
3138 writel(local, &regs->LocalCtrl);
3139 mb();
3140}
3141
3142
3143/*
3144 * Read a whole byte from the EEPROM.
3145 */
3146static int __devinit read_eeprom_byte(struct net_device *dev,
3147 unsigned long offset)
3148{
3149 struct ace_private *ap = netdev_priv(dev);
3150 struct ace_regs __iomem *regs = ap->regs;
3151 unsigned long flags;
3152 u32 local;
3153 int result = 0;
3154 short i;
3155
1da177e4
LT		 3156 /*
3157 * Don't take interrupts on this CPU will bit banging
3158 * the %#%#@$ I2C device
3159 */
3160 local_irq_save(flags);
3161
3162 eeprom_start(regs);
3163
3164 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3165 if (eeprom_check_ack(regs)) {
3166 local_irq_restore(flags);
3167 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3168 result = -EIO;
3169 goto eeprom_read_error;
3170 }
3171
3172 eeprom_prep(regs, (offset >> 8) & 0xff);
3173 if (eeprom_check_ack(regs)) {
3174 local_irq_restore(flags);
3175 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3176 ap->name);
3177 result = -EIO;
3178 goto eeprom_read_error;
3179 }
3180
3181 eeprom_prep(regs, offset & 0xff);
3182 if (eeprom_check_ack(regs)) {
3183 local_irq_restore(flags);
3184 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3185 ap->name);
3186 result = -EIO;
3187 goto eeprom_read_error;
3188 }
3189
3190 eeprom_start(regs);
3191 eeprom_prep(regs, EEPROM_READ_SELECT);
3192 if (eeprom_check_ack(regs)) {
3193 local_irq_restore(flags);
3194 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3195 ap->name);
3196 result = -EIO;
3197 goto eeprom_read_error;
3198 }
3199
3200 for (i = 0; i < 8; i++) {
3201 local = readl(&regs->LocalCtrl);
3202 local &= ~EEPROM_WRITE_ENABLE;
3203 writel(local, &regs->LocalCtrl);
3204 readl(&regs->LocalCtrl);
3205 udelay(ACE_LONG_DELAY);
3206 mb();
3207 local |= EEPROM_CLK_OUT;
3208 writel(local, &regs->LocalCtrl);
3209 readl(&regs->LocalCtrl);
3210 mb();
3211 udelay(ACE_SHORT_DELAY);
3212 /* sample data mid high clk */
3213 result = (result << 1) |
3214 ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3215 udelay(ACE_SHORT_DELAY);
3216 mb();
3217 local = readl(&regs->LocalCtrl);
3218 local &= ~EEPROM_CLK_OUT;
3219 writel(local, &regs->LocalCtrl);
3220 readl(&regs->LocalCtrl);
3221 udelay(ACE_SHORT_DELAY);
3222 mb();
3223 if (i == 7) {
3224 local |= EEPROM_WRITE_ENABLE;
3225 writel(local, &regs->LocalCtrl);
3226 readl(&regs->LocalCtrl);
3227 mb();
3228 udelay(ACE_SHORT_DELAY);
3229 }
3230 }
3231
3232 local |= EEPROM_DATA_OUT;
3233 writel(local, &regs->LocalCtrl);
3234 readl(&regs->LocalCtrl);
3235 mb();
3236 udelay(ACE_SHORT_DELAY);
3237 writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3238 readl(&regs->LocalCtrl);
3239 udelay(ACE_LONG_DELAY);
3240 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3241 readl(&regs->LocalCtrl);
3242 mb();
3243 udelay(ACE_SHORT_DELAY);
3244 eeprom_stop(regs);
3245
3246 local_irq_restore(flags);
3247 out:
3248 return result;
3249
3250 eeprom_read_error:
3251 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3252 ap->name, offset);
3253 goto out;
3254}
Linux 6.x block layer and io_uring tree(s)