[linux-2.6-block.git] / drivers / mtd / spi-nor / mtk-quadspi.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Bayi Cheng <bayi.cheng@mediatek.com>
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/spi-nor.h>

#define MTK_NOR_CMD_REG			0x00
#define MTK_NOR_CNT_REG			0x04
#define MTK_NOR_RDSR_REG		0x08
#define MTK_NOR_RDATA_REG		0x0c
#define MTK_NOR_RADR0_REG		0x10
#define MTK_NOR_RADR1_REG		0x14
#define MTK_NOR_RADR2_REG		0x18
#define MTK_NOR_WDATA_REG		0x1c
#define MTK_NOR_PRGDATA0_REG		0x20
#define MTK_NOR_PRGDATA1_REG		0x24
#define MTK_NOR_PRGDATA2_REG		0x28
#define MTK_NOR_PRGDATA3_REG		0x2c
#define MTK_NOR_PRGDATA4_REG		0x30
#define MTK_NOR_PRGDATA5_REG		0x34
#define MTK_NOR_SHREG0_REG		0x38
#define MTK_NOR_SHREG1_REG		0x3c
#define MTK_NOR_SHREG2_REG		0x40
#define MTK_NOR_SHREG3_REG		0x44
#define MTK_NOR_SHREG4_REG		0x48
#define MTK_NOR_SHREG5_REG		0x4c
#define MTK_NOR_SHREG6_REG		0x50
#define MTK_NOR_SHREG7_REG		0x54
#define MTK_NOR_SHREG8_REG		0x58
#define MTK_NOR_SHREG9_REG		0x5c
#define MTK_NOR_CFG1_REG		0x60
#define MTK_NOR_CFG2_REG		0x64
#define MTK_NOR_CFG3_REG		0x68
#define MTK_NOR_STATUS0_REG		0x70
#define MTK_NOR_STATUS1_REG		0x74
#define MTK_NOR_STATUS2_REG		0x78
#define MTK_NOR_STATUS3_REG		0x7c
#define MTK_NOR_FLHCFG_REG		0x84
#define MTK_NOR_TIME_REG		0x94
#define MTK_NOR_PP_DATA_REG		0x98
#define MTK_NOR_PREBUF_STUS_REG		0x9c
#define MTK_NOR_DELSEL0_REG		0xa0
#define MTK_NOR_DELSEL1_REG		0xa4
#define MTK_NOR_INTRSTUS_REG		0xa8
#define MTK_NOR_INTREN_REG		0xac
#define MTK_NOR_CHKSUM_CTL_REG		0xb8
#define MTK_NOR_CHKSUM_REG		0xbc
#define MTK_NOR_CMD2_REG		0xc0
#define MTK_NOR_WRPROT_REG		0xc4
#define MTK_NOR_RADR3_REG		0xc8
#define MTK_NOR_DUAL_REG		0xcc
#define MTK_NOR_DELSEL2_REG		0xd0
#define MTK_NOR_DELSEL3_REG		0xd4
#define MTK_NOR_DELSEL4_REG		0xd8

/* commands for mtk nor controller */
#define MTK_NOR_READ_CMD		0x0
#define MTK_NOR_RDSR_CMD		0x2
#define MTK_NOR_PRG_CMD			0x4
#define MTK_NOR_WR_CMD			0x10
#define MTK_NOR_PIO_WR_CMD		0x90
#define MTK_NOR_WRSR_CMD		0x20
#define MTK_NOR_PIO_READ_CMD		0x81
#define MTK_NOR_WR_BUF_ENABLE		0x1
#define MTK_NOR_WR_BUF_DISABLE		0x0
#define MTK_NOR_ENABLE_SF_CMD		0x30
#define MTK_NOR_DUAD_ADDR_EN		0x8
#define MTK_NOR_QUAD_READ_EN		0x4
#define MTK_NOR_DUAL_ADDR_EN		0x2
#define MTK_NOR_DUAL_READ_EN		0x1
#define MTK_NOR_DUAL_DISABLE		0x0
#define MTK_NOR_FAST_READ		0x1

#define SFLASH_WRBUF_SIZE		128

/* Can shift up to 48 bits (6 bytes) of TX/RX */
#define MTK_NOR_MAX_RX_TX_SHIFT		6
/* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */
#define MTK_NOR_MAX_SHIFT		7
/* nor controller 4-byte address mode enable bit */
#define MTK_NOR_4B_ADDR_EN		BIT(4)

/* Helpers for accessing the program data / shift data registers */
#define MTK_NOR_PRG_REG(n)		(MTK_NOR_PRGDATA0_REG + 4 * (n))
#define MTK_NOR_SHREG(n)		(MTK_NOR_SHREG0_REG + 4 * (n))

struct mtk_nor {
	struct spi_nor nor;
	struct device *dev;
	void __iomem *base;	/* nor flash base address */
	struct clk *spi_clk;
	struct clk *nor_clk;
};

static void mtk_nor_set_read_mode(struct mtk_nor *mtk_nor)
{
	struct spi_nor *nor = &mtk_nor->nor;

	switch (nor->read_proto) {
	case SNOR_PROTO_1_1_1:
		writeb(nor->read_opcode, mtk_nor->base +
		       MTK_NOR_PRGDATA3_REG);
		writeb(MTK_NOR_FAST_READ, mtk_nor->base +
		       MTK_NOR_CFG1_REG);
		break;
	case SNOR_PROTO_1_1_2:
		writeb(nor->read_opcode, mtk_nor->base +
		       MTK_NOR_PRGDATA3_REG);
		writeb(MTK_NOR_DUAL_READ_EN, mtk_nor->base +
		       MTK_NOR_DUAL_REG);
		break;
	case SNOR_PROTO_1_1_4:
		writeb(nor->read_opcode, mtk_nor->base +
		       MTK_NOR_PRGDATA4_REG);
		writeb(MTK_NOR_QUAD_READ_EN, mtk_nor->base +
		       MTK_NOR_DUAL_REG);
		break;
	default:
		writeb(MTK_NOR_DUAL_DISABLE, mtk_nor->base +
		       MTK_NOR_DUAL_REG);
		break;
	}
}

static int mtk_nor_execute_cmd(struct mtk_nor *mtk_nor, u8 cmdval)
{
	int reg;
	u8 val = cmdval & 0x1f;

	writeb(cmdval, mtk_nor->base + MTK_NOR_CMD_REG);
	return readl_poll_timeout(mtk_nor->base + MTK_NOR_CMD_REG, reg,
				  !(reg & val), 100, 10000);
}

static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op,
			    const u8 *tx, size_t txlen, u8 *rx, size_t rxlen)
{
	size_t len = 1 + txlen + rxlen;
	int i, ret, idx;

	if (len > MTK_NOR_MAX_SHIFT)
		return -EINVAL;

	writeb(len * 8, mtk_nor->base + MTK_NOR_CNT_REG);

	/* start at PRGDATA5, go down to PRGDATA0 */
	idx = MTK_NOR_MAX_RX_TX_SHIFT - 1;

	/* opcode */
	writeb(op, mtk_nor->base + MTK_NOR_PRG_REG(idx));
	idx--;

	/* program TX data */
	for (i = 0; i < txlen; i++, idx--)
		writeb(tx[i], mtk_nor->base + MTK_NOR_PRG_REG(idx));

	/* clear out rest of TX registers */
	while (idx >= 0) {
		writeb(0, mtk_nor->base + MTK_NOR_PRG_REG(idx));
		idx--;
	}

	ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PRG_CMD);
	if (ret)
		return ret;

	/* restart at first RX byte */
	idx = rxlen - 1;

	/* read out RX data */
	for (i = 0; i < rxlen; i++, idx--)
		rx[i] = readb(mtk_nor->base + MTK_NOR_SHREG(idx));

	return 0;
}

/* Do a WRSR (Write Status Register) command */
static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, const u8 sr)
{
	writeb(sr, mtk_nor->base + MTK_NOR_PRGDATA5_REG);
	writeb(8, mtk_nor->base + MTK_NOR_CNT_REG);
	return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WRSR_CMD);
}

static int mtk_nor_write_buffer_enable(struct mtk_nor *mtk_nor)
{
	u8 reg;

	/* the bit0 of MTK_NOR_CFG2_REG is pre-fetch buffer
	 * 0: pre-fetch buffer use for read
	 * 1: pre-fetch buffer use for page program
	 */
	writel(MTK_NOR_WR_BUF_ENABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
	return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
				  0x01 == (reg & 0x01), 100, 10000);
}

static int mtk_nor_write_buffer_disable(struct mtk_nor *mtk_nor)
{
	u8 reg;

	writel(MTK_NOR_WR_BUF_DISABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
	return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
				  MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100,
				  10000);
}

static void mtk_nor_set_addr_width(struct mtk_nor *mtk_nor)
{
	u8 val;
	struct spi_nor *nor = &mtk_nor->nor;

	val = readb(mtk_nor->base + MTK_NOR_DUAL_REG);

	switch (nor->addr_width) {
	case 3:
		val &= ~MTK_NOR_4B_ADDR_EN;
		break;
	case 4:
		val |= MTK_NOR_4B_ADDR_EN;
		break;
	default:
		dev_warn(mtk_nor->dev, "Unexpected address width %u.\n",
			 nor->addr_width);
		break;
	}

	writeb(val, mtk_nor->base + MTK_NOR_DUAL_REG);
}

static void mtk_nor_set_addr(struct mtk_nor *mtk_nor, u32 addr)
{
	int i;

	mtk_nor_set_addr_width(mtk_nor);

	for (i = 0; i < 3; i++) {
		writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR0_REG + i * 4);
		addr >>= 8;
	}
	/* Last register is non-contiguous */
	writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR3_REG);
}

static ssize_t mtk_nor_read(struct spi_nor *nor, loff_t from, size_t length,
			    u_char *buffer)
{
	int i, ret;
	int addr = (int)from;
	u8 *buf = (u8 *)buffer;
	struct mtk_nor *mtk_nor = nor->priv;

	/* set mode for fast read mode ,dual mode or quad mode */
	mtk_nor_set_read_mode(mtk_nor);
	mtk_nor_set_addr(mtk_nor, addr);

	for (i = 0; i < length; i++) {
		ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_READ_CMD);
		if (ret < 0)
			return ret;
		buf[i] = readb(mtk_nor->base + MTK_NOR_RDATA_REG);
	}
	return length;
}

static int mtk_nor_write_single_byte(struct mtk_nor *mtk_nor,
				     int addr, int length, u8 *data)
{
	int i, ret;

	mtk_nor_set_addr(mtk_nor, addr);

	for (i = 0; i < length; i++) {
		writeb(*data++, mtk_nor->base + MTK_NOR_WDATA_REG);
		ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_WR_CMD);
		if (ret < 0)
			return ret;
	}
	return 0;
}

static int mtk_nor_write_buffer(struct mtk_nor *mtk_nor, int addr,
				const u8 *buf)
{
	int i, bufidx, data;

	mtk_nor_set_addr(mtk_nor, addr);

	bufidx = 0;
	for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) {
		data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 |
		       buf[bufidx + 1]<<8 | buf[bufidx];
		bufidx += 4;
		writel(data, mtk_nor->base + MTK_NOR_PP_DATA_REG);
	}
	return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WR_CMD);
}

static ssize_t mtk_nor_write(struct spi_nor *nor, loff_t to, size_t len,
			     const u_char *buf)
{
	int ret;
	struct mtk_nor *mtk_nor = nor->priv;
	size_t i;

	ret = mtk_nor_write_buffer_enable(mtk_nor);
	if (ret < 0) {
		dev_warn(mtk_nor->dev, "write buffer enable failed!\n");
		return ret;
	}

	for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) {
		ret = mtk_nor_write_buffer(mtk_nor, to, buf);
		if (ret < 0) {
			dev_err(mtk_nor->dev, "write buffer failed!\n");
			return ret;
		}
		to += SFLASH_WRBUF_SIZE;
		buf += SFLASH_WRBUF_SIZE;
	}
	ret = mtk_nor_write_buffer_disable(mtk_nor);
	if (ret < 0) {
		dev_warn(mtk_nor->dev, "write buffer disable failed!\n");
		return ret;
	}

	if (i < len) {
		ret = mtk_nor_write_single_byte(mtk_nor, to,
						(int)(len - i), (u8 *)buf);
		if (ret < 0) {
			dev_err(mtk_nor->dev, "write single byte failed!\n");
			return ret;
		}
	}

	return len;
}

static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len)
{
	int ret;
	struct mtk_nor *mtk_nor = nor->priv;

	switch (opcode) {
	case SPINOR_OP_RDSR:
		ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_RDSR_CMD);
		if (ret < 0)
			return ret;
		if (len == 1)
			*buf = readb(mtk_nor->base + MTK_NOR_RDSR_REG);
		else
			dev_err(mtk_nor->dev, "len should be 1 for read status!\n");
		break;
	default:
		ret = mtk_nor_do_tx_rx(mtk_nor, opcode, NULL, 0, buf, len);
		break;
	}
	return ret;
}

static int mtk_nor_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
			     size_t len)
{
	int ret;
	struct mtk_nor *mtk_nor = nor->priv;

	switch (opcode) {
	case SPINOR_OP_WRSR:
		/* We only handle 1 byte */
		ret = mtk_nor_wr_sr(mtk_nor, *buf);
		break;
	default:
		ret = mtk_nor_do_tx_rx(mtk_nor, opcode, buf, len, NULL, 0);
		if (ret)
			dev_warn(mtk_nor->dev, "write reg failure!\n");
		break;
	}
	return ret;
}

static void mtk_nor_disable_clk(struct mtk_nor *mtk_nor)
{
	clk_disable_unprepare(mtk_nor->spi_clk);
	clk_disable_unprepare(mtk_nor->nor_clk);
}

static int mtk_nor_enable_clk(struct mtk_nor *mtk_nor)
{
	int ret;

	ret = clk_prepare_enable(mtk_nor->spi_clk);
	if (ret)
		return ret;

	ret = clk_prepare_enable(mtk_nor->nor_clk);
	if (ret) {
		clk_disable_unprepare(mtk_nor->spi_clk);
		return ret;
	}

	return 0;
}

static const struct spi_nor_controller_ops mtk_controller_ops = {
	.read_reg = mtk_nor_read_reg,
	.write_reg = mtk_nor_write_reg,
	.read = mtk_nor_read,
	.write = mtk_nor_write,
};

static int mtk_nor_init(struct mtk_nor *mtk_nor,
			struct device_node *flash_node)
{
	const struct spi_nor_hwcaps hwcaps = {
		.mask = SNOR_HWCAPS_READ |
			SNOR_HWCAPS_READ_FAST |
			SNOR_HWCAPS_READ_1_1_2 |
			SNOR_HWCAPS_PP,
	};
	int ret;
	struct spi_nor *nor;

	/* initialize controller to accept commands */
	writel(MTK_NOR_ENABLE_SF_CMD, mtk_nor->base + MTK_NOR_WRPROT_REG);

	nor = &mtk_nor->nor;
	nor->dev = mtk_nor->dev;
	nor->priv = mtk_nor;
	spi_nor_set_flash_node(nor, flash_node);
	nor->controller_ops = &mtk_controller_ops;

	nor->mtd.name = "mtk_nor";
	/* initialized with NULL */
	ret = spi_nor_scan(nor, NULL, &hwcaps);
	if (ret)
		return ret;

	return mtd_device_register(&nor->mtd, NULL, 0);
}

static int mtk_nor_drv_probe(struct platform_device *pdev)
{
	struct device_node *flash_np;
	struct resource *res;
	int ret;
	struct mtk_nor *mtk_nor;

	if (!pdev->dev.of_node) {
		dev_err(&pdev->dev, "No DT found\n");
		return -EINVAL;
	}

	mtk_nor = devm_kzalloc(&pdev->dev, sizeof(*mtk_nor), GFP_KERNEL);
	if (!mtk_nor)
		return -ENOMEM;
	platform_set_drvdata(pdev, mtk_nor);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mtk_nor->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mtk_nor->base))
		return PTR_ERR(mtk_nor->base);

	mtk_nor->spi_clk = devm_clk_get(&pdev->dev, "spi");
	if (IS_ERR(mtk_nor->spi_clk))
		return PTR_ERR(mtk_nor->spi_clk);

	mtk_nor->nor_clk = devm_clk_get(&pdev->dev, "sf");
	if (IS_ERR(mtk_nor->nor_clk))
		return PTR_ERR(mtk_nor->nor_clk);

	mtk_nor->dev = &pdev->dev;

	ret = mtk_nor_enable_clk(mtk_nor);
	if (ret)
		return ret;

	/* only support one attached flash */
	flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
	if (!flash_np) {
		dev_err(&pdev->dev, "no SPI flash device to configure\n");
		ret = -ENODEV;
		goto nor_free;
	}
	ret = mtk_nor_init(mtk_nor, flash_np);

nor_free:
	if (ret)
		mtk_nor_disable_clk(mtk_nor);

	return ret;
}

static int mtk_nor_drv_remove(struct platform_device *pdev)
{
	struct mtk_nor *mtk_nor = platform_get_drvdata(pdev);

	mtk_nor_disable_clk(mtk_nor);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mtk_nor_suspend(struct device *dev)
{
	struct mtk_nor *mtk_nor = dev_get_drvdata(dev);

	mtk_nor_disable_clk(mtk_nor);

	return 0;
}

static int mtk_nor_resume(struct device *dev)
{
	struct mtk_nor *mtk_nor = dev_get_drvdata(dev);

	return mtk_nor_enable_clk(mtk_nor);
}

static const struct dev_pm_ops mtk_nor_dev_pm_ops = {
	.suspend = mtk_nor_suspend,
	.resume = mtk_nor_resume,
};

#define MTK_NOR_DEV_PM_OPS	(&mtk_nor_dev_pm_ops)
#else
#define MTK_NOR_DEV_PM_OPS	NULL
#endif

static const struct of_device_id mtk_nor_of_ids[] = {
	{ .compatible = "mediatek,mt8173-nor"},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_nor_of_ids);

static struct platform_driver mtk_nor_driver = {
	.probe = mtk_nor_drv_probe,
	.remove = mtk_nor_drv_remove,
	.driver = {
		.name = "mtk-nor",
		.pm = MTK_NOR_DEV_PM_OPS,
		.of_match_table = mtk_nor_of_ids,
	},
};

module_platform_driver(mtk_nor_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek SPI NOR Flash Driver");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
3ce351b5 BC	2	/*
	3	* Copyright (c) 2015 MediaTek Inc.
	4	* Author: Bayi Cheng <bayi.cheng@mediatek.com>
3ce351b5 BC	5	*/
	6
	7	#include <linux/clk.h>
	8	#include <linux/delay.h>
	9	#include <linux/device.h>
	10	#include <linux/init.h>
	11	#include <linux/io.h>
	12	#include <linux/iopoll.h>
	13	#include <linux/ioport.h>
	14	#include <linux/math64.h>
	15	#include <linux/module.h>
3ce351b5 BC	16	#include <linux/mutex.h>
	17	#include <linux/of.h>
	18	#include <linux/of_device.h>
3ce351b5 BC	19	#include <linux/platform_device.h>
	20	#include <linux/slab.h>
	21	#include <linux/mtd/mtd.h>
	22	#include <linux/mtd/partitions.h>
	23	#include <linux/mtd/spi-nor.h>
	24
	25	#define MTK_NOR_CMD_REG 0x00
	26	#define MTK_NOR_CNT_REG 0x04
	27	#define MTK_NOR_RDSR_REG 0x08
	28	#define MTK_NOR_RDATA_REG 0x0c
	29	#define MTK_NOR_RADR0_REG 0x10
	30	#define MTK_NOR_RADR1_REG 0x14
	31	#define MTK_NOR_RADR2_REG 0x18
	32	#define MTK_NOR_WDATA_REG 0x1c
	33	#define MTK_NOR_PRGDATA0_REG 0x20
	34	#define MTK_NOR_PRGDATA1_REG 0x24
	35	#define MTK_NOR_PRGDATA2_REG 0x28
	36	#define MTK_NOR_PRGDATA3_REG 0x2c
	37	#define MTK_NOR_PRGDATA4_REG 0x30
	38	#define MTK_NOR_PRGDATA5_REG 0x34
	39	#define MTK_NOR_SHREG0_REG 0x38
	40	#define MTK_NOR_SHREG1_REG 0x3c
	41	#define MTK_NOR_SHREG2_REG 0x40
	42	#define MTK_NOR_SHREG3_REG 0x44
	43	#define MTK_NOR_SHREG4_REG 0x48
	44	#define MTK_NOR_SHREG5_REG 0x4c
	45	#define MTK_NOR_SHREG6_REG 0x50
	46	#define MTK_NOR_SHREG7_REG 0x54
	47	#define MTK_NOR_SHREG8_REG 0x58
	48	#define MTK_NOR_SHREG9_REG 0x5c
	49	#define MTK_NOR_CFG1_REG 0x60
	50	#define MTK_NOR_CFG2_REG 0x64
	51	#define MTK_NOR_CFG3_REG 0x68
	52	#define MTK_NOR_STATUS0_REG 0x70
	53	#define MTK_NOR_STATUS1_REG 0x74
	54	#define MTK_NOR_STATUS2_REG 0x78
	55	#define MTK_NOR_STATUS3_REG 0x7c
	56	#define MTK_NOR_FLHCFG_REG 0x84
	57	#define MTK_NOR_TIME_REG 0x94
	58	#define MTK_NOR_PP_DATA_REG 0x98
	59	#define MTK_NOR_PREBUF_STUS_REG 0x9c
	60	#define MTK_NOR_DELSEL0_REG 0xa0
	61	#define MTK_NOR_DELSEL1_REG 0xa4
	62	#define MTK_NOR_INTRSTUS_REG 0xa8
	63	#define MTK_NOR_INTREN_REG 0xac
	64	#define MTK_NOR_CHKSUM_CTL_REG 0xb8
	65	#define MTK_NOR_CHKSUM_REG 0xbc
	66	#define MTK_NOR_CMD2_REG 0xc0
	67	#define MTK_NOR_WRPROT_REG 0xc4
	68	#define MTK_NOR_RADR3_REG 0xc8
	69	#define MTK_NOR_DUAL_REG 0xcc
	70	#define MTK_NOR_DELSEL2_REG 0xd0
	71	#define MTK_NOR_DELSEL3_REG 0xd4
	72	#define MTK_NOR_DELSEL4_REG 0xd8
	73
	74	/* commands for mtk nor controller */
	75	#define MTK_NOR_READ_CMD 0x0
	76	#define MTK_NOR_RDSR_CMD 0x2
	77	#define MTK_NOR_PRG_CMD 0x4
	78	#define MTK_NOR_WR_CMD 0x10
	79	#define MTK_NOR_PIO_WR_CMD 0x90
	80	#define MTK_NOR_WRSR_CMD 0x20
	81	#define MTK_NOR_PIO_READ_CMD 0x81
	82	#define MTK_NOR_WR_BUF_ENABLE 0x1
83	#define MTK_NOR_WR_BUF_DISABLE 0x0
84	#define MTK_NOR_ENABLE_SF_CMD 0x30
85	#define MTK_NOR_DUAD_ADDR_EN 0x8
86	#define MTK_NOR_QUAD_READ_EN 0x4
87	#define MTK_NOR_DUAL_ADDR_EN 0x2
88	#define MTK_NOR_DUAL_READ_EN 0x1
89	#define MTK_NOR_DUAL_DISABLE 0x0
90	#define MTK_NOR_FAST_READ 0x1
91
92	#define SFLASH_WRBUF_SIZE 128
93
94	/* Can shift up to 48 bits (6 bytes) of TX/RX */
95	#define MTK_NOR_MAX_RX_TX_SHIFT 6
96	/* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */
97	#define MTK_NOR_MAX_SHIFT 7
8abe904d GM	98	/* nor controller 4-byte address mode enable bit */
8abe904d GM	99	#define MTK_NOR_4B_ADDR_EN BIT(4)
3ce351b5 BC	100
	101	/* Helpers for accessing the program data / shift data registers */
	102	#define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n))
	103	#define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n))
	104
23bae78e	105	struct mtk_nor {
3ce351b5 BC	106	struct spi_nor nor;
	107	struct device *dev;
	108	void __iomem base; / nor flash base address */
	109	struct clk *spi_clk;
	110	struct clk *nor_clk;
	111	};
	112
23bae78e	113	static void mtk_nor_set_read_mode(struct mtk_nor *mtk_nor)
3ce351b5	114	{
23bae78e	115	struct spi_nor *nor = &mtk_nor->nor;
3ce351b5	116
cfc5604c CP	117	switch (nor->read_proto) {
cfc5604c CP	118	case SNOR_PROTO_1_1_1:
23bae78e	119	writeb(nor->read_opcode, mtk_nor->base +
3ce351b5	120	MTK_NOR_PRGDATA3_REG);
23bae78e	121	writeb(MTK_NOR_FAST_READ, mtk_nor->base +
3ce351b5 BC	122	MTK_NOR_CFG1_REG);
3ce351b5 BC	123	break;
cfc5604c	124	case SNOR_PROTO_1_1_2:
23bae78e	125	writeb(nor->read_opcode, mtk_nor->base +
3ce351b5	126	MTK_NOR_PRGDATA3_REG);
23bae78e	127	writeb(MTK_NOR_DUAL_READ_EN, mtk_nor->base +
3ce351b5 BC	128	MTK_NOR_DUAL_REG);
3ce351b5 BC	129	break;
cfc5604c	130	case SNOR_PROTO_1_1_4:
23bae78e	131	writeb(nor->read_opcode, mtk_nor->base +
3ce351b5	132	MTK_NOR_PRGDATA4_REG);
23bae78e	133	writeb(MTK_NOR_QUAD_READ_EN, mtk_nor->base +
3ce351b5 BC	134	MTK_NOR_DUAL_REG);
	135	break;
	136	default:
23bae78e	137	writeb(MTK_NOR_DUAL_DISABLE, mtk_nor->base +
3ce351b5 BC	138	MTK_NOR_DUAL_REG);
	139	break;
	140	}
	141	}
	142
23bae78e	143	static int mtk_nor_execute_cmd(struct mtk_nor *mtk_nor, u8 cmdval)
3ce351b5 BC	144	{
	145	int reg;
	146	u8 val = cmdval & 0x1f;
	147
23bae78e GM	148	writeb(cmdval, mtk_nor->base + MTK_NOR_CMD_REG);
23bae78e GM	149	return readl_poll_timeout(mtk_nor->base + MTK_NOR_CMD_REG, reg,
3ce351b5 BC	150	!(reg & val), 100, 10000);
	151	}
	152
23bae78e	153	static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op,
45397787	154	const u8 tx, size_t txlen, u8 rx, size_t rxlen)
3ce351b5	155	{
45397787	156	size_t len = 1 + txlen + rxlen;
3ce351b5 BC	157	int i, ret, idx;
	158
	159	if (len > MTK_NOR_MAX_SHIFT)
	160	return -EINVAL;
	161
23bae78e	162	writeb(len * 8, mtk_nor->base + MTK_NOR_CNT_REG);
3ce351b5 BC	163
	164	/* start at PRGDATA5, go down to PRGDATA0 */
	165	idx = MTK_NOR_MAX_RX_TX_SHIFT - 1;
	166
	167	/* opcode */
23bae78e	168	writeb(op, mtk_nor->base + MTK_NOR_PRG_REG(idx));
3ce351b5 BC	169	idx--;
	170
	171	/* program TX data */
	172	for (i = 0; i < txlen; i++, idx--)
23bae78e	173	writeb(tx[i], mtk_nor->base + MTK_NOR_PRG_REG(idx));
3ce351b5 BC	174
	175	/* clear out rest of TX registers */
	176	while (idx >= 0) {
23bae78e	177	writeb(0, mtk_nor->base + MTK_NOR_PRG_REG(idx));
3ce351b5 BC	178	idx--;
	179	}
	180
23bae78e	181	ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PRG_CMD);
3ce351b5 BC	182	if (ret)
	183	return ret;
	184
	185	/* restart at first RX byte */
	186	idx = rxlen - 1;
	187
	188	/* read out RX data */
	189	for (i = 0; i < rxlen; i++, idx--)
23bae78e	190	rx[i] = readb(mtk_nor->base + MTK_NOR_SHREG(idx));
3ce351b5 BC	191
	192	return 0;
	193	}
	194
	195	/* Do a WRSR (Write Status Register) command */
45397787	196	static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, const u8 sr)
3ce351b5	197	{
23bae78e GM	198	writeb(sr, mtk_nor->base + MTK_NOR_PRGDATA5_REG);
	199	writeb(8, mtk_nor->base + MTK_NOR_CNT_REG);
	200	return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WRSR_CMD);
3ce351b5 BC	201	}
3ce351b5 BC	202
23bae78e	203	static int mtk_nor_write_buffer_enable(struct mtk_nor *mtk_nor)
3ce351b5 BC	204	{
	205	u8 reg;
	206
	207	/* the bit0 of MTK_NOR_CFG2_REG is pre-fetch buffer
	208	* 0: pre-fetch buffer use for read
	209	* 1: pre-fetch buffer use for page program
	210	*/
23bae78e GM	211	writel(MTK_NOR_WR_BUF_ENABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
23bae78e GM	212	return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
3ce351b5 BC	213	0x01 == (reg & 0x01), 100, 10000);
	214	}
	215
23bae78e	216	static int mtk_nor_write_buffer_disable(struct mtk_nor *mtk_nor)
3ce351b5 BC	217	{
	218	u8 reg;
	219
23bae78e GM	220	writel(MTK_NOR_WR_BUF_DISABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
23bae78e GM	221	return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
3ce351b5 BC	222	MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100,
	223	10000);
	224	}
	225
23bae78e	226	static void mtk_nor_set_addr_width(struct mtk_nor *mtk_nor)
8abe904d GM	227	{
8abe904d GM	228	u8 val;
23bae78e	229	struct spi_nor *nor = &mtk_nor->nor;
8abe904d	230
23bae78e	231	val = readb(mtk_nor->base + MTK_NOR_DUAL_REG);
8abe904d GM	232
	233	switch (nor->addr_width) {
	234	case 3:
	235	val &= ~MTK_NOR_4B_ADDR_EN;
	236	break;
	237	case 4:
	238	val \|= MTK_NOR_4B_ADDR_EN;
	239	break;
	240	default:
23bae78e	241	dev_warn(mtk_nor->dev, "Unexpected address width %u.\n",
8abe904d GM	242	nor->addr_width);
	243	break;
	244	}
	245
23bae78e	246	writeb(val, mtk_nor->base + MTK_NOR_DUAL_REG);
8abe904d GM	247	}
8abe904d GM	248
23bae78e	249	static void mtk_nor_set_addr(struct mtk_nor *mtk_nor, u32 addr)
3ce351b5 BC	250	{
	251	int i;
	252
23bae78e	253	mtk_nor_set_addr_width(mtk_nor);
8abe904d	254
3ce351b5	255	for (i = 0; i < 3; i++) {
23bae78e	256	writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR0_REG + i * 4);
3ce351b5 BC	257	addr >>= 8;
	258	}
	259	/* Last register is non-contiguous */
23bae78e	260	writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR3_REG);
3ce351b5 BC	261	}
3ce351b5 BC	262
23bae78e GM	263	static ssize_t mtk_nor_read(struct spi_nor *nor, loff_t from, size_t length,
23bae78e GM	264	u_char *buffer)
3ce351b5 BC	265	{
	266	int i, ret;
	267	int addr = (int)from;
	268	u8 buf = (u8 )buffer;
23bae78e	269	struct mtk_nor *mtk_nor = nor->priv;
3ce351b5 BC	270
3ce351b5 BC	271	/* set mode for fast read mode ,dual mode or quad mode */
23bae78e GM	272	mtk_nor_set_read_mode(mtk_nor);
23bae78e GM	273	mtk_nor_set_addr(mtk_nor, addr);
3ce351b5	274
2dd087b1	275	for (i = 0; i < length; i++) {
23bae78e	276	ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_READ_CMD);
3ce351b5 BC	277	if (ret < 0)
3ce351b5 BC	278	return ret;
23bae78e	279	buf[i] = readb(mtk_nor->base + MTK_NOR_RDATA_REG);
3ce351b5	280	}
78b400fd	281	return length;
3ce351b5 BC	282	}
3ce351b5 BC	283
23bae78e GM	284	static int mtk_nor_write_single_byte(struct mtk_nor *mtk_nor,
23bae78e GM	285	int addr, int length, u8 *data)
3ce351b5 BC	286	{
	287	int i, ret;
	288
23bae78e	289	mtk_nor_set_addr(mtk_nor, addr);
3ce351b5 BC	290
3ce351b5 BC	291	for (i = 0; i < length; i++) {
23bae78e GM	292	writeb(*data++, mtk_nor->base + MTK_NOR_WDATA_REG);
23bae78e GM	293	ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_WR_CMD);
3ce351b5 BC	294	if (ret < 0)
3ce351b5 BC	295	return ret;
3ce351b5 BC	296	}
	297	return 0;
	298	}
	299
23bae78e GM	300	static int mtk_nor_write_buffer(struct mtk_nor *mtk_nor, int addr,
23bae78e GM	301	const u8 *buf)
3ce351b5 BC	302	{
	303	int i, bufidx, data;
	304
23bae78e	305	mtk_nor_set_addr(mtk_nor, addr);
3ce351b5 BC	306
	307	bufidx = 0;
	308	for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) {
	309	data = buf[bufidx + 3]<<24 \| buf[bufidx + 2]<<16 \|
	310	buf[bufidx + 1]<<8 \| buf[bufidx];
	311	bufidx += 4;
23bae78e	312	writel(data, mtk_nor->base + MTK_NOR_PP_DATA_REG);
3ce351b5	313	}
23bae78e	314	return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WR_CMD);
3ce351b5 BC	315	}
3ce351b5 BC	316
23bae78e GM	317	static ssize_t mtk_nor_write(struct spi_nor *nor, loff_t to, size_t len,
23bae78e GM	318	const u_char *buf)
3ce351b5 BC	319	{
3ce351b5 BC	320	int ret;
23bae78e	321	struct mtk_nor *mtk_nor = nor->priv;
78b400fd	322	size_t i;
3ce351b5	323
23bae78e	324	ret = mtk_nor_write_buffer_enable(mtk_nor);
59451e12	325	if (ret < 0) {
23bae78e	326	dev_warn(mtk_nor->dev, "write buffer enable failed!\n");
59451e12 MS	327	return ret;
59451e12 MS	328	}
3ce351b5	329
78b400fd	330	for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) {
23bae78e	331	ret = mtk_nor_write_buffer(mtk_nor, to, buf);
59451e12	332	if (ret < 0) {
23bae78e	333	dev_err(mtk_nor->dev, "write buffer failed!\n");
59451e12 MS	334	return ret;
59451e12 MS	335	}
3ce351b5 BC	336	to += SFLASH_WRBUF_SIZE;
3ce351b5 BC	337	buf += SFLASH_WRBUF_SIZE;
3ce351b5	338	}
23bae78e	339	ret = mtk_nor_write_buffer_disable(mtk_nor);
59451e12	340	if (ret < 0) {
23bae78e	341	dev_warn(mtk_nor->dev, "write buffer disable failed!\n");
59451e12 MS	342	return ret;
59451e12 MS	343	}
3ce351b5	344
78b400fd	345	if (i < len) {
23bae78e GM	346	ret = mtk_nor_write_single_byte(mtk_nor, to,
23bae78e GM	347	(int)(len - i), (u8 *)buf);
59451e12	348	if (ret < 0) {
23bae78e	349	dev_err(mtk_nor->dev, "write single byte failed!\n");
59451e12 MS	350	return ret;
59451e12 MS	351	}
3ce351b5	352	}
59451e12	353
78b400fd	354	return len;
3ce351b5 BC	355	}
3ce351b5 BC	356
45397787	357	static int mtk_nor_read_reg(struct spi_nor nor, u8 opcode, u8 buf, size_t len)
3ce351b5 BC	358	{
3ce351b5 BC	359	int ret;
23bae78e	360	struct mtk_nor *mtk_nor = nor->priv;
3ce351b5 BC	361
	362	switch (opcode) {
	363	case SPINOR_OP_RDSR:
23bae78e	364	ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_RDSR_CMD);
3ce351b5 BC	365	if (ret < 0)
	366	return ret;
	367	if (len == 1)
23bae78e	368	*buf = readb(mtk_nor->base + MTK_NOR_RDSR_REG);
3ce351b5	369	else
23bae78e	370	dev_err(mtk_nor->dev, "len should be 1 for read status!\n");
3ce351b5 BC	371	break;
3ce351b5 BC	372	default:
23bae78e	373	ret = mtk_nor_do_tx_rx(mtk_nor, opcode, NULL, 0, buf, len);
3ce351b5 BC	374	break;
	375	}
	376	return ret;
	377	}
	378
45397787 TA	379	static int mtk_nor_write_reg(struct spi_nor nor, u8 opcode, const u8 buf,
45397787 TA	380	size_t len)
3ce351b5 BC	381	{
3ce351b5 BC	382	int ret;
23bae78e	383	struct mtk_nor *mtk_nor = nor->priv;
3ce351b5 BC	384
	385	switch (opcode) {
	386	case SPINOR_OP_WRSR:
	387	/* We only handle 1 byte */
23bae78e	388	ret = mtk_nor_wr_sr(mtk_nor, *buf);
3ce351b5 BC	389	break;
3ce351b5 BC	390	default:
23bae78e	391	ret = mtk_nor_do_tx_rx(mtk_nor, opcode, buf, len, NULL, 0);
3ce351b5	392	if (ret)
23bae78e	393	dev_warn(mtk_nor->dev, "write reg failure!\n");
3ce351b5 BC	394	break;
	395	}
	396	return ret;
	397	}
	398
23bae78e	399	static void mtk_nor_disable_clk(struct mtk_nor *mtk_nor)
2ea68b75	400	{
23bae78e GM	401	clk_disable_unprepare(mtk_nor->spi_clk);
23bae78e GM	402	clk_disable_unprepare(mtk_nor->nor_clk);
2ea68b75 GM	403	}
2ea68b75 GM	404
23bae78e	405	static int mtk_nor_enable_clk(struct mtk_nor *mtk_nor)
2ea68b75 GM	406	{
	407	int ret;
	408
23bae78e	409	ret = clk_prepare_enable(mtk_nor->spi_clk);
2ea68b75 GM	410	if (ret)
	411	return ret;
	412
23bae78e	413	ret = clk_prepare_enable(mtk_nor->nor_clk);
2ea68b75	414	if (ret) {
23bae78e	415	clk_disable_unprepare(mtk_nor->spi_clk);
2ea68b75 GM	416	return ret;
	417	}
	418
	419	return 0;
	420	}
	421
45397787 TA	422	static const struct spi_nor_controller_ops mtk_controller_ops = {
	423	.read_reg = mtk_nor_read_reg,
	424	.write_reg = mtk_nor_write_reg,
	425	.read = mtk_nor_read,
	426	.write = mtk_nor_write,
	427	};
	428
23bae78e	429	static int mtk_nor_init(struct mtk_nor *mtk_nor,
92752d99	430	struct device_node *flash_node)
3ce351b5	431	{
cfc5604c	432	const struct spi_nor_hwcaps hwcaps = {
9cca9b3e GM	433	.mask = SNOR_HWCAPS_READ \|
9cca9b3e GM	434	SNOR_HWCAPS_READ_FAST \|
cfc5604c CP	435	SNOR_HWCAPS_READ_1_1_2 \|
	436	SNOR_HWCAPS_PP,
	437	};
3ce351b5 BC	438	int ret;
	439	struct spi_nor *nor;
	440
	441	/* initialize controller to accept commands */
23bae78e	442	writel(MTK_NOR_ENABLE_SF_CMD, mtk_nor->base + MTK_NOR_WRPROT_REG);
3ce351b5	443
23bae78e GM	444	nor = &mtk_nor->nor;
	445	nor->dev = mtk_nor->dev;
	446	nor->priv = mtk_nor;
3ce351b5	447	spi_nor_set_flash_node(nor, flash_node);
45397787	448	nor->controller_ops = &mtk_controller_ops;
3ce351b5	449
3ce351b5 BC	450	nor->mtd.name = "mtk_nor";
3ce351b5 BC	451	/* initialized with NULL */
cfc5604c	452	ret = spi_nor_scan(nor, NULL, &hwcaps);
3ce351b5 BC	453	if (ret)
	454	return ret;
	455
	456	return mtd_device_register(&nor->mtd, NULL, 0);
	457	}
	458
	459	static int mtk_nor_drv_probe(struct platform_device *pdev)
	460	{
	461	struct device_node *flash_np;
	462	struct resource *res;
	463	int ret;
23bae78e	464	struct mtk_nor *mtk_nor;
3ce351b5 BC	465
	466	if (!pdev->dev.of_node) {
	467	dev_err(&pdev->dev, "No DT found\n");
	468	return -EINVAL;
	469	}
	470
23bae78e GM	471	mtk_nor = devm_kzalloc(&pdev->dev, sizeof(*mtk_nor), GFP_KERNEL);
23bae78e GM	472	if (!mtk_nor)
3ce351b5	473	return -ENOMEM;
23bae78e	474	platform_set_drvdata(pdev, mtk_nor);
3ce351b5 BC	475
3ce351b5 BC	476	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
23bae78e GM	477	mtk_nor->base = devm_ioremap_resource(&pdev->dev, res);
	478	if (IS_ERR(mtk_nor->base))
	479	return PTR_ERR(mtk_nor->base);
3ce351b5	480
23bae78e GM	481	mtk_nor->spi_clk = devm_clk_get(&pdev->dev, "spi");
	482	if (IS_ERR(mtk_nor->spi_clk))
	483	return PTR_ERR(mtk_nor->spi_clk);
3ce351b5	484
23bae78e GM	485	mtk_nor->nor_clk = devm_clk_get(&pdev->dev, "sf");
	486	if (IS_ERR(mtk_nor->nor_clk))
	487	return PTR_ERR(mtk_nor->nor_clk);
3ce351b5	488
23bae78e	489	mtk_nor->dev = &pdev->dev;
2ea68b75	490
23bae78e	491	ret = mtk_nor_enable_clk(mtk_nor);
3ce351b5 BC	492	if (ret)
	493	return ret;
	494
3ce351b5 BC	495	/* only support one attached flash */
	496	flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
	497	if (!flash_np) {
	498	dev_err(&pdev->dev, "no SPI flash device to configure\n");
	499	ret = -ENODEV;
	500	goto nor_free;
	501	}
23bae78e	502	ret = mtk_nor_init(mtk_nor, flash_np);
3ce351b5 BC	503
3ce351b5 BC	504	nor_free:
2ea68b75	505	if (ret)
23bae78e	506	mtk_nor_disable_clk(mtk_nor);
2ea68b75	507
3ce351b5 BC	508	return ret;
	509	}
	510
	511	static int mtk_nor_drv_remove(struct platform_device *pdev)
	512	{
23bae78e	513	struct mtk_nor *mtk_nor = platform_get_drvdata(pdev);
3ce351b5	514
23bae78e	515	mtk_nor_disable_clk(mtk_nor);
2ea68b75 GM	516
	517	return 0;
	518	}
	519
	520	#ifdef CONFIG_PM_SLEEP
	521	static int mtk_nor_suspend(struct device *dev)
	522	{
23bae78e	523	struct mtk_nor *mtk_nor = dev_get_drvdata(dev);
2ea68b75	524
23bae78e	525	mtk_nor_disable_clk(mtk_nor);
2ea68b75	526
3ce351b5 BC	527	return 0;
	528	}
	529
2ea68b75 GM	530	static int mtk_nor_resume(struct device *dev)
2ea68b75 GM	531	{
23bae78e	532	struct mtk_nor *mtk_nor = dev_get_drvdata(dev);
2ea68b75	533
23bae78e	534	return mtk_nor_enable_clk(mtk_nor);
2ea68b75 GM	535	}
	536
	537	static const struct dev_pm_ops mtk_nor_dev_pm_ops = {
	538	.suspend = mtk_nor_suspend,
	539	.resume = mtk_nor_resume,
	540	};
	541
	542	#define MTK_NOR_DEV_PM_OPS (&mtk_nor_dev_pm_ops)
	543	#else
	544	#define MTK_NOR_DEV_PM_OPS NULL
	545	#endif
	546
3ce351b5 BC	547	static const struct of_device_id mtk_nor_of_ids[] = {
	548	{ .compatible = "mediatek,mt8173-nor"},
	549	{ /* sentinel */ }
	550	};
	551	MODULE_DEVICE_TABLE(of, mtk_nor_of_ids);
	552
	553	static struct platform_driver mtk_nor_driver = {
	554	.probe = mtk_nor_drv_probe,
	555	.remove = mtk_nor_drv_remove,
	556	.driver = {
	557	.name = "mtk-nor",
2ea68b75	558	.pm = MTK_NOR_DEV_PM_OPS,
3ce351b5 BC	559	.of_match_table = mtk_nor_of_ids,
	560	},
	561	};
	562
	563	module_platform_driver(mtk_nor_driver);
	564	MODULE_LICENSE("GPL v2");
	565	MODULE_DESCRIPTION("MediaTek SPI NOR Flash Driver");