Commit | Line | Data |
---|---|---|
2f9f7628 | 1 | /* |
fa0a8c71 | 2 | * MTD SPI driver for ST M25Pxx (and similar) serial flash chips |
2f9f7628 ML |
3 | * |
4 | * Author: Mike Lavender, mike@steroidmicros.com | |
5 | * | |
6 | * Copyright (c) 2005, Intec Automation Inc. | |
7 | * | |
8 | * Some parts are based on lart.c by Abraham Van Der Merwe | |
9 | * | |
10 | * Cleaned up and generalized based on mtd_dataflash.c | |
11 | * | |
12 | * This code is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/interrupt.h> | |
7d5230ea | 22 | #include <linux/mutex.h> |
d85316ac | 23 | #include <linux/math64.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
d43c36dc | 25 | #include <linux/sched.h> |
b34bc037 | 26 | #include <linux/mod_devicetable.h> |
7d5230ea | 27 | |
2f9f7628 ML |
28 | #include <linux/mtd/mtd.h> |
29 | #include <linux/mtd/partitions.h> | |
7d5230ea | 30 | |
2f9f7628 ML |
31 | #include <linux/spi/spi.h> |
32 | #include <linux/spi/flash.h> | |
33 | ||
2f9f7628 | 34 | /* Flash opcodes. */ |
fa0a8c71 DB |
35 | #define OPCODE_WREN 0x06 /* Write enable */ |
36 | #define OPCODE_RDSR 0x05 /* Read status register */ | |
72289824 | 37 | #define OPCODE_WRSR 0x01 /* Write status register 1 byte */ |
2230b76b | 38 | #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ |
fa0a8c71 DB |
39 | #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ |
40 | #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ | |
7854643a | 41 | #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ |
02d087db | 42 | #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ |
7854643a | 43 | #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ |
02d087db | 44 | #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ |
2f9f7628 ML |
45 | #define OPCODE_RDID 0x9f /* Read JEDEC ID */ |
46 | ||
49aac4ae GY |
47 | /* Used for SST flashes only. */ |
48 | #define OPCODE_BP 0x02 /* Byte program */ | |
49 | #define OPCODE_WRDI 0x04 /* Write disable */ | |
50 | #define OPCODE_AAI_WP 0xad /* Auto address increment word program */ | |
51 | ||
2f9f7628 ML |
52 | /* Status Register bits. */ |
53 | #define SR_WIP 1 /* Write in progress */ | |
54 | #define SR_WEL 2 /* Write enable latch */ | |
fa0a8c71 | 55 | /* meaning of other SR_* bits may differ between vendors */ |
2f9f7628 ML |
56 | #define SR_BP0 4 /* Block protect 0 */ |
57 | #define SR_BP1 8 /* Block protect 1 */ | |
58 | #define SR_BP2 0x10 /* Block protect 2 */ | |
59 | #define SR_SRWD 0x80 /* SR write protect */ | |
60 | ||
61 | /* Define max times to check status register before we give up. */ | |
89bb871e | 62 | #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */ |
837479d2 | 63 | #define MAX_CMD_SIZE 4 |
2f9f7628 | 64 | |
2230b76b BW |
65 | #ifdef CONFIG_M25PXX_USE_FAST_READ |
66 | #define OPCODE_READ OPCODE_FAST_READ | |
67 | #define FAST_READ_DUMMY_BYTE 1 | |
68 | #else | |
69 | #define OPCODE_READ OPCODE_NORM_READ | |
70 | #define FAST_READ_DUMMY_BYTE 0 | |
71 | #endif | |
2f9f7628 | 72 | |
2f9f7628 ML |
73 | /****************************************************************************/ |
74 | ||
75 | struct m25p { | |
76 | struct spi_device *spi; | |
7d5230ea | 77 | struct mutex lock; |
2f9f7628 | 78 | struct mtd_info mtd; |
fa0a8c71 | 79 | unsigned partitioned:1; |
837479d2 AV |
80 | u16 page_size; |
81 | u16 addr_width; | |
fa0a8c71 | 82 | u8 erase_opcode; |
61c3506c | 83 | u8 *command; |
2f9f7628 ML |
84 | }; |
85 | ||
86 | static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) | |
87 | { | |
88 | return container_of(mtd, struct m25p, mtd); | |
89 | } | |
90 | ||
91 | /****************************************************************************/ | |
92 | ||
93 | /* | |
94 | * Internal helper functions | |
95 | */ | |
96 | ||
97 | /* | |
98 | * Read the status register, returning its value in the location | |
99 | * Return the status register value. | |
100 | * Returns negative if error occurred. | |
101 | */ | |
102 | static int read_sr(struct m25p *flash) | |
103 | { | |
104 | ssize_t retval; | |
105 | u8 code = OPCODE_RDSR; | |
106 | u8 val; | |
107 | ||
108 | retval = spi_write_then_read(flash->spi, &code, 1, &val, 1); | |
109 | ||
110 | if (retval < 0) { | |
111 | dev_err(&flash->spi->dev, "error %d reading SR\n", | |
112 | (int) retval); | |
113 | return retval; | |
114 | } | |
115 | ||
116 | return val; | |
117 | } | |
118 | ||
72289824 MH |
119 | /* |
120 | * Write status register 1 byte | |
121 | * Returns negative if error occurred. | |
122 | */ | |
123 | static int write_sr(struct m25p *flash, u8 val) | |
124 | { | |
125 | flash->command[0] = OPCODE_WRSR; | |
126 | flash->command[1] = val; | |
127 | ||
128 | return spi_write(flash->spi, flash->command, 2); | |
129 | } | |
2f9f7628 ML |
130 | |
131 | /* | |
132 | * Set write enable latch with Write Enable command. | |
133 | * Returns negative if error occurred. | |
134 | */ | |
135 | static inline int write_enable(struct m25p *flash) | |
136 | { | |
137 | u8 code = OPCODE_WREN; | |
138 | ||
8a1a6272 | 139 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); |
2f9f7628 ML |
140 | } |
141 | ||
49aac4ae GY |
142 | /* |
143 | * Send write disble instruction to the chip. | |
144 | */ | |
145 | static inline int write_disable(struct m25p *flash) | |
146 | { | |
147 | u8 code = OPCODE_WRDI; | |
148 | ||
149 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); | |
150 | } | |
2f9f7628 ML |
151 | |
152 | /* | |
153 | * Service routine to read status register until ready, or timeout occurs. | |
154 | * Returns non-zero if error. | |
155 | */ | |
156 | static int wait_till_ready(struct m25p *flash) | |
157 | { | |
cd1a6de7 | 158 | unsigned long deadline; |
2f9f7628 ML |
159 | int sr; |
160 | ||
cd1a6de7 PH |
161 | deadline = jiffies + MAX_READY_WAIT_JIFFIES; |
162 | ||
163 | do { | |
2f9f7628 ML |
164 | if ((sr = read_sr(flash)) < 0) |
165 | break; | |
166 | else if (!(sr & SR_WIP)) | |
167 | return 0; | |
168 | ||
cd1a6de7 PH |
169 | cond_resched(); |
170 | ||
171 | } while (!time_after_eq(jiffies, deadline)); | |
2f9f7628 ML |
172 | |
173 | return 1; | |
174 | } | |
175 | ||
faff3750 CG |
176 | /* |
177 | * Erase the whole flash memory | |
178 | * | |
179 | * Returns 0 if successful, non-zero otherwise. | |
180 | */ | |
7854643a | 181 | static int erase_chip(struct m25p *flash) |
faff3750 | 182 | { |
d85316ac | 183 | DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %lldKiB\n", |
160bbab3 KS |
184 | dev_name(&flash->spi->dev), __func__, |
185 | (long long)(flash->mtd.size >> 10)); | |
faff3750 CG |
186 | |
187 | /* Wait until finished previous write command. */ | |
188 | if (wait_till_ready(flash)) | |
189 | return 1; | |
190 | ||
191 | /* Send write enable, then erase commands. */ | |
192 | write_enable(flash); | |
193 | ||
194 | /* Set up command buffer. */ | |
7854643a | 195 | flash->command[0] = OPCODE_CHIP_ERASE; |
faff3750 CG |
196 | |
197 | spi_write(flash->spi, flash->command, 1); | |
198 | ||
199 | return 0; | |
200 | } | |
2f9f7628 | 201 | |
837479d2 AV |
202 | static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd) |
203 | { | |
204 | /* opcode is in cmd[0] */ | |
205 | cmd[1] = addr >> (flash->addr_width * 8 - 8); | |
206 | cmd[2] = addr >> (flash->addr_width * 8 - 16); | |
207 | cmd[3] = addr >> (flash->addr_width * 8 - 24); | |
208 | } | |
209 | ||
210 | static int m25p_cmdsz(struct m25p *flash) | |
211 | { | |
212 | return 1 + flash->addr_width; | |
213 | } | |
214 | ||
2f9f7628 ML |
215 | /* |
216 | * Erase one sector of flash memory at offset ``offset'' which is any | |
217 | * address within the sector which should be erased. | |
218 | * | |
219 | * Returns 0 if successful, non-zero otherwise. | |
220 | */ | |
221 | static int erase_sector(struct m25p *flash, u32 offset) | |
222 | { | |
02d087db | 223 | DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %dKiB at 0x%08x\n", |
160bbab3 | 224 | dev_name(&flash->spi->dev), __func__, |
fa0a8c71 | 225 | flash->mtd.erasesize / 1024, offset); |
2f9f7628 ML |
226 | |
227 | /* Wait until finished previous write command. */ | |
228 | if (wait_till_ready(flash)) | |
229 | return 1; | |
230 | ||
231 | /* Send write enable, then erase commands. */ | |
232 | write_enable(flash); | |
233 | ||
234 | /* Set up command buffer. */ | |
fa0a8c71 | 235 | flash->command[0] = flash->erase_opcode; |
837479d2 | 236 | m25p_addr2cmd(flash, offset, flash->command); |
2f9f7628 | 237 | |
837479d2 | 238 | spi_write(flash->spi, flash->command, m25p_cmdsz(flash)); |
2f9f7628 ML |
239 | |
240 | return 0; | |
241 | } | |
242 | ||
243 | /****************************************************************************/ | |
244 | ||
245 | /* | |
246 | * MTD implementation | |
247 | */ | |
248 | ||
249 | /* | |
250 | * Erase an address range on the flash chip. The address range may extend | |
251 | * one or more erase sectors. Return an error is there is a problem erasing. | |
252 | */ | |
253 | static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) | |
254 | { | |
255 | struct m25p *flash = mtd_to_m25p(mtd); | |
256 | u32 addr,len; | |
d85316ac | 257 | uint32_t rem; |
2f9f7628 | 258 | |
d85316ac | 259 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%llx, len %lld\n", |
160bbab3 KS |
260 | dev_name(&flash->spi->dev), __func__, "at", |
261 | (long long)instr->addr, (long long)instr->len); | |
2f9f7628 ML |
262 | |
263 | /* sanity checks */ | |
264 | if (instr->addr + instr->len > flash->mtd.size) | |
265 | return -EINVAL; | |
d85316ac AB |
266 | div_u64_rem(instr->len, mtd->erasesize, &rem); |
267 | if (rem) | |
2f9f7628 | 268 | return -EINVAL; |
2f9f7628 ML |
269 | |
270 | addr = instr->addr; | |
271 | len = instr->len; | |
272 | ||
7d5230ea | 273 | mutex_lock(&flash->lock); |
2f9f7628 | 274 | |
7854643a | 275 | /* whole-chip erase? */ |
3f33b0aa SF |
276 | if (len == flash->mtd.size) { |
277 | if (erase_chip(flash)) { | |
278 | instr->state = MTD_ERASE_FAILED; | |
279 | mutex_unlock(&flash->lock); | |
280 | return -EIO; | |
281 | } | |
7854643a CG |
282 | |
283 | /* REVISIT in some cases we could speed up erasing large regions | |
284 | * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up | |
285 | * to use "small sector erase", but that's not always optimal. | |
286 | */ | |
287 | ||
288 | /* "sector"-at-a-time erase */ | |
faff3750 CG |
289 | } else { |
290 | while (len) { | |
291 | if (erase_sector(flash, addr)) { | |
292 | instr->state = MTD_ERASE_FAILED; | |
293 | mutex_unlock(&flash->lock); | |
294 | return -EIO; | |
295 | } | |
296 | ||
297 | addr += mtd->erasesize; | |
298 | len -= mtd->erasesize; | |
2f9f7628 | 299 | } |
2f9f7628 ML |
300 | } |
301 | ||
7d5230ea | 302 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
303 | |
304 | instr->state = MTD_ERASE_DONE; | |
305 | mtd_erase_callback(instr); | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
310 | /* | |
311 | * Read an address range from the flash chip. The address range | |
312 | * may be any size provided it is within the physical boundaries. | |
313 | */ | |
314 | static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, | |
315 | size_t *retlen, u_char *buf) | |
316 | { | |
317 | struct m25p *flash = mtd_to_m25p(mtd); | |
318 | struct spi_transfer t[2]; | |
319 | struct spi_message m; | |
320 | ||
321 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n", | |
160bbab3 | 322 | dev_name(&flash->spi->dev), __func__, "from", |
2f9f7628 ML |
323 | (u32)from, len); |
324 | ||
325 | /* sanity checks */ | |
326 | if (!len) | |
327 | return 0; | |
328 | ||
329 | if (from + len > flash->mtd.size) | |
330 | return -EINVAL; | |
331 | ||
8275c642 VW |
332 | spi_message_init(&m); |
333 | memset(t, 0, (sizeof t)); | |
334 | ||
2230b76b BW |
335 | /* NOTE: |
336 | * OPCODE_FAST_READ (if available) is faster. | |
337 | * Should add 1 byte DUMMY_BYTE. | |
338 | */ | |
8275c642 | 339 | t[0].tx_buf = flash->command; |
837479d2 | 340 | t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE; |
8275c642 VW |
341 | spi_message_add_tail(&t[0], &m); |
342 | ||
343 | t[1].rx_buf = buf; | |
344 | t[1].len = len; | |
345 | spi_message_add_tail(&t[1], &m); | |
346 | ||
347 | /* Byte count starts at zero. */ | |
348 | if (retlen) | |
349 | *retlen = 0; | |
350 | ||
7d5230ea | 351 | mutex_lock(&flash->lock); |
2f9f7628 ML |
352 | |
353 | /* Wait till previous write/erase is done. */ | |
354 | if (wait_till_ready(flash)) { | |
355 | /* REVISIT status return?? */ | |
7d5230ea | 356 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
357 | return 1; |
358 | } | |
359 | ||
fa0a8c71 DB |
360 | /* FIXME switch to OPCODE_FAST_READ. It's required for higher |
361 | * clocks; and at this writing, every chip this driver handles | |
362 | * supports that opcode. | |
363 | */ | |
2f9f7628 ML |
364 | |
365 | /* Set up the write data buffer. */ | |
366 | flash->command[0] = OPCODE_READ; | |
837479d2 | 367 | m25p_addr2cmd(flash, from, flash->command); |
2f9f7628 | 368 | |
2f9f7628 ML |
369 | spi_sync(flash->spi, &m); |
370 | ||
837479d2 | 371 | *retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE; |
2f9f7628 | 372 | |
7d5230ea | 373 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
374 | |
375 | return 0; | |
376 | } | |
377 | ||
378 | /* | |
379 | * Write an address range to the flash chip. Data must be written in | |
380 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
381 | * it is within the physical boundaries. | |
382 | */ | |
383 | static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, | |
384 | size_t *retlen, const u_char *buf) | |
385 | { | |
386 | struct m25p *flash = mtd_to_m25p(mtd); | |
387 | u32 page_offset, page_size; | |
388 | struct spi_transfer t[2]; | |
389 | struct spi_message m; | |
390 | ||
391 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n", | |
160bbab3 | 392 | dev_name(&flash->spi->dev), __func__, "to", |
2f9f7628 ML |
393 | (u32)to, len); |
394 | ||
395 | if (retlen) | |
396 | *retlen = 0; | |
397 | ||
398 | /* sanity checks */ | |
399 | if (!len) | |
400 | return(0); | |
401 | ||
402 | if (to + len > flash->mtd.size) | |
403 | return -EINVAL; | |
404 | ||
8275c642 VW |
405 | spi_message_init(&m); |
406 | memset(t, 0, (sizeof t)); | |
407 | ||
408 | t[0].tx_buf = flash->command; | |
837479d2 | 409 | t[0].len = m25p_cmdsz(flash); |
8275c642 VW |
410 | spi_message_add_tail(&t[0], &m); |
411 | ||
412 | t[1].tx_buf = buf; | |
413 | spi_message_add_tail(&t[1], &m); | |
414 | ||
7d5230ea | 415 | mutex_lock(&flash->lock); |
2f9f7628 ML |
416 | |
417 | /* Wait until finished previous write command. */ | |
bc018863 CG |
418 | if (wait_till_ready(flash)) { |
419 | mutex_unlock(&flash->lock); | |
2f9f7628 | 420 | return 1; |
bc018863 | 421 | } |
2f9f7628 ML |
422 | |
423 | write_enable(flash); | |
424 | ||
2f9f7628 ML |
425 | /* Set up the opcode in the write buffer. */ |
426 | flash->command[0] = OPCODE_PP; | |
837479d2 | 427 | m25p_addr2cmd(flash, to, flash->command); |
2f9f7628 | 428 | |
837479d2 | 429 | page_offset = to & (flash->page_size - 1); |
2f9f7628 ML |
430 | |
431 | /* do all the bytes fit onto one page? */ | |
837479d2 | 432 | if (page_offset + len <= flash->page_size) { |
2f9f7628 ML |
433 | t[1].len = len; |
434 | ||
435 | spi_sync(flash->spi, &m); | |
436 | ||
837479d2 | 437 | *retlen = m.actual_length - m25p_cmdsz(flash); |
2f9f7628 ML |
438 | } else { |
439 | u32 i; | |
440 | ||
441 | /* the size of data remaining on the first page */ | |
837479d2 | 442 | page_size = flash->page_size - page_offset; |
2f9f7628 | 443 | |
2f9f7628 ML |
444 | t[1].len = page_size; |
445 | spi_sync(flash->spi, &m); | |
446 | ||
837479d2 | 447 | *retlen = m.actual_length - m25p_cmdsz(flash); |
2f9f7628 | 448 | |
837479d2 | 449 | /* write everything in flash->page_size chunks */ |
2f9f7628 ML |
450 | for (i = page_size; i < len; i += page_size) { |
451 | page_size = len - i; | |
837479d2 AV |
452 | if (page_size > flash->page_size) |
453 | page_size = flash->page_size; | |
2f9f7628 ML |
454 | |
455 | /* write the next page to flash */ | |
837479d2 | 456 | m25p_addr2cmd(flash, to + i, flash->command); |
2f9f7628 ML |
457 | |
458 | t[1].tx_buf = buf + i; | |
459 | t[1].len = page_size; | |
460 | ||
461 | wait_till_ready(flash); | |
462 | ||
463 | write_enable(flash); | |
464 | ||
465 | spi_sync(flash->spi, &m); | |
466 | ||
7111763d | 467 | if (retlen) |
837479d2 | 468 | *retlen += m.actual_length - m25p_cmdsz(flash); |
7d5230ea DB |
469 | } |
470 | } | |
2f9f7628 | 471 | |
7d5230ea | 472 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
473 | |
474 | return 0; | |
475 | } | |
476 | ||
49aac4ae GY |
477 | static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, |
478 | size_t *retlen, const u_char *buf) | |
479 | { | |
480 | struct m25p *flash = mtd_to_m25p(mtd); | |
481 | struct spi_transfer t[2]; | |
482 | struct spi_message m; | |
483 | size_t actual; | |
484 | int cmd_sz, ret; | |
485 | ||
486 | if (retlen) | |
487 | *retlen = 0; | |
488 | ||
489 | /* sanity checks */ | |
490 | if (!len) | |
491 | return 0; | |
492 | ||
493 | if (to + len > flash->mtd.size) | |
494 | return -EINVAL; | |
495 | ||
496 | spi_message_init(&m); | |
497 | memset(t, 0, (sizeof t)); | |
498 | ||
499 | t[0].tx_buf = flash->command; | |
837479d2 | 500 | t[0].len = m25p_cmdsz(flash); |
49aac4ae GY |
501 | spi_message_add_tail(&t[0], &m); |
502 | ||
503 | t[1].tx_buf = buf; | |
504 | spi_message_add_tail(&t[1], &m); | |
505 | ||
506 | mutex_lock(&flash->lock); | |
507 | ||
508 | /* Wait until finished previous write command. */ | |
509 | ret = wait_till_ready(flash); | |
510 | if (ret) | |
511 | goto time_out; | |
512 | ||
513 | write_enable(flash); | |
514 | ||
515 | actual = to % 2; | |
516 | /* Start write from odd address. */ | |
517 | if (actual) { | |
518 | flash->command[0] = OPCODE_BP; | |
837479d2 | 519 | m25p_addr2cmd(flash, to, flash->command); |
49aac4ae GY |
520 | |
521 | /* write one byte. */ | |
522 | t[1].len = 1; | |
523 | spi_sync(flash->spi, &m); | |
524 | ret = wait_till_ready(flash); | |
525 | if (ret) | |
526 | goto time_out; | |
837479d2 | 527 | *retlen += m.actual_length - m25p_cmdsz(flash); |
49aac4ae GY |
528 | } |
529 | to += actual; | |
530 | ||
531 | flash->command[0] = OPCODE_AAI_WP; | |
837479d2 | 532 | m25p_addr2cmd(flash, to, flash->command); |
49aac4ae GY |
533 | |
534 | /* Write out most of the data here. */ | |
837479d2 | 535 | cmd_sz = m25p_cmdsz(flash); |
49aac4ae GY |
536 | for (; actual < len - 1; actual += 2) { |
537 | t[0].len = cmd_sz; | |
538 | /* write two bytes. */ | |
539 | t[1].len = 2; | |
540 | t[1].tx_buf = buf + actual; | |
541 | ||
542 | spi_sync(flash->spi, &m); | |
543 | ret = wait_till_ready(flash); | |
544 | if (ret) | |
545 | goto time_out; | |
546 | *retlen += m.actual_length - cmd_sz; | |
547 | cmd_sz = 1; | |
548 | to += 2; | |
549 | } | |
550 | write_disable(flash); | |
551 | ret = wait_till_ready(flash); | |
552 | if (ret) | |
553 | goto time_out; | |
554 | ||
555 | /* Write out trailing byte if it exists. */ | |
556 | if (actual != len) { | |
557 | write_enable(flash); | |
558 | flash->command[0] = OPCODE_BP; | |
837479d2 AV |
559 | m25p_addr2cmd(flash, to, flash->command); |
560 | t[0].len = m25p_cmdsz(flash); | |
49aac4ae GY |
561 | t[1].len = 1; |
562 | t[1].tx_buf = buf + actual; | |
563 | ||
564 | spi_sync(flash->spi, &m); | |
565 | ret = wait_till_ready(flash); | |
566 | if (ret) | |
567 | goto time_out; | |
837479d2 | 568 | *retlen += m.actual_length - m25p_cmdsz(flash); |
49aac4ae GY |
569 | write_disable(flash); |
570 | } | |
571 | ||
572 | time_out: | |
573 | mutex_unlock(&flash->lock); | |
574 | return ret; | |
575 | } | |
2f9f7628 ML |
576 | |
577 | /****************************************************************************/ | |
578 | ||
579 | /* | |
580 | * SPI device driver setup and teardown | |
581 | */ | |
582 | ||
583 | struct flash_info { | |
fa0a8c71 DB |
584 | /* JEDEC id zero means "no ID" (most older chips); otherwise it has |
585 | * a high byte of zero plus three data bytes: the manufacturer id, | |
586 | * then a two byte device id. | |
587 | */ | |
588 | u32 jedec_id; | |
d0e8c47c | 589 | u16 ext_id; |
fa0a8c71 DB |
590 | |
591 | /* The size listed here is what works with OPCODE_SE, which isn't | |
592 | * necessarily called a "sector" by the vendor. | |
593 | */ | |
2f9f7628 | 594 | unsigned sector_size; |
fa0a8c71 DB |
595 | u16 n_sectors; |
596 | ||
837479d2 AV |
597 | u16 page_size; |
598 | u16 addr_width; | |
599 | ||
fa0a8c71 DB |
600 | u16 flags; |
601 | #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ | |
837479d2 | 602 | #define M25P_NO_ERASE 0x02 /* No erase command needed */ |
2f9f7628 ML |
603 | }; |
604 | ||
b34bc037 AV |
605 | #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
606 | ((kernel_ulong_t)&(struct flash_info) { \ | |
607 | .jedec_id = (_jedec_id), \ | |
608 | .ext_id = (_ext_id), \ | |
609 | .sector_size = (_sector_size), \ | |
610 | .n_sectors = (_n_sectors), \ | |
837479d2 AV |
611 | .page_size = 256, \ |
612 | .addr_width = 3, \ | |
b34bc037 AV |
613 | .flags = (_flags), \ |
614 | }) | |
fa0a8c71 | 615 | |
837479d2 AV |
616 | #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \ |
617 | ((kernel_ulong_t)&(struct flash_info) { \ | |
618 | .sector_size = (_sector_size), \ | |
619 | .n_sectors = (_n_sectors), \ | |
620 | .page_size = (_page_size), \ | |
621 | .addr_width = (_addr_width), \ | |
622 | .flags = M25P_NO_ERASE, \ | |
623 | }) | |
fa0a8c71 DB |
624 | |
625 | /* NOTE: double check command sets and memory organization when you add | |
626 | * more flash chips. This current list focusses on newer chips, which | |
627 | * have been converging on command sets which including JEDEC ID. | |
628 | */ | |
b34bc037 | 629 | static const struct spi_device_id m25p_ids[] = { |
fa0a8c71 | 630 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
b34bc037 AV |
631 | { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, |
632 | { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, | |
fa0a8c71 | 633 | |
b34bc037 AV |
634 | { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, |
635 | { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, | |
fa0a8c71 | 636 | |
b34bc037 AV |
637 | { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, |
638 | { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, | |
639 | { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, | |
640 | { "at26df321", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, | |
fa0a8c71 | 641 | |
ab1ff210 | 642 | /* Macronix */ |
df0094d7 | 643 | { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, |
b34bc037 AV |
644 | { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) }, |
645 | { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) }, | |
646 | { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, | |
647 | { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, | |
ab1ff210 | 648 | |
fa0a8c71 DB |
649 | /* Spansion -- single (large) sector size only, at least |
650 | * for the chips listed here (without boot sectors). | |
651 | */ | |
b34bc037 AV |
652 | { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, |
653 | { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, | |
654 | { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, | |
655 | { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, | |
656 | { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, | |
657 | { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, | |
658 | { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, | |
659 | { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) }, | |
660 | { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) }, | |
fa0a8c71 DB |
661 | |
662 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
b34bc037 AV |
663 | { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K) }, |
664 | { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K) }, | |
665 | { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K) }, | |
666 | { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K) }, | |
667 | { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K) }, | |
668 | { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K) }, | |
669 | { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K) }, | |
670 | { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K) }, | |
fa0a8c71 DB |
671 | |
672 | /* ST Microelectronics -- newer production may have feature updates */ | |
b34bc037 AV |
673 | { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, |
674 | { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, | |
675 | { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, | |
676 | { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, | |
677 | { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, | |
678 | { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, | |
679 | { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, | |
680 | { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, | |
681 | { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, | |
682 | ||
683 | { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, | |
684 | { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, | |
685 | { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, | |
686 | ||
687 | { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, | |
688 | { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, | |
fa0a8c71 | 689 | |
02d087db | 690 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ |
b34bc037 AV |
691 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, |
692 | { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, | |
693 | { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, | |
694 | { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, | |
695 | { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, | |
696 | { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, | |
697 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, | |
837479d2 AV |
698 | |
699 | /* Catalyst / On Semiconductor -- non-JEDEC */ | |
700 | { "cat25c11", CAT25_INFO( 16, 8, 16, 1) }, | |
701 | { "cat25c03", CAT25_INFO( 32, 8, 16, 2) }, | |
702 | { "cat25c09", CAT25_INFO( 128, 8, 32, 2) }, | |
703 | { "cat25c17", CAT25_INFO( 256, 8, 32, 2) }, | |
704 | { "cat25128", CAT25_INFO(2048, 8, 64, 2) }, | |
b34bc037 | 705 | { }, |
2f9f7628 | 706 | }; |
b34bc037 | 707 | MODULE_DEVICE_TABLE(spi, m25p_ids); |
2f9f7628 | 708 | |
b34bc037 | 709 | static const struct spi_device_id *__devinit jedec_probe(struct spi_device *spi) |
fa0a8c71 DB |
710 | { |
711 | int tmp; | |
712 | u8 code = OPCODE_RDID; | |
daa84735 | 713 | u8 id[5]; |
fa0a8c71 | 714 | u32 jedec; |
d0e8c47c | 715 | u16 ext_jedec; |
fa0a8c71 DB |
716 | struct flash_info *info; |
717 | ||
718 | /* JEDEC also defines an optional "extended device information" | |
719 | * string for after vendor-specific data, after the three bytes | |
720 | * we use here. Supporting some chips might require using it. | |
721 | */ | |
daa84735 | 722 | tmp = spi_write_then_read(spi, &code, 1, id, 5); |
fa0a8c71 DB |
723 | if (tmp < 0) { |
724 | DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n", | |
160bbab3 | 725 | dev_name(&spi->dev), tmp); |
fa0a8c71 DB |
726 | return NULL; |
727 | } | |
728 | jedec = id[0]; | |
729 | jedec = jedec << 8; | |
730 | jedec |= id[1]; | |
731 | jedec = jedec << 8; | |
732 | jedec |= id[2]; | |
733 | ||
18c6182b AV |
734 | /* |
735 | * Some chips (like Numonyx M25P80) have JEDEC and non-JEDEC variants, | |
736 | * which depend on technology process. Officially RDID command doesn't | |
737 | * exist for non-JEDEC chips, but for compatibility they return ID 0. | |
738 | */ | |
739 | if (jedec == 0) | |
740 | return NULL; | |
741 | ||
d0e8c47c CG |
742 | ext_jedec = id[3] << 8 | id[4]; |
743 | ||
b34bc037 AV |
744 | for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) { |
745 | info = (void *)m25p_ids[tmp].driver_data; | |
a3d3f73c | 746 | if (info->jedec_id == jedec) { |
9168ab86 | 747 | if (info->ext_id != 0 && info->ext_id != ext_jedec) |
d0e8c47c | 748 | continue; |
b34bc037 | 749 | return &m25p_ids[tmp]; |
a3d3f73c | 750 | } |
fa0a8c71 | 751 | } |
fa0a8c71 DB |
752 | return NULL; |
753 | } | |
754 | ||
755 | ||
2f9f7628 ML |
756 | /* |
757 | * board specific setup should have ensured the SPI clock used here | |
758 | * matches what the READ command supports, at least until this driver | |
759 | * understands FAST_READ (for clocks over 25 MHz). | |
760 | */ | |
761 | static int __devinit m25p_probe(struct spi_device *spi) | |
762 | { | |
18c6182b | 763 | const struct spi_device_id *id = spi_get_device_id(spi); |
2f9f7628 ML |
764 | struct flash_platform_data *data; |
765 | struct m25p *flash; | |
766 | struct flash_info *info; | |
767 | unsigned i; | |
768 | ||
769 | /* Platform data helps sort out which chip type we have, as | |
fa0a8c71 DB |
770 | * well as how this board partitions it. If we don't have |
771 | * a chip ID, try the JEDEC id commands; they'll work for most | |
772 | * newer chips, even if we don't recognize the particular chip. | |
2f9f7628 ML |
773 | */ |
774 | data = spi->dev.platform_data; | |
fa0a8c71 | 775 | if (data && data->type) { |
18c6182b | 776 | const struct spi_device_id *plat_id; |
2f9f7628 | 777 | |
b34bc037 | 778 | for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) { |
18c6182b AV |
779 | plat_id = &m25p_ids[i]; |
780 | if (strcmp(data->type, plat_id->name)) | |
b34bc037 AV |
781 | continue; |
782 | break; | |
fa0a8c71 | 783 | } |
fa0a8c71 | 784 | |
18c6182b AV |
785 | if (plat_id) |
786 | id = plat_id; | |
787 | else | |
788 | dev_warn(&spi->dev, "unrecognized id %s\n", data->type); | |
b34bc037 | 789 | } |
fa0a8c71 | 790 | |
18c6182b AV |
791 | info = (void *)id->driver_data; |
792 | ||
793 | if (info->jedec_id) { | |
794 | const struct spi_device_id *jid; | |
795 | ||
796 | jid = jedec_probe(spi); | |
797 | if (!jid) { | |
798 | dev_info(&spi->dev, "non-JEDEC variant of %s\n", | |
799 | id->name); | |
800 | } else if (jid != id) { | |
801 | /* | |
802 | * JEDEC knows better, so overwrite platform ID. We | |
803 | * can't trust partitions any longer, but we'll let | |
804 | * mtd apply them anyway, since some partitions may be | |
805 | * marked read-only, and we don't want to lose that | |
806 | * information, even if it's not 100% accurate. | |
807 | */ | |
808 | dev_warn(&spi->dev, "found %s, expected %s\n", | |
809 | jid->name, id->name); | |
810 | id = jid; | |
811 | info = (void *)jid->driver_data; | |
812 | } | |
813 | } | |
2f9f7628 | 814 | |
e94b1766 | 815 | flash = kzalloc(sizeof *flash, GFP_KERNEL); |
2f9f7628 ML |
816 | if (!flash) |
817 | return -ENOMEM; | |
837479d2 | 818 | flash->command = kmalloc(MAX_CMD_SIZE + FAST_READ_DUMMY_BYTE, GFP_KERNEL); |
61c3506c JS |
819 | if (!flash->command) { |
820 | kfree(flash); | |
821 | return -ENOMEM; | |
822 | } | |
2f9f7628 ML |
823 | |
824 | flash->spi = spi; | |
7d5230ea | 825 | mutex_init(&flash->lock); |
2f9f7628 ML |
826 | dev_set_drvdata(&spi->dev, flash); |
827 | ||
72289824 | 828 | /* |
ea60658a GY |
829 | * Atmel and SST serial flash tend to power |
830 | * up with the software protection bits set | |
72289824 MH |
831 | */ |
832 | ||
ea60658a GY |
833 | if (info->jedec_id >> 16 == 0x1f || |
834 | info->jedec_id >> 16 == 0xbf) { | |
72289824 MH |
835 | write_enable(flash); |
836 | write_sr(flash, 0); | |
837 | } | |
838 | ||
fa0a8c71 | 839 | if (data && data->name) |
2f9f7628 ML |
840 | flash->mtd.name = data->name; |
841 | else | |
160bbab3 | 842 | flash->mtd.name = dev_name(&spi->dev); |
2f9f7628 ML |
843 | |
844 | flash->mtd.type = MTD_NORFLASH; | |
783ed81f | 845 | flash->mtd.writesize = 1; |
2f9f7628 ML |
846 | flash->mtd.flags = MTD_CAP_NORFLASH; |
847 | flash->mtd.size = info->sector_size * info->n_sectors; | |
2f9f7628 ML |
848 | flash->mtd.erase = m25p80_erase; |
849 | flash->mtd.read = m25p80_read; | |
49aac4ae GY |
850 | |
851 | /* sst flash chips use AAI word program */ | |
852 | if (info->jedec_id >> 16 == 0xbf) | |
853 | flash->mtd.write = sst_write; | |
854 | else | |
855 | flash->mtd.write = m25p80_write; | |
2f9f7628 | 856 | |
fa0a8c71 DB |
857 | /* prefer "small sector" erase if possible */ |
858 | if (info->flags & SECT_4K) { | |
859 | flash->erase_opcode = OPCODE_BE_4K; | |
860 | flash->mtd.erasesize = 4096; | |
861 | } else { | |
862 | flash->erase_opcode = OPCODE_SE; | |
863 | flash->mtd.erasesize = info->sector_size; | |
864 | } | |
865 | ||
837479d2 AV |
866 | if (info->flags & M25P_NO_ERASE) |
867 | flash->mtd.flags |= MTD_NO_ERASE; | |
868 | ||
87f39f04 | 869 | flash->mtd.dev.parent = &spi->dev; |
837479d2 AV |
870 | flash->page_size = info->page_size; |
871 | flash->addr_width = info->addr_width; | |
87f39f04 | 872 | |
b34bc037 | 873 | dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name, |
d85316ac | 874 | (long long)flash->mtd.size >> 10); |
2f9f7628 ML |
875 | |
876 | DEBUG(MTD_DEBUG_LEVEL2, | |
d85316ac | 877 | "mtd .name = %s, .size = 0x%llx (%lldMiB) " |
02d087db | 878 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", |
2f9f7628 | 879 | flash->mtd.name, |
d85316ac | 880 | (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20), |
2f9f7628 ML |
881 | flash->mtd.erasesize, flash->mtd.erasesize / 1024, |
882 | flash->mtd.numeraseregions); | |
883 | ||
884 | if (flash->mtd.numeraseregions) | |
885 | for (i = 0; i < flash->mtd.numeraseregions; i++) | |
886 | DEBUG(MTD_DEBUG_LEVEL2, | |
d85316ac | 887 | "mtd.eraseregions[%d] = { .offset = 0x%llx, " |
02d087db | 888 | ".erasesize = 0x%.8x (%uKiB), " |
2f9f7628 | 889 | ".numblocks = %d }\n", |
d85316ac | 890 | i, (long long)flash->mtd.eraseregions[i].offset, |
2f9f7628 ML |
891 | flash->mtd.eraseregions[i].erasesize, |
892 | flash->mtd.eraseregions[i].erasesize / 1024, | |
893 | flash->mtd.eraseregions[i].numblocks); | |
894 | ||
895 | ||
896 | /* partitions should match sector boundaries; and it may be good to | |
897 | * use readonly partitions for writeprotected sectors (BP2..BP0). | |
898 | */ | |
899 | if (mtd_has_partitions()) { | |
900 | struct mtd_partition *parts = NULL; | |
901 | int nr_parts = 0; | |
902 | ||
a4b6d516 DB |
903 | if (mtd_has_cmdlinepart()) { |
904 | static const char *part_probes[] | |
905 | = { "cmdlinepart", NULL, }; | |
2f9f7628 | 906 | |
a4b6d516 DB |
907 | nr_parts = parse_mtd_partitions(&flash->mtd, |
908 | part_probes, &parts, 0); | |
909 | } | |
2f9f7628 ML |
910 | |
911 | if (nr_parts <= 0 && data && data->parts) { | |
912 | parts = data->parts; | |
913 | nr_parts = data->nr_parts; | |
914 | } | |
915 | ||
916 | if (nr_parts > 0) { | |
fa0a8c71 | 917 | for (i = 0; i < nr_parts; i++) { |
2f9f7628 | 918 | DEBUG(MTD_DEBUG_LEVEL2, "partitions[%d] = " |
d85316ac AB |
919 | "{.name = %s, .offset = 0x%llx, " |
920 | ".size = 0x%llx (%lldKiB) }\n", | |
fa0a8c71 | 921 | i, parts[i].name, |
d85316ac AB |
922 | (long long)parts[i].offset, |
923 | (long long)parts[i].size, | |
924 | (long long)(parts[i].size >> 10)); | |
2f9f7628 ML |
925 | } |
926 | flash->partitioned = 1; | |
927 | return add_mtd_partitions(&flash->mtd, parts, nr_parts); | |
928 | } | |
edcb3b14 | 929 | } else if (data && data->nr_parts) |
2f9f7628 ML |
930 | dev_warn(&spi->dev, "ignoring %d default partitions on %s\n", |
931 | data->nr_parts, data->name); | |
932 | ||
933 | return add_mtd_device(&flash->mtd) == 1 ? -ENODEV : 0; | |
934 | } | |
935 | ||
936 | ||
937 | static int __devexit m25p_remove(struct spi_device *spi) | |
938 | { | |
939 | struct m25p *flash = dev_get_drvdata(&spi->dev); | |
940 | int status; | |
941 | ||
942 | /* Clean up MTD stuff. */ | |
943 | if (mtd_has_partitions() && flash->partitioned) | |
944 | status = del_mtd_partitions(&flash->mtd); | |
945 | else | |
946 | status = del_mtd_device(&flash->mtd); | |
61c3506c JS |
947 | if (status == 0) { |
948 | kfree(flash->command); | |
2f9f7628 | 949 | kfree(flash); |
61c3506c | 950 | } |
2f9f7628 ML |
951 | return 0; |
952 | } | |
953 | ||
954 | ||
955 | static struct spi_driver m25p80_driver = { | |
956 | .driver = { | |
957 | .name = "m25p80", | |
958 | .bus = &spi_bus_type, | |
959 | .owner = THIS_MODULE, | |
960 | }, | |
b34bc037 | 961 | .id_table = m25p_ids, |
2f9f7628 ML |
962 | .probe = m25p_probe, |
963 | .remove = __devexit_p(m25p_remove), | |
fa0a8c71 DB |
964 | |
965 | /* REVISIT: many of these chips have deep power-down modes, which | |
966 | * should clearly be entered on suspend() to minimize power use. | |
967 | * And also when they're otherwise idle... | |
968 | */ | |
2f9f7628 ML |
969 | }; |
970 | ||
971 | ||
627df23c | 972 | static int __init m25p80_init(void) |
2f9f7628 ML |
973 | { |
974 | return spi_register_driver(&m25p80_driver); | |
975 | } | |
976 | ||
977 | ||
627df23c | 978 | static void __exit m25p80_exit(void) |
2f9f7628 ML |
979 | { |
980 | spi_unregister_driver(&m25p80_driver); | |
981 | } | |
982 | ||
983 | ||
984 | module_init(m25p80_init); | |
985 | module_exit(m25p80_exit); | |
986 | ||
987 | MODULE_LICENSE("GPL"); | |
988 | MODULE_AUTHOR("Mike Lavender"); | |
989 | MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips"); |