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mmc: sh_mmcif: Terminate DMA transactions when detecting timeout or error
[linux-2.6-block.git] / drivers / mmc / host / sh_mmcif.c
CommitLineData
fdc50a94
YG		 1/*
2 * MMCIF eMMC driver.
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10 *
11 *
12 * TODO
13 * 1. DMA
14 * 2. Power management
15 * 3. Handle MMC errors better
16 *
17 */
18
f985da17
GL		 19/*
20 * The MMCIF driver is now processing MMC requests asynchronously, according
21 * to the Linux MMC API requirement.
22 *
23 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
24 * data, and optional stop. To achieve asynchronous processing each of these
25 * stages is split into two halves: a top and a bottom half. The top half
26 * initialises the hardware, installs a timeout handler to handle completion
27 * timeouts, and returns. In case of the command stage this immediately returns
28 * control to the caller, leaving all further processing to run asynchronously.
29 * All further request processing is performed by the bottom halves.
30 *
31 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
32 * thread, a DMA completion callback, if DMA is used, a timeout work, and
33 * request- and stage-specific handler methods.
34 *
35 * Each bottom half run begins with either a hardware interrupt, a DMA callback
36 * invocation, or a timeout work run. In case of an error or a successful
37 * processing completion, the MMC core is informed and the request processing is
38 * finished. In case processing has to continue, i.e., if data has to be read
39 * from or written to the card, or if a stop command has to be sent, the next
40 * top half is called, which performs the necessary hardware handling and
41 * reschedules the timeout work. This returns the driver state machine into the
42 * bottom half waiting state.
43 */
44
86df1745 45#include <linux/bitops.h>
aa0787a9
GL		 46#include <linux/clk.h>
47#include <linux/completion.h>
e47bf32a 48#include <linux/delay.h>
fdc50a94 49#include <linux/dma-mapping.h>
a782d688 50#include <linux/dmaengine.h>
fdc50a94
YG		 51#include <linux/mmc/card.h>
52#include <linux/mmc/core.h>
e47bf32a 53#include <linux/mmc/host.h>
fdc50a94
YG		 54#include <linux/mmc/mmc.h>
55#include <linux/mmc/sdio.h>
fdc50a94 56#include <linux/mmc/sh_mmcif.h>
e480606a 57#include <linux/mmc/slot-gpio.h>
bf68a812 58#include <linux/mod_devicetable.h>
a782d688 59#include <linux/pagemap.h>
e47bf32a 60#include <linux/platform_device.h>
efe6a8ad 61#include <linux/pm_qos.h>
faca6648 62#include <linux/pm_runtime.h>
3b0beafc 63#include <linux/spinlock.h>
88b47679 64#include <linux/module.h>
fdc50a94
YG		 65
66#define DRIVER_NAME "sh_mmcif"
67#define DRIVER_VERSION "2010-04-28"
68
fdc50a94
YG		 69/* CE_CMD_SET */
70#define CMD_MASK 0x3f000000
71#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
72#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
73#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
74#define CMD_SET_RBSY (1 << 21) /* R1b */
75#define CMD_SET_CCSEN (1 << 20)
76#define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
77#define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
78#define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
79#define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
80#define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
81#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
82#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
83#define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
84#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
85#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
86#define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
87#define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
88#define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
89#define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
90#define CMD_SET_CCSH (1 << 5)
555061f9 91#define CMD_SET_DARS (1 << 2) /* Dual Data Rate */
fdc50a94
YG		 92#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
93#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
94#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
95
96/* CE_CMD_CTRL */
97#define CMD_CTRL_BREAK (1 << 0)
98
99/* CE_BLOCK_SET */
100#define BLOCK_SIZE_MASK 0x0000ffff
101
fdc50a94
YG		 102/* CE_INT */
103#define INT_CCSDE (1 << 29)
104#define INT_CMD12DRE (1 << 26)
105#define INT_CMD12RBE (1 << 25)
106#define INT_CMD12CRE (1 << 24)
107#define INT_DTRANE (1 << 23)
108#define INT_BUFRE (1 << 22)
109#define INT_BUFWEN (1 << 21)
110#define INT_BUFREN (1 << 20)
111#define INT_CCSRCV (1 << 19)
112#define INT_RBSYE (1 << 17)
113#define INT_CRSPE (1 << 16)
114#define INT_CMDVIO (1 << 15)
115#define INT_BUFVIO (1 << 14)
116#define INT_WDATERR (1 << 11)
117#define INT_RDATERR (1 << 10)
118#define INT_RIDXERR (1 << 9)
119#define INT_RSPERR (1 << 8)
120#define INT_CCSTO (1 << 5)
121#define INT_CRCSTO (1 << 4)
122#define INT_WDATTO (1 << 3)
123#define INT_RDATTO (1 << 2)
124#define INT_RBSYTO (1 << 1)
125#define INT_RSPTO (1 << 0)
126#define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
127 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
128 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
129 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
130
131/* CE_INT_MASK */
132#define MASK_ALL 0x00000000
133#define MASK_MCCSDE (1 << 29)
134#define MASK_MCMD12DRE (1 << 26)
135#define MASK_MCMD12RBE (1 << 25)
136#define MASK_MCMD12CRE (1 << 24)
137#define MASK_MDTRANE (1 << 23)
138#define MASK_MBUFRE (1 << 22)
139#define MASK_MBUFWEN (1 << 21)
140#define MASK_MBUFREN (1 << 20)
141#define MASK_MCCSRCV (1 << 19)
142#define MASK_MRBSYE (1 << 17)
143#define MASK_MCRSPE (1 << 16)
144#define MASK_MCMDVIO (1 << 15)
145#define MASK_MBUFVIO (1 << 14)
146#define MASK_MWDATERR (1 << 11)
147#define MASK_MRDATERR (1 << 10)
148#define MASK_MRIDXERR (1 << 9)
149#define MASK_MRSPERR (1 << 8)
150#define MASK_MCCSTO (1 << 5)
151#define MASK_MCRCSTO (1 << 4)
152#define MASK_MWDATTO (1 << 3)
153#define MASK_MRDATTO (1 << 2)
154#define MASK_MRBSYTO (1 << 1)
155#define MASK_MRSPTO (1 << 0)
156
ee4b8887
GL		 157#define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
158 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
159 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
160 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
161
fdc50a94
YG		 162/* CE_HOST_STS1 */
163#define STS1_CMDSEQ (1 << 31)
164
165/* CE_HOST_STS2 */
166#define STS2_CRCSTE (1 << 31)
167#define STS2_CRC16E (1 << 30)
168#define STS2_AC12CRCE (1 << 29)
169#define STS2_RSPCRC7E (1 << 28)
170#define STS2_CRCSTEBE (1 << 27)
171#define STS2_RDATEBE (1 << 26)
172#define STS2_AC12REBE (1 << 25)
173#define STS2_RSPEBE (1 << 24)
174#define STS2_AC12IDXE (1 << 23)
175#define STS2_RSPIDXE (1 << 22)
176#define STS2_CCSTO (1 << 15)
177#define STS2_RDATTO (1 << 14)
178#define STS2_DATBSYTO (1 << 13)
179#define STS2_CRCSTTO (1 << 12)
180#define STS2_AC12BSYTO (1 << 11)
181#define STS2_RSPBSYTO (1 << 10)
182#define STS2_AC12RSPTO (1 << 9)
183#define STS2_RSPTO (1 << 8)
184#define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
185 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
186#define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
187 STS2_DATBSYTO | STS2_CRCSTTO | \
188 STS2_AC12BSYTO | STS2_RSPBSYTO | \
189 STS2_AC12RSPTO | STS2_RSPTO)
190
fdc50a94
YG		 191#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
192#define CLKDEV_MMC_DATA 20000000 /* 20MHz */
193#define CLKDEV_INIT 400000 /* 400 KHz */
194
3b0beafc
GL		 195enum mmcif_state {
196 STATE_IDLE,
197 STATE_REQUEST,
198 STATE_IOS,
199};
200
f985da17
GL		 201enum mmcif_wait_for {
202 MMCIF_WAIT_FOR_REQUEST,
203 MMCIF_WAIT_FOR_CMD,
204 MMCIF_WAIT_FOR_MREAD,
205 MMCIF_WAIT_FOR_MWRITE,
206 MMCIF_WAIT_FOR_READ,
207 MMCIF_WAIT_FOR_WRITE,
208 MMCIF_WAIT_FOR_READ_END,
209 MMCIF_WAIT_FOR_WRITE_END,
210 MMCIF_WAIT_FOR_STOP,
211};
212
fdc50a94
YG		 213struct sh_mmcif_host {
214 struct mmc_host *mmc;
f985da17 215 struct mmc_request *mrq;
fdc50a94
YG		 216 struct platform_device *pd;
217 struct clk *hclk;
218 unsigned int clk;
219 int bus_width;
555061f9 220 unsigned char timing;
aa0787a9 221 bool sd_error;
f985da17 222 bool dying;
fdc50a94
YG		 223 long timeout;
224 void __iomem *addr;
f985da17 225 u32 *pio_ptr;
ee4b8887 226 spinlock_t lock; /* protect sh_mmcif_host::state */
3b0beafc 227 enum mmcif_state state;
f985da17
GL		 228 enum mmcif_wait_for wait_for;
229 struct delayed_work timeout_work;
230 size_t blocksize;
231 int sg_idx;
232 int sg_blkidx;
faca6648 233 bool power;
c9b0cef2 234 bool card_present;
fdc50a94 235
a782d688
GL		 236 /* DMA support */
237 struct dma_chan *chan_rx;
238 struct dma_chan *chan_tx;
239 struct completion dma_complete;
f38f94c6 240 bool dma_active;
a782d688 241};
fdc50a94
YG		 242
243static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
244 unsigned int reg, u32 val)
245{
487d9fc5 246 writel(val | readl(host->addr + reg), host->addr + reg);
fdc50a94
YG		 247}
248
249static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
250 unsigned int reg, u32 val)
251{
487d9fc5 252 writel(~val & readl(host->addr + reg), host->addr + reg);
fdc50a94
YG		 253}
254
a782d688
GL		 255static void mmcif_dma_complete(void *arg)
256{
257 struct sh_mmcif_host *host = arg;
69983404
GL		 258 struct mmc_data *data = host->mrq->data;
259
a782d688
GL		 260 dev_dbg(&host->pd->dev, "Command completed\n");
261
69983404 262 if (WARN(!data, "%s: NULL data in DMA completion!\n",
a782d688
GL		 263 dev_name(&host->pd->dev)))
264 return;
265
a782d688
GL		 266 complete(&host->dma_complete);
267}
268
269static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
270{
69983404
GL		 271 struct mmc_data *data = host->mrq->data;
272 struct scatterlist *sg = data->sg;
a782d688
GL		 273 struct dma_async_tx_descriptor *desc = NULL;
274 struct dma_chan *chan = host->chan_rx;
275 dma_cookie_t cookie = -EINVAL;
276 int ret;
277
69983404 278 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
1ed828db 279 DMA_FROM_DEVICE);
a782d688 280 if (ret > 0) {
f38f94c6 281 host->dma_active = true;
16052827 282 desc = dmaengine_prep_slave_sg(chan, sg, ret,
05f5799c 283 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
a782d688
GL		 284 }
285
286 if (desc) {
287 desc->callback = mmcif_dma_complete;
288 desc->callback_param = host;
a5ece7d2
LW		 289 cookie = dmaengine_submit(desc);
290 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
291 dma_async_issue_pending(chan);
a782d688
GL		 292 }
293 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
69983404 294 __func__, data->sg_len, ret, cookie);
a782d688
GL		 295
296 if (!desc) {
297 /* DMA failed, fall back to PIO */
298 if (ret >= 0)
299 ret = -EIO;
300 host->chan_rx = NULL;
f38f94c6 301 host->dma_active = false;
a782d688
GL		 302 dma_release_channel(chan);
303 /* Free the Tx channel too */
304 chan = host->chan_tx;
305 if (chan) {
306 host->chan_tx = NULL;
307 dma_release_channel(chan);
308 }
309 dev_warn(&host->pd->dev,
310 "DMA failed: %d, falling back to PIO\n", ret);
311 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
312 }
313
314 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
69983404 315 desc, cookie, data->sg_len);
a782d688
GL		 316}
317
318static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
319{
69983404
GL		 320 struct mmc_data *data = host->mrq->data;
321 struct scatterlist *sg = data->sg;
a782d688
GL		 322 struct dma_async_tx_descriptor *desc = NULL;
323 struct dma_chan *chan = host->chan_tx;
324 dma_cookie_t cookie = -EINVAL;
325 int ret;
326
69983404 327 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
1ed828db 328 DMA_TO_DEVICE);
a782d688 329 if (ret > 0) {
f38f94c6 330 host->dma_active = true;
16052827 331 desc = dmaengine_prep_slave_sg(chan, sg, ret,
05f5799c 332 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
a782d688
GL		 333 }
334
335 if (desc) {
336 desc->callback = mmcif_dma_complete;
337 desc->callback_param = host;
a5ece7d2
LW		 338 cookie = dmaengine_submit(desc);
339 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
340 dma_async_issue_pending(chan);
a782d688
GL		 341 }
342 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
69983404 343 __func__, data->sg_len, ret, cookie);
a782d688
GL		 344
345 if (!desc) {
346 /* DMA failed, fall back to PIO */
347 if (ret >= 0)
348 ret = -EIO;
349 host->chan_tx = NULL;
f38f94c6 350 host->dma_active = false;
a782d688
GL		 351 dma_release_channel(chan);
352 /* Free the Rx channel too */
353 chan = host->chan_rx;
354 if (chan) {
355 host->chan_rx = NULL;
356 dma_release_channel(chan);
357 }
358 dev_warn(&host->pd->dev,
359 "DMA failed: %d, falling back to PIO\n", ret);
360 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
361 }
362
363 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
364 desc, cookie);
365}
366
a782d688
GL		 367static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
368 struct sh_mmcif_plat_data *pdata)
369{
0e79f9ae
GL		 370 struct resource *res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);
371 struct dma_slave_config cfg;
372 dma_cap_mask_t mask;
373 int ret;
a782d688 374
f38f94c6 375 host->dma_active = false;
a782d688 376
bf68a812
GL		 377 if (!pdata)
378 return;
379
0e79f9ae
GL		 380 if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0)
381 return;
a782d688 382
0e79f9ae
GL		 383 /* We can only either use DMA for both Tx and Rx or not use it at all */
384 dma_cap_zero(mask);
385 dma_cap_set(DMA_SLAVE, mask);
a782d688 386
0e79f9ae
GL		 387 host->chan_tx = dma_request_channel(mask, shdma_chan_filter,
388 (void *)pdata->slave_id_tx);
389 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
390 host->chan_tx);
a782d688 391
0e79f9ae
GL		 392 if (!host->chan_tx)
393 return;
a782d688 394
0e79f9ae
GL		 395 cfg.slave_id = pdata->slave_id_tx;
396 cfg.direction = DMA_MEM_TO_DEV;
397 cfg.dst_addr = res->start + MMCIF_CE_DATA;
398 cfg.src_addr = 0;
399 ret = dmaengine_slave_config(host->chan_tx, &cfg);
400 if (ret < 0)
401 goto ecfgtx;
402
403 host->chan_rx = dma_request_channel(mask, shdma_chan_filter,
404 (void *)pdata->slave_id_rx);
405 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
406 host->chan_rx);
407
408 if (!host->chan_rx)
409 goto erqrx;
410
411 cfg.slave_id = pdata->slave_id_rx;
412 cfg.direction = DMA_DEV_TO_MEM;
413 cfg.dst_addr = 0;
414 cfg.src_addr = res->start + MMCIF_CE_DATA;
415 ret = dmaengine_slave_config(host->chan_rx, &cfg);
416 if (ret < 0)
417 goto ecfgrx;
418
419 init_completion(&host->dma_complete);
420
421 return;
422
423ecfgrx:
424 dma_release_channel(host->chan_rx);
425 host->chan_rx = NULL;
426erqrx:
427ecfgtx:
428 dma_release_channel(host->chan_tx);
429 host->chan_tx = NULL;
a782d688
GL		 430}
431
432static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
433{
434 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
435 /* Descriptors are freed automatically */
436 if (host->chan_tx) {
437 struct dma_chan *chan = host->chan_tx;
438 host->chan_tx = NULL;
439 dma_release_channel(chan);
440 }
441 if (host->chan_rx) {
442 struct dma_chan *chan = host->chan_rx;
443 host->chan_rx = NULL;
444 dma_release_channel(chan);
445 }
446
f38f94c6 447 host->dma_active = false;
a782d688 448}
fdc50a94
YG		 449
450static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
451{
452 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
bf68a812 453 bool sup_pclk = p ? p->sup_pclk : false;
fdc50a94
YG		 454
455 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
456 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
457
458 if (!clk)
459 return;
bf68a812 460 if (sup_pclk && clk == host->clk)
fdc50a94
YG		 461 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
462 else
463 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
f9388257
SH		 464 ((fls(DIV_ROUND_UP(host->clk,
465 clk) - 1) - 1) << 16));
fdc50a94
YG		 466
467 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
468}
469
470static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
471{
472 u32 tmp;
473
487d9fc5 474 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
fdc50a94 475
487d9fc5
MD		 476 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
477 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
fdc50a94
YG		 478 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
479 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
480 /* byte swap on */
481 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
482}
483
484static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
485{
486 u32 state1, state2;
ee4b8887 487 int ret, timeout;
fdc50a94 488
aa0787a9 489 host->sd_error = false;
fdc50a94 490
487d9fc5
MD		 491 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
492 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
e47bf32a
GL		 493 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
494 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
fdc50a94
YG		 495
496 if (state1 & STS1_CMDSEQ) {
497 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
498 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
ee4b8887 499 for (timeout = 10000000; timeout; timeout--) {
487d9fc5 500 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
ee4b8887 501 & STS1_CMDSEQ))
fdc50a94
YG		 502 break;
503 mdelay(1);
504 }
ee4b8887
GL		 505 if (!timeout) {
506 dev_err(&host->pd->dev,
507 "Forced end of command sequence timeout err\n");
508 return -EIO;
509 }
fdc50a94 510 sh_mmcif_sync_reset(host);
e47bf32a 511 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
fdc50a94
YG		 512 return -EIO;
513 }
514
515 if (state2 & STS2_CRC_ERR) {
ee4b8887 516 dev_dbg(&host->pd->dev, ": CRC error\n");
fdc50a94
YG		 517 ret = -EIO;
518 } else if (state2 & STS2_TIMEOUT_ERR) {
ee4b8887 519 dev_dbg(&host->pd->dev, ": Timeout\n");
fdc50a94
YG		 520 ret = -ETIMEDOUT;
521 } else {
ee4b8887 522 dev_dbg(&host->pd->dev, ": End/Index error\n");
fdc50a94
YG		 523 ret = -EIO;
524 }
525 return ret;
526}
527
f985da17 528static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
fdc50a94 529{
f985da17
GL		 530 struct mmc_data *data = host->mrq->data;
531
532 host->sg_blkidx += host->blocksize;
533
534 /* data->sg->length must be a multiple of host->blocksize? */
535 BUG_ON(host->sg_blkidx > data->sg->length);
536
537 if (host->sg_blkidx == data->sg->length) {
538 host->sg_blkidx = 0;
539 if (++host->sg_idx < data->sg_len)
540 host->pio_ptr = sg_virt(++data->sg);
541 } else {
542 host->pio_ptr = p;
543 }
544
545 if (host->sg_idx == data->sg_len)
546 return false;
547
548 return true;
549}
550
551static void sh_mmcif_single_read(struct sh_mmcif_host *host,
552 struct mmc_request *mrq)
553{
554 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
555 BLOCK_SIZE_MASK) + 3;
556
557 host->wait_for = MMCIF_WAIT_FOR_READ;
fdc50a94 558
fdc50a94
YG		 559 /* buf read enable */
560 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
f985da17
GL		 561}
562
563static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
564{
565 struct mmc_data *data = host->mrq->data;
566 u32 *p = sg_virt(data->sg);
567 int i;
568
569 if (host->sd_error) {
570 data->error = sh_mmcif_error_manage(host);
571 return false;
572 }
573
574 for (i = 0; i < host->blocksize / 4; i++)
487d9fc5 575 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
fdc50a94
YG		 576
577 /* buffer read end */
578 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
f985da17 579 host->wait_for = MMCIF_WAIT_FOR_READ_END;
fdc50a94 580
f985da17 581 return true;
fdc50a94
YG		 582}
583
f985da17
GL		 584static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
585 struct mmc_request *mrq)
fdc50a94
YG		 586{
587 struct mmc_data *data = mrq->data;
f985da17
GL		 588
589 if (!data->sg_len || !data->sg->length)
590 return;
591
592 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
593 BLOCK_SIZE_MASK;
594
595 host->wait_for = MMCIF_WAIT_FOR_MREAD;
596 host->sg_idx = 0;
597 host->sg_blkidx = 0;
598 host->pio_ptr = sg_virt(data->sg);
5df460b1 599
f985da17
GL		 600 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
601}
602
603static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
604{
605 struct mmc_data *data = host->mrq->data;
606 u32 *p = host->pio_ptr;
607 int i;
608
609 if (host->sd_error) {
610 data->error = sh_mmcif_error_manage(host);
611 return false;
fdc50a94 612 }
f985da17
GL		 613
614 BUG_ON(!data->sg->length);
615
616 for (i = 0; i < host->blocksize / 4; i++)
617 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
618
619 if (!sh_mmcif_next_block(host, p))
620 return false;
621
f985da17
GL		 622 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
623
624 return true;
fdc50a94
YG		 625}
626
f985da17 627static void sh_mmcif_single_write(struct sh_mmcif_host *host,
fdc50a94
YG		 628 struct mmc_request *mrq)
629{
f985da17
GL		 630 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
631 BLOCK_SIZE_MASK) + 3;
fdc50a94 632
f985da17 633 host->wait_for = MMCIF_WAIT_FOR_WRITE;
fdc50a94
YG		 634
635 /* buf write enable */
f985da17
GL		 636 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
637}
638
639static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
640{
641 struct mmc_data *data = host->mrq->data;
642 u32 *p = sg_virt(data->sg);
643 int i;
644
645 if (host->sd_error) {
646 data->error = sh_mmcif_error_manage(host);
647 return false;
648 }
649
650 for (i = 0; i < host->blocksize / 4; i++)
487d9fc5 651 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
fdc50a94
YG		 652
653 /* buffer write end */
654 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
f985da17 655 host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
fdc50a94 656
f985da17 657 return true;
fdc50a94
YG		 658}
659
f985da17
GL		 660static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
661 struct mmc_request *mrq)
fdc50a94
YG		 662{
663 struct mmc_data *data = mrq->data;
fdc50a94 664
f985da17
GL		 665 if (!data->sg_len || !data->sg->length)
666 return;
fdc50a94 667
f985da17
GL		 668 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
669 BLOCK_SIZE_MASK;
fdc50a94 670
f985da17
GL		 671 host->wait_for = MMCIF_WAIT_FOR_MWRITE;
672 host->sg_idx = 0;
673 host->sg_blkidx = 0;
674 host->pio_ptr = sg_virt(data->sg);
5df460b1 675
f985da17
GL		 676 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
677}
fdc50a94 678
f985da17
GL		 679static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
680{
681 struct mmc_data *data = host->mrq->data;
682 u32 *p = host->pio_ptr;
683 int i;
684
685 if (host->sd_error) {
686 data->error = sh_mmcif_error_manage(host);
687 return false;
fdc50a94 688 }
f985da17
GL		 689
690 BUG_ON(!data->sg->length);
691
692 for (i = 0; i < host->blocksize / 4; i++)
693 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
694
695 if (!sh_mmcif_next_block(host, p))
696 return false;
697
f985da17
GL		 698 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
699
700 return true;
fdc50a94
YG		 701}
702
703static void sh_mmcif_get_response(struct sh_mmcif_host *host,
704 struct mmc_command *cmd)
705{
706 if (cmd->flags & MMC_RSP_136) {
487d9fc5
MD		 707 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
708 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
709 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
710 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
fdc50a94 711 } else
487d9fc5 712 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
fdc50a94
YG		 713}
714
715static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
716 struct mmc_command *cmd)
717{
487d9fc5 718 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
fdc50a94
YG		 719}
720
721static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
69983404 722 struct mmc_request *mrq)
fdc50a94 723{
69983404
GL		 724 struct mmc_data *data = mrq->data;
725 struct mmc_command *cmd = mrq->cmd;
726 u32 opc = cmd->opcode;
fdc50a94
YG		 727 u32 tmp = 0;
728
729 /* Response Type check */
730 switch (mmc_resp_type(cmd)) {
731 case MMC_RSP_NONE:
732 tmp |= CMD_SET_RTYP_NO;
733 break;
734 case MMC_RSP_R1:
735 case MMC_RSP_R1B:
736 case MMC_RSP_R3:
737 tmp |= CMD_SET_RTYP_6B;
738 break;
739 case MMC_RSP_R2:
740 tmp |= CMD_SET_RTYP_17B;
741 break;
742 default:
e47bf32a 743 dev_err(&host->pd->dev, "Unsupported response type.\n");
fdc50a94
YG		 744 break;
745 }
746 switch (opc) {
747 /* RBSY */
a812ba0f 748 case MMC_SLEEP_AWAKE:
fdc50a94
YG		 749 case MMC_SWITCH:
750 case MMC_STOP_TRANSMISSION:
751 case MMC_SET_WRITE_PROT:
752 case MMC_CLR_WRITE_PROT:
753 case MMC_ERASE:
fdc50a94
YG		 754 tmp |= CMD_SET_RBSY;
755 break;
756 }
757 /* WDAT / DATW */
69983404 758 if (data) {
fdc50a94
YG		 759 tmp |= CMD_SET_WDAT;
760 switch (host->bus_width) {
761 case MMC_BUS_WIDTH_1:
762 tmp |= CMD_SET_DATW_1;
763 break;
764 case MMC_BUS_WIDTH_4:
765 tmp |= CMD_SET_DATW_4;
766 break;
767 case MMC_BUS_WIDTH_8:
768 tmp |= CMD_SET_DATW_8;
769 break;
770 default:
e47bf32a 771 dev_err(&host->pd->dev, "Unsupported bus width.\n");
fdc50a94
YG		 772 break;
773 }
555061f9
TK		 774 switch (host->timing) {
775 case MMC_TIMING_UHS_DDR50:
776 /*
777 * MMC core will only set this timing, if the host
778 * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF
779 * implementations with this capability, e.g. sh73a0,
780 * will have to set it in their platform data.
781 */
782 tmp |= CMD_SET_DARS;
783 break;
784 }
fdc50a94
YG		 785 }
786 /* DWEN */
787 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
788 tmp |= CMD_SET_DWEN;
789 /* CMLTE/CMD12EN */
790 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
791 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
792 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
69983404 793 data->blocks << 16);
fdc50a94
YG		 794 }
795 /* RIDXC[1:0] check bits */
796 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
797 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
798 tmp |= CMD_SET_RIDXC_BITS;
799 /* RCRC7C[1:0] check bits */
800 if (opc == MMC_SEND_OP_COND)
801 tmp |= CMD_SET_CRC7C_BITS;
802 /* RCRC7C[1:0] internal CRC7 */
803 if (opc == MMC_ALL_SEND_CID ||
804 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
805 tmp |= CMD_SET_CRC7C_INTERNAL;
806
69983404 807 return (opc << 24) | tmp;
fdc50a94
YG		 808}
809
e47bf32a 810static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
f985da17 811 struct mmc_request *mrq, u32 opc)
fdc50a94 812{
fdc50a94
YG		 813 switch (opc) {
814 case MMC_READ_MULTIPLE_BLOCK:
f985da17
GL		 815 sh_mmcif_multi_read(host, mrq);
816 return 0;
fdc50a94 817 case MMC_WRITE_MULTIPLE_BLOCK:
f985da17
GL		 818 sh_mmcif_multi_write(host, mrq);
819 return 0;
fdc50a94 820 case MMC_WRITE_BLOCK:
f985da17
GL		 821 sh_mmcif_single_write(host, mrq);
822 return 0;
fdc50a94
YG		 823 case MMC_READ_SINGLE_BLOCK:
824 case MMC_SEND_EXT_CSD:
f985da17
GL		 825 sh_mmcif_single_read(host, mrq);
826 return 0;
fdc50a94 827 default:
e47bf32a 828 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
ee4b8887 829 return -EINVAL;
fdc50a94 830 }
fdc50a94
YG		 831}
832
833static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
ee4b8887 834 struct mmc_request *mrq)
fdc50a94 835{
ee4b8887 836 struct mmc_command *cmd = mrq->cmd;
f985da17
GL		 837 u32 opc = cmd->opcode;
838 u32 mask;
fdc50a94 839
fdc50a94 840 switch (opc) {
ee4b8887 841 /* response busy check */
a812ba0f 842 case MMC_SLEEP_AWAKE:
fdc50a94
YG		 843 case MMC_SWITCH:
844 case MMC_STOP_TRANSMISSION:
845 case MMC_SET_WRITE_PROT:
846 case MMC_CLR_WRITE_PROT:
847 case MMC_ERASE:
ee4b8887 848 mask = MASK_START_CMD | MASK_MRBSYE;
fdc50a94
YG		 849 break;
850 default:
ee4b8887 851 mask = MASK_START_CMD | MASK_MCRSPE;
fdc50a94
YG		 852 break;
853 }
fdc50a94 854
69983404 855 if (mrq->data) {
487d9fc5
MD		 856 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
857 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
858 mrq->data->blksz);
fdc50a94 859 }
69983404 860 opc = sh_mmcif_set_cmd(host, mrq);
fdc50a94 861
487d9fc5
MD		 862 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
863 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
fdc50a94 864 /* set arg */
487d9fc5 865 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
fdc50a94 866 /* set cmd */
487d9fc5 867 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
fdc50a94 868
f985da17
GL		 869 host->wait_for = MMCIF_WAIT_FOR_CMD;
870 schedule_delayed_work(&host->timeout_work, host->timeout);
fdc50a94
YG		 871}
872
873static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
ee4b8887 874 struct mmc_request *mrq)
fdc50a94 875{
69983404
GL		 876 switch (mrq->cmd->opcode) {
877 case MMC_READ_MULTIPLE_BLOCK:
fdc50a94 878 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
69983404
GL		 879 break;
880 case MMC_WRITE_MULTIPLE_BLOCK:
fdc50a94 881 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
69983404
GL		 882 break;
883 default:
e47bf32a 884 dev_err(&host->pd->dev, "unsupported stop cmd\n");
69983404 885 mrq->stop->error = sh_mmcif_error_manage(host);
fdc50a94
YG		 886 return;
887 }
888
f985da17 889 host->wait_for = MMCIF_WAIT_FOR_STOP;
fdc50a94
YG		 890}
891
892static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
893{
894 struct sh_mmcif_host *host = mmc_priv(mmc);
3b0beafc
GL		 895 unsigned long flags;
896
897 spin_lock_irqsave(&host->lock, flags);
898 if (host->state != STATE_IDLE) {
899 spin_unlock_irqrestore(&host->lock, flags);
900 mrq->cmd->error = -EAGAIN;
901 mmc_request_done(mmc, mrq);
902 return;
903 }
904
905 host->state = STATE_REQUEST;
906 spin_unlock_irqrestore(&host->lock, flags);
fdc50a94
YG		 907
908 switch (mrq->cmd->opcode) {
909 /* MMCIF does not support SD/SDIO command */
7541ca98
LP		 910 case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */
911 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
912 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)
913 break;
fdc50a94 914 case MMC_APP_CMD:
92ff0c5b 915 case SD_IO_RW_DIRECT:
3b0beafc 916 host->state = STATE_IDLE;
fdc50a94
YG		 917 mrq->cmd->error = -ETIMEDOUT;
918 mmc_request_done(mmc, mrq);
919 return;
fdc50a94
YG		 920 default:
921 break;
922 }
f985da17
GL		 923
924 host->mrq = mrq;
fdc50a94 925
f985da17 926 sh_mmcif_start_cmd(host, mrq);
fdc50a94
YG		 927}
928
a6609267
GL		 929static int sh_mmcif_clk_update(struct sh_mmcif_host *host)
930{
931 int ret = clk_enable(host->hclk);
932
933 if (!ret) {
934 host->clk = clk_get_rate(host->hclk);
935 host->mmc->f_max = host->clk / 2;
936 host->mmc->f_min = host->clk / 512;
937 }
938
939 return ret;
940}
941
7d17baa0
GL		 942static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)
943{
944 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
945 struct mmc_host *mmc = host->mmc;
946
bf68a812 947 if (pd && pd->set_pwr)
7d17baa0
GL		 948 pd->set_pwr(host->pd, ios->power_mode != MMC_POWER_OFF);
949 if (!IS_ERR(mmc->supply.vmmc))
950 /* Errors ignored... */
951 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
952 ios->power_mode ? ios->vdd : 0);
953}
954
fdc50a94
YG		 955static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
956{
957 struct sh_mmcif_host *host = mmc_priv(mmc);
3b0beafc
GL		 958 unsigned long flags;
959
960 spin_lock_irqsave(&host->lock, flags);
961 if (host->state != STATE_IDLE) {
962 spin_unlock_irqrestore(&host->lock, flags);
963 return;
964 }
965
966 host->state = STATE_IOS;
967 spin_unlock_irqrestore(&host->lock, flags);
fdc50a94 968
f5e0cec4 969 if (ios->power_mode == MMC_POWER_UP) {
c9b0cef2 970 if (!host->card_present) {
faca6648
GL		 971 /* See if we also get DMA */
972 sh_mmcif_request_dma(host, host->pd->dev.platform_data);
c9b0cef2 973 host->card_present = true;
faca6648 974 }
7d17baa0 975 sh_mmcif_set_power(host, ios);
f5e0cec4 976 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
fdc50a94
YG		 977 /* clock stop */
978 sh_mmcif_clock_control(host, 0);
faca6648 979 if (ios->power_mode == MMC_POWER_OFF) {
c9b0cef2 980 if (host->card_present) {
faca6648 981 sh_mmcif_release_dma(host);
c9b0cef2 982 host->card_present = false;
faca6648 983 }
c9b0cef2
GL		 984 }
985 if (host->power) {
f8a8ced7 986 pm_runtime_put_sync(&host->pd->dev);
b289174f 987 clk_disable(host->hclk);
c9b0cef2 988 host->power = false;
7d17baa0
GL		 989 if (ios->power_mode == MMC_POWER_OFF)
990 sh_mmcif_set_power(host, ios);
faca6648 991 }
3b0beafc 992 host->state = STATE_IDLE;
fdc50a94 993 return;
fdc50a94
YG		 994 }
995
c9b0cef2
GL		 996 if (ios->clock) {
997 if (!host->power) {
a6609267 998 sh_mmcif_clk_update(host);
c9b0cef2
GL		 999 pm_runtime_get_sync(&host->pd->dev);
1000 host->power = true;
1001 sh_mmcif_sync_reset(host);
1002 }
fdc50a94 1003 sh_mmcif_clock_control(host, ios->clock);
c9b0cef2 1004 }
fdc50a94 1005
555061f9 1006 host->timing = ios->timing;
fdc50a94 1007 host->bus_width = ios->bus_width;
3b0beafc 1008 host->state = STATE_IDLE;
fdc50a94
YG		 1009}
1010
777271d0
AH		 1011static int sh_mmcif_get_cd(struct mmc_host *mmc)
1012{
1013 struct sh_mmcif_host *host = mmc_priv(mmc);
1014 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
e480606a
GL		 1015 int ret = mmc_gpio_get_cd(mmc);
1016
1017 if (ret >= 0)
1018 return ret;
777271d0 1019
bf68a812 1020 if (!p || !p->get_cd)
777271d0
AH		 1021 return -ENOSYS;
1022 else
1023 return p->get_cd(host->pd);
1024}
1025
fdc50a94
YG		 1026static struct mmc_host_ops sh_mmcif_ops = {
1027 .request = sh_mmcif_request,
1028 .set_ios = sh_mmcif_set_ios,
777271d0 1029 .get_cd = sh_mmcif_get_cd,
fdc50a94
YG		 1030};
1031
f985da17
GL		 1032static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1033{
1034 struct mmc_command *cmd = host->mrq->cmd;
69983404 1035 struct mmc_data *data = host->mrq->data;
f985da17
GL		 1036 long time;
1037
1038 if (host->sd_error) {
1039 switch (cmd->opcode) {
1040 case MMC_ALL_SEND_CID:
1041 case MMC_SELECT_CARD:
1042 case MMC_APP_CMD:
1043 cmd->error = -ETIMEDOUT;
1044 host->sd_error = false;
1045 break;
1046 default:
1047 cmd->error = sh_mmcif_error_manage(host);
1048 dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n",
1049 cmd->opcode, cmd->error);
1050 break;
1051 }
1052 return false;
1053 }
1054 if (!(cmd->flags & MMC_RSP_PRESENT)) {
1055 cmd->error = 0;
1056 return false;
1057 }
1058
1059 sh_mmcif_get_response(host, cmd);
1060
69983404 1061 if (!data)
f985da17
GL		 1062 return false;
1063
69983404 1064 if (data->flags & MMC_DATA_READ) {
f985da17
GL		 1065 if (host->chan_rx)
1066 sh_mmcif_start_dma_rx(host);
1067 } else {
1068 if (host->chan_tx)
1069 sh_mmcif_start_dma_tx(host);
1070 }
1071
1072 if (!host->dma_active) {
69983404
GL		 1073 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1074 if (!data->error)
f985da17
GL		 1075 return true;
1076 return false;
1077 }
1078
1079 /* Running in the IRQ thread, can sleep */
1080 time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1081 host->timeout);
eae30983
TK		 1082
1083 if (data->flags & MMC_DATA_READ)
1084 dma_unmap_sg(host->chan_rx->device->dev,
1085 data->sg, data->sg_len,
1086 DMA_FROM_DEVICE);
1087 else
1088 dma_unmap_sg(host->chan_tx->device->dev,
1089 data->sg, data->sg_len,
1090 DMA_TO_DEVICE);
1091
f985da17
GL		 1092 if (host->sd_error) {
1093 dev_err(host->mmc->parent,
1094 "Error IRQ while waiting for DMA completion!\n");
1095 /* Woken up by an error IRQ: abort DMA */
69983404 1096 data->error = sh_mmcif_error_manage(host);
f985da17 1097 } else if (!time) {
69983404 1098 data->error = -ETIMEDOUT;
f985da17 1099 } else if (time < 0) {
69983404 1100 data->error = time;
f985da17
GL		 1101 }
1102 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1103 BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1104 host->dma_active = false;
1105
eae30983 1106 if (data->error) {
69983404 1107 data->bytes_xfered = 0;
eae30983
TK		 1108 /* Abort DMA */
1109 if (data->flags & MMC_DATA_READ)
1110 dmaengine_terminate_all(host->chan_rx);
1111 else
1112 dmaengine_terminate_all(host->chan_tx);
1113 }
f985da17
GL		 1114
1115 return false;
1116}
1117
1118static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1119{
1120 struct sh_mmcif_host *host = dev_id;
1121 struct mmc_request *mrq = host->mrq;
5df460b1 1122 bool wait = false;
f985da17
GL		 1123
1124 cancel_delayed_work_sync(&host->timeout_work);
1125
1126 /*
1127 * All handlers return true, if processing continues, and false, if the
1128 * request has to be completed - successfully or not
1129 */
1130 switch (host->wait_for) {
1131 case MMCIF_WAIT_FOR_REQUEST:
1132 /* We're too late, the timeout has already kicked in */
1133 return IRQ_HANDLED;
1134 case MMCIF_WAIT_FOR_CMD:
5df460b1
GL		 1135 /* Wait for data? */
1136 wait = sh_mmcif_end_cmd(host);
f985da17
GL		 1137 break;
1138 case MMCIF_WAIT_FOR_MREAD:
5df460b1
GL		 1139 /* Wait for more data? */
1140 wait = sh_mmcif_mread_block(host);
f985da17
GL		 1141 break;
1142 case MMCIF_WAIT_FOR_READ:
5df460b1
GL		 1143 /* Wait for data end? */
1144 wait = sh_mmcif_read_block(host);
f985da17
GL		 1145 break;
1146 case MMCIF_WAIT_FOR_MWRITE:
5df460b1
GL		 1147 /* Wait data to write? */
1148 wait = sh_mmcif_mwrite_block(host);
f985da17
GL		 1149 break;
1150 case MMCIF_WAIT_FOR_WRITE:
5df460b1
GL		 1151 /* Wait for data end? */
1152 wait = sh_mmcif_write_block(host);
f985da17
GL		 1153 break;
1154 case MMCIF_WAIT_FOR_STOP:
1155 if (host->sd_error) {
1156 mrq->stop->error = sh_mmcif_error_manage(host);
1157 break;
1158 }
1159 sh_mmcif_get_cmd12response(host, mrq->stop);
1160 mrq->stop->error = 0;
1161 break;
1162 case MMCIF_WAIT_FOR_READ_END:
1163 case MMCIF_WAIT_FOR_WRITE_END:
1164 if (host->sd_error)
91ab252a 1165 mrq->data->error = sh_mmcif_error_manage(host);
f985da17
GL		 1166 break;
1167 default:
1168 BUG();
1169 }
1170
5df460b1
GL		 1171 if (wait) {
1172 schedule_delayed_work(&host->timeout_work, host->timeout);
1173 /* Wait for more data */
1174 return IRQ_HANDLED;
1175 }
1176
f985da17 1177 if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
91ab252a 1178 struct mmc_data *data = mrq->data;
69983404
GL		 1179 if (!mrq->cmd->error && data && !data->error)
1180 data->bytes_xfered =
1181 data->blocks * data->blksz;
f985da17 1182
69983404 1183 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
f985da17 1184 sh_mmcif_stop_cmd(host, mrq);
5df460b1
GL		 1185 if (!mrq->stop->error) {
1186 schedule_delayed_work(&host->timeout_work, host->timeout);
f985da17 1187 return IRQ_HANDLED;
5df460b1 1188 }
f985da17
GL		 1189 }
1190 }
1191
1192 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1193 host->state = STATE_IDLE;
69983404 1194 host->mrq = NULL;
f985da17
GL		 1195 mmc_request_done(host->mmc, mrq);
1196
1197 return IRQ_HANDLED;
1198}
1199
fdc50a94
YG		 1200static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1201{
1202 struct sh_mmcif_host *host = dev_id;
aa0787a9 1203 u32 state;
fdc50a94
YG		 1204 int err = 0;
1205
487d9fc5 1206 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
fdc50a94 1207
8a8284a9
GL		 1208 if (state & INT_ERR_STS) {
1209 /* error interrupts - process first */
1210 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1211 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1212 err = 1;
1213 } else if (state & INT_RBSYE) {
487d9fc5
MD		 1214 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1215 ~(INT_RBSYE | INT_CRSPE));
fdc50a94
YG		 1216 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
1217 } else if (state & INT_CRSPE) {
487d9fc5 1218 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
fdc50a94
YG		 1219 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
1220 } else if (state & INT_BUFREN) {
487d9fc5 1221 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
fdc50a94
YG		 1222 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
1223 } else if (state & INT_BUFWEN) {
487d9fc5 1224 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
fdc50a94
YG		 1225 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
1226 } else if (state & INT_CMD12DRE) {
487d9fc5 1227 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
fdc50a94
YG		 1228 ~(INT_CMD12DRE | INT_CMD12RBE |
1229 INT_CMD12CRE | INT_BUFRE));
1230 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
1231 } else if (state & INT_BUFRE) {
487d9fc5 1232 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
fdc50a94
YG		 1233 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
1234 } else if (state & INT_DTRANE) {
7a7eb328
GL		 1235 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1236 ~(INT_CMD12DRE | INT_CMD12RBE |
1237 INT_CMD12CRE | INT_DTRANE));
fdc50a94
YG		 1238 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
1239 } else if (state & INT_CMD12RBE) {
487d9fc5 1240 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
fdc50a94
YG		 1241 ~(INT_CMD12RBE | INT_CMD12CRE));
1242 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
fdc50a94 1243 } else {
faca6648 1244 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
487d9fc5 1245 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
fdc50a94
YG		 1246 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1247 err = 1;
1248 }
1249 if (err) {
aa0787a9 1250 host->sd_error = true;
e47bf32a 1251 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
fdc50a94 1252 }
f985da17
GL		 1253 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1254 if (!host->dma_active)
1255 return IRQ_WAKE_THREAD;
1256 else if (host->sd_error)
1257 mmcif_dma_complete(host);
1258 } else {
aa0787a9 1259 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
f985da17 1260 }
fdc50a94
YG		 1261
1262 return IRQ_HANDLED;
1263}
1264
f985da17
GL		 1265static void mmcif_timeout_work(struct work_struct *work)
1266{
1267 struct delayed_work *d = container_of(work, struct delayed_work, work);
1268 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1269 struct mmc_request *mrq = host->mrq;
1270
1271 if (host->dying)
1272 /* Don't run after mmc_remove_host() */
1273 return;
1274
1275 /*
1276 * Handle races with cancel_delayed_work(), unless
1277 * cancel_delayed_work_sync() is used
1278 */
1279 switch (host->wait_for) {
1280 case MMCIF_WAIT_FOR_CMD:
1281 mrq->cmd->error = sh_mmcif_error_manage(host);
1282 break;
1283 case MMCIF_WAIT_FOR_STOP:
1284 mrq->stop->error = sh_mmcif_error_manage(host);
1285 break;
1286 case MMCIF_WAIT_FOR_MREAD:
1287 case MMCIF_WAIT_FOR_MWRITE:
1288 case MMCIF_WAIT_FOR_READ:
1289 case MMCIF_WAIT_FOR_WRITE:
1290 case MMCIF_WAIT_FOR_READ_END:
1291 case MMCIF_WAIT_FOR_WRITE_END:
69983404 1292 mrq->data->error = sh_mmcif_error_manage(host);
f985da17
GL		 1293 break;
1294 default:
1295 BUG();
1296 }
1297
1298 host->state = STATE_IDLE;
1299 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
f985da17
GL		 1300 host->mrq = NULL;
1301 mmc_request_done(host->mmc, mrq);
1302}
1303
7d17baa0
GL		 1304static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1305{
1306 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
1307 struct mmc_host *mmc = host->mmc;
1308
1309 mmc_regulator_get_supply(mmc);
1310
bf68a812
GL		 1311 if (!pd)
1312 return;
1313
7d17baa0
GL		 1314 if (!mmc->ocr_avail)
1315 mmc->ocr_avail = pd->ocr;
1316 else if (pd->ocr)
1317 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1318}
1319
c3be1efd 1320static int sh_mmcif_probe(struct platform_device *pdev)
fdc50a94
YG		 1321{
1322 int ret = 0, irq[2];
1323 struct mmc_host *mmc;
e47bf32a 1324 struct sh_mmcif_host *host;
e1aae2eb 1325 struct sh_mmcif_plat_data *pd = pdev->dev.platform_data;
fdc50a94
YG		 1326 struct resource *res;
1327 void __iomem *reg;
2cd5b3e0 1328 const char *name;
fdc50a94
YG		 1329
1330 irq[0] = platform_get_irq(pdev, 0);
1331 irq[1] = platform_get_irq(pdev, 1);
2cd5b3e0 1332 if (irq[0] < 0) {
e47bf32a 1333 dev_err(&pdev->dev, "Get irq error\n");
fdc50a94
YG		 1334 return -ENXIO;
1335 }
1336 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1337 if (!res) {
1338 dev_err(&pdev->dev, "platform_get_resource error.\n");
1339 return -ENXIO;
1340 }
1341 reg = ioremap(res->start, resource_size(res));
1342 if (!reg) {
1343 dev_err(&pdev->dev, "ioremap error.\n");
1344 return -ENOMEM;
1345 }
e1aae2eb 1346
fdc50a94
YG		 1347 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1348 if (!mmc) {
1349 ret = -ENOMEM;
e1aae2eb 1350 goto ealloch;
fdc50a94
YG		 1351 }
1352 host = mmc_priv(mmc);
1353 host->mmc = mmc;
1354 host->addr = reg;
f9fd54f2 1355 host->timeout = msecs_to_jiffies(1000);
fdc50a94 1356
fdc50a94
YG		 1357 host->pd = pdev;
1358
3b0beafc 1359 spin_lock_init(&host->lock);
fdc50a94
YG		 1360
1361 mmc->ops = &sh_mmcif_ops;
7d17baa0
GL		 1362 sh_mmcif_init_ocr(host);
1363
a812ba0f 1364 mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY;
bf68a812 1365 if (pd && pd->caps)
fdc50a94 1366 mmc->caps |= pd->caps;
a782d688 1367 mmc->max_segs = 32;
fdc50a94 1368 mmc->max_blk_size = 512;
a782d688
GL		 1369 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1370 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
fdc50a94
YG		 1371 mmc->max_seg_size = mmc->max_req_size;
1372
fdc50a94 1373 platform_set_drvdata(pdev, host);
a782d688 1374
faca6648
GL		 1375 pm_runtime_enable(&pdev->dev);
1376 host->power = false;
1377
047a9ce7 1378 host->hclk = clk_get(&pdev->dev, NULL);
b289174f
GL		 1379 if (IS_ERR(host->hclk)) {
1380 ret = PTR_ERR(host->hclk);
047a9ce7 1381 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
b289174f
GL		 1382 goto eclkget;
1383 }
a6609267
GL		 1384 ret = sh_mmcif_clk_update(host);
1385 if (ret < 0)
1386 goto eclkupdate;
b289174f 1387
faca6648
GL		 1388 ret = pm_runtime_resume(&pdev->dev);
1389 if (ret < 0)
e1aae2eb 1390 goto eresume;
a782d688 1391
5ba85d95 1392 INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
fdc50a94 1393
b289174f 1394 sh_mmcif_sync_reset(host);
3b0beafc
GL		 1395 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1396
2cd5b3e0
SK		 1397 name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error";
1398 ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, name, host);
fdc50a94 1399 if (ret) {
2cd5b3e0 1400 dev_err(&pdev->dev, "request_irq error (%s)\n", name);
e1aae2eb 1401 goto ereqirq0;
fdc50a94 1402 }
2cd5b3e0
SK		 1403 if (irq[1] >= 0) {
1404 ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt,
1405 0, "sh_mmc:int", host);
1406 if (ret) {
1407 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1408 goto ereqirq1;
1409 }
fdc50a94
YG		 1410 }
1411
e480606a
GL		 1412 if (pd && pd->use_cd_gpio) {
1413 ret = mmc_gpio_request_cd(mmc, pd->cd_gpio);
1414 if (ret < 0)
1415 goto erqcd;
1416 }
1417
b289174f 1418 clk_disable(host->hclk);
5ba85d95
GL		 1419 ret = mmc_add_host(mmc);
1420 if (ret < 0)
e1aae2eb 1421 goto emmcaddh;
fdc50a94 1422
efe6a8ad
RW		 1423 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1424
e47bf32a
GL		 1425 dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1426 dev_dbg(&pdev->dev, "chip ver H'%04x\n",
487d9fc5 1427 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
fdc50a94
YG		 1428 return ret;
1429
e1aae2eb 1430emmcaddh:
e480606a 1431erqcd:
2cd5b3e0
SK		 1432 if (irq[1] >= 0)
1433 free_irq(irq[1], host);
e1aae2eb 1434ereqirq1:
5ba85d95 1435 free_irq(irq[0], host);
e1aae2eb 1436ereqirq0:
faca6648 1437 pm_runtime_suspend(&pdev->dev);
e1aae2eb 1438eresume:
fdc50a94 1439 clk_disable(host->hclk);
a6609267 1440eclkupdate:
b289174f 1441 clk_put(host->hclk);
e1aae2eb 1442eclkget:
b289174f 1443 pm_runtime_disable(&pdev->dev);
fdc50a94 1444 mmc_free_host(mmc);
e1aae2eb
GL		 1445ealloch:
1446 iounmap(reg);
fdc50a94
YG		 1447 return ret;
1448}
1449
6e0ee714 1450static int sh_mmcif_remove(struct platform_device *pdev)
fdc50a94
YG		 1451{
1452 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1453 int irq[2];
1454
f985da17 1455 host->dying = true;
b289174f 1456 clk_enable(host->hclk);
faca6648 1457 pm_runtime_get_sync(&pdev->dev);
fdc50a94 1458
efe6a8ad
RW		 1459 dev_pm_qos_hide_latency_limit(&pdev->dev);
1460
faca6648 1461 mmc_remove_host(host->mmc);
3b0beafc
GL		 1462 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1463
f985da17
GL		 1464 /*
1465 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1466 * mmc_remove_host() call above. But swapping order doesn't help either
1467 * (a query on the linux-mmc mailing list didn't bring any replies).
1468 */
1469 cancel_delayed_work_sync(&host->timeout_work);
1470
fdc50a94
YG		 1471 if (host->addr)
1472 iounmap(host->addr);
1473
aa0787a9
GL		 1474 irq[0] = platform_get_irq(pdev, 0);
1475 irq[1] = platform_get_irq(pdev, 1);
fdc50a94
YG		 1476
1477 free_irq(irq[0], host);
2cd5b3e0
SK		 1478 if (irq[1] >= 0)
1479 free_irq(irq[1], host);
fdc50a94 1480
aa0787a9
GL		 1481 platform_set_drvdata(pdev, NULL);
1482
a0d28ba0 1483 clk_disable(host->hclk);
fdc50a94 1484 mmc_free_host(host->mmc);
faca6648
GL		 1485 pm_runtime_put_sync(&pdev->dev);
1486 pm_runtime_disable(&pdev->dev);
fdc50a94
YG		 1487
1488 return 0;
1489}
1490
faca6648
GL		 1491#ifdef CONFIG_PM
1492static int sh_mmcif_suspend(struct device *dev)
1493{
b289174f 1494 struct sh_mmcif_host *host = dev_get_drvdata(dev);
faca6648
GL		 1495 int ret = mmc_suspend_host(host->mmc);
1496
b289174f 1497 if (!ret)
faca6648 1498 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
faca6648
GL		 1499
1500 return ret;
1501}
1502
1503static int sh_mmcif_resume(struct device *dev)
1504{
b289174f 1505 struct sh_mmcif_host *host = dev_get_drvdata(dev);
faca6648
GL		 1506
1507 return mmc_resume_host(host->mmc);
1508}
1509#else
1510#define sh_mmcif_suspend NULL
1511#define sh_mmcif_resume NULL
1512#endif /* CONFIG_PM */
1513
bf68a812
GL		 1514static const struct of_device_id mmcif_of_match[] = {
1515 { .compatible = "renesas,sh-mmcif" },
1516 { }
1517};
1518MODULE_DEVICE_TABLE(of, mmcif_of_match);
1519
faca6648
GL		 1520static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1521 .suspend = sh_mmcif_suspend,
1522 .resume = sh_mmcif_resume,
1523};
1524
fdc50a94
YG		 1525static struct platform_driver sh_mmcif_driver = {
1526 .probe = sh_mmcif_probe,
1527 .remove = sh_mmcif_remove,
1528 .driver = {
1529 .name = DRIVER_NAME,
faca6648 1530 .pm = &sh_mmcif_dev_pm_ops,
bf68a812
GL		 1531 .owner = THIS_MODULE,
1532 .of_match_table = mmcif_of_match,
fdc50a94
YG		 1533 },
1534};
1535
d1f81a64 1536module_platform_driver(sh_mmcif_driver);
fdc50a94
YG		 1537
1538MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1539MODULE_LICENSE("GPL");
aa0787a9 1540MODULE_ALIAS("platform:" DRIVER_NAME);
fdc50a94 1541MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");
Linux 6.x block layer and io_uring tree(s)