Commit | Line | Data |
---|---|---|
fdc50a94 YG |
1 | /* |
2 | * MMCIF eMMC driver. | |
3 | * | |
4 | * Copyright (C) 2010 Renesas Solutions Corp. | |
5 | * Yusuke Goda <yusuke.goda.sx@renesas.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License. | |
10 | * | |
11 | * | |
12 | * TODO | |
13 | * 1. DMA | |
14 | * 2. Power management | |
15 | * 3. Handle MMC errors better | |
16 | * | |
17 | */ | |
18 | ||
f985da17 GL |
19 | /* |
20 | * The MMCIF driver is now processing MMC requests asynchronously, according | |
21 | * to the Linux MMC API requirement. | |
22 | * | |
23 | * The MMCIF driver processes MMC requests in up to 3 stages: command, optional | |
24 | * data, and optional stop. To achieve asynchronous processing each of these | |
25 | * stages is split into two halves: a top and a bottom half. The top half | |
26 | * initialises the hardware, installs a timeout handler to handle completion | |
27 | * timeouts, and returns. In case of the command stage this immediately returns | |
28 | * control to the caller, leaving all further processing to run asynchronously. | |
29 | * All further request processing is performed by the bottom halves. | |
30 | * | |
31 | * The bottom half further consists of a "hard" IRQ handler, an IRQ handler | |
32 | * thread, a DMA completion callback, if DMA is used, a timeout work, and | |
33 | * request- and stage-specific handler methods. | |
34 | * | |
35 | * Each bottom half run begins with either a hardware interrupt, a DMA callback | |
36 | * invocation, or a timeout work run. In case of an error or a successful | |
37 | * processing completion, the MMC core is informed and the request processing is | |
38 | * finished. In case processing has to continue, i.e., if data has to be read | |
39 | * from or written to the card, or if a stop command has to be sent, the next | |
40 | * top half is called, which performs the necessary hardware handling and | |
41 | * reschedules the timeout work. This returns the driver state machine into the | |
42 | * bottom half waiting state. | |
43 | */ | |
44 | ||
86df1745 | 45 | #include <linux/bitops.h> |
aa0787a9 GL |
46 | #include <linux/clk.h> |
47 | #include <linux/completion.h> | |
e47bf32a | 48 | #include <linux/delay.h> |
fdc50a94 | 49 | #include <linux/dma-mapping.h> |
a782d688 | 50 | #include <linux/dmaengine.h> |
fdc50a94 YG |
51 | #include <linux/mmc/card.h> |
52 | #include <linux/mmc/core.h> | |
e47bf32a | 53 | #include <linux/mmc/host.h> |
fdc50a94 YG |
54 | #include <linux/mmc/mmc.h> |
55 | #include <linux/mmc/sdio.h> | |
fdc50a94 | 56 | #include <linux/mmc/sh_mmcif.h> |
e480606a | 57 | #include <linux/mmc/slot-gpio.h> |
bf68a812 | 58 | #include <linux/mod_devicetable.h> |
8047310e | 59 | #include <linux/mutex.h> |
a782d688 | 60 | #include <linux/pagemap.h> |
e47bf32a | 61 | #include <linux/platform_device.h> |
efe6a8ad | 62 | #include <linux/pm_qos.h> |
faca6648 | 63 | #include <linux/pm_runtime.h> |
d00cadac | 64 | #include <linux/sh_dma.h> |
3b0beafc | 65 | #include <linux/spinlock.h> |
88b47679 | 66 | #include <linux/module.h> |
fdc50a94 YG |
67 | |
68 | #define DRIVER_NAME "sh_mmcif" | |
69 | #define DRIVER_VERSION "2010-04-28" | |
70 | ||
fdc50a94 YG |
71 | /* CE_CMD_SET */ |
72 | #define CMD_MASK 0x3f000000 | |
73 | #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) | |
74 | #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ | |
75 | #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ | |
76 | #define CMD_SET_RBSY (1 << 21) /* R1b */ | |
77 | #define CMD_SET_CCSEN (1 << 20) | |
78 | #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ | |
79 | #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ | |
80 | #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ | |
81 | #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ | |
82 | #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ | |
83 | #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ | |
84 | #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ | |
85 | #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ | |
86 | #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ | |
87 | #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ | |
88 | #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ | |
89 | #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ | |
90 | #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ | |
91 | #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ | |
92 | #define CMD_SET_CCSH (1 << 5) | |
555061f9 | 93 | #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ |
fdc50a94 YG |
94 | #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ |
95 | #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ | |
96 | #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ | |
97 | ||
98 | /* CE_CMD_CTRL */ | |
99 | #define CMD_CTRL_BREAK (1 << 0) | |
100 | ||
101 | /* CE_BLOCK_SET */ | |
102 | #define BLOCK_SIZE_MASK 0x0000ffff | |
103 | ||
fdc50a94 YG |
104 | /* CE_INT */ |
105 | #define INT_CCSDE (1 << 29) | |
106 | #define INT_CMD12DRE (1 << 26) | |
107 | #define INT_CMD12RBE (1 << 25) | |
108 | #define INT_CMD12CRE (1 << 24) | |
109 | #define INT_DTRANE (1 << 23) | |
110 | #define INT_BUFRE (1 << 22) | |
111 | #define INT_BUFWEN (1 << 21) | |
112 | #define INT_BUFREN (1 << 20) | |
113 | #define INT_CCSRCV (1 << 19) | |
114 | #define INT_RBSYE (1 << 17) | |
115 | #define INT_CRSPE (1 << 16) | |
116 | #define INT_CMDVIO (1 << 15) | |
117 | #define INT_BUFVIO (1 << 14) | |
118 | #define INT_WDATERR (1 << 11) | |
119 | #define INT_RDATERR (1 << 10) | |
120 | #define INT_RIDXERR (1 << 9) | |
121 | #define INT_RSPERR (1 << 8) | |
122 | #define INT_CCSTO (1 << 5) | |
123 | #define INT_CRCSTO (1 << 4) | |
124 | #define INT_WDATTO (1 << 3) | |
125 | #define INT_RDATTO (1 << 2) | |
126 | #define INT_RBSYTO (1 << 1) | |
127 | #define INT_RSPTO (1 << 0) | |
128 | #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ | |
129 | INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ | |
130 | INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ | |
131 | INT_RDATTO | INT_RBSYTO | INT_RSPTO) | |
132 | ||
8af50750 GL |
133 | #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ |
134 | INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ | |
135 | INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) | |
136 | ||
fdc50a94 YG |
137 | /* CE_INT_MASK */ |
138 | #define MASK_ALL 0x00000000 | |
139 | #define MASK_MCCSDE (1 << 29) | |
140 | #define MASK_MCMD12DRE (1 << 26) | |
141 | #define MASK_MCMD12RBE (1 << 25) | |
142 | #define MASK_MCMD12CRE (1 << 24) | |
143 | #define MASK_MDTRANE (1 << 23) | |
144 | #define MASK_MBUFRE (1 << 22) | |
145 | #define MASK_MBUFWEN (1 << 21) | |
146 | #define MASK_MBUFREN (1 << 20) | |
147 | #define MASK_MCCSRCV (1 << 19) | |
148 | #define MASK_MRBSYE (1 << 17) | |
149 | #define MASK_MCRSPE (1 << 16) | |
150 | #define MASK_MCMDVIO (1 << 15) | |
151 | #define MASK_MBUFVIO (1 << 14) | |
152 | #define MASK_MWDATERR (1 << 11) | |
153 | #define MASK_MRDATERR (1 << 10) | |
154 | #define MASK_MRIDXERR (1 << 9) | |
155 | #define MASK_MRSPERR (1 << 8) | |
156 | #define MASK_MCCSTO (1 << 5) | |
157 | #define MASK_MCRCSTO (1 << 4) | |
158 | #define MASK_MWDATTO (1 << 3) | |
159 | #define MASK_MRDATTO (1 << 2) | |
160 | #define MASK_MRBSYTO (1 << 1) | |
161 | #define MASK_MRSPTO (1 << 0) | |
162 | ||
ee4b8887 GL |
163 | #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ |
164 | MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ | |
165 | MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \ | |
166 | MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) | |
167 | ||
8af50750 GL |
168 | #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ |
169 | MASK_MBUFREN | MASK_MBUFWEN | \ | |
170 | MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ | |
171 | MASK_MCMD12RBE | MASK_MCMD12CRE) | |
172 | ||
fdc50a94 YG |
173 | /* CE_HOST_STS1 */ |
174 | #define STS1_CMDSEQ (1 << 31) | |
175 | ||
176 | /* CE_HOST_STS2 */ | |
177 | #define STS2_CRCSTE (1 << 31) | |
178 | #define STS2_CRC16E (1 << 30) | |
179 | #define STS2_AC12CRCE (1 << 29) | |
180 | #define STS2_RSPCRC7E (1 << 28) | |
181 | #define STS2_CRCSTEBE (1 << 27) | |
182 | #define STS2_RDATEBE (1 << 26) | |
183 | #define STS2_AC12REBE (1 << 25) | |
184 | #define STS2_RSPEBE (1 << 24) | |
185 | #define STS2_AC12IDXE (1 << 23) | |
186 | #define STS2_RSPIDXE (1 << 22) | |
187 | #define STS2_CCSTO (1 << 15) | |
188 | #define STS2_RDATTO (1 << 14) | |
189 | #define STS2_DATBSYTO (1 << 13) | |
190 | #define STS2_CRCSTTO (1 << 12) | |
191 | #define STS2_AC12BSYTO (1 << 11) | |
192 | #define STS2_RSPBSYTO (1 << 10) | |
193 | #define STS2_AC12RSPTO (1 << 9) | |
194 | #define STS2_RSPTO (1 << 8) | |
195 | #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ | |
196 | STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) | |
197 | #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ | |
198 | STS2_DATBSYTO | STS2_CRCSTTO | \ | |
199 | STS2_AC12BSYTO | STS2_RSPBSYTO | \ | |
200 | STS2_AC12RSPTO | STS2_RSPTO) | |
201 | ||
fdc50a94 YG |
202 | #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ |
203 | #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ | |
204 | #define CLKDEV_INIT 400000 /* 400 KHz */ | |
205 | ||
3b0beafc GL |
206 | enum mmcif_state { |
207 | STATE_IDLE, | |
208 | STATE_REQUEST, | |
209 | STATE_IOS, | |
8047310e | 210 | STATE_TIMEOUT, |
3b0beafc GL |
211 | }; |
212 | ||
f985da17 GL |
213 | enum mmcif_wait_for { |
214 | MMCIF_WAIT_FOR_REQUEST, | |
215 | MMCIF_WAIT_FOR_CMD, | |
216 | MMCIF_WAIT_FOR_MREAD, | |
217 | MMCIF_WAIT_FOR_MWRITE, | |
218 | MMCIF_WAIT_FOR_READ, | |
219 | MMCIF_WAIT_FOR_WRITE, | |
220 | MMCIF_WAIT_FOR_READ_END, | |
221 | MMCIF_WAIT_FOR_WRITE_END, | |
222 | MMCIF_WAIT_FOR_STOP, | |
223 | }; | |
224 | ||
fdc50a94 YG |
225 | struct sh_mmcif_host { |
226 | struct mmc_host *mmc; | |
f985da17 | 227 | struct mmc_request *mrq; |
fdc50a94 YG |
228 | struct platform_device *pd; |
229 | struct clk *hclk; | |
230 | unsigned int clk; | |
231 | int bus_width; | |
555061f9 | 232 | unsigned char timing; |
aa0787a9 | 233 | bool sd_error; |
f985da17 | 234 | bool dying; |
fdc50a94 YG |
235 | long timeout; |
236 | void __iomem *addr; | |
f985da17 | 237 | u32 *pio_ptr; |
ee4b8887 | 238 | spinlock_t lock; /* protect sh_mmcif_host::state */ |
3b0beafc | 239 | enum mmcif_state state; |
f985da17 GL |
240 | enum mmcif_wait_for wait_for; |
241 | struct delayed_work timeout_work; | |
242 | size_t blocksize; | |
243 | int sg_idx; | |
244 | int sg_blkidx; | |
faca6648 | 245 | bool power; |
c9b0cef2 | 246 | bool card_present; |
8047310e | 247 | struct mutex thread_lock; |
fdc50a94 | 248 | |
a782d688 GL |
249 | /* DMA support */ |
250 | struct dma_chan *chan_rx; | |
251 | struct dma_chan *chan_tx; | |
252 | struct completion dma_complete; | |
f38f94c6 | 253 | bool dma_active; |
a782d688 | 254 | }; |
fdc50a94 YG |
255 | |
256 | static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, | |
257 | unsigned int reg, u32 val) | |
258 | { | |
487d9fc5 | 259 | writel(val | readl(host->addr + reg), host->addr + reg); |
fdc50a94 YG |
260 | } |
261 | ||
262 | static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, | |
263 | unsigned int reg, u32 val) | |
264 | { | |
487d9fc5 | 265 | writel(~val & readl(host->addr + reg), host->addr + reg); |
fdc50a94 YG |
266 | } |
267 | ||
a782d688 GL |
268 | static void mmcif_dma_complete(void *arg) |
269 | { | |
270 | struct sh_mmcif_host *host = arg; | |
8047310e | 271 | struct mmc_request *mrq = host->mrq; |
69983404 | 272 | |
a782d688 GL |
273 | dev_dbg(&host->pd->dev, "Command completed\n"); |
274 | ||
8047310e | 275 | if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", |
a782d688 GL |
276 | dev_name(&host->pd->dev))) |
277 | return; | |
278 | ||
a782d688 GL |
279 | complete(&host->dma_complete); |
280 | } | |
281 | ||
282 | static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) | |
283 | { | |
69983404 GL |
284 | struct mmc_data *data = host->mrq->data; |
285 | struct scatterlist *sg = data->sg; | |
a782d688 GL |
286 | struct dma_async_tx_descriptor *desc = NULL; |
287 | struct dma_chan *chan = host->chan_rx; | |
288 | dma_cookie_t cookie = -EINVAL; | |
289 | int ret; | |
290 | ||
69983404 | 291 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, |
1ed828db | 292 | DMA_FROM_DEVICE); |
a782d688 | 293 | if (ret > 0) { |
f38f94c6 | 294 | host->dma_active = true; |
16052827 | 295 | desc = dmaengine_prep_slave_sg(chan, sg, ret, |
05f5799c | 296 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
a782d688 GL |
297 | } |
298 | ||
299 | if (desc) { | |
300 | desc->callback = mmcif_dma_complete; | |
301 | desc->callback_param = host; | |
a5ece7d2 LW |
302 | cookie = dmaengine_submit(desc); |
303 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); | |
304 | dma_async_issue_pending(chan); | |
a782d688 GL |
305 | } |
306 | dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", | |
69983404 | 307 | __func__, data->sg_len, ret, cookie); |
a782d688 GL |
308 | |
309 | if (!desc) { | |
310 | /* DMA failed, fall back to PIO */ | |
311 | if (ret >= 0) | |
312 | ret = -EIO; | |
313 | host->chan_rx = NULL; | |
f38f94c6 | 314 | host->dma_active = false; |
a782d688 GL |
315 | dma_release_channel(chan); |
316 | /* Free the Tx channel too */ | |
317 | chan = host->chan_tx; | |
318 | if (chan) { | |
319 | host->chan_tx = NULL; | |
320 | dma_release_channel(chan); | |
321 | } | |
322 | dev_warn(&host->pd->dev, | |
323 | "DMA failed: %d, falling back to PIO\n", ret); | |
324 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
325 | } | |
326 | ||
327 | dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, | |
69983404 | 328 | desc, cookie, data->sg_len); |
a782d688 GL |
329 | } |
330 | ||
331 | static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) | |
332 | { | |
69983404 GL |
333 | struct mmc_data *data = host->mrq->data; |
334 | struct scatterlist *sg = data->sg; | |
a782d688 GL |
335 | struct dma_async_tx_descriptor *desc = NULL; |
336 | struct dma_chan *chan = host->chan_tx; | |
337 | dma_cookie_t cookie = -EINVAL; | |
338 | int ret; | |
339 | ||
69983404 | 340 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, |
1ed828db | 341 | DMA_TO_DEVICE); |
a782d688 | 342 | if (ret > 0) { |
f38f94c6 | 343 | host->dma_active = true; |
16052827 | 344 | desc = dmaengine_prep_slave_sg(chan, sg, ret, |
05f5799c | 345 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
a782d688 GL |
346 | } |
347 | ||
348 | if (desc) { | |
349 | desc->callback = mmcif_dma_complete; | |
350 | desc->callback_param = host; | |
a5ece7d2 LW |
351 | cookie = dmaengine_submit(desc); |
352 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); | |
353 | dma_async_issue_pending(chan); | |
a782d688 GL |
354 | } |
355 | dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", | |
69983404 | 356 | __func__, data->sg_len, ret, cookie); |
a782d688 GL |
357 | |
358 | if (!desc) { | |
359 | /* DMA failed, fall back to PIO */ | |
360 | if (ret >= 0) | |
361 | ret = -EIO; | |
362 | host->chan_tx = NULL; | |
f38f94c6 | 363 | host->dma_active = false; |
a782d688 GL |
364 | dma_release_channel(chan); |
365 | /* Free the Rx channel too */ | |
366 | chan = host->chan_rx; | |
367 | if (chan) { | |
368 | host->chan_rx = NULL; | |
369 | dma_release_channel(chan); | |
370 | } | |
371 | dev_warn(&host->pd->dev, | |
372 | "DMA failed: %d, falling back to PIO\n", ret); | |
373 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
374 | } | |
375 | ||
376 | dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, | |
377 | desc, cookie); | |
378 | } | |
379 | ||
a782d688 GL |
380 | static void sh_mmcif_request_dma(struct sh_mmcif_host *host, |
381 | struct sh_mmcif_plat_data *pdata) | |
382 | { | |
0e79f9ae GL |
383 | struct resource *res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); |
384 | struct dma_slave_config cfg; | |
385 | dma_cap_mask_t mask; | |
386 | int ret; | |
a782d688 | 387 | |
f38f94c6 | 388 | host->dma_active = false; |
a782d688 | 389 | |
bf68a812 GL |
390 | if (!pdata) |
391 | return; | |
392 | ||
0e79f9ae GL |
393 | if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) |
394 | return; | |
a782d688 | 395 | |
0e79f9ae GL |
396 | /* We can only either use DMA for both Tx and Rx or not use it at all */ |
397 | dma_cap_zero(mask); | |
398 | dma_cap_set(DMA_SLAVE, mask); | |
a782d688 | 399 | |
0e79f9ae GL |
400 | host->chan_tx = dma_request_channel(mask, shdma_chan_filter, |
401 | (void *)pdata->slave_id_tx); | |
402 | dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__, | |
403 | host->chan_tx); | |
a782d688 | 404 | |
0e79f9ae GL |
405 | if (!host->chan_tx) |
406 | return; | |
a782d688 | 407 | |
0e79f9ae GL |
408 | cfg.slave_id = pdata->slave_id_tx; |
409 | cfg.direction = DMA_MEM_TO_DEV; | |
410 | cfg.dst_addr = res->start + MMCIF_CE_DATA; | |
411 | cfg.src_addr = 0; | |
412 | ret = dmaengine_slave_config(host->chan_tx, &cfg); | |
413 | if (ret < 0) | |
414 | goto ecfgtx; | |
415 | ||
416 | host->chan_rx = dma_request_channel(mask, shdma_chan_filter, | |
417 | (void *)pdata->slave_id_rx); | |
418 | dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__, | |
419 | host->chan_rx); | |
420 | ||
421 | if (!host->chan_rx) | |
422 | goto erqrx; | |
423 | ||
424 | cfg.slave_id = pdata->slave_id_rx; | |
425 | cfg.direction = DMA_DEV_TO_MEM; | |
426 | cfg.dst_addr = 0; | |
427 | cfg.src_addr = res->start + MMCIF_CE_DATA; | |
428 | ret = dmaengine_slave_config(host->chan_rx, &cfg); | |
429 | if (ret < 0) | |
430 | goto ecfgrx; | |
431 | ||
0e79f9ae GL |
432 | return; |
433 | ||
434 | ecfgrx: | |
435 | dma_release_channel(host->chan_rx); | |
436 | host->chan_rx = NULL; | |
437 | erqrx: | |
438 | ecfgtx: | |
439 | dma_release_channel(host->chan_tx); | |
440 | host->chan_tx = NULL; | |
a782d688 GL |
441 | } |
442 | ||
443 | static void sh_mmcif_release_dma(struct sh_mmcif_host *host) | |
444 | { | |
445 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
446 | /* Descriptors are freed automatically */ | |
447 | if (host->chan_tx) { | |
448 | struct dma_chan *chan = host->chan_tx; | |
449 | host->chan_tx = NULL; | |
450 | dma_release_channel(chan); | |
451 | } | |
452 | if (host->chan_rx) { | |
453 | struct dma_chan *chan = host->chan_rx; | |
454 | host->chan_rx = NULL; | |
455 | dma_release_channel(chan); | |
456 | } | |
457 | ||
f38f94c6 | 458 | host->dma_active = false; |
a782d688 | 459 | } |
fdc50a94 YG |
460 | |
461 | static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) | |
462 | { | |
463 | struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; | |
bf68a812 | 464 | bool sup_pclk = p ? p->sup_pclk : false; |
fdc50a94 YG |
465 | |
466 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); | |
467 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); | |
468 | ||
469 | if (!clk) | |
470 | return; | |
bf68a812 | 471 | if (sup_pclk && clk == host->clk) |
fdc50a94 YG |
472 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); |
473 | else | |
474 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & | |
f9388257 SH |
475 | ((fls(DIV_ROUND_UP(host->clk, |
476 | clk) - 1) - 1) << 16)); | |
fdc50a94 YG |
477 | |
478 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); | |
479 | } | |
480 | ||
481 | static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) | |
482 | { | |
483 | u32 tmp; | |
484 | ||
487d9fc5 | 485 | tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); |
fdc50a94 | 486 | |
487d9fc5 MD |
487 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); |
488 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); | |
fdc50a94 YG |
489 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | |
490 | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); | |
491 | /* byte swap on */ | |
492 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); | |
493 | } | |
494 | ||
495 | static int sh_mmcif_error_manage(struct sh_mmcif_host *host) | |
496 | { | |
497 | u32 state1, state2; | |
ee4b8887 | 498 | int ret, timeout; |
fdc50a94 | 499 | |
aa0787a9 | 500 | host->sd_error = false; |
fdc50a94 | 501 | |
487d9fc5 MD |
502 | state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); |
503 | state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); | |
e47bf32a GL |
504 | dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); |
505 | dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); | |
fdc50a94 YG |
506 | |
507 | if (state1 & STS1_CMDSEQ) { | |
508 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); | |
509 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); | |
ee4b8887 | 510 | for (timeout = 10000000; timeout; timeout--) { |
487d9fc5 | 511 | if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) |
ee4b8887 | 512 | & STS1_CMDSEQ)) |
fdc50a94 YG |
513 | break; |
514 | mdelay(1); | |
515 | } | |
ee4b8887 GL |
516 | if (!timeout) { |
517 | dev_err(&host->pd->dev, | |
518 | "Forced end of command sequence timeout err\n"); | |
519 | return -EIO; | |
520 | } | |
fdc50a94 | 521 | sh_mmcif_sync_reset(host); |
e47bf32a | 522 | dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); |
fdc50a94 YG |
523 | return -EIO; |
524 | } | |
525 | ||
526 | if (state2 & STS2_CRC_ERR) { | |
e475b270 TK |
527 | dev_err(&host->pd->dev, " CRC error: state %u, wait %u\n", |
528 | host->state, host->wait_for); | |
fdc50a94 YG |
529 | ret = -EIO; |
530 | } else if (state2 & STS2_TIMEOUT_ERR) { | |
e475b270 TK |
531 | dev_err(&host->pd->dev, " Timeout: state %u, wait %u\n", |
532 | host->state, host->wait_for); | |
fdc50a94 YG |
533 | ret = -ETIMEDOUT; |
534 | } else { | |
e475b270 TK |
535 | dev_dbg(&host->pd->dev, " End/Index error: state %u, wait %u\n", |
536 | host->state, host->wait_for); | |
fdc50a94 YG |
537 | ret = -EIO; |
538 | } | |
539 | return ret; | |
540 | } | |
541 | ||
f985da17 | 542 | static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) |
fdc50a94 | 543 | { |
f985da17 GL |
544 | struct mmc_data *data = host->mrq->data; |
545 | ||
546 | host->sg_blkidx += host->blocksize; | |
547 | ||
548 | /* data->sg->length must be a multiple of host->blocksize? */ | |
549 | BUG_ON(host->sg_blkidx > data->sg->length); | |
550 | ||
551 | if (host->sg_blkidx == data->sg->length) { | |
552 | host->sg_blkidx = 0; | |
553 | if (++host->sg_idx < data->sg_len) | |
554 | host->pio_ptr = sg_virt(++data->sg); | |
555 | } else { | |
556 | host->pio_ptr = p; | |
557 | } | |
558 | ||
99eb9d8d | 559 | return host->sg_idx != data->sg_len; |
f985da17 GL |
560 | } |
561 | ||
562 | static void sh_mmcif_single_read(struct sh_mmcif_host *host, | |
563 | struct mmc_request *mrq) | |
564 | { | |
565 | host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & | |
566 | BLOCK_SIZE_MASK) + 3; | |
567 | ||
568 | host->wait_for = MMCIF_WAIT_FOR_READ; | |
fdc50a94 | 569 | |
fdc50a94 YG |
570 | /* buf read enable */ |
571 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); | |
f985da17 GL |
572 | } |
573 | ||
574 | static bool sh_mmcif_read_block(struct sh_mmcif_host *host) | |
575 | { | |
576 | struct mmc_data *data = host->mrq->data; | |
577 | u32 *p = sg_virt(data->sg); | |
578 | int i; | |
579 | ||
580 | if (host->sd_error) { | |
581 | data->error = sh_mmcif_error_manage(host); | |
e475b270 | 582 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); |
f985da17 GL |
583 | return false; |
584 | } | |
585 | ||
586 | for (i = 0; i < host->blocksize / 4; i++) | |
487d9fc5 | 587 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); |
fdc50a94 YG |
588 | |
589 | /* buffer read end */ | |
590 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); | |
f985da17 | 591 | host->wait_for = MMCIF_WAIT_FOR_READ_END; |
fdc50a94 | 592 | |
f985da17 | 593 | return true; |
fdc50a94 YG |
594 | } |
595 | ||
f985da17 GL |
596 | static void sh_mmcif_multi_read(struct sh_mmcif_host *host, |
597 | struct mmc_request *mrq) | |
fdc50a94 YG |
598 | { |
599 | struct mmc_data *data = mrq->data; | |
f985da17 GL |
600 | |
601 | if (!data->sg_len || !data->sg->length) | |
602 | return; | |
603 | ||
604 | host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & | |
605 | BLOCK_SIZE_MASK; | |
606 | ||
607 | host->wait_for = MMCIF_WAIT_FOR_MREAD; | |
608 | host->sg_idx = 0; | |
609 | host->sg_blkidx = 0; | |
610 | host->pio_ptr = sg_virt(data->sg); | |
5df460b1 | 611 | |
f985da17 GL |
612 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
613 | } | |
614 | ||
615 | static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) | |
616 | { | |
617 | struct mmc_data *data = host->mrq->data; | |
618 | u32 *p = host->pio_ptr; | |
619 | int i; | |
620 | ||
621 | if (host->sd_error) { | |
622 | data->error = sh_mmcif_error_manage(host); | |
e475b270 | 623 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); |
f985da17 | 624 | return false; |
fdc50a94 | 625 | } |
f985da17 GL |
626 | |
627 | BUG_ON(!data->sg->length); | |
628 | ||
629 | for (i = 0; i < host->blocksize / 4; i++) | |
630 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); | |
631 | ||
632 | if (!sh_mmcif_next_block(host, p)) | |
633 | return false; | |
634 | ||
f985da17 GL |
635 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
636 | ||
637 | return true; | |
fdc50a94 YG |
638 | } |
639 | ||
f985da17 | 640 | static void sh_mmcif_single_write(struct sh_mmcif_host *host, |
fdc50a94 YG |
641 | struct mmc_request *mrq) |
642 | { | |
f985da17 GL |
643 | host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
644 | BLOCK_SIZE_MASK) + 3; | |
fdc50a94 | 645 | |
f985da17 | 646 | host->wait_for = MMCIF_WAIT_FOR_WRITE; |
fdc50a94 YG |
647 | |
648 | /* buf write enable */ | |
f985da17 GL |
649 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
650 | } | |
651 | ||
652 | static bool sh_mmcif_write_block(struct sh_mmcif_host *host) | |
653 | { | |
654 | struct mmc_data *data = host->mrq->data; | |
655 | u32 *p = sg_virt(data->sg); | |
656 | int i; | |
657 | ||
658 | if (host->sd_error) { | |
659 | data->error = sh_mmcif_error_manage(host); | |
e475b270 | 660 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); |
f985da17 GL |
661 | return false; |
662 | } | |
663 | ||
664 | for (i = 0; i < host->blocksize / 4; i++) | |
487d9fc5 | 665 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); |
fdc50a94 YG |
666 | |
667 | /* buffer write end */ | |
668 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); | |
f985da17 | 669 | host->wait_for = MMCIF_WAIT_FOR_WRITE_END; |
fdc50a94 | 670 | |
f985da17 | 671 | return true; |
fdc50a94 YG |
672 | } |
673 | ||
f985da17 GL |
674 | static void sh_mmcif_multi_write(struct sh_mmcif_host *host, |
675 | struct mmc_request *mrq) | |
fdc50a94 YG |
676 | { |
677 | struct mmc_data *data = mrq->data; | |
fdc50a94 | 678 | |
f985da17 GL |
679 | if (!data->sg_len || !data->sg->length) |
680 | return; | |
fdc50a94 | 681 | |
f985da17 GL |
682 | host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
683 | BLOCK_SIZE_MASK; | |
fdc50a94 | 684 | |
f985da17 GL |
685 | host->wait_for = MMCIF_WAIT_FOR_MWRITE; |
686 | host->sg_idx = 0; | |
687 | host->sg_blkidx = 0; | |
688 | host->pio_ptr = sg_virt(data->sg); | |
5df460b1 | 689 | |
f985da17 GL |
690 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
691 | } | |
fdc50a94 | 692 | |
f985da17 GL |
693 | static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) |
694 | { | |
695 | struct mmc_data *data = host->mrq->data; | |
696 | u32 *p = host->pio_ptr; | |
697 | int i; | |
698 | ||
699 | if (host->sd_error) { | |
700 | data->error = sh_mmcif_error_manage(host); | |
e475b270 | 701 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); |
f985da17 | 702 | return false; |
fdc50a94 | 703 | } |
f985da17 GL |
704 | |
705 | BUG_ON(!data->sg->length); | |
706 | ||
707 | for (i = 0; i < host->blocksize / 4; i++) | |
708 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); | |
709 | ||
710 | if (!sh_mmcif_next_block(host, p)) | |
711 | return false; | |
712 | ||
f985da17 GL |
713 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
714 | ||
715 | return true; | |
fdc50a94 YG |
716 | } |
717 | ||
718 | static void sh_mmcif_get_response(struct sh_mmcif_host *host, | |
719 | struct mmc_command *cmd) | |
720 | { | |
721 | if (cmd->flags & MMC_RSP_136) { | |
487d9fc5 MD |
722 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); |
723 | cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); | |
724 | cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); | |
725 | cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); | |
fdc50a94 | 726 | } else |
487d9fc5 | 727 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); |
fdc50a94 YG |
728 | } |
729 | ||
730 | static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, | |
731 | struct mmc_command *cmd) | |
732 | { | |
487d9fc5 | 733 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); |
fdc50a94 YG |
734 | } |
735 | ||
736 | static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, | |
69983404 | 737 | struct mmc_request *mrq) |
fdc50a94 | 738 | { |
69983404 GL |
739 | struct mmc_data *data = mrq->data; |
740 | struct mmc_command *cmd = mrq->cmd; | |
741 | u32 opc = cmd->opcode; | |
fdc50a94 YG |
742 | u32 tmp = 0; |
743 | ||
744 | /* Response Type check */ | |
745 | switch (mmc_resp_type(cmd)) { | |
746 | case MMC_RSP_NONE: | |
747 | tmp |= CMD_SET_RTYP_NO; | |
748 | break; | |
749 | case MMC_RSP_R1: | |
750 | case MMC_RSP_R1B: | |
751 | case MMC_RSP_R3: | |
752 | tmp |= CMD_SET_RTYP_6B; | |
753 | break; | |
754 | case MMC_RSP_R2: | |
755 | tmp |= CMD_SET_RTYP_17B; | |
756 | break; | |
757 | default: | |
e47bf32a | 758 | dev_err(&host->pd->dev, "Unsupported response type.\n"); |
fdc50a94 YG |
759 | break; |
760 | } | |
761 | switch (opc) { | |
762 | /* RBSY */ | |
a812ba0f | 763 | case MMC_SLEEP_AWAKE: |
fdc50a94 YG |
764 | case MMC_SWITCH: |
765 | case MMC_STOP_TRANSMISSION: | |
766 | case MMC_SET_WRITE_PROT: | |
767 | case MMC_CLR_WRITE_PROT: | |
768 | case MMC_ERASE: | |
fdc50a94 YG |
769 | tmp |= CMD_SET_RBSY; |
770 | break; | |
771 | } | |
772 | /* WDAT / DATW */ | |
69983404 | 773 | if (data) { |
fdc50a94 YG |
774 | tmp |= CMD_SET_WDAT; |
775 | switch (host->bus_width) { | |
776 | case MMC_BUS_WIDTH_1: | |
777 | tmp |= CMD_SET_DATW_1; | |
778 | break; | |
779 | case MMC_BUS_WIDTH_4: | |
780 | tmp |= CMD_SET_DATW_4; | |
781 | break; | |
782 | case MMC_BUS_WIDTH_8: | |
783 | tmp |= CMD_SET_DATW_8; | |
784 | break; | |
785 | default: | |
e47bf32a | 786 | dev_err(&host->pd->dev, "Unsupported bus width.\n"); |
fdc50a94 YG |
787 | break; |
788 | } | |
555061f9 TK |
789 | switch (host->timing) { |
790 | case MMC_TIMING_UHS_DDR50: | |
791 | /* | |
792 | * MMC core will only set this timing, if the host | |
793 | * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF | |
794 | * implementations with this capability, e.g. sh73a0, | |
795 | * will have to set it in their platform data. | |
796 | */ | |
797 | tmp |= CMD_SET_DARS; | |
798 | break; | |
799 | } | |
fdc50a94 YG |
800 | } |
801 | /* DWEN */ | |
802 | if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) | |
803 | tmp |= CMD_SET_DWEN; | |
804 | /* CMLTE/CMD12EN */ | |
805 | if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { | |
806 | tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; | |
807 | sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, | |
69983404 | 808 | data->blocks << 16); |
fdc50a94 YG |
809 | } |
810 | /* RIDXC[1:0] check bits */ | |
811 | if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || | |
812 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
813 | tmp |= CMD_SET_RIDXC_BITS; | |
814 | /* RCRC7C[1:0] check bits */ | |
815 | if (opc == MMC_SEND_OP_COND) | |
816 | tmp |= CMD_SET_CRC7C_BITS; | |
817 | /* RCRC7C[1:0] internal CRC7 */ | |
818 | if (opc == MMC_ALL_SEND_CID || | |
819 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
820 | tmp |= CMD_SET_CRC7C_INTERNAL; | |
821 | ||
69983404 | 822 | return (opc << 24) | tmp; |
fdc50a94 YG |
823 | } |
824 | ||
e47bf32a | 825 | static int sh_mmcif_data_trans(struct sh_mmcif_host *host, |
f985da17 | 826 | struct mmc_request *mrq, u32 opc) |
fdc50a94 | 827 | { |
fdc50a94 YG |
828 | switch (opc) { |
829 | case MMC_READ_MULTIPLE_BLOCK: | |
f985da17 GL |
830 | sh_mmcif_multi_read(host, mrq); |
831 | return 0; | |
fdc50a94 | 832 | case MMC_WRITE_MULTIPLE_BLOCK: |
f985da17 GL |
833 | sh_mmcif_multi_write(host, mrq); |
834 | return 0; | |
fdc50a94 | 835 | case MMC_WRITE_BLOCK: |
f985da17 GL |
836 | sh_mmcif_single_write(host, mrq); |
837 | return 0; | |
fdc50a94 YG |
838 | case MMC_READ_SINGLE_BLOCK: |
839 | case MMC_SEND_EXT_CSD: | |
f985da17 GL |
840 | sh_mmcif_single_read(host, mrq); |
841 | return 0; | |
fdc50a94 | 842 | default: |
e475b270 | 843 | dev_err(&host->pd->dev, "Unsupported CMD%d\n", opc); |
ee4b8887 | 844 | return -EINVAL; |
fdc50a94 | 845 | } |
fdc50a94 YG |
846 | } |
847 | ||
848 | static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, | |
ee4b8887 | 849 | struct mmc_request *mrq) |
fdc50a94 | 850 | { |
ee4b8887 | 851 | struct mmc_command *cmd = mrq->cmd; |
f985da17 GL |
852 | u32 opc = cmd->opcode; |
853 | u32 mask; | |
fdc50a94 | 854 | |
fdc50a94 | 855 | switch (opc) { |
ee4b8887 | 856 | /* response busy check */ |
a812ba0f | 857 | case MMC_SLEEP_AWAKE: |
fdc50a94 YG |
858 | case MMC_SWITCH: |
859 | case MMC_STOP_TRANSMISSION: | |
860 | case MMC_SET_WRITE_PROT: | |
861 | case MMC_CLR_WRITE_PROT: | |
862 | case MMC_ERASE: | |
ee4b8887 | 863 | mask = MASK_START_CMD | MASK_MRBSYE; |
fdc50a94 YG |
864 | break; |
865 | default: | |
ee4b8887 | 866 | mask = MASK_START_CMD | MASK_MCRSPE; |
fdc50a94 YG |
867 | break; |
868 | } | |
fdc50a94 | 869 | |
69983404 | 870 | if (mrq->data) { |
487d9fc5 MD |
871 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); |
872 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, | |
873 | mrq->data->blksz); | |
fdc50a94 | 874 | } |
69983404 | 875 | opc = sh_mmcif_set_cmd(host, mrq); |
fdc50a94 | 876 | |
487d9fc5 MD |
877 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); |
878 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); | |
fdc50a94 | 879 | /* set arg */ |
487d9fc5 | 880 | sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); |
fdc50a94 | 881 | /* set cmd */ |
487d9fc5 | 882 | sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); |
fdc50a94 | 883 | |
f985da17 GL |
884 | host->wait_for = MMCIF_WAIT_FOR_CMD; |
885 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
fdc50a94 YG |
886 | } |
887 | ||
888 | static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, | |
ee4b8887 | 889 | struct mmc_request *mrq) |
fdc50a94 | 890 | { |
69983404 GL |
891 | switch (mrq->cmd->opcode) { |
892 | case MMC_READ_MULTIPLE_BLOCK: | |
fdc50a94 | 893 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); |
69983404 GL |
894 | break; |
895 | case MMC_WRITE_MULTIPLE_BLOCK: | |
fdc50a94 | 896 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); |
69983404 GL |
897 | break; |
898 | default: | |
e47bf32a | 899 | dev_err(&host->pd->dev, "unsupported stop cmd\n"); |
69983404 | 900 | mrq->stop->error = sh_mmcif_error_manage(host); |
fdc50a94 YG |
901 | return; |
902 | } | |
903 | ||
f985da17 | 904 | host->wait_for = MMCIF_WAIT_FOR_STOP; |
fdc50a94 YG |
905 | } |
906 | ||
907 | static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
908 | { | |
909 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
3b0beafc GL |
910 | unsigned long flags; |
911 | ||
912 | spin_lock_irqsave(&host->lock, flags); | |
913 | if (host->state != STATE_IDLE) { | |
e475b270 | 914 | dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); |
3b0beafc GL |
915 | spin_unlock_irqrestore(&host->lock, flags); |
916 | mrq->cmd->error = -EAGAIN; | |
917 | mmc_request_done(mmc, mrq); | |
918 | return; | |
919 | } | |
920 | ||
921 | host->state = STATE_REQUEST; | |
922 | spin_unlock_irqrestore(&host->lock, flags); | |
fdc50a94 YG |
923 | |
924 | switch (mrq->cmd->opcode) { | |
925 | /* MMCIF does not support SD/SDIO command */ | |
7541ca98 LP |
926 | case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ |
927 | case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ | |
928 | if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) | |
929 | break; | |
fdc50a94 | 930 | case MMC_APP_CMD: |
92ff0c5b | 931 | case SD_IO_RW_DIRECT: |
3b0beafc | 932 | host->state = STATE_IDLE; |
fdc50a94 YG |
933 | mrq->cmd->error = -ETIMEDOUT; |
934 | mmc_request_done(mmc, mrq); | |
935 | return; | |
fdc50a94 YG |
936 | default: |
937 | break; | |
938 | } | |
f985da17 GL |
939 | |
940 | host->mrq = mrq; | |
fdc50a94 | 941 | |
f985da17 | 942 | sh_mmcif_start_cmd(host, mrq); |
fdc50a94 YG |
943 | } |
944 | ||
a6609267 GL |
945 | static int sh_mmcif_clk_update(struct sh_mmcif_host *host) |
946 | { | |
947 | int ret = clk_enable(host->hclk); | |
948 | ||
949 | if (!ret) { | |
950 | host->clk = clk_get_rate(host->hclk); | |
951 | host->mmc->f_max = host->clk / 2; | |
952 | host->mmc->f_min = host->clk / 512; | |
953 | } | |
954 | ||
955 | return ret; | |
956 | } | |
957 | ||
7d17baa0 GL |
958 | static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) |
959 | { | |
7d17baa0 GL |
960 | struct mmc_host *mmc = host->mmc; |
961 | ||
7d17baa0 GL |
962 | if (!IS_ERR(mmc->supply.vmmc)) |
963 | /* Errors ignored... */ | |
964 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, | |
965 | ios->power_mode ? ios->vdd : 0); | |
966 | } | |
967 | ||
fdc50a94 YG |
968 | static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
969 | { | |
970 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
3b0beafc GL |
971 | unsigned long flags; |
972 | ||
973 | spin_lock_irqsave(&host->lock, flags); | |
974 | if (host->state != STATE_IDLE) { | |
e475b270 | 975 | dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); |
3b0beafc GL |
976 | spin_unlock_irqrestore(&host->lock, flags); |
977 | return; | |
978 | } | |
979 | ||
980 | host->state = STATE_IOS; | |
981 | spin_unlock_irqrestore(&host->lock, flags); | |
fdc50a94 | 982 | |
f5e0cec4 | 983 | if (ios->power_mode == MMC_POWER_UP) { |
c9b0cef2 | 984 | if (!host->card_present) { |
faca6648 GL |
985 | /* See if we also get DMA */ |
986 | sh_mmcif_request_dma(host, host->pd->dev.platform_data); | |
c9b0cef2 | 987 | host->card_present = true; |
faca6648 | 988 | } |
7d17baa0 | 989 | sh_mmcif_set_power(host, ios); |
f5e0cec4 | 990 | } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { |
fdc50a94 YG |
991 | /* clock stop */ |
992 | sh_mmcif_clock_control(host, 0); | |
faca6648 | 993 | if (ios->power_mode == MMC_POWER_OFF) { |
c9b0cef2 | 994 | if (host->card_present) { |
faca6648 | 995 | sh_mmcif_release_dma(host); |
c9b0cef2 | 996 | host->card_present = false; |
faca6648 | 997 | } |
c9b0cef2 GL |
998 | } |
999 | if (host->power) { | |
f8a8ced7 | 1000 | pm_runtime_put_sync(&host->pd->dev); |
b289174f | 1001 | clk_disable(host->hclk); |
c9b0cef2 | 1002 | host->power = false; |
7d17baa0 GL |
1003 | if (ios->power_mode == MMC_POWER_OFF) |
1004 | sh_mmcif_set_power(host, ios); | |
faca6648 | 1005 | } |
3b0beafc | 1006 | host->state = STATE_IDLE; |
fdc50a94 | 1007 | return; |
fdc50a94 YG |
1008 | } |
1009 | ||
c9b0cef2 GL |
1010 | if (ios->clock) { |
1011 | if (!host->power) { | |
a6609267 | 1012 | sh_mmcif_clk_update(host); |
c9b0cef2 GL |
1013 | pm_runtime_get_sync(&host->pd->dev); |
1014 | host->power = true; | |
1015 | sh_mmcif_sync_reset(host); | |
1016 | } | |
fdc50a94 | 1017 | sh_mmcif_clock_control(host, ios->clock); |
c9b0cef2 | 1018 | } |
fdc50a94 | 1019 | |
555061f9 | 1020 | host->timing = ios->timing; |
fdc50a94 | 1021 | host->bus_width = ios->bus_width; |
3b0beafc | 1022 | host->state = STATE_IDLE; |
fdc50a94 YG |
1023 | } |
1024 | ||
777271d0 AH |
1025 | static int sh_mmcif_get_cd(struct mmc_host *mmc) |
1026 | { | |
1027 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
1028 | struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; | |
e480606a GL |
1029 | int ret = mmc_gpio_get_cd(mmc); |
1030 | ||
1031 | if (ret >= 0) | |
1032 | return ret; | |
777271d0 | 1033 | |
bf68a812 | 1034 | if (!p || !p->get_cd) |
777271d0 AH |
1035 | return -ENOSYS; |
1036 | else | |
1037 | return p->get_cd(host->pd); | |
1038 | } | |
1039 | ||
fdc50a94 YG |
1040 | static struct mmc_host_ops sh_mmcif_ops = { |
1041 | .request = sh_mmcif_request, | |
1042 | .set_ios = sh_mmcif_set_ios, | |
777271d0 | 1043 | .get_cd = sh_mmcif_get_cd, |
fdc50a94 YG |
1044 | }; |
1045 | ||
f985da17 GL |
1046 | static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) |
1047 | { | |
1048 | struct mmc_command *cmd = host->mrq->cmd; | |
69983404 | 1049 | struct mmc_data *data = host->mrq->data; |
f985da17 GL |
1050 | long time; |
1051 | ||
1052 | if (host->sd_error) { | |
1053 | switch (cmd->opcode) { | |
1054 | case MMC_ALL_SEND_CID: | |
1055 | case MMC_SELECT_CARD: | |
1056 | case MMC_APP_CMD: | |
1057 | cmd->error = -ETIMEDOUT; | |
f985da17 GL |
1058 | break; |
1059 | default: | |
1060 | cmd->error = sh_mmcif_error_manage(host); | |
f985da17 GL |
1061 | break; |
1062 | } | |
e475b270 TK |
1063 | dev_dbg(&host->pd->dev, "CMD%d error %d\n", |
1064 | cmd->opcode, cmd->error); | |
aba9d646 | 1065 | host->sd_error = false; |
f985da17 GL |
1066 | return false; |
1067 | } | |
1068 | if (!(cmd->flags & MMC_RSP_PRESENT)) { | |
1069 | cmd->error = 0; | |
1070 | return false; | |
1071 | } | |
1072 | ||
1073 | sh_mmcif_get_response(host, cmd); | |
1074 | ||
69983404 | 1075 | if (!data) |
f985da17 GL |
1076 | return false; |
1077 | ||
90f1cb43 GL |
1078 | /* |
1079 | * Completion can be signalled from DMA callback and error, so, have to | |
1080 | * reset here, before setting .dma_active | |
1081 | */ | |
1082 | init_completion(&host->dma_complete); | |
1083 | ||
69983404 | 1084 | if (data->flags & MMC_DATA_READ) { |
f985da17 GL |
1085 | if (host->chan_rx) |
1086 | sh_mmcif_start_dma_rx(host); | |
1087 | } else { | |
1088 | if (host->chan_tx) | |
1089 | sh_mmcif_start_dma_tx(host); | |
1090 | } | |
1091 | ||
1092 | if (!host->dma_active) { | |
69983404 | 1093 | data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); |
99eb9d8d | 1094 | return !data->error; |
f985da17 GL |
1095 | } |
1096 | ||
1097 | /* Running in the IRQ thread, can sleep */ | |
1098 | time = wait_for_completion_interruptible_timeout(&host->dma_complete, | |
1099 | host->timeout); | |
eae30983 TK |
1100 | |
1101 | if (data->flags & MMC_DATA_READ) | |
1102 | dma_unmap_sg(host->chan_rx->device->dev, | |
1103 | data->sg, data->sg_len, | |
1104 | DMA_FROM_DEVICE); | |
1105 | else | |
1106 | dma_unmap_sg(host->chan_tx->device->dev, | |
1107 | data->sg, data->sg_len, | |
1108 | DMA_TO_DEVICE); | |
1109 | ||
f985da17 GL |
1110 | if (host->sd_error) { |
1111 | dev_err(host->mmc->parent, | |
1112 | "Error IRQ while waiting for DMA completion!\n"); | |
1113 | /* Woken up by an error IRQ: abort DMA */ | |
69983404 | 1114 | data->error = sh_mmcif_error_manage(host); |
f985da17 | 1115 | } else if (!time) { |
e475b270 | 1116 | dev_err(host->mmc->parent, "DMA timeout!\n"); |
69983404 | 1117 | data->error = -ETIMEDOUT; |
f985da17 | 1118 | } else if (time < 0) { |
e475b270 TK |
1119 | dev_err(host->mmc->parent, |
1120 | "wait_for_completion_...() error %ld!\n", time); | |
69983404 | 1121 | data->error = time; |
f985da17 GL |
1122 | } |
1123 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, | |
1124 | BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
1125 | host->dma_active = false; | |
1126 | ||
eae30983 | 1127 | if (data->error) { |
69983404 | 1128 | data->bytes_xfered = 0; |
eae30983 TK |
1129 | /* Abort DMA */ |
1130 | if (data->flags & MMC_DATA_READ) | |
1131 | dmaengine_terminate_all(host->chan_rx); | |
1132 | else | |
1133 | dmaengine_terminate_all(host->chan_tx); | |
1134 | } | |
f985da17 GL |
1135 | |
1136 | return false; | |
1137 | } | |
1138 | ||
1139 | static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) | |
1140 | { | |
1141 | struct sh_mmcif_host *host = dev_id; | |
8047310e | 1142 | struct mmc_request *mrq; |
5df460b1 | 1143 | bool wait = false; |
f985da17 GL |
1144 | |
1145 | cancel_delayed_work_sync(&host->timeout_work); | |
1146 | ||
8047310e GL |
1147 | mutex_lock(&host->thread_lock); |
1148 | ||
1149 | mrq = host->mrq; | |
1150 | if (!mrq) { | |
1151 | dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n", | |
1152 | host->state, host->wait_for); | |
1153 | mutex_unlock(&host->thread_lock); | |
1154 | return IRQ_HANDLED; | |
1155 | } | |
1156 | ||
f985da17 GL |
1157 | /* |
1158 | * All handlers return true, if processing continues, and false, if the | |
1159 | * request has to be completed - successfully or not | |
1160 | */ | |
1161 | switch (host->wait_for) { | |
1162 | case MMCIF_WAIT_FOR_REQUEST: | |
1163 | /* We're too late, the timeout has already kicked in */ | |
8047310e | 1164 | mutex_unlock(&host->thread_lock); |
f985da17 GL |
1165 | return IRQ_HANDLED; |
1166 | case MMCIF_WAIT_FOR_CMD: | |
5df460b1 GL |
1167 | /* Wait for data? */ |
1168 | wait = sh_mmcif_end_cmd(host); | |
f985da17 GL |
1169 | break; |
1170 | case MMCIF_WAIT_FOR_MREAD: | |
5df460b1 GL |
1171 | /* Wait for more data? */ |
1172 | wait = sh_mmcif_mread_block(host); | |
f985da17 GL |
1173 | break; |
1174 | case MMCIF_WAIT_FOR_READ: | |
5df460b1 GL |
1175 | /* Wait for data end? */ |
1176 | wait = sh_mmcif_read_block(host); | |
f985da17 GL |
1177 | break; |
1178 | case MMCIF_WAIT_FOR_MWRITE: | |
5df460b1 GL |
1179 | /* Wait data to write? */ |
1180 | wait = sh_mmcif_mwrite_block(host); | |
f985da17 GL |
1181 | break; |
1182 | case MMCIF_WAIT_FOR_WRITE: | |
5df460b1 GL |
1183 | /* Wait for data end? */ |
1184 | wait = sh_mmcif_write_block(host); | |
f985da17 GL |
1185 | break; |
1186 | case MMCIF_WAIT_FOR_STOP: | |
1187 | if (host->sd_error) { | |
1188 | mrq->stop->error = sh_mmcif_error_manage(host); | |
e475b270 | 1189 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->stop->error); |
f985da17 GL |
1190 | break; |
1191 | } | |
1192 | sh_mmcif_get_cmd12response(host, mrq->stop); | |
1193 | mrq->stop->error = 0; | |
1194 | break; | |
1195 | case MMCIF_WAIT_FOR_READ_END: | |
1196 | case MMCIF_WAIT_FOR_WRITE_END: | |
e475b270 | 1197 | if (host->sd_error) { |
91ab252a | 1198 | mrq->data->error = sh_mmcif_error_manage(host); |
e475b270 TK |
1199 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->data->error); |
1200 | } | |
f985da17 GL |
1201 | break; |
1202 | default: | |
1203 | BUG(); | |
1204 | } | |
1205 | ||
5df460b1 GL |
1206 | if (wait) { |
1207 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
1208 | /* Wait for more data */ | |
8047310e | 1209 | mutex_unlock(&host->thread_lock); |
5df460b1 GL |
1210 | return IRQ_HANDLED; |
1211 | } | |
1212 | ||
f985da17 | 1213 | if (host->wait_for != MMCIF_WAIT_FOR_STOP) { |
91ab252a | 1214 | struct mmc_data *data = mrq->data; |
69983404 GL |
1215 | if (!mrq->cmd->error && data && !data->error) |
1216 | data->bytes_xfered = | |
1217 | data->blocks * data->blksz; | |
f985da17 | 1218 | |
69983404 | 1219 | if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { |
f985da17 | 1220 | sh_mmcif_stop_cmd(host, mrq); |
5df460b1 GL |
1221 | if (!mrq->stop->error) { |
1222 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
8047310e | 1223 | mutex_unlock(&host->thread_lock); |
f985da17 | 1224 | return IRQ_HANDLED; |
5df460b1 | 1225 | } |
f985da17 GL |
1226 | } |
1227 | } | |
1228 | ||
1229 | host->wait_for = MMCIF_WAIT_FOR_REQUEST; | |
1230 | host->state = STATE_IDLE; | |
69983404 | 1231 | host->mrq = NULL; |
f985da17 GL |
1232 | mmc_request_done(host->mmc, mrq); |
1233 | ||
8047310e GL |
1234 | mutex_unlock(&host->thread_lock); |
1235 | ||
f985da17 GL |
1236 | return IRQ_HANDLED; |
1237 | } | |
1238 | ||
fdc50a94 YG |
1239 | static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) |
1240 | { | |
1241 | struct sh_mmcif_host *host = dev_id; | |
aa0787a9 | 1242 | u32 state; |
fdc50a94 | 1243 | |
487d9fc5 | 1244 | state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); |
19f1ba51 GL |
1245 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, |
1246 | ~(state & sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK))); | |
8af50750 | 1247 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); |
fdc50a94 | 1248 | |
8af50750 GL |
1249 | if (state & ~MASK_CLEAN) |
1250 | dev_dbg(&host->pd->dev, "IRQ state = 0x%08x incompletely cleared\n", | |
1251 | state); | |
1252 | ||
1253 | if (state & INT_ERR_STS || state & ~INT_ALL) { | |
aa0787a9 | 1254 | host->sd_error = true; |
8af50750 | 1255 | dev_dbg(&host->pd->dev, "int err state = 0x%08x\n", state); |
fdc50a94 | 1256 | } |
f985da17 | 1257 | if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { |
8af50750 GL |
1258 | if (!host->mrq) |
1259 | dev_dbg(&host->pd->dev, "NULL IRQ state = 0x%08x\n", state); | |
f985da17 GL |
1260 | if (!host->dma_active) |
1261 | return IRQ_WAKE_THREAD; | |
1262 | else if (host->sd_error) | |
1263 | mmcif_dma_complete(host); | |
1264 | } else { | |
aa0787a9 | 1265 | dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); |
f985da17 | 1266 | } |
fdc50a94 YG |
1267 | |
1268 | return IRQ_HANDLED; | |
1269 | } | |
1270 | ||
f985da17 GL |
1271 | static void mmcif_timeout_work(struct work_struct *work) |
1272 | { | |
1273 | struct delayed_work *d = container_of(work, struct delayed_work, work); | |
1274 | struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); | |
1275 | struct mmc_request *mrq = host->mrq; | |
8047310e | 1276 | unsigned long flags; |
f985da17 GL |
1277 | |
1278 | if (host->dying) | |
1279 | /* Don't run after mmc_remove_host() */ | |
1280 | return; | |
1281 | ||
e475b270 | 1282 | dev_err(&host->pd->dev, "Timeout waiting for %u on CMD%u\n", |
8047310e GL |
1283 | host->wait_for, mrq->cmd->opcode); |
1284 | ||
1285 | spin_lock_irqsave(&host->lock, flags); | |
1286 | if (host->state == STATE_IDLE) { | |
1287 | spin_unlock_irqrestore(&host->lock, flags); | |
1288 | return; | |
1289 | } | |
1290 | ||
1291 | host->state = STATE_TIMEOUT; | |
1292 | spin_unlock_irqrestore(&host->lock, flags); | |
1293 | ||
f985da17 GL |
1294 | /* |
1295 | * Handle races with cancel_delayed_work(), unless | |
1296 | * cancel_delayed_work_sync() is used | |
1297 | */ | |
1298 | switch (host->wait_for) { | |
1299 | case MMCIF_WAIT_FOR_CMD: | |
1300 | mrq->cmd->error = sh_mmcif_error_manage(host); | |
1301 | break; | |
1302 | case MMCIF_WAIT_FOR_STOP: | |
1303 | mrq->stop->error = sh_mmcif_error_manage(host); | |
1304 | break; | |
1305 | case MMCIF_WAIT_FOR_MREAD: | |
1306 | case MMCIF_WAIT_FOR_MWRITE: | |
1307 | case MMCIF_WAIT_FOR_READ: | |
1308 | case MMCIF_WAIT_FOR_WRITE: | |
1309 | case MMCIF_WAIT_FOR_READ_END: | |
1310 | case MMCIF_WAIT_FOR_WRITE_END: | |
69983404 | 1311 | mrq->data->error = sh_mmcif_error_manage(host); |
f985da17 GL |
1312 | break; |
1313 | default: | |
1314 | BUG(); | |
1315 | } | |
1316 | ||
1317 | host->state = STATE_IDLE; | |
1318 | host->wait_for = MMCIF_WAIT_FOR_REQUEST; | |
f985da17 GL |
1319 | host->mrq = NULL; |
1320 | mmc_request_done(host->mmc, mrq); | |
1321 | } | |
1322 | ||
7d17baa0 GL |
1323 | static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) |
1324 | { | |
1325 | struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; | |
1326 | struct mmc_host *mmc = host->mmc; | |
1327 | ||
1328 | mmc_regulator_get_supply(mmc); | |
1329 | ||
bf68a812 GL |
1330 | if (!pd) |
1331 | return; | |
1332 | ||
7d17baa0 GL |
1333 | if (!mmc->ocr_avail) |
1334 | mmc->ocr_avail = pd->ocr; | |
1335 | else if (pd->ocr) | |
1336 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); | |
1337 | } | |
1338 | ||
c3be1efd | 1339 | static int sh_mmcif_probe(struct platform_device *pdev) |
fdc50a94 YG |
1340 | { |
1341 | int ret = 0, irq[2]; | |
1342 | struct mmc_host *mmc; | |
e47bf32a | 1343 | struct sh_mmcif_host *host; |
e1aae2eb | 1344 | struct sh_mmcif_plat_data *pd = pdev->dev.platform_data; |
fdc50a94 YG |
1345 | struct resource *res; |
1346 | void __iomem *reg; | |
2cd5b3e0 | 1347 | const char *name; |
fdc50a94 YG |
1348 | |
1349 | irq[0] = platform_get_irq(pdev, 0); | |
1350 | irq[1] = platform_get_irq(pdev, 1); | |
2cd5b3e0 | 1351 | if (irq[0] < 0) { |
e47bf32a | 1352 | dev_err(&pdev->dev, "Get irq error\n"); |
fdc50a94 YG |
1353 | return -ENXIO; |
1354 | } | |
1355 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1356 | if (!res) { | |
1357 | dev_err(&pdev->dev, "platform_get_resource error.\n"); | |
1358 | return -ENXIO; | |
1359 | } | |
1360 | reg = ioremap(res->start, resource_size(res)); | |
1361 | if (!reg) { | |
1362 | dev_err(&pdev->dev, "ioremap error.\n"); | |
1363 | return -ENOMEM; | |
1364 | } | |
e1aae2eb | 1365 | |
fdc50a94 YG |
1366 | mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); |
1367 | if (!mmc) { | |
1368 | ret = -ENOMEM; | |
e1aae2eb | 1369 | goto ealloch; |
fdc50a94 | 1370 | } |
2c9054dc SB |
1371 | |
1372 | ret = mmc_of_parse(mmc); | |
1373 | if (ret < 0) | |
1374 | goto eofparse; | |
1375 | ||
fdc50a94 YG |
1376 | host = mmc_priv(mmc); |
1377 | host->mmc = mmc; | |
1378 | host->addr = reg; | |
f9fd54f2 | 1379 | host->timeout = msecs_to_jiffies(1000); |
fdc50a94 | 1380 | |
fdc50a94 YG |
1381 | host->pd = pdev; |
1382 | ||
3b0beafc | 1383 | spin_lock_init(&host->lock); |
fdc50a94 YG |
1384 | |
1385 | mmc->ops = &sh_mmcif_ops; | |
7d17baa0 GL |
1386 | sh_mmcif_init_ocr(host); |
1387 | ||
eca889f6 | 1388 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; |
bf68a812 | 1389 | if (pd && pd->caps) |
fdc50a94 | 1390 | mmc->caps |= pd->caps; |
a782d688 | 1391 | mmc->max_segs = 32; |
fdc50a94 | 1392 | mmc->max_blk_size = 512; |
a782d688 GL |
1393 | mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; |
1394 | mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; | |
fdc50a94 YG |
1395 | mmc->max_seg_size = mmc->max_req_size; |
1396 | ||
fdc50a94 | 1397 | platform_set_drvdata(pdev, host); |
a782d688 | 1398 | |
faca6648 GL |
1399 | pm_runtime_enable(&pdev->dev); |
1400 | host->power = false; | |
1401 | ||
047a9ce7 | 1402 | host->hclk = clk_get(&pdev->dev, NULL); |
b289174f GL |
1403 | if (IS_ERR(host->hclk)) { |
1404 | ret = PTR_ERR(host->hclk); | |
047a9ce7 | 1405 | dev_err(&pdev->dev, "cannot get clock: %d\n", ret); |
b289174f GL |
1406 | goto eclkget; |
1407 | } | |
a6609267 GL |
1408 | ret = sh_mmcif_clk_update(host); |
1409 | if (ret < 0) | |
1410 | goto eclkupdate; | |
b289174f | 1411 | |
faca6648 GL |
1412 | ret = pm_runtime_resume(&pdev->dev); |
1413 | if (ret < 0) | |
e1aae2eb | 1414 | goto eresume; |
a782d688 | 1415 | |
5ba85d95 | 1416 | INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); |
fdc50a94 | 1417 | |
b289174f | 1418 | sh_mmcif_sync_reset(host); |
3b0beafc GL |
1419 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
1420 | ||
2cd5b3e0 SK |
1421 | name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error"; |
1422 | ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, name, host); | |
fdc50a94 | 1423 | if (ret) { |
2cd5b3e0 | 1424 | dev_err(&pdev->dev, "request_irq error (%s)\n", name); |
e1aae2eb | 1425 | goto ereqirq0; |
fdc50a94 | 1426 | } |
2cd5b3e0 SK |
1427 | if (irq[1] >= 0) { |
1428 | ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, | |
1429 | 0, "sh_mmc:int", host); | |
1430 | if (ret) { | |
1431 | dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); | |
1432 | goto ereqirq1; | |
1433 | } | |
fdc50a94 YG |
1434 | } |
1435 | ||
e480606a | 1436 | if (pd && pd->use_cd_gpio) { |
214fc309 | 1437 | ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0); |
e480606a GL |
1438 | if (ret < 0) |
1439 | goto erqcd; | |
1440 | } | |
1441 | ||
8047310e GL |
1442 | mutex_init(&host->thread_lock); |
1443 | ||
b289174f | 1444 | clk_disable(host->hclk); |
5ba85d95 GL |
1445 | ret = mmc_add_host(mmc); |
1446 | if (ret < 0) | |
e1aae2eb | 1447 | goto emmcaddh; |
fdc50a94 | 1448 | |
efe6a8ad RW |
1449 | dev_pm_qos_expose_latency_limit(&pdev->dev, 100); |
1450 | ||
e47bf32a GL |
1451 | dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); |
1452 | dev_dbg(&pdev->dev, "chip ver H'%04x\n", | |
487d9fc5 | 1453 | sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); |
fdc50a94 YG |
1454 | return ret; |
1455 | ||
e1aae2eb | 1456 | emmcaddh: |
e480606a | 1457 | erqcd: |
2cd5b3e0 SK |
1458 | if (irq[1] >= 0) |
1459 | free_irq(irq[1], host); | |
e1aae2eb | 1460 | ereqirq1: |
5ba85d95 | 1461 | free_irq(irq[0], host); |
e1aae2eb | 1462 | ereqirq0: |
faca6648 | 1463 | pm_runtime_suspend(&pdev->dev); |
e1aae2eb | 1464 | eresume: |
fdc50a94 | 1465 | clk_disable(host->hclk); |
a6609267 | 1466 | eclkupdate: |
b289174f | 1467 | clk_put(host->hclk); |
e1aae2eb | 1468 | eclkget: |
b289174f | 1469 | pm_runtime_disable(&pdev->dev); |
2c9054dc | 1470 | eofparse: |
fdc50a94 | 1471 | mmc_free_host(mmc); |
e1aae2eb GL |
1472 | ealloch: |
1473 | iounmap(reg); | |
fdc50a94 YG |
1474 | return ret; |
1475 | } | |
1476 | ||
6e0ee714 | 1477 | static int sh_mmcif_remove(struct platform_device *pdev) |
fdc50a94 YG |
1478 | { |
1479 | struct sh_mmcif_host *host = platform_get_drvdata(pdev); | |
1480 | int irq[2]; | |
1481 | ||
f985da17 | 1482 | host->dying = true; |
b289174f | 1483 | clk_enable(host->hclk); |
faca6648 | 1484 | pm_runtime_get_sync(&pdev->dev); |
fdc50a94 | 1485 | |
efe6a8ad RW |
1486 | dev_pm_qos_hide_latency_limit(&pdev->dev); |
1487 | ||
faca6648 | 1488 | mmc_remove_host(host->mmc); |
3b0beafc GL |
1489 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
1490 | ||
f985da17 GL |
1491 | /* |
1492 | * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the | |
1493 | * mmc_remove_host() call above. But swapping order doesn't help either | |
1494 | * (a query on the linux-mmc mailing list didn't bring any replies). | |
1495 | */ | |
1496 | cancel_delayed_work_sync(&host->timeout_work); | |
1497 | ||
fdc50a94 YG |
1498 | if (host->addr) |
1499 | iounmap(host->addr); | |
1500 | ||
aa0787a9 GL |
1501 | irq[0] = platform_get_irq(pdev, 0); |
1502 | irq[1] = platform_get_irq(pdev, 1); | |
fdc50a94 YG |
1503 | |
1504 | free_irq(irq[0], host); | |
2cd5b3e0 SK |
1505 | if (irq[1] >= 0) |
1506 | free_irq(irq[1], host); | |
fdc50a94 | 1507 | |
a0d28ba0 | 1508 | clk_disable(host->hclk); |
fdc50a94 | 1509 | mmc_free_host(host->mmc); |
faca6648 GL |
1510 | pm_runtime_put_sync(&pdev->dev); |
1511 | pm_runtime_disable(&pdev->dev); | |
fdc50a94 YG |
1512 | |
1513 | return 0; | |
1514 | } | |
1515 | ||
faca6648 GL |
1516 | #ifdef CONFIG_PM |
1517 | static int sh_mmcif_suspend(struct device *dev) | |
1518 | { | |
b289174f | 1519 | struct sh_mmcif_host *host = dev_get_drvdata(dev); |
faca6648 GL |
1520 | int ret = mmc_suspend_host(host->mmc); |
1521 | ||
b289174f | 1522 | if (!ret) |
faca6648 | 1523 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
faca6648 GL |
1524 | |
1525 | return ret; | |
1526 | } | |
1527 | ||
1528 | static int sh_mmcif_resume(struct device *dev) | |
1529 | { | |
b289174f | 1530 | struct sh_mmcif_host *host = dev_get_drvdata(dev); |
faca6648 GL |
1531 | |
1532 | return mmc_resume_host(host->mmc); | |
1533 | } | |
1534 | #else | |
1535 | #define sh_mmcif_suspend NULL | |
1536 | #define sh_mmcif_resume NULL | |
1537 | #endif /* CONFIG_PM */ | |
1538 | ||
bf68a812 GL |
1539 | static const struct of_device_id mmcif_of_match[] = { |
1540 | { .compatible = "renesas,sh-mmcif" }, | |
1541 | { } | |
1542 | }; | |
1543 | MODULE_DEVICE_TABLE(of, mmcif_of_match); | |
1544 | ||
faca6648 GL |
1545 | static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { |
1546 | .suspend = sh_mmcif_suspend, | |
1547 | .resume = sh_mmcif_resume, | |
1548 | }; | |
1549 | ||
fdc50a94 YG |
1550 | static struct platform_driver sh_mmcif_driver = { |
1551 | .probe = sh_mmcif_probe, | |
1552 | .remove = sh_mmcif_remove, | |
1553 | .driver = { | |
1554 | .name = DRIVER_NAME, | |
faca6648 | 1555 | .pm = &sh_mmcif_dev_pm_ops, |
bf68a812 GL |
1556 | .owner = THIS_MODULE, |
1557 | .of_match_table = mmcif_of_match, | |
fdc50a94 YG |
1558 | }, |
1559 | }; | |
1560 | ||
d1f81a64 | 1561 | module_platform_driver(sh_mmcif_driver); |
fdc50a94 YG |
1562 | |
1563 | MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); | |
1564 | MODULE_LICENSE("GPL"); | |
aa0787a9 | 1565 | MODULE_ALIAS("platform:" DRIVER_NAME); |
fdc50a94 | 1566 | MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); |