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mmc: sdhi: add OF support, make platform data optional
[linux-2.6-block.git] / drivers / mmc / host / sh_mmcif.c
CommitLineData
fdc50a94
YG		 1/*
2 * MMCIF eMMC driver.
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10 *
11 *
12 * TODO
13 * 1. DMA
14 * 2. Power management
15 * 3. Handle MMC errors better
16 *
17 */
18
f985da17
GL		 19/*
20 * The MMCIF driver is now processing MMC requests asynchronously, according
21 * to the Linux MMC API requirement.
22 *
23 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
24 * data, and optional stop. To achieve asynchronous processing each of these
25 * stages is split into two halves: a top and a bottom half. The top half
26 * initialises the hardware, installs a timeout handler to handle completion
27 * timeouts, and returns. In case of the command stage this immediately returns
28 * control to the caller, leaving all further processing to run asynchronously.
29 * All further request processing is performed by the bottom halves.
30 *
31 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
32 * thread, a DMA completion callback, if DMA is used, a timeout work, and
33 * request- and stage-specific handler methods.
34 *
35 * Each bottom half run begins with either a hardware interrupt, a DMA callback
36 * invocation, or a timeout work run. In case of an error or a successful
37 * processing completion, the MMC core is informed and the request processing is
38 * finished. In case processing has to continue, i.e., if data has to be read
39 * from or written to the card, or if a stop command has to be sent, the next
40 * top half is called, which performs the necessary hardware handling and
41 * reschedules the timeout work. This returns the driver state machine into the
42 * bottom half waiting state.
43 */
44
86df1745 45#include <linux/bitops.h>
aa0787a9
GL		 46#include <linux/clk.h>
47#include <linux/completion.h>
e47bf32a 48#include <linux/delay.h>
fdc50a94 49#include <linux/dma-mapping.h>
a782d688 50#include <linux/dmaengine.h>
fdc50a94
YG		 51#include <linux/mmc/card.h>
52#include <linux/mmc/core.h>
e47bf32a 53#include <linux/mmc/host.h>
fdc50a94
YG		 54#include <linux/mmc/mmc.h>
55#include <linux/mmc/sdio.h>
fdc50a94 56#include <linux/mmc/sh_mmcif.h>
a782d688 57#include <linux/pagemap.h>
e47bf32a 58#include <linux/platform_device.h>
efe6a8ad 59#include <linux/pm_qos.h>
faca6648 60#include <linux/pm_runtime.h>
3b0beafc 61#include <linux/spinlock.h>
88b47679 62#include <linux/module.h>
fdc50a94
YG		 63
64#define DRIVER_NAME "sh_mmcif"
65#define DRIVER_VERSION "2010-04-28"
66
fdc50a94
YG		 67/* CE_CMD_SET */
68#define CMD_MASK 0x3f000000
69#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
70#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
71#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
72#define CMD_SET_RBSY (1 << 21) /* R1b */
73#define CMD_SET_CCSEN (1 << 20)
74#define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
75#define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
76#define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
77#define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
78#define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
79#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
80#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
81#define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
82#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
83#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
84#define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
85#define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
86#define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
87#define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
88#define CMD_SET_CCSH (1 << 5)
89#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
90#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
91#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
92
93/* CE_CMD_CTRL */
94#define CMD_CTRL_BREAK (1 << 0)
95
96/* CE_BLOCK_SET */
97#define BLOCK_SIZE_MASK 0x0000ffff
98
fdc50a94
YG		 99/* CE_INT */
100#define INT_CCSDE (1 << 29)
101#define INT_CMD12DRE (1 << 26)
102#define INT_CMD12RBE (1 << 25)
103#define INT_CMD12CRE (1 << 24)
104#define INT_DTRANE (1 << 23)
105#define INT_BUFRE (1 << 22)
106#define INT_BUFWEN (1 << 21)
107#define INT_BUFREN (1 << 20)
108#define INT_CCSRCV (1 << 19)
109#define INT_RBSYE (1 << 17)
110#define INT_CRSPE (1 << 16)
111#define INT_CMDVIO (1 << 15)
112#define INT_BUFVIO (1 << 14)
113#define INT_WDATERR (1 << 11)
114#define INT_RDATERR (1 << 10)
115#define INT_RIDXERR (1 << 9)
116#define INT_RSPERR (1 << 8)
117#define INT_CCSTO (1 << 5)
118#define INT_CRCSTO (1 << 4)
119#define INT_WDATTO (1 << 3)
120#define INT_RDATTO (1 << 2)
121#define INT_RBSYTO (1 << 1)
122#define INT_RSPTO (1 << 0)
123#define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
124 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
125 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
126 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
127
128/* CE_INT_MASK */
129#define MASK_ALL 0x00000000
130#define MASK_MCCSDE (1 << 29)
131#define MASK_MCMD12DRE (1 << 26)
132#define MASK_MCMD12RBE (1 << 25)
133#define MASK_MCMD12CRE (1 << 24)
134#define MASK_MDTRANE (1 << 23)
135#define MASK_MBUFRE (1 << 22)
136#define MASK_MBUFWEN (1 << 21)
137#define MASK_MBUFREN (1 << 20)
138#define MASK_MCCSRCV (1 << 19)
139#define MASK_MRBSYE (1 << 17)
140#define MASK_MCRSPE (1 << 16)
141#define MASK_MCMDVIO (1 << 15)
142#define MASK_MBUFVIO (1 << 14)
143#define MASK_MWDATERR (1 << 11)
144#define MASK_MRDATERR (1 << 10)
145#define MASK_MRIDXERR (1 << 9)
146#define MASK_MRSPERR (1 << 8)
147#define MASK_MCCSTO (1 << 5)
148#define MASK_MCRCSTO (1 << 4)
149#define MASK_MWDATTO (1 << 3)
150#define MASK_MRDATTO (1 << 2)
151#define MASK_MRBSYTO (1 << 1)
152#define MASK_MRSPTO (1 << 0)
153
ee4b8887
GL		 154#define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
155 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
156 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
157 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
158
fdc50a94
YG		 159/* CE_HOST_STS1 */
160#define STS1_CMDSEQ (1 << 31)
161
162/* CE_HOST_STS2 */
163#define STS2_CRCSTE (1 << 31)
164#define STS2_CRC16E (1 << 30)
165#define STS2_AC12CRCE (1 << 29)
166#define STS2_RSPCRC7E (1 << 28)
167#define STS2_CRCSTEBE (1 << 27)
168#define STS2_RDATEBE (1 << 26)
169#define STS2_AC12REBE (1 << 25)
170#define STS2_RSPEBE (1 << 24)
171#define STS2_AC12IDXE (1 << 23)
172#define STS2_RSPIDXE (1 << 22)
173#define STS2_CCSTO (1 << 15)
174#define STS2_RDATTO (1 << 14)
175#define STS2_DATBSYTO (1 << 13)
176#define STS2_CRCSTTO (1 << 12)
177#define STS2_AC12BSYTO (1 << 11)
178#define STS2_RSPBSYTO (1 << 10)
179#define STS2_AC12RSPTO (1 << 9)
180#define STS2_RSPTO (1 << 8)
181#define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
182 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
183#define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
184 STS2_DATBSYTO | STS2_CRCSTTO | \
185 STS2_AC12BSYTO | STS2_RSPBSYTO | \
186 STS2_AC12RSPTO | STS2_RSPTO)
187
fdc50a94
YG		 188#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
189#define CLKDEV_MMC_DATA 20000000 /* 20MHz */
190#define CLKDEV_INIT 400000 /* 400 KHz */
191
3b0beafc
GL		 192enum mmcif_state {
193 STATE_IDLE,
194 STATE_REQUEST,
195 STATE_IOS,
196};
197
f985da17
GL		 198enum mmcif_wait_for {
199 MMCIF_WAIT_FOR_REQUEST,
200 MMCIF_WAIT_FOR_CMD,
201 MMCIF_WAIT_FOR_MREAD,
202 MMCIF_WAIT_FOR_MWRITE,
203 MMCIF_WAIT_FOR_READ,
204 MMCIF_WAIT_FOR_WRITE,
205 MMCIF_WAIT_FOR_READ_END,
206 MMCIF_WAIT_FOR_WRITE_END,
207 MMCIF_WAIT_FOR_STOP,
208};
209
fdc50a94
YG		 210struct sh_mmcif_host {
211 struct mmc_host *mmc;
f985da17 212 struct mmc_request *mrq;
fdc50a94 213 struct platform_device *pd;
714c4a6e
GL		 214 struct sh_dmae_slave dma_slave_tx;
215 struct sh_dmae_slave dma_slave_rx;
fdc50a94
YG		 216 struct clk *hclk;
217 unsigned int clk;
218 int bus_width;
aa0787a9 219 bool sd_error;
f985da17 220 bool dying;
fdc50a94
YG		 221 long timeout;
222 void __iomem *addr;
f985da17 223 u32 *pio_ptr;
ee4b8887 224 spinlock_t lock; /* protect sh_mmcif_host::state */
3b0beafc 225 enum mmcif_state state;
f985da17
GL		 226 enum mmcif_wait_for wait_for;
227 struct delayed_work timeout_work;
228 size_t blocksize;
229 int sg_idx;
230 int sg_blkidx;
faca6648 231 bool power;
c9b0cef2 232 bool card_present;
fdc50a94 233
a782d688
GL		 234 /* DMA support */
235 struct dma_chan *chan_rx;
236 struct dma_chan *chan_tx;
237 struct completion dma_complete;
f38f94c6 238 bool dma_active;
a782d688 239};
fdc50a94
YG		 240
241static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
242 unsigned int reg, u32 val)
243{
487d9fc5 244 writel(val | readl(host->addr + reg), host->addr + reg);
fdc50a94
YG		 245}
246
247static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
248 unsigned int reg, u32 val)
249{
487d9fc5 250 writel(~val & readl(host->addr + reg), host->addr + reg);
fdc50a94
YG		 251}
252
a782d688
GL		 253static void mmcif_dma_complete(void *arg)
254{
255 struct sh_mmcif_host *host = arg;
69983404
GL		 256 struct mmc_data *data = host->mrq->data;
257
a782d688
GL		 258 dev_dbg(&host->pd->dev, "Command completed\n");
259
69983404 260 if (WARN(!data, "%s: NULL data in DMA completion!\n",
a782d688
GL		 261 dev_name(&host->pd->dev)))
262 return;
263
69983404 264 if (data->flags & MMC_DATA_READ)
1ed828db 265 dma_unmap_sg(host->chan_rx->device->dev,
69983404 266 data->sg, data->sg_len,
a782d688
GL		 267 DMA_FROM_DEVICE);
268 else
1ed828db 269 dma_unmap_sg(host->chan_tx->device->dev,
69983404 270 data->sg, data->sg_len,
a782d688
GL		 271 DMA_TO_DEVICE);
272
273 complete(&host->dma_complete);
274}
275
276static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
277{
69983404
GL		 278 struct mmc_data *data = host->mrq->data;
279 struct scatterlist *sg = data->sg;
a782d688
GL		 280 struct dma_async_tx_descriptor *desc = NULL;
281 struct dma_chan *chan = host->chan_rx;
282 dma_cookie_t cookie = -EINVAL;
283 int ret;
284
69983404 285 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
1ed828db 286 DMA_FROM_DEVICE);
a782d688 287 if (ret > 0) {
f38f94c6 288 host->dma_active = true;
16052827 289 desc = dmaengine_prep_slave_sg(chan, sg, ret,
05f5799c 290 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
a782d688
GL		 291 }
292
293 if (desc) {
294 desc->callback = mmcif_dma_complete;
295 desc->callback_param = host;
a5ece7d2
LW		 296 cookie = dmaengine_submit(desc);
297 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
298 dma_async_issue_pending(chan);
a782d688
GL		 299 }
300 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
69983404 301 __func__, data->sg_len, ret, cookie);
a782d688
GL		 302
303 if (!desc) {
304 /* DMA failed, fall back to PIO */
305 if (ret >= 0)
306 ret = -EIO;
307 host->chan_rx = NULL;
f38f94c6 308 host->dma_active = false;
a782d688
GL		 309 dma_release_channel(chan);
310 /* Free the Tx channel too */
311 chan = host->chan_tx;
312 if (chan) {
313 host->chan_tx = NULL;
314 dma_release_channel(chan);
315 }
316 dev_warn(&host->pd->dev,
317 "DMA failed: %d, falling back to PIO\n", ret);
318 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
319 }
320
321 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
69983404 322 desc, cookie, data->sg_len);
a782d688
GL		 323}
324
325static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
326{
69983404
GL		 327 struct mmc_data *data = host->mrq->data;
328 struct scatterlist *sg = data->sg;
a782d688
GL		 329 struct dma_async_tx_descriptor *desc = NULL;
330 struct dma_chan *chan = host->chan_tx;
331 dma_cookie_t cookie = -EINVAL;
332 int ret;
333
69983404 334 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
1ed828db 335 DMA_TO_DEVICE);
a782d688 336 if (ret > 0) {
f38f94c6 337 host->dma_active = true;
16052827 338 desc = dmaengine_prep_slave_sg(chan, sg, ret,
05f5799c 339 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
a782d688
GL		 340 }
341
342 if (desc) {
343 desc->callback = mmcif_dma_complete;
344 desc->callback_param = host;
a5ece7d2
LW		 345 cookie = dmaengine_submit(desc);
346 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
347 dma_async_issue_pending(chan);
a782d688
GL		 348 }
349 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
69983404 350 __func__, data->sg_len, ret, cookie);
a782d688
GL		 351
352 if (!desc) {
353 /* DMA failed, fall back to PIO */
354 if (ret >= 0)
355 ret = -EIO;
356 host->chan_tx = NULL;
f38f94c6 357 host->dma_active = false;
a782d688
GL		 358 dma_release_channel(chan);
359 /* Free the Rx channel too */
360 chan = host->chan_rx;
361 if (chan) {
362 host->chan_rx = NULL;
363 dma_release_channel(chan);
364 }
365 dev_warn(&host->pd->dev,
366 "DMA failed: %d, falling back to PIO\n", ret);
367 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
368 }
369
370 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
371 desc, cookie);
372}
373
374static bool sh_mmcif_filter(struct dma_chan *chan, void *arg)
375{
376 dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
377 chan->private = arg;
378 return true;
379}
380
381static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
382 struct sh_mmcif_plat_data *pdata)
383{
714c4a6e 384 struct sh_dmae_slave *tx, *rx;
f38f94c6 385 host->dma_active = false;
a782d688
GL		 386
387 /* We can only either use DMA for both Tx and Rx or not use it at all */
388 if (pdata->dma) {
714c4a6e
GL		 389 dev_warn(&host->pd->dev,
390 "Update your platform to use embedded DMA slave IDs\n");
391 tx = &pdata->dma->chan_priv_tx;
392 rx = &pdata->dma->chan_priv_rx;
393 } else {
394 tx = &host->dma_slave_tx;
395 tx->slave_id = pdata->slave_id_tx;
396 rx = &host->dma_slave_rx;
397 rx->slave_id = pdata->slave_id_rx;
398 }
399 if (tx->slave_id > 0 && rx->slave_id > 0) {
a782d688
GL		 400 dma_cap_mask_t mask;
401
402 dma_cap_zero(mask);
403 dma_cap_set(DMA_SLAVE, mask);
404
714c4a6e 405 host->chan_tx = dma_request_channel(mask, sh_mmcif_filter, tx);
a782d688
GL		 406 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
407 host->chan_tx);
408
409 if (!host->chan_tx)
410 return;
411
714c4a6e 412 host->chan_rx = dma_request_channel(mask, sh_mmcif_filter, rx);
a782d688
GL		 413 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
414 host->chan_rx);
415
416 if (!host->chan_rx) {
417 dma_release_channel(host->chan_tx);
418 host->chan_tx = NULL;
419 return;
420 }
421
422 init_completion(&host->dma_complete);
423 }
424}
425
426static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
427{
428 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
429 /* Descriptors are freed automatically */
430 if (host->chan_tx) {
431 struct dma_chan *chan = host->chan_tx;
432 host->chan_tx = NULL;
433 dma_release_channel(chan);
434 }
435 if (host->chan_rx) {
436 struct dma_chan *chan = host->chan_rx;
437 host->chan_rx = NULL;
438 dma_release_channel(chan);
439 }
440
f38f94c6 441 host->dma_active = false;
a782d688 442}
fdc50a94
YG		 443
444static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
445{
446 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
447
448 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
449 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
450
451 if (!clk)
452 return;
453 if (p->sup_pclk && clk == host->clk)
454 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
455 else
456 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
f9388257
SH		 457 ((fls(DIV_ROUND_UP(host->clk,
458 clk) - 1) - 1) << 16));
fdc50a94
YG		 459
460 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
461}
462
463static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
464{
465 u32 tmp;
466
487d9fc5 467 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
fdc50a94 468
487d9fc5
MD		 469 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
470 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
fdc50a94
YG		 471 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
472 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
473 /* byte swap on */
474 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
475}
476
477static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
478{
479 u32 state1, state2;
ee4b8887 480 int ret, timeout;
fdc50a94 481
aa0787a9 482 host->sd_error = false;
fdc50a94 483
487d9fc5
MD		 484 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
485 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
e47bf32a
GL		 486 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
487 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
fdc50a94
YG		 488
489 if (state1 & STS1_CMDSEQ) {
490 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
491 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
ee4b8887 492 for (timeout = 10000000; timeout; timeout--) {
487d9fc5 493 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
ee4b8887 494 & STS1_CMDSEQ))
fdc50a94
YG		 495 break;
496 mdelay(1);
497 }
ee4b8887
GL		 498 if (!timeout) {
499 dev_err(&host->pd->dev,
500 "Forced end of command sequence timeout err\n");
501 return -EIO;
502 }
fdc50a94 503 sh_mmcif_sync_reset(host);
e47bf32a 504 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
fdc50a94
YG		 505 return -EIO;
506 }
507
508 if (state2 & STS2_CRC_ERR) {
ee4b8887 509 dev_dbg(&host->pd->dev, ": CRC error\n");
fdc50a94
YG		 510 ret = -EIO;
511 } else if (state2 & STS2_TIMEOUT_ERR) {
ee4b8887 512 dev_dbg(&host->pd->dev, ": Timeout\n");
fdc50a94
YG		 513 ret = -ETIMEDOUT;
514 } else {
ee4b8887 515 dev_dbg(&host->pd->dev, ": End/Index error\n");
fdc50a94
YG		 516 ret = -EIO;
517 }
518 return ret;
519}
520
f985da17 521static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
fdc50a94 522{
f985da17
GL		 523 struct mmc_data *data = host->mrq->data;
524
525 host->sg_blkidx += host->blocksize;
526
527 /* data->sg->length must be a multiple of host->blocksize? */
528 BUG_ON(host->sg_blkidx > data->sg->length);
529
530 if (host->sg_blkidx == data->sg->length) {
531 host->sg_blkidx = 0;
532 if (++host->sg_idx < data->sg_len)
533 host->pio_ptr = sg_virt(++data->sg);
534 } else {
535 host->pio_ptr = p;
536 }
537
538 if (host->sg_idx == data->sg_len)
539 return false;
540
541 return true;
542}
543
544static void sh_mmcif_single_read(struct sh_mmcif_host *host,
545 struct mmc_request *mrq)
546{
547 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
548 BLOCK_SIZE_MASK) + 3;
549
550 host->wait_for = MMCIF_WAIT_FOR_READ;
551 schedule_delayed_work(&host->timeout_work, host->timeout);
fdc50a94 552
fdc50a94
YG		 553 /* buf read enable */
554 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
f985da17
GL		 555}
556
557static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
558{
559 struct mmc_data *data = host->mrq->data;
560 u32 *p = sg_virt(data->sg);
561 int i;
562
563 if (host->sd_error) {
564 data->error = sh_mmcif_error_manage(host);
565 return false;
566 }
567
568 for (i = 0; i < host->blocksize / 4; i++)
487d9fc5 569 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
fdc50a94
YG		 570
571 /* buffer read end */
572 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
f985da17 573 host->wait_for = MMCIF_WAIT_FOR_READ_END;
fdc50a94 574
f985da17 575 return true;
fdc50a94
YG		 576}
577
f985da17
GL		 578static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
579 struct mmc_request *mrq)
fdc50a94
YG		 580{
581 struct mmc_data *data = mrq->data;
f985da17
GL		 582
583 if (!data->sg_len || !data->sg->length)
584 return;
585
586 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
587 BLOCK_SIZE_MASK;
588
589 host->wait_for = MMCIF_WAIT_FOR_MREAD;
590 host->sg_idx = 0;
591 host->sg_blkidx = 0;
592 host->pio_ptr = sg_virt(data->sg);
593 schedule_delayed_work(&host->timeout_work, host->timeout);
594 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
595}
596
597static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
598{
599 struct mmc_data *data = host->mrq->data;
600 u32 *p = host->pio_ptr;
601 int i;
602
603 if (host->sd_error) {
604 data->error = sh_mmcif_error_manage(host);
605 return false;
fdc50a94 606 }
f985da17
GL		 607
608 BUG_ON(!data->sg->length);
609
610 for (i = 0; i < host->blocksize / 4; i++)
611 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
612
613 if (!sh_mmcif_next_block(host, p))
614 return false;
615
616 schedule_delayed_work(&host->timeout_work, host->timeout);
617 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
618
619 return true;
fdc50a94
YG		 620}
621
f985da17 622static void sh_mmcif_single_write(struct sh_mmcif_host *host,
fdc50a94
YG		 623 struct mmc_request *mrq)
624{
f985da17
GL		 625 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
626 BLOCK_SIZE_MASK) + 3;
fdc50a94 627
f985da17
GL		 628 host->wait_for = MMCIF_WAIT_FOR_WRITE;
629 schedule_delayed_work(&host->timeout_work, host->timeout);
fdc50a94
YG		 630
631 /* buf write enable */
f985da17
GL		 632 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
633}
634
635static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
636{
637 struct mmc_data *data = host->mrq->data;
638 u32 *p = sg_virt(data->sg);
639 int i;
640
641 if (host->sd_error) {
642 data->error = sh_mmcif_error_manage(host);
643 return false;
644 }
645
646 for (i = 0; i < host->blocksize / 4; i++)
487d9fc5 647 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
fdc50a94
YG		 648
649 /* buffer write end */
650 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
f985da17 651 host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
fdc50a94 652
f985da17 653 return true;
fdc50a94
YG		 654}
655
f985da17
GL		 656static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
657 struct mmc_request *mrq)
fdc50a94
YG		 658{
659 struct mmc_data *data = mrq->data;
fdc50a94 660
f985da17
GL		 661 if (!data->sg_len || !data->sg->length)
662 return;
fdc50a94 663
f985da17
GL		 664 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
665 BLOCK_SIZE_MASK;
fdc50a94 666
f985da17
GL		 667 host->wait_for = MMCIF_WAIT_FOR_MWRITE;
668 host->sg_idx = 0;
669 host->sg_blkidx = 0;
670 host->pio_ptr = sg_virt(data->sg);
671 schedule_delayed_work(&host->timeout_work, host->timeout);
672 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
673}
fdc50a94 674
f985da17
GL		 675static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
676{
677 struct mmc_data *data = host->mrq->data;
678 u32 *p = host->pio_ptr;
679 int i;
680
681 if (host->sd_error) {
682 data->error = sh_mmcif_error_manage(host);
683 return false;
fdc50a94 684 }
f985da17
GL		 685
686 BUG_ON(!data->sg->length);
687
688 for (i = 0; i < host->blocksize / 4; i++)
689 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
690
691 if (!sh_mmcif_next_block(host, p))
692 return false;
693
694 schedule_delayed_work(&host->timeout_work, host->timeout);
695 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
696
697 return true;
fdc50a94
YG		 698}
699
700static void sh_mmcif_get_response(struct sh_mmcif_host *host,
701 struct mmc_command *cmd)
702{
703 if (cmd->flags & MMC_RSP_136) {
487d9fc5
MD		 704 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
705 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
706 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
707 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
fdc50a94 708 } else
487d9fc5 709 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
fdc50a94
YG		 710}
711
712static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
713 struct mmc_command *cmd)
714{
487d9fc5 715 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
fdc50a94
YG		 716}
717
718static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
69983404 719 struct mmc_request *mrq)
fdc50a94 720{
69983404
GL		 721 struct mmc_data *data = mrq->data;
722 struct mmc_command *cmd = mrq->cmd;
723 u32 opc = cmd->opcode;
fdc50a94
YG		 724 u32 tmp = 0;
725
726 /* Response Type check */
727 switch (mmc_resp_type(cmd)) {
728 case MMC_RSP_NONE:
729 tmp |= CMD_SET_RTYP_NO;
730 break;
731 case MMC_RSP_R1:
732 case MMC_RSP_R1B:
733 case MMC_RSP_R3:
734 tmp |= CMD_SET_RTYP_6B;
735 break;
736 case MMC_RSP_R2:
737 tmp |= CMD_SET_RTYP_17B;
738 break;
739 default:
e47bf32a 740 dev_err(&host->pd->dev, "Unsupported response type.\n");
fdc50a94
YG		 741 break;
742 }
743 switch (opc) {
744 /* RBSY */
745 case MMC_SWITCH:
746 case MMC_STOP_TRANSMISSION:
747 case MMC_SET_WRITE_PROT:
748 case MMC_CLR_WRITE_PROT:
749 case MMC_ERASE:
fdc50a94
YG		 750 tmp |= CMD_SET_RBSY;
751 break;
752 }
753 /* WDAT / DATW */
69983404 754 if (data) {
fdc50a94
YG		 755 tmp |= CMD_SET_WDAT;
756 switch (host->bus_width) {
757 case MMC_BUS_WIDTH_1:
758 tmp |= CMD_SET_DATW_1;
759 break;
760 case MMC_BUS_WIDTH_4:
761 tmp |= CMD_SET_DATW_4;
762 break;
763 case MMC_BUS_WIDTH_8:
764 tmp |= CMD_SET_DATW_8;
765 break;
766 default:
e47bf32a 767 dev_err(&host->pd->dev, "Unsupported bus width.\n");
fdc50a94
YG		 768 break;
769 }
770 }
771 /* DWEN */
772 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
773 tmp |= CMD_SET_DWEN;
774 /* CMLTE/CMD12EN */
775 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
776 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
777 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
69983404 778 data->blocks << 16);
fdc50a94
YG		 779 }
780 /* RIDXC[1:0] check bits */
781 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
782 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
783 tmp |= CMD_SET_RIDXC_BITS;
784 /* RCRC7C[1:0] check bits */
785 if (opc == MMC_SEND_OP_COND)
786 tmp |= CMD_SET_CRC7C_BITS;
787 /* RCRC7C[1:0] internal CRC7 */
788 if (opc == MMC_ALL_SEND_CID ||
789 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
790 tmp |= CMD_SET_CRC7C_INTERNAL;
791
69983404 792 return (opc << 24) | tmp;
fdc50a94
YG		 793}
794
e47bf32a 795static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
f985da17 796 struct mmc_request *mrq, u32 opc)
fdc50a94 797{
fdc50a94
YG		 798 switch (opc) {
799 case MMC_READ_MULTIPLE_BLOCK:
f985da17
GL		 800 sh_mmcif_multi_read(host, mrq);
801 return 0;
fdc50a94 802 case MMC_WRITE_MULTIPLE_BLOCK:
f985da17
GL		 803 sh_mmcif_multi_write(host, mrq);
804 return 0;
fdc50a94 805 case MMC_WRITE_BLOCK:
f985da17
GL		 806 sh_mmcif_single_write(host, mrq);
807 return 0;
fdc50a94
YG		 808 case MMC_READ_SINGLE_BLOCK:
809 case MMC_SEND_EXT_CSD:
f985da17
GL		 810 sh_mmcif_single_read(host, mrq);
811 return 0;
fdc50a94 812 default:
e47bf32a 813 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
ee4b8887 814 return -EINVAL;
fdc50a94 815 }
fdc50a94
YG		 816}
817
818static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
ee4b8887 819 struct mmc_request *mrq)
fdc50a94 820{
ee4b8887 821 struct mmc_command *cmd = mrq->cmd;
f985da17
GL		 822 u32 opc = cmd->opcode;
823 u32 mask;
fdc50a94 824
fdc50a94 825 switch (opc) {
ee4b8887 826 /* response busy check */
fdc50a94
YG		 827 case MMC_SWITCH:
828 case MMC_STOP_TRANSMISSION:
829 case MMC_SET_WRITE_PROT:
830 case MMC_CLR_WRITE_PROT:
831 case MMC_ERASE:
ee4b8887 832 mask = MASK_START_CMD | MASK_MRBSYE;
fdc50a94
YG		 833 break;
834 default:
ee4b8887 835 mask = MASK_START_CMD | MASK_MCRSPE;
fdc50a94
YG		 836 break;
837 }
fdc50a94 838
69983404 839 if (mrq->data) {
487d9fc5
MD		 840 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
841 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
842 mrq->data->blksz);
fdc50a94 843 }
69983404 844 opc = sh_mmcif_set_cmd(host, mrq);
fdc50a94 845
487d9fc5
MD		 846 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
847 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
fdc50a94 848 /* set arg */
487d9fc5 849 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
fdc50a94 850 /* set cmd */
487d9fc5 851 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
fdc50a94 852
f985da17
GL		 853 host->wait_for = MMCIF_WAIT_FOR_CMD;
854 schedule_delayed_work(&host->timeout_work, host->timeout);
fdc50a94
YG		 855}
856
857static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
ee4b8887 858 struct mmc_request *mrq)
fdc50a94 859{
69983404
GL		 860 switch (mrq->cmd->opcode) {
861 case MMC_READ_MULTIPLE_BLOCK:
fdc50a94 862 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
69983404
GL		 863 break;
864 case MMC_WRITE_MULTIPLE_BLOCK:
fdc50a94 865 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
69983404
GL		 866 break;
867 default:
e47bf32a 868 dev_err(&host->pd->dev, "unsupported stop cmd\n");
69983404 869 mrq->stop->error = sh_mmcif_error_manage(host);
fdc50a94
YG		 870 return;
871 }
872
f985da17
GL		 873 host->wait_for = MMCIF_WAIT_FOR_STOP;
874 schedule_delayed_work(&host->timeout_work, host->timeout);
fdc50a94
YG		 875}
876
877static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
878{
879 struct sh_mmcif_host *host = mmc_priv(mmc);
3b0beafc
GL		 880 unsigned long flags;
881
882 spin_lock_irqsave(&host->lock, flags);
883 if (host->state != STATE_IDLE) {
884 spin_unlock_irqrestore(&host->lock, flags);
885 mrq->cmd->error = -EAGAIN;
886 mmc_request_done(mmc, mrq);
887 return;
888 }
889
890 host->state = STATE_REQUEST;
891 spin_unlock_irqrestore(&host->lock, flags);
fdc50a94
YG		 892
893 switch (mrq->cmd->opcode) {
894 /* MMCIF does not support SD/SDIO command */
7541ca98
LP		 895 case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */
896 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
897 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)
898 break;
fdc50a94 899 case MMC_APP_CMD:
3b0beafc 900 host->state = STATE_IDLE;
fdc50a94
YG		 901 mrq->cmd->error = -ETIMEDOUT;
902 mmc_request_done(mmc, mrq);
903 return;
fdc50a94
YG		 904 default:
905 break;
906 }
f985da17
GL		 907
908 host->mrq = mrq;
fdc50a94 909
f985da17 910 sh_mmcif_start_cmd(host, mrq);
fdc50a94
YG		 911}
912
a6609267
GL		 913static int sh_mmcif_clk_update(struct sh_mmcif_host *host)
914{
915 int ret = clk_enable(host->hclk);
916
917 if (!ret) {
918 host->clk = clk_get_rate(host->hclk);
919 host->mmc->f_max = host->clk / 2;
920 host->mmc->f_min = host->clk / 512;
921 }
922
923 return ret;
924}
925
7d17baa0
GL		 926static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)
927{
928 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
929 struct mmc_host *mmc = host->mmc;
930
931 if (pd->set_pwr)
932 pd->set_pwr(host->pd, ios->power_mode != MMC_POWER_OFF);
933 if (!IS_ERR(mmc->supply.vmmc))
934 /* Errors ignored... */
935 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
936 ios->power_mode ? ios->vdd : 0);
937}
938
fdc50a94
YG		 939static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
940{
941 struct sh_mmcif_host *host = mmc_priv(mmc);
3b0beafc
GL		 942 unsigned long flags;
943
944 spin_lock_irqsave(&host->lock, flags);
945 if (host->state != STATE_IDLE) {
946 spin_unlock_irqrestore(&host->lock, flags);
947 return;
948 }
949
950 host->state = STATE_IOS;
951 spin_unlock_irqrestore(&host->lock, flags);
fdc50a94 952
f5e0cec4 953 if (ios->power_mode == MMC_POWER_UP) {
c9b0cef2 954 if (!host->card_present) {
faca6648
GL		 955 /* See if we also get DMA */
956 sh_mmcif_request_dma(host, host->pd->dev.platform_data);
c9b0cef2 957 host->card_present = true;
faca6648 958 }
7d17baa0 959 sh_mmcif_set_power(host, ios);
f5e0cec4 960 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
fdc50a94
YG		 961 /* clock stop */
962 sh_mmcif_clock_control(host, 0);
faca6648 963 if (ios->power_mode == MMC_POWER_OFF) {
c9b0cef2 964 if (host->card_present) {
faca6648 965 sh_mmcif_release_dma(host);
c9b0cef2 966 host->card_present = false;
faca6648 967 }
c9b0cef2
GL		 968 }
969 if (host->power) {
970 pm_runtime_put(&host->pd->dev);
b289174f 971 clk_disable(host->hclk);
c9b0cef2 972 host->power = false;
7d17baa0
GL		 973 if (ios->power_mode == MMC_POWER_OFF)
974 sh_mmcif_set_power(host, ios);
faca6648 975 }
3b0beafc 976 host->state = STATE_IDLE;
fdc50a94 977 return;
fdc50a94
YG		 978 }
979
c9b0cef2
GL		 980 if (ios->clock) {
981 if (!host->power) {
a6609267 982 sh_mmcif_clk_update(host);
c9b0cef2
GL		 983 pm_runtime_get_sync(&host->pd->dev);
984 host->power = true;
985 sh_mmcif_sync_reset(host);
986 }
fdc50a94 987 sh_mmcif_clock_control(host, ios->clock);
c9b0cef2 988 }
fdc50a94
YG		 989
990 host->bus_width = ios->bus_width;
3b0beafc 991 host->state = STATE_IDLE;
fdc50a94
YG		 992}
993
777271d0
AH		 994static int sh_mmcif_get_cd(struct mmc_host *mmc)
995{
996 struct sh_mmcif_host *host = mmc_priv(mmc);
997 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
998
999 if (!p->get_cd)
1000 return -ENOSYS;
1001 else
1002 return p->get_cd(host->pd);
1003}
1004
fdc50a94
YG		 1005static struct mmc_host_ops sh_mmcif_ops = {
1006 .request = sh_mmcif_request,
1007 .set_ios = sh_mmcif_set_ios,
777271d0 1008 .get_cd = sh_mmcif_get_cd,
fdc50a94
YG		 1009};
1010
f985da17
GL		 1011static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1012{
1013 struct mmc_command *cmd = host->mrq->cmd;
69983404 1014 struct mmc_data *data = host->mrq->data;
f985da17
GL		 1015 long time;
1016
1017 if (host->sd_error) {
1018 switch (cmd->opcode) {
1019 case MMC_ALL_SEND_CID:
1020 case MMC_SELECT_CARD:
1021 case MMC_APP_CMD:
1022 cmd->error = -ETIMEDOUT;
1023 host->sd_error = false;
1024 break;
1025 default:
1026 cmd->error = sh_mmcif_error_manage(host);
1027 dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n",
1028 cmd->opcode, cmd->error);
1029 break;
1030 }
1031 return false;
1032 }
1033 if (!(cmd->flags & MMC_RSP_PRESENT)) {
1034 cmd->error = 0;
1035 return false;
1036 }
1037
1038 sh_mmcif_get_response(host, cmd);
1039
69983404 1040 if (!data)
f985da17
GL		 1041 return false;
1042
69983404 1043 if (data->flags & MMC_DATA_READ) {
f985da17
GL		 1044 if (host->chan_rx)
1045 sh_mmcif_start_dma_rx(host);
1046 } else {
1047 if (host->chan_tx)
1048 sh_mmcif_start_dma_tx(host);
1049 }
1050
1051 if (!host->dma_active) {
69983404
GL		 1052 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1053 if (!data->error)
f985da17
GL		 1054 return true;
1055 return false;
1056 }
1057
1058 /* Running in the IRQ thread, can sleep */
1059 time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1060 host->timeout);
1061 if (host->sd_error) {
1062 dev_err(host->mmc->parent,
1063 "Error IRQ while waiting for DMA completion!\n");
1064 /* Woken up by an error IRQ: abort DMA */
69983404 1065 if (data->flags & MMC_DATA_READ)
f985da17
GL		 1066 dmaengine_terminate_all(host->chan_rx);
1067 else
1068 dmaengine_terminate_all(host->chan_tx);
69983404 1069 data->error = sh_mmcif_error_manage(host);
f985da17 1070 } else if (!time) {
69983404 1071 data->error = -ETIMEDOUT;
f985da17 1072 } else if (time < 0) {
69983404 1073 data->error = time;
f985da17
GL		 1074 }
1075 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1076 BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1077 host->dma_active = false;
1078
69983404
GL		 1079 if (data->error)
1080 data->bytes_xfered = 0;
f985da17
GL		 1081
1082 return false;
1083}
1084
1085static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1086{
1087 struct sh_mmcif_host *host = dev_id;
1088 struct mmc_request *mrq = host->mrq;
69983404 1089 struct mmc_data *data = mrq->data;
f985da17
GL		 1090
1091 cancel_delayed_work_sync(&host->timeout_work);
1092
1093 /*
1094 * All handlers return true, if processing continues, and false, if the
1095 * request has to be completed - successfully or not
1096 */
1097 switch (host->wait_for) {
1098 case MMCIF_WAIT_FOR_REQUEST:
1099 /* We're too late, the timeout has already kicked in */
1100 return IRQ_HANDLED;
1101 case MMCIF_WAIT_FOR_CMD:
1102 if (sh_mmcif_end_cmd(host))
1103 /* Wait for data */
1104 return IRQ_HANDLED;
1105 break;
1106 case MMCIF_WAIT_FOR_MREAD:
1107 if (sh_mmcif_mread_block(host))
1108 /* Wait for more data */
1109 return IRQ_HANDLED;
1110 break;
1111 case MMCIF_WAIT_FOR_READ:
1112 if (sh_mmcif_read_block(host))
1113 /* Wait for data end */
1114 return IRQ_HANDLED;
1115 break;
1116 case MMCIF_WAIT_FOR_MWRITE:
1117 if (sh_mmcif_mwrite_block(host))
1118 /* Wait data to write */
1119 return IRQ_HANDLED;
1120 break;
1121 case MMCIF_WAIT_FOR_WRITE:
1122 if (sh_mmcif_write_block(host))
1123 /* Wait for data end */
1124 return IRQ_HANDLED;
1125 break;
1126 case MMCIF_WAIT_FOR_STOP:
1127 if (host->sd_error) {
1128 mrq->stop->error = sh_mmcif_error_manage(host);
1129 break;
1130 }
1131 sh_mmcif_get_cmd12response(host, mrq->stop);
1132 mrq->stop->error = 0;
1133 break;
1134 case MMCIF_WAIT_FOR_READ_END:
1135 case MMCIF_WAIT_FOR_WRITE_END:
1136 if (host->sd_error)
69983404 1137 data->error = sh_mmcif_error_manage(host);
f985da17
GL		 1138 break;
1139 default:
1140 BUG();
1141 }
1142
1143 if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
69983404
GL		 1144 if (!mrq->cmd->error && data && !data->error)
1145 data->bytes_xfered =
1146 data->blocks * data->blksz;
f985da17 1147
69983404 1148 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
f985da17
GL		 1149 sh_mmcif_stop_cmd(host, mrq);
1150 if (!mrq->stop->error)
1151 return IRQ_HANDLED;
1152 }
1153 }
1154
1155 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1156 host->state = STATE_IDLE;
69983404 1157 host->mrq = NULL;
f985da17
GL		 1158 mmc_request_done(host->mmc, mrq);
1159
1160 return IRQ_HANDLED;
1161}
1162
fdc50a94
YG		 1163static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1164{
1165 struct sh_mmcif_host *host = dev_id;
aa0787a9 1166 u32 state;
fdc50a94
YG		 1167 int err = 0;
1168
487d9fc5 1169 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
fdc50a94 1170
8a8284a9
GL		 1171 if (state & INT_ERR_STS) {
1172 /* error interrupts - process first */
1173 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1174 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1175 err = 1;
1176 } else if (state & INT_RBSYE) {
487d9fc5
MD		 1177 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1178 ~(INT_RBSYE | INT_CRSPE));
fdc50a94
YG		 1179 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
1180 } else if (state & INT_CRSPE) {
487d9fc5 1181 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
fdc50a94
YG		 1182 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
1183 } else if (state & INT_BUFREN) {
487d9fc5 1184 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
fdc50a94
YG		 1185 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
1186 } else if (state & INT_BUFWEN) {
487d9fc5 1187 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
fdc50a94
YG		 1188 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
1189 } else if (state & INT_CMD12DRE) {
487d9fc5 1190 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
fdc50a94
YG		 1191 ~(INT_CMD12DRE | INT_CMD12RBE |
1192 INT_CMD12CRE | INT_BUFRE));
1193 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
1194 } else if (state & INT_BUFRE) {
487d9fc5 1195 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
fdc50a94
YG		 1196 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
1197 } else if (state & INT_DTRANE) {
487d9fc5 1198 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
fdc50a94
YG		 1199 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
1200 } else if (state & INT_CMD12RBE) {
487d9fc5 1201 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
fdc50a94
YG		 1202 ~(INT_CMD12RBE | INT_CMD12CRE));
1203 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
fdc50a94 1204 } else {
faca6648 1205 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
487d9fc5 1206 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
fdc50a94
YG		 1207 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1208 err = 1;
1209 }
1210 if (err) {
aa0787a9 1211 host->sd_error = true;
e47bf32a 1212 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
fdc50a94 1213 }
f985da17
GL		 1214 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1215 if (!host->dma_active)
1216 return IRQ_WAKE_THREAD;
1217 else if (host->sd_error)
1218 mmcif_dma_complete(host);
1219 } else {
aa0787a9 1220 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
f985da17 1221 }
fdc50a94
YG		 1222
1223 return IRQ_HANDLED;
1224}
1225
f985da17
GL		 1226static void mmcif_timeout_work(struct work_struct *work)
1227{
1228 struct delayed_work *d = container_of(work, struct delayed_work, work);
1229 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1230 struct mmc_request *mrq = host->mrq;
1231
1232 if (host->dying)
1233 /* Don't run after mmc_remove_host() */
1234 return;
1235
1236 /*
1237 * Handle races with cancel_delayed_work(), unless
1238 * cancel_delayed_work_sync() is used
1239 */
1240 switch (host->wait_for) {
1241 case MMCIF_WAIT_FOR_CMD:
1242 mrq->cmd->error = sh_mmcif_error_manage(host);
1243 break;
1244 case MMCIF_WAIT_FOR_STOP:
1245 mrq->stop->error = sh_mmcif_error_manage(host);
1246 break;
1247 case MMCIF_WAIT_FOR_MREAD:
1248 case MMCIF_WAIT_FOR_MWRITE:
1249 case MMCIF_WAIT_FOR_READ:
1250 case MMCIF_WAIT_FOR_WRITE:
1251 case MMCIF_WAIT_FOR_READ_END:
1252 case MMCIF_WAIT_FOR_WRITE_END:
69983404 1253 mrq->data->error = sh_mmcif_error_manage(host);
f985da17
GL		 1254 break;
1255 default:
1256 BUG();
1257 }
1258
1259 host->state = STATE_IDLE;
1260 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
f985da17
GL		 1261 host->mrq = NULL;
1262 mmc_request_done(host->mmc, mrq);
1263}
1264
7d17baa0
GL		 1265static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1266{
1267 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
1268 struct mmc_host *mmc = host->mmc;
1269
1270 mmc_regulator_get_supply(mmc);
1271
1272 if (!mmc->ocr_avail)
1273 mmc->ocr_avail = pd->ocr;
1274 else if (pd->ocr)
1275 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1276}
1277
fdc50a94
YG		 1278static int __devinit sh_mmcif_probe(struct platform_device *pdev)
1279{
1280 int ret = 0, irq[2];
1281 struct mmc_host *mmc;
e47bf32a 1282 struct sh_mmcif_host *host;
e1aae2eb 1283 struct sh_mmcif_plat_data *pd = pdev->dev.platform_data;
fdc50a94
YG		 1284 struct resource *res;
1285 void __iomem *reg;
1286 char clk_name[8];
1287
e1aae2eb
GL		 1288 if (!pd) {
1289 dev_err(&pdev->dev, "sh_mmcif plat data error.\n");
1290 return -ENXIO;
1291 }
1292
fdc50a94
YG		 1293 irq[0] = platform_get_irq(pdev, 0);
1294 irq[1] = platform_get_irq(pdev, 1);
1295 if (irq[0] < 0 || irq[1] < 0) {
e47bf32a 1296 dev_err(&pdev->dev, "Get irq error\n");
fdc50a94
YG		 1297 return -ENXIO;
1298 }
1299 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1300 if (!res) {
1301 dev_err(&pdev->dev, "platform_get_resource error.\n");
1302 return -ENXIO;
1303 }
1304 reg = ioremap(res->start, resource_size(res));
1305 if (!reg) {
1306 dev_err(&pdev->dev, "ioremap error.\n");
1307 return -ENOMEM;
1308 }
e1aae2eb 1309
fdc50a94
YG		 1310 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1311 if (!mmc) {
1312 ret = -ENOMEM;
e1aae2eb 1313 goto ealloch;
fdc50a94
YG		 1314 }
1315 host = mmc_priv(mmc);
1316 host->mmc = mmc;
1317 host->addr = reg;
1318 host->timeout = 1000;
1319
fdc50a94
YG		 1320 host->pd = pdev;
1321
3b0beafc 1322 spin_lock_init(&host->lock);
fdc50a94
YG		 1323
1324 mmc->ops = &sh_mmcif_ops;
7d17baa0
GL		 1325 sh_mmcif_init_ocr(host);
1326
fdc50a94
YG		 1327 mmc->caps = MMC_CAP_MMC_HIGHSPEED;
1328 if (pd->caps)
1329 mmc->caps |= pd->caps;
a782d688 1330 mmc->max_segs = 32;
fdc50a94 1331 mmc->max_blk_size = 512;
a782d688
GL		 1332 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1333 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
fdc50a94
YG		 1334 mmc->max_seg_size = mmc->max_req_size;
1335
fdc50a94 1336 platform_set_drvdata(pdev, host);
a782d688 1337
faca6648
GL		 1338 pm_runtime_enable(&pdev->dev);
1339 host->power = false;
1340
b289174f
GL		 1341 snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
1342 host->hclk = clk_get(&pdev->dev, clk_name);
1343 if (IS_ERR(host->hclk)) {
1344 ret = PTR_ERR(host->hclk);
1345 dev_err(&pdev->dev, "cannot get clock \"%s\": %d\n", clk_name, ret);
1346 goto eclkget;
1347 }
a6609267
GL		 1348 ret = sh_mmcif_clk_update(host);
1349 if (ret < 0)
1350 goto eclkupdate;
b289174f 1351
faca6648
GL		 1352 ret = pm_runtime_resume(&pdev->dev);
1353 if (ret < 0)
e1aae2eb 1354 goto eresume;
a782d688 1355
5ba85d95 1356 INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
fdc50a94 1357
b289174f 1358 sh_mmcif_sync_reset(host);
3b0beafc
GL		 1359 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1360
f985da17 1361 ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:error", host);
fdc50a94 1362 if (ret) {
e47bf32a 1363 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
e1aae2eb 1364 goto ereqirq0;
fdc50a94 1365 }
f985da17 1366 ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:int", host);
fdc50a94 1367 if (ret) {
e47bf32a 1368 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
e1aae2eb 1369 goto ereqirq1;
fdc50a94
YG		 1370 }
1371
b289174f 1372 clk_disable(host->hclk);
5ba85d95
GL		 1373 ret = mmc_add_host(mmc);
1374 if (ret < 0)
e1aae2eb 1375 goto emmcaddh;
fdc50a94 1376
efe6a8ad
RW		 1377 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1378
e47bf32a
GL		 1379 dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1380 dev_dbg(&pdev->dev, "chip ver H'%04x\n",
487d9fc5 1381 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
fdc50a94
YG		 1382 return ret;
1383
e1aae2eb 1384emmcaddh:
5ba85d95 1385 free_irq(irq[1], host);
e1aae2eb 1386ereqirq1:
5ba85d95 1387 free_irq(irq[0], host);
e1aae2eb 1388ereqirq0:
faca6648 1389 pm_runtime_suspend(&pdev->dev);
e1aae2eb 1390eresume:
fdc50a94 1391 clk_disable(host->hclk);
a6609267 1392eclkupdate:
b289174f 1393 clk_put(host->hclk);
e1aae2eb 1394eclkget:
b289174f 1395 pm_runtime_disable(&pdev->dev);
fdc50a94 1396 mmc_free_host(mmc);
e1aae2eb
GL		 1397ealloch:
1398 iounmap(reg);
fdc50a94
YG		 1399 return ret;
1400}
1401
1402static int __devexit sh_mmcif_remove(struct platform_device *pdev)
1403{
1404 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1405 int irq[2];
1406
f985da17 1407 host->dying = true;
b289174f 1408 clk_enable(host->hclk);
faca6648 1409 pm_runtime_get_sync(&pdev->dev);
fdc50a94 1410
efe6a8ad
RW		 1411 dev_pm_qos_hide_latency_limit(&pdev->dev);
1412
faca6648 1413 mmc_remove_host(host->mmc);
3b0beafc
GL		 1414 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1415
f985da17
GL		 1416 /*
1417 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1418 * mmc_remove_host() call above. But swapping order doesn't help either
1419 * (a query on the linux-mmc mailing list didn't bring any replies).
1420 */
1421 cancel_delayed_work_sync(&host->timeout_work);
1422
fdc50a94
YG		 1423 if (host->addr)
1424 iounmap(host->addr);
1425
aa0787a9
GL		 1426 irq[0] = platform_get_irq(pdev, 0);
1427 irq[1] = platform_get_irq(pdev, 1);
fdc50a94
YG		 1428
1429 free_irq(irq[0], host);
1430 free_irq(irq[1], host);
1431
aa0787a9
GL		 1432 platform_set_drvdata(pdev, NULL);
1433
fdc50a94 1434 mmc_free_host(host->mmc);
faca6648 1435 pm_runtime_put_sync(&pdev->dev);
b289174f 1436 clk_disable(host->hclk);
faca6648 1437 pm_runtime_disable(&pdev->dev);
fdc50a94
YG		 1438
1439 return 0;
1440}
1441
faca6648
GL		 1442#ifdef CONFIG_PM
1443static int sh_mmcif_suspend(struct device *dev)
1444{
b289174f 1445 struct sh_mmcif_host *host = dev_get_drvdata(dev);
faca6648
GL		 1446 int ret = mmc_suspend_host(host->mmc);
1447
b289174f 1448 if (!ret)
faca6648 1449 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
faca6648
GL		 1450
1451 return ret;
1452}
1453
1454static int sh_mmcif_resume(struct device *dev)
1455{
b289174f 1456 struct sh_mmcif_host *host = dev_get_drvdata(dev);
faca6648
GL		 1457
1458 return mmc_resume_host(host->mmc);
1459}
1460#else
1461#define sh_mmcif_suspend NULL
1462#define sh_mmcif_resume NULL
1463#endif /* CONFIG_PM */
1464
1465static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1466 .suspend = sh_mmcif_suspend,
1467 .resume = sh_mmcif_resume,
1468};
1469
fdc50a94
YG		 1470static struct platform_driver sh_mmcif_driver = {
1471 .probe = sh_mmcif_probe,
1472 .remove = sh_mmcif_remove,
1473 .driver = {
1474 .name = DRIVER_NAME,
faca6648 1475 .pm = &sh_mmcif_dev_pm_ops,
fdc50a94
YG		 1476 },
1477};
1478
d1f81a64 1479module_platform_driver(sh_mmcif_driver);
fdc50a94
YG		 1480
1481MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1482MODULE_LICENSE("GPL");
aa0787a9 1483MODULE_ALIAS("platform:" DRIVER_NAME);
fdc50a94 1484MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");
Linux 6.x block layer and io_uring tree(s)