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mmc: sh_mmcif: reset error code for any opcode
[linux-2.6-block.git] / drivers / mmc / host / sh_mmcif.c
CommitLineData
fdc50a94
YG		 1/*
2 * MMCIF eMMC driver.
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10 *
11 *
12 * TODO
13 * 1. DMA
14 * 2. Power management
15 * 3. Handle MMC errors better
16 *
17 */
18
f985da17
GL		 19/*
20 * The MMCIF driver is now processing MMC requests asynchronously, according
21 * to the Linux MMC API requirement.
22 *
23 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
24 * data, and optional stop. To achieve asynchronous processing each of these
25 * stages is split into two halves: a top and a bottom half. The top half
26 * initialises the hardware, installs a timeout handler to handle completion
27 * timeouts, and returns. In case of the command stage this immediately returns
28 * control to the caller, leaving all further processing to run asynchronously.
29 * All further request processing is performed by the bottom halves.
30 *
31 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
32 * thread, a DMA completion callback, if DMA is used, a timeout work, and
33 * request- and stage-specific handler methods.
34 *
35 * Each bottom half run begins with either a hardware interrupt, a DMA callback
36 * invocation, or a timeout work run. In case of an error or a successful
37 * processing completion, the MMC core is informed and the request processing is
38 * finished. In case processing has to continue, i.e., if data has to be read
39 * from or written to the card, or if a stop command has to be sent, the next
40 * top half is called, which performs the necessary hardware handling and
41 * reschedules the timeout work. This returns the driver state machine into the
42 * bottom half waiting state.
43 */
44
86df1745 45#include <linux/bitops.h>
aa0787a9
GL		 46#include <linux/clk.h>
47#include <linux/completion.h>
e47bf32a 48#include <linux/delay.h>
fdc50a94 49#include <linux/dma-mapping.h>
a782d688 50#include <linux/dmaengine.h>
fdc50a94
YG		 51#include <linux/mmc/card.h>
52#include <linux/mmc/core.h>
e47bf32a 53#include <linux/mmc/host.h>
fdc50a94
YG		 54#include <linux/mmc/mmc.h>
55#include <linux/mmc/sdio.h>
fdc50a94 56#include <linux/mmc/sh_mmcif.h>
e480606a 57#include <linux/mmc/slot-gpio.h>
bf68a812 58#include <linux/mod_devicetable.h>
8047310e 59#include <linux/mutex.h>
a782d688 60#include <linux/pagemap.h>
e47bf32a 61#include <linux/platform_device.h>
efe6a8ad 62#include <linux/pm_qos.h>
faca6648 63#include <linux/pm_runtime.h>
3b0beafc 64#include <linux/spinlock.h>
88b47679 65#include <linux/module.h>
fdc50a94
YG		 66
67#define DRIVER_NAME "sh_mmcif"
68#define DRIVER_VERSION "2010-04-28"
69
fdc50a94
YG		 70/* CE_CMD_SET */
71#define CMD_MASK 0x3f000000
72#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
73#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
74#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
75#define CMD_SET_RBSY (1 << 21) /* R1b */
76#define CMD_SET_CCSEN (1 << 20)
77#define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
78#define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
79#define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
80#define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
81#define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
82#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
83#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
84#define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
85#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
86#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
87#define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
88#define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
89#define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
90#define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
91#define CMD_SET_CCSH (1 << 5)
555061f9 92#define CMD_SET_DARS (1 << 2) /* Dual Data Rate */
fdc50a94
YG		 93#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
94#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
95#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
96
97/* CE_CMD_CTRL */
98#define CMD_CTRL_BREAK (1 << 0)
99
100/* CE_BLOCK_SET */
101#define BLOCK_SIZE_MASK 0x0000ffff
102
fdc50a94
YG		 103/* CE_INT */
104#define INT_CCSDE (1 << 29)
105#define INT_CMD12DRE (1 << 26)
106#define INT_CMD12RBE (1 << 25)
107#define INT_CMD12CRE (1 << 24)
108#define INT_DTRANE (1 << 23)
109#define INT_BUFRE (1 << 22)
110#define INT_BUFWEN (1 << 21)
111#define INT_BUFREN (1 << 20)
112#define INT_CCSRCV (1 << 19)
113#define INT_RBSYE (1 << 17)
114#define INT_CRSPE (1 << 16)
115#define INT_CMDVIO (1 << 15)
116#define INT_BUFVIO (1 << 14)
117#define INT_WDATERR (1 << 11)
118#define INT_RDATERR (1 << 10)
119#define INT_RIDXERR (1 << 9)
120#define INT_RSPERR (1 << 8)
121#define INT_CCSTO (1 << 5)
122#define INT_CRCSTO (1 << 4)
123#define INT_WDATTO (1 << 3)
124#define INT_RDATTO (1 << 2)
125#define INT_RBSYTO (1 << 1)
126#define INT_RSPTO (1 << 0)
127#define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
128 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
129 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
130 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
131
132/* CE_INT_MASK */
133#define MASK_ALL 0x00000000
134#define MASK_MCCSDE (1 << 29)
135#define MASK_MCMD12DRE (1 << 26)
136#define MASK_MCMD12RBE (1 << 25)
137#define MASK_MCMD12CRE (1 << 24)
138#define MASK_MDTRANE (1 << 23)
139#define MASK_MBUFRE (1 << 22)
140#define MASK_MBUFWEN (1 << 21)
141#define MASK_MBUFREN (1 << 20)
142#define MASK_MCCSRCV (1 << 19)
143#define MASK_MRBSYE (1 << 17)
144#define MASK_MCRSPE (1 << 16)
145#define MASK_MCMDVIO (1 << 15)
146#define MASK_MBUFVIO (1 << 14)
147#define MASK_MWDATERR (1 << 11)
148#define MASK_MRDATERR (1 << 10)
149#define MASK_MRIDXERR (1 << 9)
150#define MASK_MRSPERR (1 << 8)
151#define MASK_MCCSTO (1 << 5)
152#define MASK_MCRCSTO (1 << 4)
153#define MASK_MWDATTO (1 << 3)
154#define MASK_MRDATTO (1 << 2)
155#define MASK_MRBSYTO (1 << 1)
156#define MASK_MRSPTO (1 << 0)
157
ee4b8887
GL		 158#define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
159 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
160 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
161 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
162
fdc50a94
YG		 163/* CE_HOST_STS1 */
164#define STS1_CMDSEQ (1 << 31)
165
166/* CE_HOST_STS2 */
167#define STS2_CRCSTE (1 << 31)
168#define STS2_CRC16E (1 << 30)
169#define STS2_AC12CRCE (1 << 29)
170#define STS2_RSPCRC7E (1 << 28)
171#define STS2_CRCSTEBE (1 << 27)
172#define STS2_RDATEBE (1 << 26)
173#define STS2_AC12REBE (1 << 25)
174#define STS2_RSPEBE (1 << 24)
175#define STS2_AC12IDXE (1 << 23)
176#define STS2_RSPIDXE (1 << 22)
177#define STS2_CCSTO (1 << 15)
178#define STS2_RDATTO (1 << 14)
179#define STS2_DATBSYTO (1 << 13)
180#define STS2_CRCSTTO (1 << 12)
181#define STS2_AC12BSYTO (1 << 11)
182#define STS2_RSPBSYTO (1 << 10)
183#define STS2_AC12RSPTO (1 << 9)
184#define STS2_RSPTO (1 << 8)
185#define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
186 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
187#define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
188 STS2_DATBSYTO | STS2_CRCSTTO | \
189 STS2_AC12BSYTO | STS2_RSPBSYTO | \
190 STS2_AC12RSPTO | STS2_RSPTO)
191
fdc50a94
YG		 192#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
193#define CLKDEV_MMC_DATA 20000000 /* 20MHz */
194#define CLKDEV_INIT 400000 /* 400 KHz */
195
3b0beafc
GL		 196enum mmcif_state {
197 STATE_IDLE,
198 STATE_REQUEST,
199 STATE_IOS,
8047310e 200 STATE_TIMEOUT,
3b0beafc
GL		 201};
202
f985da17
GL		 203enum mmcif_wait_for {
204 MMCIF_WAIT_FOR_REQUEST,
205 MMCIF_WAIT_FOR_CMD,
206 MMCIF_WAIT_FOR_MREAD,
207 MMCIF_WAIT_FOR_MWRITE,
208 MMCIF_WAIT_FOR_READ,
209 MMCIF_WAIT_FOR_WRITE,
210 MMCIF_WAIT_FOR_READ_END,
211 MMCIF_WAIT_FOR_WRITE_END,
212 MMCIF_WAIT_FOR_STOP,
213};
214
fdc50a94
YG		 215struct sh_mmcif_host {
216 struct mmc_host *mmc;
f985da17 217 struct mmc_request *mrq;
fdc50a94
YG		 218 struct platform_device *pd;
219 struct clk *hclk;
220 unsigned int clk;
221 int bus_width;
555061f9 222 unsigned char timing;
aa0787a9 223 bool sd_error;
f985da17 224 bool dying;
fdc50a94
YG		 225 long timeout;
226 void __iomem *addr;
f985da17 227 u32 *pio_ptr;
ee4b8887 228 spinlock_t lock; /* protect sh_mmcif_host::state */
3b0beafc 229 enum mmcif_state state;
f985da17
GL		 230 enum mmcif_wait_for wait_for;
231 struct delayed_work timeout_work;
232 size_t blocksize;
233 int sg_idx;
234 int sg_blkidx;
faca6648 235 bool power;
c9b0cef2 236 bool card_present;
8047310e 237 struct mutex thread_lock;
fdc50a94 238
a782d688
GL		 239 /* DMA support */
240 struct dma_chan *chan_rx;
241 struct dma_chan *chan_tx;
242 struct completion dma_complete;
f38f94c6 243 bool dma_active;
a782d688 244};
fdc50a94
YG		 245
246static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
247 unsigned int reg, u32 val)
248{
487d9fc5 249 writel(val | readl(host->addr + reg), host->addr + reg);
fdc50a94
YG		 250}
251
252static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
253 unsigned int reg, u32 val)
254{
487d9fc5 255 writel(~val & readl(host->addr + reg), host->addr + reg);
fdc50a94
YG		 256}
257
a782d688
GL		 258static void mmcif_dma_complete(void *arg)
259{
260 struct sh_mmcif_host *host = arg;
8047310e 261 struct mmc_request *mrq = host->mrq;
69983404 262
a782d688
GL		 263 dev_dbg(&host->pd->dev, "Command completed\n");
264
8047310e 265 if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n",
a782d688
GL		 266 dev_name(&host->pd->dev)))
267 return;
268
a782d688
GL		 269 complete(&host->dma_complete);
270}
271
272static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
273{
69983404
GL		 274 struct mmc_data *data = host->mrq->data;
275 struct scatterlist *sg = data->sg;
a782d688
GL		 276 struct dma_async_tx_descriptor *desc = NULL;
277 struct dma_chan *chan = host->chan_rx;
278 dma_cookie_t cookie = -EINVAL;
279 int ret;
280
69983404 281 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
1ed828db 282 DMA_FROM_DEVICE);
a782d688 283 if (ret > 0) {
f38f94c6 284 host->dma_active = true;
16052827 285 desc = dmaengine_prep_slave_sg(chan, sg, ret,
05f5799c 286 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
a782d688
GL		 287 }
288
289 if (desc) {
290 desc->callback = mmcif_dma_complete;
291 desc->callback_param = host;
a5ece7d2
LW		 292 cookie = dmaengine_submit(desc);
293 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
294 dma_async_issue_pending(chan);
a782d688
GL		 295 }
296 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
69983404 297 __func__, data->sg_len, ret, cookie);
a782d688
GL		 298
299 if (!desc) {
300 /* DMA failed, fall back to PIO */
301 if (ret >= 0)
302 ret = -EIO;
303 host->chan_rx = NULL;
f38f94c6 304 host->dma_active = false;
a782d688
GL		 305 dma_release_channel(chan);
306 /* Free the Tx channel too */
307 chan = host->chan_tx;
308 if (chan) {
309 host->chan_tx = NULL;
310 dma_release_channel(chan);
311 }
312 dev_warn(&host->pd->dev,
313 "DMA failed: %d, falling back to PIO\n", ret);
314 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
315 }
316
317 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
69983404 318 desc, cookie, data->sg_len);
a782d688
GL		 319}
320
321static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
322{
69983404
GL		 323 struct mmc_data *data = host->mrq->data;
324 struct scatterlist *sg = data->sg;
a782d688
GL		 325 struct dma_async_tx_descriptor *desc = NULL;
326 struct dma_chan *chan = host->chan_tx;
327 dma_cookie_t cookie = -EINVAL;
328 int ret;
329
69983404 330 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
1ed828db 331 DMA_TO_DEVICE);
a782d688 332 if (ret > 0) {
f38f94c6 333 host->dma_active = true;
16052827 334 desc = dmaengine_prep_slave_sg(chan, sg, ret,
05f5799c 335 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
a782d688
GL		 336 }
337
338 if (desc) {
339 desc->callback = mmcif_dma_complete;
340 desc->callback_param = host;
a5ece7d2
LW		 341 cookie = dmaengine_submit(desc);
342 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
343 dma_async_issue_pending(chan);
a782d688
GL		 344 }
345 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
69983404 346 __func__, data->sg_len, ret, cookie);
a782d688
GL		 347
348 if (!desc) {
349 /* DMA failed, fall back to PIO */
350 if (ret >= 0)
351 ret = -EIO;
352 host->chan_tx = NULL;
f38f94c6 353 host->dma_active = false;
a782d688
GL		 354 dma_release_channel(chan);
355 /* Free the Rx channel too */
356 chan = host->chan_rx;
357 if (chan) {
358 host->chan_rx = NULL;
359 dma_release_channel(chan);
360 }
361 dev_warn(&host->pd->dev,
362 "DMA failed: %d, falling back to PIO\n", ret);
363 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
364 }
365
366 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
367 desc, cookie);
368}
369
a782d688
GL		 370static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
371 struct sh_mmcif_plat_data *pdata)
372{
0e79f9ae
GL		 373 struct resource *res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);
374 struct dma_slave_config cfg;
375 dma_cap_mask_t mask;
376 int ret;
a782d688 377
f38f94c6 378 host->dma_active = false;
a782d688 379
bf68a812
GL		 380 if (!pdata)
381 return;
382
0e79f9ae
GL		 383 if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0)
384 return;
a782d688 385
0e79f9ae
GL		 386 /* We can only either use DMA for both Tx and Rx or not use it at all */
387 dma_cap_zero(mask);
388 dma_cap_set(DMA_SLAVE, mask);
a782d688 389
0e79f9ae
GL		 390 host->chan_tx = dma_request_channel(mask, shdma_chan_filter,
391 (void *)pdata->slave_id_tx);
392 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
393 host->chan_tx);
a782d688 394
0e79f9ae
GL		 395 if (!host->chan_tx)
396 return;
a782d688 397
0e79f9ae
GL		 398 cfg.slave_id = pdata->slave_id_tx;
399 cfg.direction = DMA_MEM_TO_DEV;
400 cfg.dst_addr = res->start + MMCIF_CE_DATA;
401 cfg.src_addr = 0;
402 ret = dmaengine_slave_config(host->chan_tx, &cfg);
403 if (ret < 0)
404 goto ecfgtx;
405
406 host->chan_rx = dma_request_channel(mask, shdma_chan_filter,
407 (void *)pdata->slave_id_rx);
408 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
409 host->chan_rx);
410
411 if (!host->chan_rx)
412 goto erqrx;
413
414 cfg.slave_id = pdata->slave_id_rx;
415 cfg.direction = DMA_DEV_TO_MEM;
416 cfg.dst_addr = 0;
417 cfg.src_addr = res->start + MMCIF_CE_DATA;
418 ret = dmaengine_slave_config(host->chan_rx, &cfg);
419 if (ret < 0)
420 goto ecfgrx;
421
422 init_completion(&host->dma_complete);
423
424 return;
425
426ecfgrx:
427 dma_release_channel(host->chan_rx);
428 host->chan_rx = NULL;
429erqrx:
430ecfgtx:
431 dma_release_channel(host->chan_tx);
432 host->chan_tx = NULL;
a782d688
GL		 433}
434
435static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
436{
437 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
438 /* Descriptors are freed automatically */
439 if (host->chan_tx) {
440 struct dma_chan *chan = host->chan_tx;
441 host->chan_tx = NULL;
442 dma_release_channel(chan);
443 }
444 if (host->chan_rx) {
445 struct dma_chan *chan = host->chan_rx;
446 host->chan_rx = NULL;
447 dma_release_channel(chan);
448 }
449
f38f94c6 450 host->dma_active = false;
a782d688 451}
fdc50a94
YG		 452
453static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
454{
455 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
bf68a812 456 bool sup_pclk = p ? p->sup_pclk : false;
fdc50a94
YG		 457
458 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
459 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
460
461 if (!clk)
462 return;
bf68a812 463 if (sup_pclk && clk == host->clk)
fdc50a94
YG		 464 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
465 else
466 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
f9388257
SH		 467 ((fls(DIV_ROUND_UP(host->clk,
468 clk) - 1) - 1) << 16));
fdc50a94
YG		 469
470 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
471}
472
473static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
474{
475 u32 tmp;
476
487d9fc5 477 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
fdc50a94 478
487d9fc5
MD		 479 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
480 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
fdc50a94
YG		 481 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
482 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
483 /* byte swap on */
484 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
485}
486
487static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
488{
489 u32 state1, state2;
ee4b8887 490 int ret, timeout;
fdc50a94 491
aa0787a9 492 host->sd_error = false;
fdc50a94 493
487d9fc5
MD		 494 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
495 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
e47bf32a
GL		 496 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
497 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
fdc50a94
YG		 498
499 if (state1 & STS1_CMDSEQ) {
500 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
501 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
ee4b8887 502 for (timeout = 10000000; timeout; timeout--) {
487d9fc5 503 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
ee4b8887 504 & STS1_CMDSEQ))
fdc50a94
YG		 505 break;
506 mdelay(1);
507 }
ee4b8887
GL		 508 if (!timeout) {
509 dev_err(&host->pd->dev,
510 "Forced end of command sequence timeout err\n");
511 return -EIO;
512 }
fdc50a94 513 sh_mmcif_sync_reset(host);
e47bf32a 514 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
fdc50a94
YG		 515 return -EIO;
516 }
517
518 if (state2 & STS2_CRC_ERR) {
ee4b8887 519 dev_dbg(&host->pd->dev, ": CRC error\n");
fdc50a94
YG		 520 ret = -EIO;
521 } else if (state2 & STS2_TIMEOUT_ERR) {
ee4b8887 522 dev_dbg(&host->pd->dev, ": Timeout\n");
fdc50a94
YG		 523 ret = -ETIMEDOUT;
524 } else {
ee4b8887 525 dev_dbg(&host->pd->dev, ": End/Index error\n");
fdc50a94
YG		 526 ret = -EIO;
527 }
528 return ret;
529}
530
f985da17 531static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
fdc50a94 532{
f985da17
GL		 533 struct mmc_data *data = host->mrq->data;
534
535 host->sg_blkidx += host->blocksize;
536
537 /* data->sg->length must be a multiple of host->blocksize? */
538 BUG_ON(host->sg_blkidx > data->sg->length);
539
540 if (host->sg_blkidx == data->sg->length) {
541 host->sg_blkidx = 0;
542 if (++host->sg_idx < data->sg_len)
543 host->pio_ptr = sg_virt(++data->sg);
544 } else {
545 host->pio_ptr = p;
546 }
547
99eb9d8d 548 return host->sg_idx != data->sg_len;
f985da17
GL		 549}
550
551static void sh_mmcif_single_read(struct sh_mmcif_host *host,
552 struct mmc_request *mrq)
553{
554 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
555 BLOCK_SIZE_MASK) + 3;
556
557 host->wait_for = MMCIF_WAIT_FOR_READ;
fdc50a94 558
fdc50a94
YG		 559 /* buf read enable */
560 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
f985da17
GL		 561}
562
563static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
564{
565 struct mmc_data *data = host->mrq->data;
566 u32 *p = sg_virt(data->sg);
567 int i;
568
569 if (host->sd_error) {
570 data->error = sh_mmcif_error_manage(host);
571 return false;
572 }
573
574 for (i = 0; i < host->blocksize / 4; i++)
487d9fc5 575 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
fdc50a94
YG		 576
577 /* buffer read end */
578 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
f985da17 579 host->wait_for = MMCIF_WAIT_FOR_READ_END;
fdc50a94 580
f985da17 581 return true;
fdc50a94
YG		 582}
583
f985da17
GL		 584static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
585 struct mmc_request *mrq)
fdc50a94
YG		 586{
587 struct mmc_data *data = mrq->data;
f985da17
GL		 588
589 if (!data->sg_len || !data->sg->length)
590 return;
591
592 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
593 BLOCK_SIZE_MASK;
594
595 host->wait_for = MMCIF_WAIT_FOR_MREAD;
596 host->sg_idx = 0;
597 host->sg_blkidx = 0;
598 host->pio_ptr = sg_virt(data->sg);
5df460b1 599
f985da17
GL		 600 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
601}
602
603static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
604{
605 struct mmc_data *data = host->mrq->data;
606 u32 *p = host->pio_ptr;
607 int i;
608
609 if (host->sd_error) {
610 data->error = sh_mmcif_error_manage(host);
611 return false;
fdc50a94 612 }
f985da17
GL		 613
614 BUG_ON(!data->sg->length);
615
616 for (i = 0; i < host->blocksize / 4; i++)
617 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
618
619 if (!sh_mmcif_next_block(host, p))
620 return false;
621
f985da17
GL		 622 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
623
624 return true;
fdc50a94
YG		 625}
626
f985da17 627static void sh_mmcif_single_write(struct sh_mmcif_host *host,
fdc50a94
YG		 628 struct mmc_request *mrq)
629{
f985da17
GL		 630 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
631 BLOCK_SIZE_MASK) + 3;
fdc50a94 632
f985da17 633 host->wait_for = MMCIF_WAIT_FOR_WRITE;
fdc50a94
YG		 634
635 /* buf write enable */
f985da17
GL		 636 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
637}
638
639static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
640{
641 struct mmc_data *data = host->mrq->data;
642 u32 *p = sg_virt(data->sg);
643 int i;
644
645 if (host->sd_error) {
646 data->error = sh_mmcif_error_manage(host);
647 return false;
648 }
649
650 for (i = 0; i < host->blocksize / 4; i++)
487d9fc5 651 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
fdc50a94
YG		 652
653 /* buffer write end */
654 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
f985da17 655 host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
fdc50a94 656
f985da17 657 return true;
fdc50a94
YG		 658}
659
f985da17
GL		 660static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
661 struct mmc_request *mrq)
fdc50a94
YG		 662{
663 struct mmc_data *data = mrq->data;
fdc50a94 664
f985da17
GL		 665 if (!data->sg_len || !data->sg->length)
666 return;
fdc50a94 667
f985da17
GL		 668 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
669 BLOCK_SIZE_MASK;
fdc50a94 670
f985da17
GL		 671 host->wait_for = MMCIF_WAIT_FOR_MWRITE;
672 host->sg_idx = 0;
673 host->sg_blkidx = 0;
674 host->pio_ptr = sg_virt(data->sg);
5df460b1 675
f985da17
GL		 676 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
677}
fdc50a94 678
f985da17
GL		 679static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
680{
681 struct mmc_data *data = host->mrq->data;
682 u32 *p = host->pio_ptr;
683 int i;
684
685 if (host->sd_error) {
686 data->error = sh_mmcif_error_manage(host);
687 return false;
fdc50a94 688 }
f985da17
GL		 689
690 BUG_ON(!data->sg->length);
691
692 for (i = 0; i < host->blocksize / 4; i++)
693 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
694
695 if (!sh_mmcif_next_block(host, p))
696 return false;
697
f985da17
GL		 698 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
699
700 return true;
fdc50a94
YG		 701}
702
703static void sh_mmcif_get_response(struct sh_mmcif_host *host,
704 struct mmc_command *cmd)
705{
706 if (cmd->flags & MMC_RSP_136) {
487d9fc5
MD		 707 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
708 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
709 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
710 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
fdc50a94 711 } else
487d9fc5 712 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
fdc50a94
YG		 713}
714
715static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
716 struct mmc_command *cmd)
717{
487d9fc5 718 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
fdc50a94
YG		 719}
720
721static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
69983404 722 struct mmc_request *mrq)
fdc50a94 723{
69983404
GL		 724 struct mmc_data *data = mrq->data;
725 struct mmc_command *cmd = mrq->cmd;
726 u32 opc = cmd->opcode;
fdc50a94
YG		 727 u32 tmp = 0;
728
729 /* Response Type check */
730 switch (mmc_resp_type(cmd)) {
731 case MMC_RSP_NONE:
732 tmp |= CMD_SET_RTYP_NO;
733 break;
734 case MMC_RSP_R1:
735 case MMC_RSP_R1B:
736 case MMC_RSP_R3:
737 tmp |= CMD_SET_RTYP_6B;
738 break;
739 case MMC_RSP_R2:
740 tmp |= CMD_SET_RTYP_17B;
741 break;
742 default:
e47bf32a 743 dev_err(&host->pd->dev, "Unsupported response type.\n");
fdc50a94
YG		 744 break;
745 }
746 switch (opc) {
747 /* RBSY */
a812ba0f 748 case MMC_SLEEP_AWAKE:
fdc50a94
YG		 749 case MMC_SWITCH:
750 case MMC_STOP_TRANSMISSION:
751 case MMC_SET_WRITE_PROT:
752 case MMC_CLR_WRITE_PROT:
753 case MMC_ERASE:
fdc50a94
YG		 754 tmp |= CMD_SET_RBSY;
755 break;
756 }
757 /* WDAT / DATW */
69983404 758 if (data) {
fdc50a94
YG		 759 tmp |= CMD_SET_WDAT;
760 switch (host->bus_width) {
761 case MMC_BUS_WIDTH_1:
762 tmp |= CMD_SET_DATW_1;
763 break;
764 case MMC_BUS_WIDTH_4:
765 tmp |= CMD_SET_DATW_4;
766 break;
767 case MMC_BUS_WIDTH_8:
768 tmp |= CMD_SET_DATW_8;
769 break;
770 default:
e47bf32a 771 dev_err(&host->pd->dev, "Unsupported bus width.\n");
fdc50a94
YG		 772 break;
773 }
555061f9
TK		 774 switch (host->timing) {
775 case MMC_TIMING_UHS_DDR50:
776 /*
777 * MMC core will only set this timing, if the host
778 * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF
779 * implementations with this capability, e.g. sh73a0,
780 * will have to set it in their platform data.
781 */
782 tmp |= CMD_SET_DARS;
783 break;
784 }
fdc50a94
YG		 785 }
786 /* DWEN */
787 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
788 tmp |= CMD_SET_DWEN;
789 /* CMLTE/CMD12EN */
790 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
791 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
792 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
69983404 793 data->blocks << 16);
fdc50a94
YG		 794 }
795 /* RIDXC[1:0] check bits */
796 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
797 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
798 tmp |= CMD_SET_RIDXC_BITS;
799 /* RCRC7C[1:0] check bits */
800 if (opc == MMC_SEND_OP_COND)
801 tmp |= CMD_SET_CRC7C_BITS;
802 /* RCRC7C[1:0] internal CRC7 */
803 if (opc == MMC_ALL_SEND_CID ||
804 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
805 tmp |= CMD_SET_CRC7C_INTERNAL;
806
69983404 807 return (opc << 24) | tmp;
fdc50a94
YG		 808}
809
e47bf32a 810static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
f985da17 811 struct mmc_request *mrq, u32 opc)
fdc50a94 812{
fdc50a94
YG		 813 switch (opc) {
814 case MMC_READ_MULTIPLE_BLOCK:
f985da17
GL		 815 sh_mmcif_multi_read(host, mrq);
816 return 0;
fdc50a94 817 case MMC_WRITE_MULTIPLE_BLOCK:
f985da17
GL		 818 sh_mmcif_multi_write(host, mrq);
819 return 0;
fdc50a94 820 case MMC_WRITE_BLOCK:
f985da17
GL		 821 sh_mmcif_single_write(host, mrq);
822 return 0;
fdc50a94
YG		 823 case MMC_READ_SINGLE_BLOCK:
824 case MMC_SEND_EXT_CSD:
f985da17
GL		 825 sh_mmcif_single_read(host, mrq);
826 return 0;
fdc50a94 827 default:
e47bf32a 828 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
ee4b8887 829 return -EINVAL;
fdc50a94 830 }
fdc50a94
YG		 831}
832
833static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
ee4b8887 834 struct mmc_request *mrq)
fdc50a94 835{
ee4b8887 836 struct mmc_command *cmd = mrq->cmd;
f985da17
GL		 837 u32 opc = cmd->opcode;
838 u32 mask;
fdc50a94 839
fdc50a94 840 switch (opc) {
ee4b8887 841 /* response busy check */
a812ba0f 842 case MMC_SLEEP_AWAKE:
fdc50a94
YG		 843 case MMC_SWITCH:
844 case MMC_STOP_TRANSMISSION:
845 case MMC_SET_WRITE_PROT:
846 case MMC_CLR_WRITE_PROT:
847 case MMC_ERASE:
ee4b8887 848 mask = MASK_START_CMD | MASK_MRBSYE;
fdc50a94
YG		 849 break;
850 default:
ee4b8887 851 mask = MASK_START_CMD | MASK_MCRSPE;
fdc50a94
YG		 852 break;
853 }
fdc50a94 854
69983404 855 if (mrq->data) {
487d9fc5
MD		 856 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
857 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
858 mrq->data->blksz);
fdc50a94 859 }
69983404 860 opc = sh_mmcif_set_cmd(host, mrq);
fdc50a94 861
487d9fc5
MD		 862 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
863 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
fdc50a94 864 /* set arg */
487d9fc5 865 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
fdc50a94 866 /* set cmd */
487d9fc5 867 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
fdc50a94 868
f985da17
GL		 869 host->wait_for = MMCIF_WAIT_FOR_CMD;
870 schedule_delayed_work(&host->timeout_work, host->timeout);
fdc50a94
YG		 871}
872
873static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
ee4b8887 874 struct mmc_request *mrq)
fdc50a94 875{
69983404
GL		 876 switch (mrq->cmd->opcode) {
877 case MMC_READ_MULTIPLE_BLOCK:
fdc50a94 878 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
69983404
GL		 879 break;
880 case MMC_WRITE_MULTIPLE_BLOCK:
fdc50a94 881 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
69983404
GL		 882 break;
883 default:
e47bf32a 884 dev_err(&host->pd->dev, "unsupported stop cmd\n");
69983404 885 mrq->stop->error = sh_mmcif_error_manage(host);
fdc50a94
YG		 886 return;
887 }
888
f985da17 889 host->wait_for = MMCIF_WAIT_FOR_STOP;
fdc50a94
YG		 890}
891
892static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
893{
894 struct sh_mmcif_host *host = mmc_priv(mmc);
3b0beafc
GL		 895 unsigned long flags;
896
897 spin_lock_irqsave(&host->lock, flags);
898 if (host->state != STATE_IDLE) {
899 spin_unlock_irqrestore(&host->lock, flags);
900 mrq->cmd->error = -EAGAIN;
901 mmc_request_done(mmc, mrq);
902 return;
903 }
904
905 host->state = STATE_REQUEST;
906 spin_unlock_irqrestore(&host->lock, flags);
fdc50a94
YG		 907
908 switch (mrq->cmd->opcode) {
909 /* MMCIF does not support SD/SDIO command */
7541ca98
LP		 910 case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */
911 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
912 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)
913 break;
fdc50a94 914 case MMC_APP_CMD:
92ff0c5b 915 case SD_IO_RW_DIRECT:
3b0beafc 916 host->state = STATE_IDLE;
fdc50a94
YG		 917 mrq->cmd->error = -ETIMEDOUT;
918 mmc_request_done(mmc, mrq);
919 return;
fdc50a94
YG		 920 default:
921 break;
922 }
f985da17
GL		 923
924 host->mrq = mrq;
fdc50a94 925
f985da17 926 sh_mmcif_start_cmd(host, mrq);
fdc50a94
YG		 927}
928
a6609267
GL		 929static int sh_mmcif_clk_update(struct sh_mmcif_host *host)
930{
931 int ret = clk_enable(host->hclk);
932
933 if (!ret) {
934 host->clk = clk_get_rate(host->hclk);
935 host->mmc->f_max = host->clk / 2;
936 host->mmc->f_min = host->clk / 512;
937 }
938
939 return ret;
940}
941
7d17baa0
GL		 942static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)
943{
944 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
945 struct mmc_host *mmc = host->mmc;
946
bf68a812 947 if (pd && pd->set_pwr)
7d17baa0
GL		 948 pd->set_pwr(host->pd, ios->power_mode != MMC_POWER_OFF);
949 if (!IS_ERR(mmc->supply.vmmc))
950 /* Errors ignored... */
951 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
952 ios->power_mode ? ios->vdd : 0);
953}
954
fdc50a94
YG		 955static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
956{
957 struct sh_mmcif_host *host = mmc_priv(mmc);
3b0beafc
GL		 958 unsigned long flags;
959
960 spin_lock_irqsave(&host->lock, flags);
961 if (host->state != STATE_IDLE) {
962 spin_unlock_irqrestore(&host->lock, flags);
963 return;
964 }
965
966 host->state = STATE_IOS;
967 spin_unlock_irqrestore(&host->lock, flags);
fdc50a94 968
f5e0cec4 969 if (ios->power_mode == MMC_POWER_UP) {
c9b0cef2 970 if (!host->card_present) {
faca6648
GL		 971 /* See if we also get DMA */
972 sh_mmcif_request_dma(host, host->pd->dev.platform_data);
c9b0cef2 973 host->card_present = true;
faca6648 974 }
7d17baa0 975 sh_mmcif_set_power(host, ios);
f5e0cec4 976 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
fdc50a94
YG		 977 /* clock stop */
978 sh_mmcif_clock_control(host, 0);
faca6648 979 if (ios->power_mode == MMC_POWER_OFF) {
c9b0cef2 980 if (host->card_present) {
faca6648 981 sh_mmcif_release_dma(host);
c9b0cef2 982 host->card_present = false;
faca6648 983 }
c9b0cef2
GL		 984 }
985 if (host->power) {
f8a8ced7 986 pm_runtime_put_sync(&host->pd->dev);
b289174f 987 clk_disable(host->hclk);
c9b0cef2 988 host->power = false;
7d17baa0
GL		 989 if (ios->power_mode == MMC_POWER_OFF)
990 sh_mmcif_set_power(host, ios);
faca6648 991 }
3b0beafc 992 host->state = STATE_IDLE;
fdc50a94 993 return;
fdc50a94
YG		 994 }
995
c9b0cef2
GL		 996 if (ios->clock) {
997 if (!host->power) {
a6609267 998 sh_mmcif_clk_update(host);
c9b0cef2
GL		 999 pm_runtime_get_sync(&host->pd->dev);
1000 host->power = true;
1001 sh_mmcif_sync_reset(host);
1002 }
fdc50a94 1003 sh_mmcif_clock_control(host, ios->clock);
c9b0cef2 1004 }
fdc50a94 1005
555061f9 1006 host->timing = ios->timing;
fdc50a94 1007 host->bus_width = ios->bus_width;
3b0beafc 1008 host->state = STATE_IDLE;
fdc50a94
YG		 1009}
1010
777271d0
AH		 1011static int sh_mmcif_get_cd(struct mmc_host *mmc)
1012{
1013 struct sh_mmcif_host *host = mmc_priv(mmc);
1014 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
e480606a
GL		 1015 int ret = mmc_gpio_get_cd(mmc);
1016
1017 if (ret >= 0)
1018 return ret;
777271d0 1019
bf68a812 1020 if (!p || !p->get_cd)
777271d0
AH		 1021 return -ENOSYS;
1022 else
1023 return p->get_cd(host->pd);
1024}
1025
fdc50a94
YG		 1026static struct mmc_host_ops sh_mmcif_ops = {
1027 .request = sh_mmcif_request,
1028 .set_ios = sh_mmcif_set_ios,
777271d0 1029 .get_cd = sh_mmcif_get_cd,
fdc50a94
YG		 1030};
1031
f985da17
GL		 1032static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1033{
1034 struct mmc_command *cmd = host->mrq->cmd;
69983404 1035 struct mmc_data *data = host->mrq->data;
f985da17
GL		 1036 long time;
1037
1038 if (host->sd_error) {
1039 switch (cmd->opcode) {
1040 case MMC_ALL_SEND_CID:
1041 case MMC_SELECT_CARD:
1042 case MMC_APP_CMD:
1043 cmd->error = -ETIMEDOUT;
f985da17
GL		 1044 break;
1045 default:
1046 cmd->error = sh_mmcif_error_manage(host);
1047 dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n",
1048 cmd->opcode, cmd->error);
1049 break;
1050 }
aba9d646 1051 host->sd_error = false;
f985da17
GL		 1052 return false;
1053 }
1054 if (!(cmd->flags & MMC_RSP_PRESENT)) {
1055 cmd->error = 0;
1056 return false;
1057 }
1058
1059 sh_mmcif_get_response(host, cmd);
1060
69983404 1061 if (!data)
f985da17
GL		 1062 return false;
1063
69983404 1064 if (data->flags & MMC_DATA_READ) {
f985da17
GL		 1065 if (host->chan_rx)
1066 sh_mmcif_start_dma_rx(host);
1067 } else {
1068 if (host->chan_tx)
1069 sh_mmcif_start_dma_tx(host);
1070 }
1071
1072 if (!host->dma_active) {
69983404 1073 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
99eb9d8d 1074 return !data->error;
f985da17
GL		 1075 }
1076
1077 /* Running in the IRQ thread, can sleep */
1078 time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1079 host->timeout);
eae30983
TK		 1080
1081 if (data->flags & MMC_DATA_READ)
1082 dma_unmap_sg(host->chan_rx->device->dev,
1083 data->sg, data->sg_len,
1084 DMA_FROM_DEVICE);
1085 else
1086 dma_unmap_sg(host->chan_tx->device->dev,
1087 data->sg, data->sg_len,
1088 DMA_TO_DEVICE);
1089
f985da17
GL		 1090 if (host->sd_error) {
1091 dev_err(host->mmc->parent,
1092 "Error IRQ while waiting for DMA completion!\n");
1093 /* Woken up by an error IRQ: abort DMA */
69983404 1094 data->error = sh_mmcif_error_manage(host);
f985da17 1095 } else if (!time) {
69983404 1096 data->error = -ETIMEDOUT;
f985da17 1097 } else if (time < 0) {
69983404 1098 data->error = time;
f985da17
GL		 1099 }
1100 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1101 BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1102 host->dma_active = false;
1103
eae30983 1104 if (data->error) {
69983404 1105 data->bytes_xfered = 0;
eae30983
TK		 1106 /* Abort DMA */
1107 if (data->flags & MMC_DATA_READ)
1108 dmaengine_terminate_all(host->chan_rx);
1109 else
1110 dmaengine_terminate_all(host->chan_tx);
1111 }
f985da17
GL		 1112
1113 return false;
1114}
1115
1116static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1117{
1118 struct sh_mmcif_host *host = dev_id;
8047310e 1119 struct mmc_request *mrq;
5df460b1 1120 bool wait = false;
f985da17
GL		 1121
1122 cancel_delayed_work_sync(&host->timeout_work);
1123
8047310e
GL		 1124 mutex_lock(&host->thread_lock);
1125
1126 mrq = host->mrq;
1127 if (!mrq) {
1128 dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n",
1129 host->state, host->wait_for);
1130 mutex_unlock(&host->thread_lock);
1131 return IRQ_HANDLED;
1132 }
1133
f985da17
GL		 1134 /*
1135 * All handlers return true, if processing continues, and false, if the
1136 * request has to be completed - successfully or not
1137 */
1138 switch (host->wait_for) {
1139 case MMCIF_WAIT_FOR_REQUEST:
1140 /* We're too late, the timeout has already kicked in */
8047310e 1141 mutex_unlock(&host->thread_lock);
f985da17
GL		 1142 return IRQ_HANDLED;
1143 case MMCIF_WAIT_FOR_CMD:
5df460b1
GL		 1144 /* Wait for data? */
1145 wait = sh_mmcif_end_cmd(host);
f985da17
GL		 1146 break;
1147 case MMCIF_WAIT_FOR_MREAD:
5df460b1
GL		 1148 /* Wait for more data? */
1149 wait = sh_mmcif_mread_block(host);
f985da17
GL		 1150 break;
1151 case MMCIF_WAIT_FOR_READ:
5df460b1
GL		 1152 /* Wait for data end? */
1153 wait = sh_mmcif_read_block(host);
f985da17
GL		 1154 break;
1155 case MMCIF_WAIT_FOR_MWRITE:
5df460b1
GL		 1156 /* Wait data to write? */
1157 wait = sh_mmcif_mwrite_block(host);
f985da17
GL		 1158 break;
1159 case MMCIF_WAIT_FOR_WRITE:
5df460b1
GL		 1160 /* Wait for data end? */
1161 wait = sh_mmcif_write_block(host);
f985da17
GL		 1162 break;
1163 case MMCIF_WAIT_FOR_STOP:
1164 if (host->sd_error) {
1165 mrq->stop->error = sh_mmcif_error_manage(host);
1166 break;
1167 }
1168 sh_mmcif_get_cmd12response(host, mrq->stop);
1169 mrq->stop->error = 0;
1170 break;
1171 case MMCIF_WAIT_FOR_READ_END:
1172 case MMCIF_WAIT_FOR_WRITE_END:
1173 if (host->sd_error)
91ab252a 1174 mrq->data->error = sh_mmcif_error_manage(host);
f985da17
GL		 1175 break;
1176 default:
1177 BUG();
1178 }
1179
5df460b1
GL		 1180 if (wait) {
1181 schedule_delayed_work(&host->timeout_work, host->timeout);
1182 /* Wait for more data */
8047310e 1183 mutex_unlock(&host->thread_lock);
5df460b1
GL		 1184 return IRQ_HANDLED;
1185 }
1186
f985da17 1187 if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
91ab252a 1188 struct mmc_data *data = mrq->data;
69983404
GL		 1189 if (!mrq->cmd->error && data && !data->error)
1190 data->bytes_xfered =
1191 data->blocks * data->blksz;
f985da17 1192
69983404 1193 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
f985da17 1194 sh_mmcif_stop_cmd(host, mrq);
5df460b1
GL		 1195 if (!mrq->stop->error) {
1196 schedule_delayed_work(&host->timeout_work, host->timeout);
8047310e 1197 mutex_unlock(&host->thread_lock);
f985da17 1198 return IRQ_HANDLED;
5df460b1 1199 }
f985da17
GL		 1200 }
1201 }
1202
1203 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1204 host->state = STATE_IDLE;
69983404 1205 host->mrq = NULL;
f985da17
GL		 1206 mmc_request_done(host->mmc, mrq);
1207
8047310e
GL		 1208 mutex_unlock(&host->thread_lock);
1209
f985da17
GL		 1210 return IRQ_HANDLED;
1211}
1212
fdc50a94
YG		 1213static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1214{
1215 struct sh_mmcif_host *host = dev_id;
aa0787a9 1216 u32 state;
fdc50a94
YG		 1217 int err = 0;
1218
487d9fc5 1219 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
fdc50a94 1220
8a8284a9
GL		 1221 if (state & INT_ERR_STS) {
1222 /* error interrupts - process first */
1223 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1224 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1225 err = 1;
1226 } else if (state & INT_RBSYE) {
487d9fc5
MD		 1227 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1228 ~(INT_RBSYE | INT_CRSPE));
fdc50a94
YG		 1229 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
1230 } else if (state & INT_CRSPE) {
487d9fc5 1231 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
fdc50a94
YG		 1232 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
1233 } else if (state & INT_BUFREN) {
487d9fc5 1234 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
fdc50a94
YG		 1235 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
1236 } else if (state & INT_BUFWEN) {
487d9fc5 1237 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
fdc50a94
YG		 1238 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
1239 } else if (state & INT_CMD12DRE) {
487d9fc5 1240 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
fdc50a94
YG		 1241 ~(INT_CMD12DRE | INT_CMD12RBE |
1242 INT_CMD12CRE | INT_BUFRE));
1243 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
1244 } else if (state & INT_BUFRE) {
487d9fc5 1245 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
fdc50a94
YG		 1246 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
1247 } else if (state & INT_DTRANE) {
7a7eb328
GL		 1248 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1249 ~(INT_CMD12DRE | INT_CMD12RBE |
1250 INT_CMD12CRE | INT_DTRANE));
fdc50a94
YG		 1251 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
1252 } else if (state & INT_CMD12RBE) {
487d9fc5 1253 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
fdc50a94
YG		 1254 ~(INT_CMD12RBE | INT_CMD12CRE));
1255 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
fdc50a94 1256 } else {
faca6648 1257 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
487d9fc5 1258 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
fdc50a94
YG		 1259 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1260 err = 1;
1261 }
1262 if (err) {
aa0787a9 1263 host->sd_error = true;
e47bf32a 1264 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
fdc50a94 1265 }
f985da17
GL		 1266 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1267 if (!host->dma_active)
1268 return IRQ_WAKE_THREAD;
1269 else if (host->sd_error)
1270 mmcif_dma_complete(host);
1271 } else {
aa0787a9 1272 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
f985da17 1273 }
fdc50a94
YG		 1274
1275 return IRQ_HANDLED;
1276}
1277
f985da17
GL		 1278static void mmcif_timeout_work(struct work_struct *work)
1279{
1280 struct delayed_work *d = container_of(work, struct delayed_work, work);
1281 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1282 struct mmc_request *mrq = host->mrq;
8047310e 1283 unsigned long flags;
f985da17
GL		 1284
1285 if (host->dying)
1286 /* Don't run after mmc_remove_host() */
1287 return;
1288
8047310e
GL		 1289 dev_dbg(&host->pd->dev, "Timeout waiting for %u, opcode %u\n",
1290 host->wait_for, mrq->cmd->opcode);
1291
1292 spin_lock_irqsave(&host->lock, flags);
1293 if (host->state == STATE_IDLE) {
1294 spin_unlock_irqrestore(&host->lock, flags);
1295 return;
1296 }
1297
1298 host->state = STATE_TIMEOUT;
1299 spin_unlock_irqrestore(&host->lock, flags);
1300
f985da17
GL		 1301 /*
1302 * Handle races with cancel_delayed_work(), unless
1303 * cancel_delayed_work_sync() is used
1304 */
1305 switch (host->wait_for) {
1306 case MMCIF_WAIT_FOR_CMD:
1307 mrq->cmd->error = sh_mmcif_error_manage(host);
1308 break;
1309 case MMCIF_WAIT_FOR_STOP:
1310 mrq->stop->error = sh_mmcif_error_manage(host);
1311 break;
1312 case MMCIF_WAIT_FOR_MREAD:
1313 case MMCIF_WAIT_FOR_MWRITE:
1314 case MMCIF_WAIT_FOR_READ:
1315 case MMCIF_WAIT_FOR_WRITE:
1316 case MMCIF_WAIT_FOR_READ_END:
1317 case MMCIF_WAIT_FOR_WRITE_END:
69983404 1318 mrq->data->error = sh_mmcif_error_manage(host);
f985da17
GL		 1319 break;
1320 default:
1321 BUG();
1322 }
1323
1324 host->state = STATE_IDLE;
1325 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
f985da17
GL		 1326 host->mrq = NULL;
1327 mmc_request_done(host->mmc, mrq);
1328}
1329
7d17baa0
GL		 1330static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1331{
1332 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
1333 struct mmc_host *mmc = host->mmc;
1334
1335 mmc_regulator_get_supply(mmc);
1336
bf68a812
GL		 1337 if (!pd)
1338 return;
1339
7d17baa0
GL		 1340 if (!mmc->ocr_avail)
1341 mmc->ocr_avail = pd->ocr;
1342 else if (pd->ocr)
1343 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1344}
1345
c3be1efd 1346static int sh_mmcif_probe(struct platform_device *pdev)
fdc50a94
YG		 1347{
1348 int ret = 0, irq[2];
1349 struct mmc_host *mmc;
e47bf32a 1350 struct sh_mmcif_host *host;
e1aae2eb 1351 struct sh_mmcif_plat_data *pd = pdev->dev.platform_data;
fdc50a94
YG		 1352 struct resource *res;
1353 void __iomem *reg;
2cd5b3e0 1354 const char *name;
fdc50a94
YG		 1355
1356 irq[0] = platform_get_irq(pdev, 0);
1357 irq[1] = platform_get_irq(pdev, 1);
2cd5b3e0 1358 if (irq[0] < 0) {
e47bf32a 1359 dev_err(&pdev->dev, "Get irq error\n");
fdc50a94
YG		 1360 return -ENXIO;
1361 }
1362 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1363 if (!res) {
1364 dev_err(&pdev->dev, "platform_get_resource error.\n");
1365 return -ENXIO;
1366 }
1367 reg = ioremap(res->start, resource_size(res));
1368 if (!reg) {
1369 dev_err(&pdev->dev, "ioremap error.\n");
1370 return -ENOMEM;
1371 }
e1aae2eb 1372
fdc50a94
YG		 1373 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1374 if (!mmc) {
1375 ret = -ENOMEM;
e1aae2eb 1376 goto ealloch;
fdc50a94
YG		 1377 }
1378 host = mmc_priv(mmc);
1379 host->mmc = mmc;
1380 host->addr = reg;
f9fd54f2 1381 host->timeout = msecs_to_jiffies(1000);
fdc50a94 1382
fdc50a94
YG		 1383 host->pd = pdev;
1384
3b0beafc 1385 spin_lock_init(&host->lock);
fdc50a94
YG		 1386
1387 mmc->ops = &sh_mmcif_ops;
7d17baa0
GL		 1388 sh_mmcif_init_ocr(host);
1389
a812ba0f 1390 mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY;
bf68a812 1391 if (pd && pd->caps)
fdc50a94 1392 mmc->caps |= pd->caps;
a782d688 1393 mmc->max_segs = 32;
fdc50a94 1394 mmc->max_blk_size = 512;
a782d688
GL		 1395 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1396 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
fdc50a94
YG		 1397 mmc->max_seg_size = mmc->max_req_size;
1398
fdc50a94 1399 platform_set_drvdata(pdev, host);
a782d688 1400
faca6648
GL		 1401 pm_runtime_enable(&pdev->dev);
1402 host->power = false;
1403
047a9ce7 1404 host->hclk = clk_get(&pdev->dev, NULL);
b289174f
GL		 1405 if (IS_ERR(host->hclk)) {
1406 ret = PTR_ERR(host->hclk);
047a9ce7 1407 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
b289174f
GL		 1408 goto eclkget;
1409 }
a6609267
GL		 1410 ret = sh_mmcif_clk_update(host);
1411 if (ret < 0)
1412 goto eclkupdate;
b289174f 1413
faca6648
GL		 1414 ret = pm_runtime_resume(&pdev->dev);
1415 if (ret < 0)
e1aae2eb 1416 goto eresume;
a782d688 1417
5ba85d95 1418 INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
fdc50a94 1419
b289174f 1420 sh_mmcif_sync_reset(host);
3b0beafc
GL		 1421 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1422
2cd5b3e0
SK		 1423 name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error";
1424 ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, name, host);
fdc50a94 1425 if (ret) {
2cd5b3e0 1426 dev_err(&pdev->dev, "request_irq error (%s)\n", name);
e1aae2eb 1427 goto ereqirq0;
fdc50a94 1428 }
2cd5b3e0
SK		 1429 if (irq[1] >= 0) {
1430 ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt,
1431 0, "sh_mmc:int", host);
1432 if (ret) {
1433 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1434 goto ereqirq1;
1435 }
fdc50a94
YG		 1436 }
1437
e480606a
GL		 1438 if (pd && pd->use_cd_gpio) {
1439 ret = mmc_gpio_request_cd(mmc, pd->cd_gpio);
1440 if (ret < 0)
1441 goto erqcd;
1442 }
1443
8047310e
GL		 1444 mutex_init(&host->thread_lock);
1445
b289174f 1446 clk_disable(host->hclk);
5ba85d95
GL		 1447 ret = mmc_add_host(mmc);
1448 if (ret < 0)
e1aae2eb 1449 goto emmcaddh;
fdc50a94 1450
efe6a8ad
RW		 1451 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1452
e47bf32a
GL		 1453 dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1454 dev_dbg(&pdev->dev, "chip ver H'%04x\n",
487d9fc5 1455 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
fdc50a94
YG		 1456 return ret;
1457
e1aae2eb 1458emmcaddh:
e480606a 1459erqcd:
2cd5b3e0
SK		 1460 if (irq[1] >= 0)
1461 free_irq(irq[1], host);
e1aae2eb 1462ereqirq1:
5ba85d95 1463 free_irq(irq[0], host);
e1aae2eb 1464ereqirq0:
faca6648 1465 pm_runtime_suspend(&pdev->dev);
e1aae2eb 1466eresume:
fdc50a94 1467 clk_disable(host->hclk);
a6609267 1468eclkupdate:
b289174f 1469 clk_put(host->hclk);
e1aae2eb 1470eclkget:
b289174f 1471 pm_runtime_disable(&pdev->dev);
fdc50a94 1472 mmc_free_host(mmc);
e1aae2eb
GL		 1473ealloch:
1474 iounmap(reg);
fdc50a94
YG		 1475 return ret;
1476}
1477
6e0ee714 1478static int sh_mmcif_remove(struct platform_device *pdev)
fdc50a94
YG		 1479{
1480 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1481 int irq[2];
1482
f985da17 1483 host->dying = true;
b289174f 1484 clk_enable(host->hclk);
faca6648 1485 pm_runtime_get_sync(&pdev->dev);
fdc50a94 1486
efe6a8ad
RW		 1487 dev_pm_qos_hide_latency_limit(&pdev->dev);
1488
faca6648 1489 mmc_remove_host(host->mmc);
3b0beafc
GL		 1490 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1491
f985da17
GL		 1492 /*
1493 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1494 * mmc_remove_host() call above. But swapping order doesn't help either
1495 * (a query on the linux-mmc mailing list didn't bring any replies).
1496 */
1497 cancel_delayed_work_sync(&host->timeout_work);
1498
fdc50a94
YG		 1499 if (host->addr)
1500 iounmap(host->addr);
1501
aa0787a9
GL		 1502 irq[0] = platform_get_irq(pdev, 0);
1503 irq[1] = platform_get_irq(pdev, 1);
fdc50a94
YG		 1504
1505 free_irq(irq[0], host);
2cd5b3e0
SK		 1506 if (irq[1] >= 0)
1507 free_irq(irq[1], host);
fdc50a94 1508
aa0787a9
GL		 1509 platform_set_drvdata(pdev, NULL);
1510
a0d28ba0 1511 clk_disable(host->hclk);
fdc50a94 1512 mmc_free_host(host->mmc);
faca6648
GL		 1513 pm_runtime_put_sync(&pdev->dev);
1514 pm_runtime_disable(&pdev->dev);
fdc50a94
YG		 1515
1516 return 0;
1517}
1518
faca6648
GL		 1519#ifdef CONFIG_PM
1520static int sh_mmcif_suspend(struct device *dev)
1521{
b289174f 1522 struct sh_mmcif_host *host = dev_get_drvdata(dev);
faca6648
GL		 1523 int ret = mmc_suspend_host(host->mmc);
1524
b289174f 1525 if (!ret)
faca6648 1526 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
faca6648
GL		 1527
1528 return ret;
1529}
1530
1531static int sh_mmcif_resume(struct device *dev)
1532{
b289174f 1533 struct sh_mmcif_host *host = dev_get_drvdata(dev);
faca6648
GL		 1534
1535 return mmc_resume_host(host->mmc);
1536}
1537#else
1538#define sh_mmcif_suspend NULL
1539#define sh_mmcif_resume NULL
1540#endif /* CONFIG_PM */
1541
bf68a812
GL		 1542static const struct of_device_id mmcif_of_match[] = {
1543 { .compatible = "renesas,sh-mmcif" },
1544 { }
1545};
1546MODULE_DEVICE_TABLE(of, mmcif_of_match);
1547
faca6648
GL		 1548static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1549 .suspend = sh_mmcif_suspend,
1550 .resume = sh_mmcif_resume,
1551};
1552
fdc50a94
YG		 1553static struct platform_driver sh_mmcif_driver = {
1554 .probe = sh_mmcif_probe,
1555 .remove = sh_mmcif_remove,
1556 .driver = {
1557 .name = DRIVER_NAME,
faca6648 1558 .pm = &sh_mmcif_dev_pm_ops,
bf68a812
GL		 1559 .owner = THIS_MODULE,
1560 .of_match_table = mmcif_of_match,
fdc50a94
YG		 1561 },
1562};
1563
d1f81a64 1564module_platform_driver(sh_mmcif_driver);
fdc50a94
YG		 1565
1566MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1567MODULE_LICENSE("GPL");
aa0787a9 1568MODULE_ALIAS("platform:" DRIVER_NAME);
fdc50a94 1569MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");
Linux 6.x block layer and io_uring tree(s)