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mmc: sh_mmcif: unmap with the proper sglen
[linux-2.6-block.git] / drivers / mmc / host / sh_mmcif.c
CommitLineData
fdc50a94
YG		 1/*
2 * MMCIF eMMC driver.
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10 *
11 *
12 * TODO
13 * 1. DMA
14 * 2. Power management
15 * 3. Handle MMC errors better
16 *
17 */
18
aa0787a9
GL		 19#include <linux/clk.h>
20#include <linux/completion.h>
e47bf32a 21#include <linux/delay.h>
fdc50a94 22#include <linux/dma-mapping.h>
a782d688 23#include <linux/dmaengine.h>
fdc50a94
YG		 24#include <linux/mmc/card.h>
25#include <linux/mmc/core.h>
e47bf32a 26#include <linux/mmc/host.h>
fdc50a94
YG		 27#include <linux/mmc/mmc.h>
28#include <linux/mmc/sdio.h>
fdc50a94 29#include <linux/mmc/sh_mmcif.h>
a782d688 30#include <linux/pagemap.h>
e47bf32a 31#include <linux/platform_device.h>
fdc50a94
YG		 32
33#define DRIVER_NAME "sh_mmcif"
34#define DRIVER_VERSION "2010-04-28"
35
fdc50a94
YG		 36/* CE_CMD_SET */
37#define CMD_MASK 0x3f000000
38#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
39#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
40#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
41#define CMD_SET_RBSY (1 << 21) /* R1b */
42#define CMD_SET_CCSEN (1 << 20)
43#define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
44#define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
45#define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
46#define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
47#define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
48#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
49#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
50#define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
51#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
52#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
53#define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
54#define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
55#define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
56#define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
57#define CMD_SET_CCSH (1 << 5)
58#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
59#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
60#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
61
62/* CE_CMD_CTRL */
63#define CMD_CTRL_BREAK (1 << 0)
64
65/* CE_BLOCK_SET */
66#define BLOCK_SIZE_MASK 0x0000ffff
67
fdc50a94
YG		 68/* CE_INT */
69#define INT_CCSDE (1 << 29)
70#define INT_CMD12DRE (1 << 26)
71#define INT_CMD12RBE (1 << 25)
72#define INT_CMD12CRE (1 << 24)
73#define INT_DTRANE (1 << 23)
74#define INT_BUFRE (1 << 22)
75#define INT_BUFWEN (1 << 21)
76#define INT_BUFREN (1 << 20)
77#define INT_CCSRCV (1 << 19)
78#define INT_RBSYE (1 << 17)
79#define INT_CRSPE (1 << 16)
80#define INT_CMDVIO (1 << 15)
81#define INT_BUFVIO (1 << 14)
82#define INT_WDATERR (1 << 11)
83#define INT_RDATERR (1 << 10)
84#define INT_RIDXERR (1 << 9)
85#define INT_RSPERR (1 << 8)
86#define INT_CCSTO (1 << 5)
87#define INT_CRCSTO (1 << 4)
88#define INT_WDATTO (1 << 3)
89#define INT_RDATTO (1 << 2)
90#define INT_RBSYTO (1 << 1)
91#define INT_RSPTO (1 << 0)
92#define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
93 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
94 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
95 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
96
97/* CE_INT_MASK */
98#define MASK_ALL 0x00000000
99#define MASK_MCCSDE (1 << 29)
100#define MASK_MCMD12DRE (1 << 26)
101#define MASK_MCMD12RBE (1 << 25)
102#define MASK_MCMD12CRE (1 << 24)
103#define MASK_MDTRANE (1 << 23)
104#define MASK_MBUFRE (1 << 22)
105#define MASK_MBUFWEN (1 << 21)
106#define MASK_MBUFREN (1 << 20)
107#define MASK_MCCSRCV (1 << 19)
108#define MASK_MRBSYE (1 << 17)
109#define MASK_MCRSPE (1 << 16)
110#define MASK_MCMDVIO (1 << 15)
111#define MASK_MBUFVIO (1 << 14)
112#define MASK_MWDATERR (1 << 11)
113#define MASK_MRDATERR (1 << 10)
114#define MASK_MRIDXERR (1 << 9)
115#define MASK_MRSPERR (1 << 8)
116#define MASK_MCCSTO (1 << 5)
117#define MASK_MCRCSTO (1 << 4)
118#define MASK_MWDATTO (1 << 3)
119#define MASK_MRDATTO (1 << 2)
120#define MASK_MRBSYTO (1 << 1)
121#define MASK_MRSPTO (1 << 0)
122
123/* CE_HOST_STS1 */
124#define STS1_CMDSEQ (1 << 31)
125
126/* CE_HOST_STS2 */
127#define STS2_CRCSTE (1 << 31)
128#define STS2_CRC16E (1 << 30)
129#define STS2_AC12CRCE (1 << 29)
130#define STS2_RSPCRC7E (1 << 28)
131#define STS2_CRCSTEBE (1 << 27)
132#define STS2_RDATEBE (1 << 26)
133#define STS2_AC12REBE (1 << 25)
134#define STS2_RSPEBE (1 << 24)
135#define STS2_AC12IDXE (1 << 23)
136#define STS2_RSPIDXE (1 << 22)
137#define STS2_CCSTO (1 << 15)
138#define STS2_RDATTO (1 << 14)
139#define STS2_DATBSYTO (1 << 13)
140#define STS2_CRCSTTO (1 << 12)
141#define STS2_AC12BSYTO (1 << 11)
142#define STS2_RSPBSYTO (1 << 10)
143#define STS2_AC12RSPTO (1 << 9)
144#define STS2_RSPTO (1 << 8)
145#define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
146 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
147#define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
148 STS2_DATBSYTO | STS2_CRCSTTO | \
149 STS2_AC12BSYTO | STS2_RSPBSYTO | \
150 STS2_AC12RSPTO | STS2_RSPTO)
151
fdc50a94
YG		 152#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
153#define CLKDEV_MMC_DATA 20000000 /* 20MHz */
154#define CLKDEV_INIT 400000 /* 400 KHz */
155
156struct sh_mmcif_host {
157 struct mmc_host *mmc;
158 struct mmc_data *data;
fdc50a94
YG		 159 struct platform_device *pd;
160 struct clk *hclk;
161 unsigned int clk;
162 int bus_width;
aa0787a9 163 bool sd_error;
fdc50a94
YG		 164 long timeout;
165 void __iomem *addr;
aa0787a9 166 struct completion intr_wait;
fdc50a94 167
a782d688
GL		 168 /* DMA support */
169 struct dma_chan *chan_rx;
170 struct dma_chan *chan_tx;
171 struct completion dma_complete;
172 unsigned int dma_sglen;
173};
fdc50a94
YG		 174
175static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
176 unsigned int reg, u32 val)
177{
487d9fc5 178 writel(val | readl(host->addr + reg), host->addr + reg);
fdc50a94
YG		 179}
180
181static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
182 unsigned int reg, u32 val)
183{
487d9fc5 184 writel(~val & readl(host->addr + reg), host->addr + reg);
fdc50a94
YG		 185}
186
a782d688
GL		 187static void mmcif_dma_complete(void *arg)
188{
189 struct sh_mmcif_host *host = arg;
190 dev_dbg(&host->pd->dev, "Command completed\n");
191
192 if (WARN(!host->data, "%s: NULL data in DMA completion!\n",
193 dev_name(&host->pd->dev)))
194 return;
195
196 if (host->data->flags & MMC_DATA_READ)
1ed828db 197 dma_unmap_sg(host->chan_rx->device->dev,
9dc3fb5e 198 host->data->sg, host->data->sg_len,
a782d688
GL		 199 DMA_FROM_DEVICE);
200 else
1ed828db 201 dma_unmap_sg(host->chan_tx->device->dev,
9dc3fb5e 202 host->data->sg, host->data->sg_len,
a782d688
GL		 203 DMA_TO_DEVICE);
204
205 complete(&host->dma_complete);
206}
207
208static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
209{
210 struct scatterlist *sg = host->data->sg;
211 struct dma_async_tx_descriptor *desc = NULL;
212 struct dma_chan *chan = host->chan_rx;
213 dma_cookie_t cookie = -EINVAL;
214 int ret;
215
1ed828db
LW		 216 ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
217 DMA_FROM_DEVICE);
a782d688
GL		 218 if (ret > 0) {
219 host->dma_sglen = ret;
220 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
221 DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
222 }
223
224 if (desc) {
225 desc->callback = mmcif_dma_complete;
226 desc->callback_param = host;
227 cookie = desc->tx_submit(desc);
228 if (cookie < 0) {
229 desc = NULL;
230 ret = cookie;
231 } else {
232 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
233 chan->device->device_issue_pending(chan);
234 }
235 }
236 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
237 __func__, host->data->sg_len, ret, cookie);
238
239 if (!desc) {
240 /* DMA failed, fall back to PIO */
241 if (ret >= 0)
242 ret = -EIO;
243 host->chan_rx = NULL;
244 host->dma_sglen = 0;
245 dma_release_channel(chan);
246 /* Free the Tx channel too */
247 chan = host->chan_tx;
248 if (chan) {
249 host->chan_tx = NULL;
250 dma_release_channel(chan);
251 }
252 dev_warn(&host->pd->dev,
253 "DMA failed: %d, falling back to PIO\n", ret);
254 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
255 }
256
257 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
258 desc, cookie, host->data->sg_len);
259}
260
261static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
262{
263 struct scatterlist *sg = host->data->sg;
264 struct dma_async_tx_descriptor *desc = NULL;
265 struct dma_chan *chan = host->chan_tx;
266 dma_cookie_t cookie = -EINVAL;
267 int ret;
268
1ed828db
LW		 269 ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
270 DMA_TO_DEVICE);
a782d688
GL		 271 if (ret > 0) {
272 host->dma_sglen = ret;
273 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
274 DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
275 }
276
277 if (desc) {
278 desc->callback = mmcif_dma_complete;
279 desc->callback_param = host;
280 cookie = desc->tx_submit(desc);
281 if (cookie < 0) {
282 desc = NULL;
283 ret = cookie;
284 } else {
285 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
286 chan->device->device_issue_pending(chan);
287 }
288 }
289 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
290 __func__, host->data->sg_len, ret, cookie);
291
292 if (!desc) {
293 /* DMA failed, fall back to PIO */
294 if (ret >= 0)
295 ret = -EIO;
296 host->chan_tx = NULL;
297 host->dma_sglen = 0;
298 dma_release_channel(chan);
299 /* Free the Rx channel too */
300 chan = host->chan_rx;
301 if (chan) {
302 host->chan_rx = NULL;
303 dma_release_channel(chan);
304 }
305 dev_warn(&host->pd->dev,
306 "DMA failed: %d, falling back to PIO\n", ret);
307 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
308 }
309
310 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
311 desc, cookie);
312}
313
314static bool sh_mmcif_filter(struct dma_chan *chan, void *arg)
315{
316 dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
317 chan->private = arg;
318 return true;
319}
320
321static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
322 struct sh_mmcif_plat_data *pdata)
323{
324 host->dma_sglen = 0;
325
326 /* We can only either use DMA for both Tx and Rx or not use it at all */
327 if (pdata->dma) {
328 dma_cap_mask_t mask;
329
330 dma_cap_zero(mask);
331 dma_cap_set(DMA_SLAVE, mask);
332
333 host->chan_tx = dma_request_channel(mask, sh_mmcif_filter,
334 &pdata->dma->chan_priv_tx);
335 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
336 host->chan_tx);
337
338 if (!host->chan_tx)
339 return;
340
341 host->chan_rx = dma_request_channel(mask, sh_mmcif_filter,
342 &pdata->dma->chan_priv_rx);
343 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
344 host->chan_rx);
345
346 if (!host->chan_rx) {
347 dma_release_channel(host->chan_tx);
348 host->chan_tx = NULL;
349 return;
350 }
351
352 init_completion(&host->dma_complete);
353 }
354}
355
356static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
357{
358 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
359 /* Descriptors are freed automatically */
360 if (host->chan_tx) {
361 struct dma_chan *chan = host->chan_tx;
362 host->chan_tx = NULL;
363 dma_release_channel(chan);
364 }
365 if (host->chan_rx) {
366 struct dma_chan *chan = host->chan_rx;
367 host->chan_rx = NULL;
368 dma_release_channel(chan);
369 }
370
371 host->dma_sglen = 0;
372}
fdc50a94
YG		 373
374static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
375{
376 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
377
378 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
379 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
380
381 if (!clk)
382 return;
383 if (p->sup_pclk && clk == host->clk)
384 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
385 else
386 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
387 (ilog2(__rounddown_pow_of_two(host->clk / clk)) << 16));
388
389 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
390}
391
392static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
393{
394 u32 tmp;
395
487d9fc5 396 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
fdc50a94 397
487d9fc5
MD		 398 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
399 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
fdc50a94
YG		 400 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
401 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
402 /* byte swap on */
403 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
404}
405
406static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
407{
408 u32 state1, state2;
409 int ret, timeout = 10000000;
410
aa0787a9 411 host->sd_error = false;
fdc50a94 412
487d9fc5
MD		 413 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
414 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
e47bf32a
GL		 415 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
416 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
fdc50a94
YG		 417
418 if (state1 & STS1_CMDSEQ) {
419 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
420 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
421 while (1) {
422 timeout--;
423 if (timeout < 0) {
e47bf32a
GL		 424 dev_err(&host->pd->dev,
425 "Forceed end of command sequence timeout err\n");
fdc50a94
YG		 426 return -EIO;
427 }
487d9fc5 428 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
fdc50a94
YG		 429 & STS1_CMDSEQ))
430 break;
431 mdelay(1);
432 }
433 sh_mmcif_sync_reset(host);
e47bf32a 434 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
fdc50a94
YG		 435 return -EIO;
436 }
437
438 if (state2 & STS2_CRC_ERR) {
e47bf32a 439 dev_dbg(&host->pd->dev, ": Happened CRC error\n");
fdc50a94
YG		 440 ret = -EIO;
441 } else if (state2 & STS2_TIMEOUT_ERR) {
e47bf32a 442 dev_dbg(&host->pd->dev, ": Happened Timeout error\n");
fdc50a94
YG		 443 ret = -ETIMEDOUT;
444 } else {
e47bf32a 445 dev_dbg(&host->pd->dev, ": Happened End/Index error\n");
fdc50a94
YG		 446 ret = -EIO;
447 }
448 return ret;
449}
450
451static int sh_mmcif_single_read(struct sh_mmcif_host *host,
452 struct mmc_request *mrq)
453{
454 struct mmc_data *data = mrq->data;
455 long time;
456 u32 blocksize, i, *p = sg_virt(data->sg);
457
fdc50a94
YG		 458 /* buf read enable */
459 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
aa0787a9
GL		 460 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
461 host->timeout);
462 if (time <= 0 || host->sd_error)
fdc50a94
YG		 463 return sh_mmcif_error_manage(host);
464
fdc50a94 465 blocksize = (BLOCK_SIZE_MASK &
487d9fc5 466 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
fdc50a94 467 for (i = 0; i < blocksize / 4; i++)
487d9fc5 468 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
fdc50a94
YG		 469
470 /* buffer read end */
471 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
aa0787a9
GL		 472 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
473 host->timeout);
474 if (time <= 0 || host->sd_error)
fdc50a94
YG		 475 return sh_mmcif_error_manage(host);
476
fdc50a94
YG		 477 return 0;
478}
479
480static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
481 struct mmc_request *mrq)
482{
483 struct mmc_data *data = mrq->data;
484 long time;
485 u32 blocksize, i, j, sec, *p;
486
487d9fc5
MD		 487 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
488 MMCIF_CE_BLOCK_SET);
fdc50a94
YG		 489 for (j = 0; j < data->sg_len; j++) {
490 p = sg_virt(data->sg);
fdc50a94
YG		 491 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
492 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
493 /* buf read enable */
aa0787a9
GL		 494 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
495 host->timeout);
fdc50a94 496
aa0787a9 497 if (time <= 0 || host->sd_error)
fdc50a94
YG		 498 return sh_mmcif_error_manage(host);
499
fdc50a94 500 for (i = 0; i < blocksize / 4; i++)
487d9fc5
MD		 501 *p++ = sh_mmcif_readl(host->addr,
502 MMCIF_CE_DATA);
fdc50a94
YG		 503 }
504 if (j < data->sg_len - 1)
505 data->sg++;
506 }
507 return 0;
508}
509
510static int sh_mmcif_single_write(struct sh_mmcif_host *host,
511 struct mmc_request *mrq)
512{
513 struct mmc_data *data = mrq->data;
514 long time;
515 u32 blocksize, i, *p = sg_virt(data->sg);
516
fdc50a94
YG		 517 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
518
519 /* buf write enable */
aa0787a9
GL		 520 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
521 host->timeout);
522 if (time <= 0 || host->sd_error)
fdc50a94
YG		 523 return sh_mmcif_error_manage(host);
524
fdc50a94 525 blocksize = (BLOCK_SIZE_MASK &
487d9fc5 526 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
fdc50a94 527 for (i = 0; i < blocksize / 4; i++)
487d9fc5 528 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
fdc50a94
YG		 529
530 /* buffer write end */
531 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
532
aa0787a9
GL		 533 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
534 host->timeout);
535 if (time <= 0 || host->sd_error)
fdc50a94
YG		 536 return sh_mmcif_error_manage(host);
537
fdc50a94
YG		 538 return 0;
539}
540
541static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
542 struct mmc_request *mrq)
543{
544 struct mmc_data *data = mrq->data;
545 long time;
546 u32 i, sec, j, blocksize, *p;
547
487d9fc5
MD		 548 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
549 MMCIF_CE_BLOCK_SET);
fdc50a94
YG		 550
551 for (j = 0; j < data->sg_len; j++) {
552 p = sg_virt(data->sg);
fdc50a94
YG		 553 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
554 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
555 /* buf write enable*/
aa0787a9
GL		 556 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
557 host->timeout);
fdc50a94 558
aa0787a9 559 if (time <= 0 || host->sd_error)
fdc50a94
YG		 560 return sh_mmcif_error_manage(host);
561
fdc50a94 562 for (i = 0; i < blocksize / 4; i++)
487d9fc5
MD		 563 sh_mmcif_writel(host->addr,
564 MMCIF_CE_DATA, *p++);
fdc50a94
YG		 565 }
566 if (j < data->sg_len - 1)
567 data->sg++;
568 }
569 return 0;
570}
571
572static void sh_mmcif_get_response(struct sh_mmcif_host *host,
573 struct mmc_command *cmd)
574{
575 if (cmd->flags & MMC_RSP_136) {
487d9fc5
MD		 576 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
577 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
578 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
579 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
fdc50a94 580 } else
487d9fc5 581 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
fdc50a94
YG		 582}
583
584static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
585 struct mmc_command *cmd)
586{
487d9fc5 587 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
fdc50a94
YG		 588}
589
590static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
591 struct mmc_request *mrq, struct mmc_command *cmd, u32 opc)
592{
593 u32 tmp = 0;
594
595 /* Response Type check */
596 switch (mmc_resp_type(cmd)) {
597 case MMC_RSP_NONE:
598 tmp |= CMD_SET_RTYP_NO;
599 break;
600 case MMC_RSP_R1:
601 case MMC_RSP_R1B:
602 case MMC_RSP_R3:
603 tmp |= CMD_SET_RTYP_6B;
604 break;
605 case MMC_RSP_R2:
606 tmp |= CMD_SET_RTYP_17B;
607 break;
608 default:
e47bf32a 609 dev_err(&host->pd->dev, "Unsupported response type.\n");
fdc50a94
YG		 610 break;
611 }
612 switch (opc) {
613 /* RBSY */
614 case MMC_SWITCH:
615 case MMC_STOP_TRANSMISSION:
616 case MMC_SET_WRITE_PROT:
617 case MMC_CLR_WRITE_PROT:
618 case MMC_ERASE:
619 case MMC_GEN_CMD:
620 tmp |= CMD_SET_RBSY;
621 break;
622 }
623 /* WDAT / DATW */
624 if (host->data) {
625 tmp |= CMD_SET_WDAT;
626 switch (host->bus_width) {
627 case MMC_BUS_WIDTH_1:
628 tmp |= CMD_SET_DATW_1;
629 break;
630 case MMC_BUS_WIDTH_4:
631 tmp |= CMD_SET_DATW_4;
632 break;
633 case MMC_BUS_WIDTH_8:
634 tmp |= CMD_SET_DATW_8;
635 break;
636 default:
e47bf32a 637 dev_err(&host->pd->dev, "Unsupported bus width.\n");
fdc50a94
YG		 638 break;
639 }
640 }
641 /* DWEN */
642 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
643 tmp |= CMD_SET_DWEN;
644 /* CMLTE/CMD12EN */
645 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
646 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
647 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
648 mrq->data->blocks << 16);
649 }
650 /* RIDXC[1:0] check bits */
651 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
652 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
653 tmp |= CMD_SET_RIDXC_BITS;
654 /* RCRC7C[1:0] check bits */
655 if (opc == MMC_SEND_OP_COND)
656 tmp |= CMD_SET_CRC7C_BITS;
657 /* RCRC7C[1:0] internal CRC7 */
658 if (opc == MMC_ALL_SEND_CID ||
659 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
660 tmp |= CMD_SET_CRC7C_INTERNAL;
661
662 return opc = ((opc << 24) | tmp);
663}
664
e47bf32a 665static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
fdc50a94
YG		 666 struct mmc_request *mrq, u32 opc)
667{
e47bf32a 668 int ret;
fdc50a94
YG		 669
670 switch (opc) {
671 case MMC_READ_MULTIPLE_BLOCK:
672 ret = sh_mmcif_multi_read(host, mrq);
673 break;
674 case MMC_WRITE_MULTIPLE_BLOCK:
675 ret = sh_mmcif_multi_write(host, mrq);
676 break;
677 case MMC_WRITE_BLOCK:
678 ret = sh_mmcif_single_write(host, mrq);
679 break;
680 case MMC_READ_SINGLE_BLOCK:
681 case MMC_SEND_EXT_CSD:
682 ret = sh_mmcif_single_read(host, mrq);
683 break;
684 default:
e47bf32a 685 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
fdc50a94
YG		 686 ret = -EINVAL;
687 break;
688 }
689 return ret;
690}
691
692static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
693 struct mmc_request *mrq, struct mmc_command *cmd)
694{
695 long time;
696 int ret = 0, mask = 0;
697 u32 opc = cmd->opcode;
698
fdc50a94
YG		 699 switch (opc) {
700 /* respons busy check */
701 case MMC_SWITCH:
702 case MMC_STOP_TRANSMISSION:
703 case MMC_SET_WRITE_PROT:
704 case MMC_CLR_WRITE_PROT:
705 case MMC_ERASE:
706 case MMC_GEN_CMD:
707 mask = MASK_MRBSYE;
708 break;
709 default:
710 mask = MASK_MCRSPE;
711 break;
712 }
713 mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
714 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
715 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
716 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
717
718 if (host->data) {
487d9fc5
MD		 719 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
720 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
721 mrq->data->blksz);
fdc50a94
YG		 722 }
723 opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
724
487d9fc5
MD		 725 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
726 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
fdc50a94 727 /* set arg */
487d9fc5 728 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
fdc50a94 729 /* set cmd */
487d9fc5 730 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
fdc50a94 731
aa0787a9
GL		 732 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
733 host->timeout);
734 if (time <= 0) {
fdc50a94
YG		 735 cmd->error = sh_mmcif_error_manage(host);
736 return;
737 }
738 if (host->sd_error) {
739 switch (cmd->opcode) {
740 case MMC_ALL_SEND_CID:
741 case MMC_SELECT_CARD:
742 case MMC_APP_CMD:
743 cmd->error = -ETIMEDOUT;
744 break;
745 default:
e47bf32a
GL		 746 dev_dbg(&host->pd->dev, "Cmd(d'%d) err\n",
747 cmd->opcode);
fdc50a94
YG		 748 cmd->error = sh_mmcif_error_manage(host);
749 break;
750 }
aa0787a9 751 host->sd_error = false;
fdc50a94
YG		 752 return;
753 }
754 if (!(cmd->flags & MMC_RSP_PRESENT)) {
e47bf32a 755 cmd->error = 0;
fdc50a94
YG		 756 return;
757 }
aa0787a9 758 sh_mmcif_get_response(host, cmd);
fdc50a94 759 if (host->data) {
a782d688
GL		 760 if (!host->dma_sglen) {
761 ret = sh_mmcif_data_trans(host, mrq, cmd->opcode);
762 } else {
763 long time =
764 wait_for_completion_interruptible_timeout(&host->dma_complete,
765 host->timeout);
766 if (!time)
767 ret = -ETIMEDOUT;
768 else if (time < 0)
769 ret = time;
770 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
771 BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
772 host->dma_sglen = 0;
773 }
fdc50a94
YG		 774 if (ret < 0)
775 mrq->data->bytes_xfered = 0;
776 else
777 mrq->data->bytes_xfered =
778 mrq->data->blocks * mrq->data->blksz;
779 }
780 cmd->error = ret;
781}
782
783static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
784 struct mmc_request *mrq, struct mmc_command *cmd)
785{
786 long time;
787
788 if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK)
789 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
790 else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
791 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
792 else {
e47bf32a 793 dev_err(&host->pd->dev, "unsupported stop cmd\n");
fdc50a94
YG		 794 cmd->error = sh_mmcif_error_manage(host);
795 return;
796 }
797
aa0787a9
GL		 798 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
799 host->timeout);
800 if (time <= 0 || host->sd_error) {
fdc50a94
YG		 801 cmd->error = sh_mmcif_error_manage(host);
802 return;
803 }
804 sh_mmcif_get_cmd12response(host, cmd);
fdc50a94
YG		 805 cmd->error = 0;
806}
807
808static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
809{
810 struct sh_mmcif_host *host = mmc_priv(mmc);
811
812 switch (mrq->cmd->opcode) {
813 /* MMCIF does not support SD/SDIO command */
814 case SD_IO_SEND_OP_COND:
815 case MMC_APP_CMD:
816 mrq->cmd->error = -ETIMEDOUT;
817 mmc_request_done(mmc, mrq);
818 return;
819 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
820 if (!mrq->data) {
821 /* send_if_cond cmd (not support) */
822 mrq->cmd->error = -ETIMEDOUT;
823 mmc_request_done(mmc, mrq);
824 return;
825 }
826 break;
827 default:
828 break;
829 }
830 host->data = mrq->data;
a782d688
GL		 831 if (mrq->data) {
832 if (mrq->data->flags & MMC_DATA_READ) {
833 if (host->chan_rx)
834 sh_mmcif_start_dma_rx(host);
835 } else {
836 if (host->chan_tx)
837 sh_mmcif_start_dma_tx(host);
838 }
839 }
fdc50a94
YG		 840 sh_mmcif_start_cmd(host, mrq, mrq->cmd);
841 host->data = NULL;
842
843 if (mrq->cmd->error != 0) {
844 mmc_request_done(mmc, mrq);
845 return;
846 }
847 if (mrq->stop)
848 sh_mmcif_stop_cmd(host, mrq, mrq->stop);
849 mmc_request_done(mmc, mrq);
850}
851
852static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
853{
854 struct sh_mmcif_host *host = mmc_priv(mmc);
855 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
856
857 if (ios->power_mode == MMC_POWER_OFF) {
858 /* clock stop */
859 sh_mmcif_clock_control(host, 0);
860 if (p->down_pwr)
861 p->down_pwr(host->pd);
862 return;
863 } else if (ios->power_mode == MMC_POWER_UP) {
864 if (p->set_pwr)
865 p->set_pwr(host->pd, ios->power_mode);
866 }
867
868 if (ios->clock)
869 sh_mmcif_clock_control(host, ios->clock);
870
871 host->bus_width = ios->bus_width;
872}
873
777271d0
AH		 874static int sh_mmcif_get_cd(struct mmc_host *mmc)
875{
876 struct sh_mmcif_host *host = mmc_priv(mmc);
877 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
878
879 if (!p->get_cd)
880 return -ENOSYS;
881 else
882 return p->get_cd(host->pd);
883}
884
fdc50a94
YG		 885static struct mmc_host_ops sh_mmcif_ops = {
886 .request = sh_mmcif_request,
887 .set_ios = sh_mmcif_set_ios,
777271d0 888 .get_cd = sh_mmcif_get_cd,
fdc50a94
YG		 889};
890
891static void sh_mmcif_detect(struct mmc_host *mmc)
892{
893 mmc_detect_change(mmc, 0);
894}
895
896static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
897{
898 struct sh_mmcif_host *host = dev_id;
aa0787a9 899 u32 state;
fdc50a94
YG		 900 int err = 0;
901
487d9fc5 902 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
fdc50a94
YG		 903
904 if (state & INT_RBSYE) {
487d9fc5
MD		 905 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
906 ~(INT_RBSYE | INT_CRSPE));
fdc50a94
YG		 907 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
908 } else if (state & INT_CRSPE) {
487d9fc5 909 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
fdc50a94
YG		 910 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
911 } else if (state & INT_BUFREN) {
487d9fc5 912 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
fdc50a94
YG		 913 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
914 } else if (state & INT_BUFWEN) {
487d9fc5 915 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
fdc50a94
YG		 916 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
917 } else if (state & INT_CMD12DRE) {
487d9fc5 918 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
fdc50a94
YG		 919 ~(INT_CMD12DRE | INT_CMD12RBE |
920 INT_CMD12CRE | INT_BUFRE));
921 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
922 } else if (state & INT_BUFRE) {
487d9fc5 923 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
fdc50a94
YG		 924 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
925 } else if (state & INT_DTRANE) {
487d9fc5 926 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
fdc50a94
YG		 927 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
928 } else if (state & INT_CMD12RBE) {
487d9fc5 929 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
fdc50a94
YG		 930 ~(INT_CMD12RBE | INT_CMD12CRE));
931 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
932 } else if (state & INT_ERR_STS) {
933 /* err interrupts */
487d9fc5 934 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
fdc50a94
YG		 935 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
936 err = 1;
937 } else {
e47bf32a 938 dev_dbg(&host->pd->dev, "Not support int\n");
487d9fc5 939 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
fdc50a94
YG		 940 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
941 err = 1;
942 }
943 if (err) {
aa0787a9 944 host->sd_error = true;
e47bf32a 945 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
fdc50a94 946 }
aa0787a9
GL		 947 if (state & ~(INT_CMD12RBE | INT_CMD12CRE))
948 complete(&host->intr_wait);
949 else
950 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
fdc50a94
YG		 951
952 return IRQ_HANDLED;
953}
954
955static int __devinit sh_mmcif_probe(struct platform_device *pdev)
956{
957 int ret = 0, irq[2];
958 struct mmc_host *mmc;
e47bf32a
GL		 959 struct sh_mmcif_host *host;
960 struct sh_mmcif_plat_data *pd;
fdc50a94
YG		 961 struct resource *res;
962 void __iomem *reg;
963 char clk_name[8];
964
965 irq[0] = platform_get_irq(pdev, 0);
966 irq[1] = platform_get_irq(pdev, 1);
967 if (irq[0] < 0 || irq[1] < 0) {
e47bf32a 968 dev_err(&pdev->dev, "Get irq error\n");
fdc50a94
YG		 969 return -ENXIO;
970 }
971 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
972 if (!res) {
973 dev_err(&pdev->dev, "platform_get_resource error.\n");
974 return -ENXIO;
975 }
976 reg = ioremap(res->start, resource_size(res));
977 if (!reg) {
978 dev_err(&pdev->dev, "ioremap error.\n");
979 return -ENOMEM;
980 }
e47bf32a 981 pd = pdev->dev.platform_data;
fdc50a94
YG		 982 if (!pd) {
983 dev_err(&pdev->dev, "sh_mmcif plat data error.\n");
984 ret = -ENXIO;
985 goto clean_up;
986 }
987 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
988 if (!mmc) {
989 ret = -ENOMEM;
990 goto clean_up;
991 }
992 host = mmc_priv(mmc);
993 host->mmc = mmc;
994 host->addr = reg;
995 host->timeout = 1000;
996
997 snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
998 host->hclk = clk_get(&pdev->dev, clk_name);
999 if (IS_ERR(host->hclk)) {
1000 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
1001 ret = PTR_ERR(host->hclk);
1002 goto clean_up1;
1003 }
1004 clk_enable(host->hclk);
1005 host->clk = clk_get_rate(host->hclk);
1006 host->pd = pdev;
1007
aa0787a9 1008 init_completion(&host->intr_wait);
fdc50a94
YG		 1009
1010 mmc->ops = &sh_mmcif_ops;
1011 mmc->f_max = host->clk;
1012 /* close to 400KHz */
1013 if (mmc->f_max < 51200000)
1014 mmc->f_min = mmc->f_max / 128;
1015 else if (mmc->f_max < 102400000)
1016 mmc->f_min = mmc->f_max / 256;
1017 else
1018 mmc->f_min = mmc->f_max / 512;
1019 if (pd->ocr)
1020 mmc->ocr_avail = pd->ocr;
1021 mmc->caps = MMC_CAP_MMC_HIGHSPEED;
1022 if (pd->caps)
1023 mmc->caps |= pd->caps;
a782d688 1024 mmc->max_segs = 32;
fdc50a94 1025 mmc->max_blk_size = 512;
a782d688
GL		 1026 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1027 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
fdc50a94
YG		 1028 mmc->max_seg_size = mmc->max_req_size;
1029
1030 sh_mmcif_sync_reset(host);
1031 platform_set_drvdata(pdev, host);
a782d688
GL		 1032
1033 /* See if we also get DMA */
1034 sh_mmcif_request_dma(host, pd);
1035
fdc50a94
YG		 1036 mmc_add_host(mmc);
1037
1038 ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host);
1039 if (ret) {
e47bf32a 1040 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
fdc50a94
YG		 1041 goto clean_up2;
1042 }
1043 ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host);
1044 if (ret) {
1045 free_irq(irq[0], host);
e47bf32a 1046 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
fdc50a94
YG		 1047 goto clean_up2;
1048 }
1049
487d9fc5 1050 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
fdc50a94
YG		 1051 sh_mmcif_detect(host->mmc);
1052
e47bf32a
GL		 1053 dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1054 dev_dbg(&pdev->dev, "chip ver H'%04x\n",
487d9fc5 1055 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
fdc50a94
YG		 1056 return ret;
1057
1058clean_up2:
1059 clk_disable(host->hclk);
1060clean_up1:
1061 mmc_free_host(mmc);
1062clean_up:
1063 if (reg)
1064 iounmap(reg);
1065 return ret;
1066}
1067
1068static int __devexit sh_mmcif_remove(struct platform_device *pdev)
1069{
1070 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1071 int irq[2];
1072
aa0787a9 1073 mmc_remove_host(host->mmc);
a782d688 1074 sh_mmcif_release_dma(host);
fdc50a94
YG		 1075
1076 if (host->addr)
1077 iounmap(host->addr);
1078
aa0787a9
GL		 1079 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1080
1081 irq[0] = platform_get_irq(pdev, 0);
1082 irq[1] = platform_get_irq(pdev, 1);
fdc50a94
YG		 1083
1084 free_irq(irq[0], host);
1085 free_irq(irq[1], host);
1086
aa0787a9
GL		 1087 platform_set_drvdata(pdev, NULL);
1088
fdc50a94
YG		 1089 clk_disable(host->hclk);
1090 mmc_free_host(host->mmc);
1091
1092 return 0;
1093}
1094
1095static struct platform_driver sh_mmcif_driver = {
1096 .probe = sh_mmcif_probe,
1097 .remove = sh_mmcif_remove,
1098 .driver = {
1099 .name = DRIVER_NAME,
1100 },
1101};
1102
1103static int __init sh_mmcif_init(void)
1104{
1105 return platform_driver_register(&sh_mmcif_driver);
1106}
1107
1108static void __exit sh_mmcif_exit(void)
1109{
1110 platform_driver_unregister(&sh_mmcif_driver);
1111}
1112
1113module_init(sh_mmcif_init);
1114module_exit(sh_mmcif_exit);
1115
1116
1117MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1118MODULE_LICENSE("GPL");
aa0787a9 1119MODULE_ALIAS("platform:" DRIVER_NAME);
fdc50a94 1120MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");
Linux 6.x block layer and io_uring tree(s)