Commit | Line | Data |
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fdc50a94 YG |
1 | /* |
2 | * MMCIF eMMC driver. | |
3 | * | |
4 | * Copyright (C) 2010 Renesas Solutions Corp. | |
5 | * Yusuke Goda <yusuke.goda.sx@renesas.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License. | |
10 | * | |
11 | * | |
12 | * TODO | |
13 | * 1. DMA | |
14 | * 2. Power management | |
15 | * 3. Handle MMC errors better | |
16 | * | |
17 | */ | |
18 | ||
f985da17 GL |
19 | /* |
20 | * The MMCIF driver is now processing MMC requests asynchronously, according | |
21 | * to the Linux MMC API requirement. | |
22 | * | |
23 | * The MMCIF driver processes MMC requests in up to 3 stages: command, optional | |
24 | * data, and optional stop. To achieve asynchronous processing each of these | |
25 | * stages is split into two halves: a top and a bottom half. The top half | |
26 | * initialises the hardware, installs a timeout handler to handle completion | |
27 | * timeouts, and returns. In case of the command stage this immediately returns | |
28 | * control to the caller, leaving all further processing to run asynchronously. | |
29 | * All further request processing is performed by the bottom halves. | |
30 | * | |
31 | * The bottom half further consists of a "hard" IRQ handler, an IRQ handler | |
32 | * thread, a DMA completion callback, if DMA is used, a timeout work, and | |
33 | * request- and stage-specific handler methods. | |
34 | * | |
35 | * Each bottom half run begins with either a hardware interrupt, a DMA callback | |
36 | * invocation, or a timeout work run. In case of an error or a successful | |
37 | * processing completion, the MMC core is informed and the request processing is | |
38 | * finished. In case processing has to continue, i.e., if data has to be read | |
39 | * from or written to the card, or if a stop command has to be sent, the next | |
40 | * top half is called, which performs the necessary hardware handling and | |
41 | * reschedules the timeout work. This returns the driver state machine into the | |
42 | * bottom half waiting state. | |
43 | */ | |
44 | ||
86df1745 | 45 | #include <linux/bitops.h> |
aa0787a9 GL |
46 | #include <linux/clk.h> |
47 | #include <linux/completion.h> | |
e47bf32a | 48 | #include <linux/delay.h> |
fdc50a94 | 49 | #include <linux/dma-mapping.h> |
a782d688 | 50 | #include <linux/dmaengine.h> |
fdc50a94 YG |
51 | #include <linux/mmc/card.h> |
52 | #include <linux/mmc/core.h> | |
e47bf32a | 53 | #include <linux/mmc/host.h> |
fdc50a94 YG |
54 | #include <linux/mmc/mmc.h> |
55 | #include <linux/mmc/sdio.h> | |
fdc50a94 | 56 | #include <linux/mmc/sh_mmcif.h> |
e480606a | 57 | #include <linux/mmc/slot-gpio.h> |
bf68a812 | 58 | #include <linux/mod_devicetable.h> |
8047310e | 59 | #include <linux/mutex.h> |
a782d688 | 60 | #include <linux/pagemap.h> |
e47bf32a | 61 | #include <linux/platform_device.h> |
efe6a8ad | 62 | #include <linux/pm_qos.h> |
faca6648 | 63 | #include <linux/pm_runtime.h> |
d00cadac | 64 | #include <linux/sh_dma.h> |
3b0beafc | 65 | #include <linux/spinlock.h> |
88b47679 | 66 | #include <linux/module.h> |
fdc50a94 YG |
67 | |
68 | #define DRIVER_NAME "sh_mmcif" | |
69 | #define DRIVER_VERSION "2010-04-28" | |
70 | ||
fdc50a94 YG |
71 | /* CE_CMD_SET */ |
72 | #define CMD_MASK 0x3f000000 | |
73 | #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) | |
74 | #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ | |
75 | #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ | |
76 | #define CMD_SET_RBSY (1 << 21) /* R1b */ | |
77 | #define CMD_SET_CCSEN (1 << 20) | |
78 | #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ | |
79 | #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ | |
80 | #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ | |
81 | #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ | |
82 | #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ | |
83 | #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ | |
84 | #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ | |
85 | #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ | |
86 | #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ | |
87 | #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ | |
88 | #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ | |
89 | #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ | |
90 | #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ | |
91 | #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ | |
92 | #define CMD_SET_CCSH (1 << 5) | |
555061f9 | 93 | #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ |
fdc50a94 YG |
94 | #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ |
95 | #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ | |
96 | #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ | |
97 | ||
98 | /* CE_CMD_CTRL */ | |
99 | #define CMD_CTRL_BREAK (1 << 0) | |
100 | ||
101 | /* CE_BLOCK_SET */ | |
102 | #define BLOCK_SIZE_MASK 0x0000ffff | |
103 | ||
fdc50a94 YG |
104 | /* CE_INT */ |
105 | #define INT_CCSDE (1 << 29) | |
106 | #define INT_CMD12DRE (1 << 26) | |
107 | #define INT_CMD12RBE (1 << 25) | |
108 | #define INT_CMD12CRE (1 << 24) | |
109 | #define INT_DTRANE (1 << 23) | |
110 | #define INT_BUFRE (1 << 22) | |
111 | #define INT_BUFWEN (1 << 21) | |
112 | #define INT_BUFREN (1 << 20) | |
113 | #define INT_CCSRCV (1 << 19) | |
114 | #define INT_RBSYE (1 << 17) | |
115 | #define INT_CRSPE (1 << 16) | |
116 | #define INT_CMDVIO (1 << 15) | |
117 | #define INT_BUFVIO (1 << 14) | |
118 | #define INT_WDATERR (1 << 11) | |
119 | #define INT_RDATERR (1 << 10) | |
120 | #define INT_RIDXERR (1 << 9) | |
121 | #define INT_RSPERR (1 << 8) | |
122 | #define INT_CCSTO (1 << 5) | |
123 | #define INT_CRCSTO (1 << 4) | |
124 | #define INT_WDATTO (1 << 3) | |
125 | #define INT_RDATTO (1 << 2) | |
126 | #define INT_RBSYTO (1 << 1) | |
127 | #define INT_RSPTO (1 << 0) | |
128 | #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ | |
129 | INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ | |
130 | INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ | |
131 | INT_RDATTO | INT_RBSYTO | INT_RSPTO) | |
132 | ||
8af50750 GL |
133 | #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ |
134 | INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ | |
135 | INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) | |
136 | ||
967bcb77 GL |
137 | #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) |
138 | ||
fdc50a94 YG |
139 | /* CE_INT_MASK */ |
140 | #define MASK_ALL 0x00000000 | |
141 | #define MASK_MCCSDE (1 << 29) | |
142 | #define MASK_MCMD12DRE (1 << 26) | |
143 | #define MASK_MCMD12RBE (1 << 25) | |
144 | #define MASK_MCMD12CRE (1 << 24) | |
145 | #define MASK_MDTRANE (1 << 23) | |
146 | #define MASK_MBUFRE (1 << 22) | |
147 | #define MASK_MBUFWEN (1 << 21) | |
148 | #define MASK_MBUFREN (1 << 20) | |
149 | #define MASK_MCCSRCV (1 << 19) | |
150 | #define MASK_MRBSYE (1 << 17) | |
151 | #define MASK_MCRSPE (1 << 16) | |
152 | #define MASK_MCMDVIO (1 << 15) | |
153 | #define MASK_MBUFVIO (1 << 14) | |
154 | #define MASK_MWDATERR (1 << 11) | |
155 | #define MASK_MRDATERR (1 << 10) | |
156 | #define MASK_MRIDXERR (1 << 9) | |
157 | #define MASK_MRSPERR (1 << 8) | |
158 | #define MASK_MCCSTO (1 << 5) | |
159 | #define MASK_MCRCSTO (1 << 4) | |
160 | #define MASK_MWDATTO (1 << 3) | |
161 | #define MASK_MRDATTO (1 << 2) | |
162 | #define MASK_MRBSYTO (1 << 1) | |
163 | #define MASK_MRSPTO (1 << 0) | |
164 | ||
ee4b8887 GL |
165 | #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ |
166 | MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ | |
967bcb77 | 167 | MASK_MCRCSTO | MASK_MWDATTO | \ |
ee4b8887 GL |
168 | MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) |
169 | ||
8af50750 GL |
170 | #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ |
171 | MASK_MBUFREN | MASK_MBUFWEN | \ | |
172 | MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ | |
173 | MASK_MCMD12RBE | MASK_MCMD12CRE) | |
174 | ||
fdc50a94 YG |
175 | /* CE_HOST_STS1 */ |
176 | #define STS1_CMDSEQ (1 << 31) | |
177 | ||
178 | /* CE_HOST_STS2 */ | |
179 | #define STS2_CRCSTE (1 << 31) | |
180 | #define STS2_CRC16E (1 << 30) | |
181 | #define STS2_AC12CRCE (1 << 29) | |
182 | #define STS2_RSPCRC7E (1 << 28) | |
183 | #define STS2_CRCSTEBE (1 << 27) | |
184 | #define STS2_RDATEBE (1 << 26) | |
185 | #define STS2_AC12REBE (1 << 25) | |
186 | #define STS2_RSPEBE (1 << 24) | |
187 | #define STS2_AC12IDXE (1 << 23) | |
188 | #define STS2_RSPIDXE (1 << 22) | |
189 | #define STS2_CCSTO (1 << 15) | |
190 | #define STS2_RDATTO (1 << 14) | |
191 | #define STS2_DATBSYTO (1 << 13) | |
192 | #define STS2_CRCSTTO (1 << 12) | |
193 | #define STS2_AC12BSYTO (1 << 11) | |
194 | #define STS2_RSPBSYTO (1 << 10) | |
195 | #define STS2_AC12RSPTO (1 << 9) | |
196 | #define STS2_RSPTO (1 << 8) | |
197 | #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ | |
198 | STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) | |
199 | #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ | |
200 | STS2_DATBSYTO | STS2_CRCSTTO | \ | |
201 | STS2_AC12BSYTO | STS2_RSPBSYTO | \ | |
202 | STS2_AC12RSPTO | STS2_RSPTO) | |
203 | ||
fdc50a94 YG |
204 | #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ |
205 | #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ | |
206 | #define CLKDEV_INIT 400000 /* 400 KHz */ | |
207 | ||
3b0beafc GL |
208 | enum mmcif_state { |
209 | STATE_IDLE, | |
210 | STATE_REQUEST, | |
211 | STATE_IOS, | |
8047310e | 212 | STATE_TIMEOUT, |
3b0beafc GL |
213 | }; |
214 | ||
f985da17 GL |
215 | enum mmcif_wait_for { |
216 | MMCIF_WAIT_FOR_REQUEST, | |
217 | MMCIF_WAIT_FOR_CMD, | |
218 | MMCIF_WAIT_FOR_MREAD, | |
219 | MMCIF_WAIT_FOR_MWRITE, | |
220 | MMCIF_WAIT_FOR_READ, | |
221 | MMCIF_WAIT_FOR_WRITE, | |
222 | MMCIF_WAIT_FOR_READ_END, | |
223 | MMCIF_WAIT_FOR_WRITE_END, | |
224 | MMCIF_WAIT_FOR_STOP, | |
225 | }; | |
226 | ||
fdc50a94 YG |
227 | struct sh_mmcif_host { |
228 | struct mmc_host *mmc; | |
f985da17 | 229 | struct mmc_request *mrq; |
fdc50a94 YG |
230 | struct platform_device *pd; |
231 | struct clk *hclk; | |
232 | unsigned int clk; | |
233 | int bus_width; | |
555061f9 | 234 | unsigned char timing; |
aa0787a9 | 235 | bool sd_error; |
f985da17 | 236 | bool dying; |
fdc50a94 YG |
237 | long timeout; |
238 | void __iomem *addr; | |
f985da17 | 239 | u32 *pio_ptr; |
ee4b8887 | 240 | spinlock_t lock; /* protect sh_mmcif_host::state */ |
3b0beafc | 241 | enum mmcif_state state; |
f985da17 GL |
242 | enum mmcif_wait_for wait_for; |
243 | struct delayed_work timeout_work; | |
244 | size_t blocksize; | |
245 | int sg_idx; | |
246 | int sg_blkidx; | |
faca6648 | 247 | bool power; |
c9b0cef2 | 248 | bool card_present; |
967bcb77 | 249 | bool ccs_enable; /* Command Completion Signal support */ |
6d6fd367 | 250 | bool clk_ctrl2_enable; |
8047310e | 251 | struct mutex thread_lock; |
fdc50a94 | 252 | |
a782d688 GL |
253 | /* DMA support */ |
254 | struct dma_chan *chan_rx; | |
255 | struct dma_chan *chan_tx; | |
256 | struct completion dma_complete; | |
f38f94c6 | 257 | bool dma_active; |
a782d688 | 258 | }; |
fdc50a94 | 259 | |
70830b41 KM |
260 | static const struct of_device_id mmcif_of_match[] = { |
261 | { .compatible = "renesas,sh-mmcif" }, | |
262 | { } | |
263 | }; | |
264 | MODULE_DEVICE_TABLE(of, mmcif_of_match); | |
265 | ||
fdc50a94 YG |
266 | static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, |
267 | unsigned int reg, u32 val) | |
268 | { | |
487d9fc5 | 269 | writel(val | readl(host->addr + reg), host->addr + reg); |
fdc50a94 YG |
270 | } |
271 | ||
272 | static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, | |
273 | unsigned int reg, u32 val) | |
274 | { | |
487d9fc5 | 275 | writel(~val & readl(host->addr + reg), host->addr + reg); |
fdc50a94 YG |
276 | } |
277 | ||
a782d688 GL |
278 | static void mmcif_dma_complete(void *arg) |
279 | { | |
280 | struct sh_mmcif_host *host = arg; | |
8047310e | 281 | struct mmc_request *mrq = host->mrq; |
69983404 | 282 | |
a782d688 GL |
283 | dev_dbg(&host->pd->dev, "Command completed\n"); |
284 | ||
8047310e | 285 | if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", |
a782d688 GL |
286 | dev_name(&host->pd->dev))) |
287 | return; | |
288 | ||
a782d688 GL |
289 | complete(&host->dma_complete); |
290 | } | |
291 | ||
292 | static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) | |
293 | { | |
69983404 GL |
294 | struct mmc_data *data = host->mrq->data; |
295 | struct scatterlist *sg = data->sg; | |
a782d688 GL |
296 | struct dma_async_tx_descriptor *desc = NULL; |
297 | struct dma_chan *chan = host->chan_rx; | |
298 | dma_cookie_t cookie = -EINVAL; | |
299 | int ret; | |
300 | ||
69983404 | 301 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, |
1ed828db | 302 | DMA_FROM_DEVICE); |
a782d688 | 303 | if (ret > 0) { |
f38f94c6 | 304 | host->dma_active = true; |
16052827 | 305 | desc = dmaengine_prep_slave_sg(chan, sg, ret, |
05f5799c | 306 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
a782d688 GL |
307 | } |
308 | ||
309 | if (desc) { | |
310 | desc->callback = mmcif_dma_complete; | |
311 | desc->callback_param = host; | |
a5ece7d2 LW |
312 | cookie = dmaengine_submit(desc); |
313 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); | |
314 | dma_async_issue_pending(chan); | |
a782d688 GL |
315 | } |
316 | dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", | |
69983404 | 317 | __func__, data->sg_len, ret, cookie); |
a782d688 GL |
318 | |
319 | if (!desc) { | |
320 | /* DMA failed, fall back to PIO */ | |
321 | if (ret >= 0) | |
322 | ret = -EIO; | |
323 | host->chan_rx = NULL; | |
f38f94c6 | 324 | host->dma_active = false; |
a782d688 GL |
325 | dma_release_channel(chan); |
326 | /* Free the Tx channel too */ | |
327 | chan = host->chan_tx; | |
328 | if (chan) { | |
329 | host->chan_tx = NULL; | |
330 | dma_release_channel(chan); | |
331 | } | |
332 | dev_warn(&host->pd->dev, | |
333 | "DMA failed: %d, falling back to PIO\n", ret); | |
334 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
335 | } | |
336 | ||
337 | dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, | |
69983404 | 338 | desc, cookie, data->sg_len); |
a782d688 GL |
339 | } |
340 | ||
341 | static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) | |
342 | { | |
69983404 GL |
343 | struct mmc_data *data = host->mrq->data; |
344 | struct scatterlist *sg = data->sg; | |
a782d688 GL |
345 | struct dma_async_tx_descriptor *desc = NULL; |
346 | struct dma_chan *chan = host->chan_tx; | |
347 | dma_cookie_t cookie = -EINVAL; | |
348 | int ret; | |
349 | ||
69983404 | 350 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, |
1ed828db | 351 | DMA_TO_DEVICE); |
a782d688 | 352 | if (ret > 0) { |
f38f94c6 | 353 | host->dma_active = true; |
16052827 | 354 | desc = dmaengine_prep_slave_sg(chan, sg, ret, |
05f5799c | 355 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
a782d688 GL |
356 | } |
357 | ||
358 | if (desc) { | |
359 | desc->callback = mmcif_dma_complete; | |
360 | desc->callback_param = host; | |
a5ece7d2 LW |
361 | cookie = dmaengine_submit(desc); |
362 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); | |
363 | dma_async_issue_pending(chan); | |
a782d688 GL |
364 | } |
365 | dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", | |
69983404 | 366 | __func__, data->sg_len, ret, cookie); |
a782d688 GL |
367 | |
368 | if (!desc) { | |
369 | /* DMA failed, fall back to PIO */ | |
370 | if (ret >= 0) | |
371 | ret = -EIO; | |
372 | host->chan_tx = NULL; | |
f38f94c6 | 373 | host->dma_active = false; |
a782d688 GL |
374 | dma_release_channel(chan); |
375 | /* Free the Rx channel too */ | |
376 | chan = host->chan_rx; | |
377 | if (chan) { | |
378 | host->chan_rx = NULL; | |
379 | dma_release_channel(chan); | |
380 | } | |
381 | dev_warn(&host->pd->dev, | |
382 | "DMA failed: %d, falling back to PIO\n", ret); | |
383 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
384 | } | |
385 | ||
386 | dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, | |
387 | desc, cookie); | |
388 | } | |
389 | ||
e5a233cb LP |
390 | static struct dma_chan * |
391 | sh_mmcif_request_dma_one(struct sh_mmcif_host *host, | |
392 | struct sh_mmcif_plat_data *pdata, | |
393 | enum dma_transfer_direction direction) | |
a782d688 | 394 | { |
d25006e7 | 395 | struct dma_slave_config cfg = { 0, }; |
e5a233cb | 396 | struct dma_chan *chan; |
5f48dd06 | 397 | void *slave_data = NULL; |
e5a233cb | 398 | struct resource *res; |
0e79f9ae GL |
399 | dma_cap_mask_t mask; |
400 | int ret; | |
a782d688 | 401 | |
e5a233cb LP |
402 | dma_cap_zero(mask); |
403 | dma_cap_set(DMA_SLAVE, mask); | |
404 | ||
405 | if (pdata) | |
5f48dd06 KM |
406 | slave_data = direction == DMA_MEM_TO_DEV ? |
407 | (void *)pdata->slave_id_tx : | |
408 | (void *)pdata->slave_id_rx; | |
e5a233cb LP |
409 | |
410 | chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, | |
5f48dd06 | 411 | slave_data, &host->pd->dev, |
e5a233cb LP |
412 | direction == DMA_MEM_TO_DEV ? "tx" : "rx"); |
413 | ||
414 | dev_dbg(&host->pd->dev, "%s: %s: got channel %p\n", __func__, | |
415 | direction == DMA_MEM_TO_DEV ? "TX" : "RX", chan); | |
416 | ||
417 | if (!chan) | |
418 | return NULL; | |
419 | ||
420 | res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); | |
421 | ||
e5a233cb | 422 | cfg.direction = direction; |
d25006e7 | 423 | |
e36152aa | 424 | if (direction == DMA_DEV_TO_MEM) { |
d25006e7 | 425 | cfg.src_addr = res->start + MMCIF_CE_DATA; |
e36152aa LP |
426 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
427 | } else { | |
d25006e7 | 428 | cfg.dst_addr = res->start + MMCIF_CE_DATA; |
e36152aa LP |
429 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
430 | } | |
d25006e7 | 431 | |
e5a233cb LP |
432 | ret = dmaengine_slave_config(chan, &cfg); |
433 | if (ret < 0) { | |
434 | dma_release_channel(chan); | |
435 | return NULL; | |
436 | } | |
437 | ||
438 | return chan; | |
439 | } | |
440 | ||
441 | static void sh_mmcif_request_dma(struct sh_mmcif_host *host, | |
442 | struct sh_mmcif_plat_data *pdata) | |
443 | { | |
f38f94c6 | 444 | host->dma_active = false; |
a782d688 | 445 | |
acd6d772 GL |
446 | if (pdata) { |
447 | if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) | |
448 | return; | |
449 | } else if (!host->pd->dev.of_node) { | |
0e79f9ae | 450 | return; |
acd6d772 | 451 | } |
a782d688 | 452 | |
0e79f9ae | 453 | /* We can only either use DMA for both Tx and Rx or not use it at all */ |
e5a233cb | 454 | host->chan_tx = sh_mmcif_request_dma_one(host, pdata, DMA_MEM_TO_DEV); |
0e79f9ae GL |
455 | if (!host->chan_tx) |
456 | return; | |
a782d688 | 457 | |
e5a233cb LP |
458 | host->chan_rx = sh_mmcif_request_dma_one(host, pdata, DMA_DEV_TO_MEM); |
459 | if (!host->chan_rx) { | |
460 | dma_release_channel(host->chan_tx); | |
461 | host->chan_tx = NULL; | |
462 | } | |
a782d688 GL |
463 | } |
464 | ||
465 | static void sh_mmcif_release_dma(struct sh_mmcif_host *host) | |
466 | { | |
467 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
468 | /* Descriptors are freed automatically */ | |
469 | if (host->chan_tx) { | |
470 | struct dma_chan *chan = host->chan_tx; | |
471 | host->chan_tx = NULL; | |
472 | dma_release_channel(chan); | |
473 | } | |
474 | if (host->chan_rx) { | |
475 | struct dma_chan *chan = host->chan_rx; | |
476 | host->chan_rx = NULL; | |
477 | dma_release_channel(chan); | |
478 | } | |
479 | ||
f38f94c6 | 480 | host->dma_active = false; |
a782d688 | 481 | } |
fdc50a94 YG |
482 | |
483 | static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) | |
484 | { | |
485 | struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; | |
bf68a812 | 486 | bool sup_pclk = p ? p->sup_pclk : false; |
fdc50a94 YG |
487 | |
488 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); | |
489 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); | |
490 | ||
491 | if (!clk) | |
492 | return; | |
bf68a812 | 493 | if (sup_pclk && clk == host->clk) |
fdc50a94 YG |
494 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); |
495 | else | |
496 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & | |
f9388257 SH |
497 | ((fls(DIV_ROUND_UP(host->clk, |
498 | clk) - 1) - 1) << 16)); | |
fdc50a94 YG |
499 | |
500 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); | |
501 | } | |
502 | ||
503 | static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) | |
504 | { | |
505 | u32 tmp; | |
506 | ||
487d9fc5 | 507 | tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); |
fdc50a94 | 508 | |
487d9fc5 MD |
509 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); |
510 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); | |
967bcb77 GL |
511 | if (host->ccs_enable) |
512 | tmp |= SCCSTO_29; | |
6d6fd367 GL |
513 | if (host->clk_ctrl2_enable) |
514 | sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); | |
fdc50a94 | 515 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | |
967bcb77 | 516 | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); |
fdc50a94 YG |
517 | /* byte swap on */ |
518 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); | |
519 | } | |
520 | ||
521 | static int sh_mmcif_error_manage(struct sh_mmcif_host *host) | |
522 | { | |
523 | u32 state1, state2; | |
ee4b8887 | 524 | int ret, timeout; |
fdc50a94 | 525 | |
aa0787a9 | 526 | host->sd_error = false; |
fdc50a94 | 527 | |
487d9fc5 MD |
528 | state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); |
529 | state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); | |
e47bf32a GL |
530 | dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); |
531 | dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); | |
fdc50a94 YG |
532 | |
533 | if (state1 & STS1_CMDSEQ) { | |
534 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); | |
535 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); | |
ee4b8887 | 536 | for (timeout = 10000000; timeout; timeout--) { |
487d9fc5 | 537 | if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) |
ee4b8887 | 538 | & STS1_CMDSEQ)) |
fdc50a94 YG |
539 | break; |
540 | mdelay(1); | |
541 | } | |
ee4b8887 GL |
542 | if (!timeout) { |
543 | dev_err(&host->pd->dev, | |
544 | "Forced end of command sequence timeout err\n"); | |
545 | return -EIO; | |
546 | } | |
fdc50a94 | 547 | sh_mmcif_sync_reset(host); |
e47bf32a | 548 | dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); |
fdc50a94 YG |
549 | return -EIO; |
550 | } | |
551 | ||
552 | if (state2 & STS2_CRC_ERR) { | |
e475b270 TK |
553 | dev_err(&host->pd->dev, " CRC error: state %u, wait %u\n", |
554 | host->state, host->wait_for); | |
fdc50a94 YG |
555 | ret = -EIO; |
556 | } else if (state2 & STS2_TIMEOUT_ERR) { | |
e475b270 TK |
557 | dev_err(&host->pd->dev, " Timeout: state %u, wait %u\n", |
558 | host->state, host->wait_for); | |
fdc50a94 YG |
559 | ret = -ETIMEDOUT; |
560 | } else { | |
e475b270 TK |
561 | dev_dbg(&host->pd->dev, " End/Index error: state %u, wait %u\n", |
562 | host->state, host->wait_for); | |
fdc50a94 YG |
563 | ret = -EIO; |
564 | } | |
565 | return ret; | |
566 | } | |
567 | ||
f985da17 | 568 | static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) |
fdc50a94 | 569 | { |
f985da17 GL |
570 | struct mmc_data *data = host->mrq->data; |
571 | ||
572 | host->sg_blkidx += host->blocksize; | |
573 | ||
574 | /* data->sg->length must be a multiple of host->blocksize? */ | |
575 | BUG_ON(host->sg_blkidx > data->sg->length); | |
576 | ||
577 | if (host->sg_blkidx == data->sg->length) { | |
578 | host->sg_blkidx = 0; | |
579 | if (++host->sg_idx < data->sg_len) | |
580 | host->pio_ptr = sg_virt(++data->sg); | |
581 | } else { | |
582 | host->pio_ptr = p; | |
583 | } | |
584 | ||
99eb9d8d | 585 | return host->sg_idx != data->sg_len; |
f985da17 GL |
586 | } |
587 | ||
588 | static void sh_mmcif_single_read(struct sh_mmcif_host *host, | |
589 | struct mmc_request *mrq) | |
590 | { | |
591 | host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & | |
592 | BLOCK_SIZE_MASK) + 3; | |
593 | ||
594 | host->wait_for = MMCIF_WAIT_FOR_READ; | |
fdc50a94 | 595 | |
fdc50a94 YG |
596 | /* buf read enable */ |
597 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); | |
f985da17 GL |
598 | } |
599 | ||
600 | static bool sh_mmcif_read_block(struct sh_mmcif_host *host) | |
601 | { | |
602 | struct mmc_data *data = host->mrq->data; | |
603 | u32 *p = sg_virt(data->sg); | |
604 | int i; | |
605 | ||
606 | if (host->sd_error) { | |
607 | data->error = sh_mmcif_error_manage(host); | |
e475b270 | 608 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); |
f985da17 GL |
609 | return false; |
610 | } | |
611 | ||
612 | for (i = 0; i < host->blocksize / 4; i++) | |
487d9fc5 | 613 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); |
fdc50a94 YG |
614 | |
615 | /* buffer read end */ | |
616 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); | |
f985da17 | 617 | host->wait_for = MMCIF_WAIT_FOR_READ_END; |
fdc50a94 | 618 | |
f985da17 | 619 | return true; |
fdc50a94 YG |
620 | } |
621 | ||
f985da17 GL |
622 | static void sh_mmcif_multi_read(struct sh_mmcif_host *host, |
623 | struct mmc_request *mrq) | |
fdc50a94 YG |
624 | { |
625 | struct mmc_data *data = mrq->data; | |
f985da17 GL |
626 | |
627 | if (!data->sg_len || !data->sg->length) | |
628 | return; | |
629 | ||
630 | host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & | |
631 | BLOCK_SIZE_MASK; | |
632 | ||
633 | host->wait_for = MMCIF_WAIT_FOR_MREAD; | |
634 | host->sg_idx = 0; | |
635 | host->sg_blkidx = 0; | |
636 | host->pio_ptr = sg_virt(data->sg); | |
5df460b1 | 637 | |
f985da17 GL |
638 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
639 | } | |
640 | ||
641 | static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) | |
642 | { | |
643 | struct mmc_data *data = host->mrq->data; | |
644 | u32 *p = host->pio_ptr; | |
645 | int i; | |
646 | ||
647 | if (host->sd_error) { | |
648 | data->error = sh_mmcif_error_manage(host); | |
e475b270 | 649 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); |
f985da17 | 650 | return false; |
fdc50a94 | 651 | } |
f985da17 GL |
652 | |
653 | BUG_ON(!data->sg->length); | |
654 | ||
655 | for (i = 0; i < host->blocksize / 4; i++) | |
656 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); | |
657 | ||
658 | if (!sh_mmcif_next_block(host, p)) | |
659 | return false; | |
660 | ||
f985da17 GL |
661 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
662 | ||
663 | return true; | |
fdc50a94 YG |
664 | } |
665 | ||
f985da17 | 666 | static void sh_mmcif_single_write(struct sh_mmcif_host *host, |
fdc50a94 YG |
667 | struct mmc_request *mrq) |
668 | { | |
f985da17 GL |
669 | host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
670 | BLOCK_SIZE_MASK) + 3; | |
fdc50a94 | 671 | |
f985da17 | 672 | host->wait_for = MMCIF_WAIT_FOR_WRITE; |
fdc50a94 YG |
673 | |
674 | /* buf write enable */ | |
f985da17 GL |
675 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
676 | } | |
677 | ||
678 | static bool sh_mmcif_write_block(struct sh_mmcif_host *host) | |
679 | { | |
680 | struct mmc_data *data = host->mrq->data; | |
681 | u32 *p = sg_virt(data->sg); | |
682 | int i; | |
683 | ||
684 | if (host->sd_error) { | |
685 | data->error = sh_mmcif_error_manage(host); | |
e475b270 | 686 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); |
f985da17 GL |
687 | return false; |
688 | } | |
689 | ||
690 | for (i = 0; i < host->blocksize / 4; i++) | |
487d9fc5 | 691 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); |
fdc50a94 YG |
692 | |
693 | /* buffer write end */ | |
694 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); | |
f985da17 | 695 | host->wait_for = MMCIF_WAIT_FOR_WRITE_END; |
fdc50a94 | 696 | |
f985da17 | 697 | return true; |
fdc50a94 YG |
698 | } |
699 | ||
f985da17 GL |
700 | static void sh_mmcif_multi_write(struct sh_mmcif_host *host, |
701 | struct mmc_request *mrq) | |
fdc50a94 YG |
702 | { |
703 | struct mmc_data *data = mrq->data; | |
fdc50a94 | 704 | |
f985da17 GL |
705 | if (!data->sg_len || !data->sg->length) |
706 | return; | |
fdc50a94 | 707 | |
f985da17 GL |
708 | host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
709 | BLOCK_SIZE_MASK; | |
fdc50a94 | 710 | |
f985da17 GL |
711 | host->wait_for = MMCIF_WAIT_FOR_MWRITE; |
712 | host->sg_idx = 0; | |
713 | host->sg_blkidx = 0; | |
714 | host->pio_ptr = sg_virt(data->sg); | |
5df460b1 | 715 | |
f985da17 GL |
716 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
717 | } | |
fdc50a94 | 718 | |
f985da17 GL |
719 | static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) |
720 | { | |
721 | struct mmc_data *data = host->mrq->data; | |
722 | u32 *p = host->pio_ptr; | |
723 | int i; | |
724 | ||
725 | if (host->sd_error) { | |
726 | data->error = sh_mmcif_error_manage(host); | |
e475b270 | 727 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); |
f985da17 | 728 | return false; |
fdc50a94 | 729 | } |
f985da17 GL |
730 | |
731 | BUG_ON(!data->sg->length); | |
732 | ||
733 | for (i = 0; i < host->blocksize / 4; i++) | |
734 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); | |
735 | ||
736 | if (!sh_mmcif_next_block(host, p)) | |
737 | return false; | |
738 | ||
f985da17 GL |
739 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
740 | ||
741 | return true; | |
fdc50a94 YG |
742 | } |
743 | ||
744 | static void sh_mmcif_get_response(struct sh_mmcif_host *host, | |
745 | struct mmc_command *cmd) | |
746 | { | |
747 | if (cmd->flags & MMC_RSP_136) { | |
487d9fc5 MD |
748 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); |
749 | cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); | |
750 | cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); | |
751 | cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); | |
fdc50a94 | 752 | } else |
487d9fc5 | 753 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); |
fdc50a94 YG |
754 | } |
755 | ||
756 | static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, | |
757 | struct mmc_command *cmd) | |
758 | { | |
487d9fc5 | 759 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); |
fdc50a94 YG |
760 | } |
761 | ||
762 | static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, | |
69983404 | 763 | struct mmc_request *mrq) |
fdc50a94 | 764 | { |
69983404 GL |
765 | struct mmc_data *data = mrq->data; |
766 | struct mmc_command *cmd = mrq->cmd; | |
767 | u32 opc = cmd->opcode; | |
fdc50a94 YG |
768 | u32 tmp = 0; |
769 | ||
770 | /* Response Type check */ | |
771 | switch (mmc_resp_type(cmd)) { | |
772 | case MMC_RSP_NONE: | |
773 | tmp |= CMD_SET_RTYP_NO; | |
774 | break; | |
775 | case MMC_RSP_R1: | |
776 | case MMC_RSP_R1B: | |
777 | case MMC_RSP_R3: | |
778 | tmp |= CMD_SET_RTYP_6B; | |
779 | break; | |
780 | case MMC_RSP_R2: | |
781 | tmp |= CMD_SET_RTYP_17B; | |
782 | break; | |
783 | default: | |
e47bf32a | 784 | dev_err(&host->pd->dev, "Unsupported response type.\n"); |
fdc50a94 YG |
785 | break; |
786 | } | |
787 | switch (opc) { | |
788 | /* RBSY */ | |
a812ba0f | 789 | case MMC_SLEEP_AWAKE: |
fdc50a94 YG |
790 | case MMC_SWITCH: |
791 | case MMC_STOP_TRANSMISSION: | |
792 | case MMC_SET_WRITE_PROT: | |
793 | case MMC_CLR_WRITE_PROT: | |
794 | case MMC_ERASE: | |
fdc50a94 YG |
795 | tmp |= CMD_SET_RBSY; |
796 | break; | |
797 | } | |
798 | /* WDAT / DATW */ | |
69983404 | 799 | if (data) { |
fdc50a94 YG |
800 | tmp |= CMD_SET_WDAT; |
801 | switch (host->bus_width) { | |
802 | case MMC_BUS_WIDTH_1: | |
803 | tmp |= CMD_SET_DATW_1; | |
804 | break; | |
805 | case MMC_BUS_WIDTH_4: | |
806 | tmp |= CMD_SET_DATW_4; | |
807 | break; | |
808 | case MMC_BUS_WIDTH_8: | |
809 | tmp |= CMD_SET_DATW_8; | |
810 | break; | |
811 | default: | |
e47bf32a | 812 | dev_err(&host->pd->dev, "Unsupported bus width.\n"); |
fdc50a94 YG |
813 | break; |
814 | } | |
555061f9 | 815 | switch (host->timing) { |
4039ff47 | 816 | case MMC_TIMING_MMC_DDR52: |
555061f9 TK |
817 | /* |
818 | * MMC core will only set this timing, if the host | |
4039ff47 SJ |
819 | * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR |
820 | * capability. MMCIF implementations with this | |
821 | * capability, e.g. sh73a0, will have to set it | |
822 | * in their platform data. | |
555061f9 TK |
823 | */ |
824 | tmp |= CMD_SET_DARS; | |
825 | break; | |
826 | } | |
fdc50a94 YG |
827 | } |
828 | /* DWEN */ | |
829 | if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) | |
830 | tmp |= CMD_SET_DWEN; | |
831 | /* CMLTE/CMD12EN */ | |
832 | if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { | |
833 | tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; | |
834 | sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, | |
69983404 | 835 | data->blocks << 16); |
fdc50a94 YG |
836 | } |
837 | /* RIDXC[1:0] check bits */ | |
838 | if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || | |
839 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
840 | tmp |= CMD_SET_RIDXC_BITS; | |
841 | /* RCRC7C[1:0] check bits */ | |
842 | if (opc == MMC_SEND_OP_COND) | |
843 | tmp |= CMD_SET_CRC7C_BITS; | |
844 | /* RCRC7C[1:0] internal CRC7 */ | |
845 | if (opc == MMC_ALL_SEND_CID || | |
846 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
847 | tmp |= CMD_SET_CRC7C_INTERNAL; | |
848 | ||
69983404 | 849 | return (opc << 24) | tmp; |
fdc50a94 YG |
850 | } |
851 | ||
e47bf32a | 852 | static int sh_mmcif_data_trans(struct sh_mmcif_host *host, |
f985da17 | 853 | struct mmc_request *mrq, u32 opc) |
fdc50a94 | 854 | { |
fdc50a94 YG |
855 | switch (opc) { |
856 | case MMC_READ_MULTIPLE_BLOCK: | |
f985da17 GL |
857 | sh_mmcif_multi_read(host, mrq); |
858 | return 0; | |
fdc50a94 | 859 | case MMC_WRITE_MULTIPLE_BLOCK: |
f985da17 GL |
860 | sh_mmcif_multi_write(host, mrq); |
861 | return 0; | |
fdc50a94 | 862 | case MMC_WRITE_BLOCK: |
f985da17 GL |
863 | sh_mmcif_single_write(host, mrq); |
864 | return 0; | |
fdc50a94 YG |
865 | case MMC_READ_SINGLE_BLOCK: |
866 | case MMC_SEND_EXT_CSD: | |
f985da17 GL |
867 | sh_mmcif_single_read(host, mrq); |
868 | return 0; | |
fdc50a94 | 869 | default: |
e475b270 | 870 | dev_err(&host->pd->dev, "Unsupported CMD%d\n", opc); |
ee4b8887 | 871 | return -EINVAL; |
fdc50a94 | 872 | } |
fdc50a94 YG |
873 | } |
874 | ||
875 | static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, | |
ee4b8887 | 876 | struct mmc_request *mrq) |
fdc50a94 | 877 | { |
ee4b8887 | 878 | struct mmc_command *cmd = mrq->cmd; |
f985da17 GL |
879 | u32 opc = cmd->opcode; |
880 | u32 mask; | |
dbb42d96 | 881 | unsigned long flags; |
fdc50a94 | 882 | |
fdc50a94 | 883 | switch (opc) { |
ee4b8887 | 884 | /* response busy check */ |
a812ba0f | 885 | case MMC_SLEEP_AWAKE: |
fdc50a94 YG |
886 | case MMC_SWITCH: |
887 | case MMC_STOP_TRANSMISSION: | |
888 | case MMC_SET_WRITE_PROT: | |
889 | case MMC_CLR_WRITE_PROT: | |
890 | case MMC_ERASE: | |
ee4b8887 | 891 | mask = MASK_START_CMD | MASK_MRBSYE; |
fdc50a94 YG |
892 | break; |
893 | default: | |
ee4b8887 | 894 | mask = MASK_START_CMD | MASK_MCRSPE; |
fdc50a94 YG |
895 | break; |
896 | } | |
fdc50a94 | 897 | |
967bcb77 GL |
898 | if (host->ccs_enable) |
899 | mask |= MASK_MCCSTO; | |
900 | ||
69983404 | 901 | if (mrq->data) { |
487d9fc5 MD |
902 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); |
903 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, | |
904 | mrq->data->blksz); | |
fdc50a94 | 905 | } |
69983404 | 906 | opc = sh_mmcif_set_cmd(host, mrq); |
fdc50a94 | 907 | |
967bcb77 GL |
908 | if (host->ccs_enable) |
909 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); | |
910 | else | |
911 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); | |
487d9fc5 | 912 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); |
fdc50a94 | 913 | /* set arg */ |
487d9fc5 | 914 | sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); |
fdc50a94 | 915 | /* set cmd */ |
dbb42d96 | 916 | spin_lock_irqsave(&host->lock, flags); |
487d9fc5 | 917 | sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); |
fdc50a94 | 918 | |
f985da17 GL |
919 | host->wait_for = MMCIF_WAIT_FOR_CMD; |
920 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
dbb42d96 | 921 | spin_unlock_irqrestore(&host->lock, flags); |
fdc50a94 YG |
922 | } |
923 | ||
924 | static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, | |
ee4b8887 | 925 | struct mmc_request *mrq) |
fdc50a94 | 926 | { |
69983404 GL |
927 | switch (mrq->cmd->opcode) { |
928 | case MMC_READ_MULTIPLE_BLOCK: | |
fdc50a94 | 929 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); |
69983404 GL |
930 | break; |
931 | case MMC_WRITE_MULTIPLE_BLOCK: | |
fdc50a94 | 932 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); |
69983404 GL |
933 | break; |
934 | default: | |
e47bf32a | 935 | dev_err(&host->pd->dev, "unsupported stop cmd\n"); |
69983404 | 936 | mrq->stop->error = sh_mmcif_error_manage(host); |
fdc50a94 YG |
937 | return; |
938 | } | |
939 | ||
f985da17 | 940 | host->wait_for = MMCIF_WAIT_FOR_STOP; |
fdc50a94 YG |
941 | } |
942 | ||
943 | static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
944 | { | |
945 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
3b0beafc GL |
946 | unsigned long flags; |
947 | ||
948 | spin_lock_irqsave(&host->lock, flags); | |
949 | if (host->state != STATE_IDLE) { | |
e475b270 | 950 | dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); |
3b0beafc GL |
951 | spin_unlock_irqrestore(&host->lock, flags); |
952 | mrq->cmd->error = -EAGAIN; | |
953 | mmc_request_done(mmc, mrq); | |
954 | return; | |
955 | } | |
956 | ||
957 | host->state = STATE_REQUEST; | |
958 | spin_unlock_irqrestore(&host->lock, flags); | |
fdc50a94 YG |
959 | |
960 | switch (mrq->cmd->opcode) { | |
961 | /* MMCIF does not support SD/SDIO command */ | |
7541ca98 LP |
962 | case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ |
963 | case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ | |
964 | if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) | |
965 | break; | |
fdc50a94 | 966 | case MMC_APP_CMD: |
92ff0c5b | 967 | case SD_IO_RW_DIRECT: |
3b0beafc | 968 | host->state = STATE_IDLE; |
fdc50a94 YG |
969 | mrq->cmd->error = -ETIMEDOUT; |
970 | mmc_request_done(mmc, mrq); | |
971 | return; | |
fdc50a94 YG |
972 | default: |
973 | break; | |
974 | } | |
f985da17 GL |
975 | |
976 | host->mrq = mrq; | |
fdc50a94 | 977 | |
f985da17 | 978 | sh_mmcif_start_cmd(host, mrq); |
fdc50a94 YG |
979 | } |
980 | ||
a6609267 GL |
981 | static int sh_mmcif_clk_update(struct sh_mmcif_host *host) |
982 | { | |
ac0a2e98 | 983 | int ret = clk_prepare_enable(host->hclk); |
a6609267 GL |
984 | |
985 | if (!ret) { | |
986 | host->clk = clk_get_rate(host->hclk); | |
987 | host->mmc->f_max = host->clk / 2; | |
988 | host->mmc->f_min = host->clk / 512; | |
989 | } | |
990 | ||
991 | return ret; | |
992 | } | |
993 | ||
7d17baa0 GL |
994 | static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) |
995 | { | |
7d17baa0 GL |
996 | struct mmc_host *mmc = host->mmc; |
997 | ||
7d17baa0 GL |
998 | if (!IS_ERR(mmc->supply.vmmc)) |
999 | /* Errors ignored... */ | |
1000 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, | |
1001 | ios->power_mode ? ios->vdd : 0); | |
1002 | } | |
1003 | ||
fdc50a94 YG |
1004 | static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
1005 | { | |
1006 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
3b0beafc GL |
1007 | unsigned long flags; |
1008 | ||
1009 | spin_lock_irqsave(&host->lock, flags); | |
1010 | if (host->state != STATE_IDLE) { | |
e475b270 | 1011 | dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); |
3b0beafc GL |
1012 | spin_unlock_irqrestore(&host->lock, flags); |
1013 | return; | |
1014 | } | |
1015 | ||
1016 | host->state = STATE_IOS; | |
1017 | spin_unlock_irqrestore(&host->lock, flags); | |
fdc50a94 | 1018 | |
f5e0cec4 | 1019 | if (ios->power_mode == MMC_POWER_UP) { |
c9b0cef2 | 1020 | if (!host->card_present) { |
faca6648 GL |
1021 | /* See if we also get DMA */ |
1022 | sh_mmcif_request_dma(host, host->pd->dev.platform_data); | |
c9b0cef2 | 1023 | host->card_present = true; |
faca6648 | 1024 | } |
7d17baa0 | 1025 | sh_mmcif_set_power(host, ios); |
f5e0cec4 | 1026 | } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { |
fdc50a94 YG |
1027 | /* clock stop */ |
1028 | sh_mmcif_clock_control(host, 0); | |
faca6648 | 1029 | if (ios->power_mode == MMC_POWER_OFF) { |
c9b0cef2 | 1030 | if (host->card_present) { |
faca6648 | 1031 | sh_mmcif_release_dma(host); |
c9b0cef2 | 1032 | host->card_present = false; |
faca6648 | 1033 | } |
c9b0cef2 GL |
1034 | } |
1035 | if (host->power) { | |
f8a8ced7 | 1036 | pm_runtime_put_sync(&host->pd->dev); |
ac0a2e98 | 1037 | clk_disable_unprepare(host->hclk); |
c9b0cef2 | 1038 | host->power = false; |
7d17baa0 GL |
1039 | if (ios->power_mode == MMC_POWER_OFF) |
1040 | sh_mmcif_set_power(host, ios); | |
faca6648 | 1041 | } |
3b0beafc | 1042 | host->state = STATE_IDLE; |
fdc50a94 | 1043 | return; |
fdc50a94 YG |
1044 | } |
1045 | ||
c9b0cef2 GL |
1046 | if (ios->clock) { |
1047 | if (!host->power) { | |
a6609267 | 1048 | sh_mmcif_clk_update(host); |
c9b0cef2 GL |
1049 | pm_runtime_get_sync(&host->pd->dev); |
1050 | host->power = true; | |
1051 | sh_mmcif_sync_reset(host); | |
1052 | } | |
fdc50a94 | 1053 | sh_mmcif_clock_control(host, ios->clock); |
c9b0cef2 | 1054 | } |
fdc50a94 | 1055 | |
555061f9 | 1056 | host->timing = ios->timing; |
fdc50a94 | 1057 | host->bus_width = ios->bus_width; |
3b0beafc | 1058 | host->state = STATE_IDLE; |
fdc50a94 YG |
1059 | } |
1060 | ||
777271d0 AH |
1061 | static int sh_mmcif_get_cd(struct mmc_host *mmc) |
1062 | { | |
1063 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
1064 | struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; | |
e480606a GL |
1065 | int ret = mmc_gpio_get_cd(mmc); |
1066 | ||
1067 | if (ret >= 0) | |
1068 | return ret; | |
777271d0 | 1069 | |
bf68a812 | 1070 | if (!p || !p->get_cd) |
777271d0 AH |
1071 | return -ENOSYS; |
1072 | else | |
1073 | return p->get_cd(host->pd); | |
1074 | } | |
1075 | ||
fdc50a94 YG |
1076 | static struct mmc_host_ops sh_mmcif_ops = { |
1077 | .request = sh_mmcif_request, | |
1078 | .set_ios = sh_mmcif_set_ios, | |
777271d0 | 1079 | .get_cd = sh_mmcif_get_cd, |
fdc50a94 YG |
1080 | }; |
1081 | ||
f985da17 GL |
1082 | static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) |
1083 | { | |
1084 | struct mmc_command *cmd = host->mrq->cmd; | |
69983404 | 1085 | struct mmc_data *data = host->mrq->data; |
f985da17 GL |
1086 | long time; |
1087 | ||
1088 | if (host->sd_error) { | |
1089 | switch (cmd->opcode) { | |
1090 | case MMC_ALL_SEND_CID: | |
1091 | case MMC_SELECT_CARD: | |
1092 | case MMC_APP_CMD: | |
1093 | cmd->error = -ETIMEDOUT; | |
f985da17 GL |
1094 | break; |
1095 | default: | |
1096 | cmd->error = sh_mmcif_error_manage(host); | |
f985da17 GL |
1097 | break; |
1098 | } | |
e475b270 TK |
1099 | dev_dbg(&host->pd->dev, "CMD%d error %d\n", |
1100 | cmd->opcode, cmd->error); | |
aba9d646 | 1101 | host->sd_error = false; |
f985da17 GL |
1102 | return false; |
1103 | } | |
1104 | if (!(cmd->flags & MMC_RSP_PRESENT)) { | |
1105 | cmd->error = 0; | |
1106 | return false; | |
1107 | } | |
1108 | ||
1109 | sh_mmcif_get_response(host, cmd); | |
1110 | ||
69983404 | 1111 | if (!data) |
f985da17 GL |
1112 | return false; |
1113 | ||
90f1cb43 GL |
1114 | /* |
1115 | * Completion can be signalled from DMA callback and error, so, have to | |
1116 | * reset here, before setting .dma_active | |
1117 | */ | |
1118 | init_completion(&host->dma_complete); | |
1119 | ||
69983404 | 1120 | if (data->flags & MMC_DATA_READ) { |
f985da17 GL |
1121 | if (host->chan_rx) |
1122 | sh_mmcif_start_dma_rx(host); | |
1123 | } else { | |
1124 | if (host->chan_tx) | |
1125 | sh_mmcif_start_dma_tx(host); | |
1126 | } | |
1127 | ||
1128 | if (!host->dma_active) { | |
69983404 | 1129 | data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); |
99eb9d8d | 1130 | return !data->error; |
f985da17 GL |
1131 | } |
1132 | ||
1133 | /* Running in the IRQ thread, can sleep */ | |
1134 | time = wait_for_completion_interruptible_timeout(&host->dma_complete, | |
1135 | host->timeout); | |
eae30983 TK |
1136 | |
1137 | if (data->flags & MMC_DATA_READ) | |
1138 | dma_unmap_sg(host->chan_rx->device->dev, | |
1139 | data->sg, data->sg_len, | |
1140 | DMA_FROM_DEVICE); | |
1141 | else | |
1142 | dma_unmap_sg(host->chan_tx->device->dev, | |
1143 | data->sg, data->sg_len, | |
1144 | DMA_TO_DEVICE); | |
1145 | ||
f985da17 GL |
1146 | if (host->sd_error) { |
1147 | dev_err(host->mmc->parent, | |
1148 | "Error IRQ while waiting for DMA completion!\n"); | |
1149 | /* Woken up by an error IRQ: abort DMA */ | |
69983404 | 1150 | data->error = sh_mmcif_error_manage(host); |
f985da17 | 1151 | } else if (!time) { |
e475b270 | 1152 | dev_err(host->mmc->parent, "DMA timeout!\n"); |
69983404 | 1153 | data->error = -ETIMEDOUT; |
f985da17 | 1154 | } else if (time < 0) { |
e475b270 TK |
1155 | dev_err(host->mmc->parent, |
1156 | "wait_for_completion_...() error %ld!\n", time); | |
69983404 | 1157 | data->error = time; |
f985da17 GL |
1158 | } |
1159 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, | |
1160 | BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
1161 | host->dma_active = false; | |
1162 | ||
eae30983 | 1163 | if (data->error) { |
69983404 | 1164 | data->bytes_xfered = 0; |
eae30983 TK |
1165 | /* Abort DMA */ |
1166 | if (data->flags & MMC_DATA_READ) | |
1167 | dmaengine_terminate_all(host->chan_rx); | |
1168 | else | |
1169 | dmaengine_terminate_all(host->chan_tx); | |
1170 | } | |
f985da17 GL |
1171 | |
1172 | return false; | |
1173 | } | |
1174 | ||
1175 | static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) | |
1176 | { | |
1177 | struct sh_mmcif_host *host = dev_id; | |
8047310e | 1178 | struct mmc_request *mrq; |
5df460b1 | 1179 | bool wait = false; |
dbb42d96 KT |
1180 | unsigned long flags; |
1181 | int wait_work; | |
1182 | ||
1183 | spin_lock_irqsave(&host->lock, flags); | |
1184 | wait_work = host->wait_for; | |
1185 | spin_unlock_irqrestore(&host->lock, flags); | |
f985da17 GL |
1186 | |
1187 | cancel_delayed_work_sync(&host->timeout_work); | |
1188 | ||
8047310e GL |
1189 | mutex_lock(&host->thread_lock); |
1190 | ||
1191 | mrq = host->mrq; | |
1192 | if (!mrq) { | |
1193 | dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n", | |
1194 | host->state, host->wait_for); | |
1195 | mutex_unlock(&host->thread_lock); | |
1196 | return IRQ_HANDLED; | |
1197 | } | |
1198 | ||
f985da17 GL |
1199 | /* |
1200 | * All handlers return true, if processing continues, and false, if the | |
1201 | * request has to be completed - successfully or not | |
1202 | */ | |
dbb42d96 | 1203 | switch (wait_work) { |
f985da17 GL |
1204 | case MMCIF_WAIT_FOR_REQUEST: |
1205 | /* We're too late, the timeout has already kicked in */ | |
8047310e | 1206 | mutex_unlock(&host->thread_lock); |
f985da17 GL |
1207 | return IRQ_HANDLED; |
1208 | case MMCIF_WAIT_FOR_CMD: | |
5df460b1 GL |
1209 | /* Wait for data? */ |
1210 | wait = sh_mmcif_end_cmd(host); | |
f985da17 GL |
1211 | break; |
1212 | case MMCIF_WAIT_FOR_MREAD: | |
5df460b1 GL |
1213 | /* Wait for more data? */ |
1214 | wait = sh_mmcif_mread_block(host); | |
f985da17 GL |
1215 | break; |
1216 | case MMCIF_WAIT_FOR_READ: | |
5df460b1 GL |
1217 | /* Wait for data end? */ |
1218 | wait = sh_mmcif_read_block(host); | |
f985da17 GL |
1219 | break; |
1220 | case MMCIF_WAIT_FOR_MWRITE: | |
5df460b1 GL |
1221 | /* Wait data to write? */ |
1222 | wait = sh_mmcif_mwrite_block(host); | |
f985da17 GL |
1223 | break; |
1224 | case MMCIF_WAIT_FOR_WRITE: | |
5df460b1 GL |
1225 | /* Wait for data end? */ |
1226 | wait = sh_mmcif_write_block(host); | |
f985da17 GL |
1227 | break; |
1228 | case MMCIF_WAIT_FOR_STOP: | |
1229 | if (host->sd_error) { | |
1230 | mrq->stop->error = sh_mmcif_error_manage(host); | |
e475b270 | 1231 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->stop->error); |
f985da17 GL |
1232 | break; |
1233 | } | |
1234 | sh_mmcif_get_cmd12response(host, mrq->stop); | |
1235 | mrq->stop->error = 0; | |
1236 | break; | |
1237 | case MMCIF_WAIT_FOR_READ_END: | |
1238 | case MMCIF_WAIT_FOR_WRITE_END: | |
e475b270 | 1239 | if (host->sd_error) { |
91ab252a | 1240 | mrq->data->error = sh_mmcif_error_manage(host); |
e475b270 TK |
1241 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->data->error); |
1242 | } | |
f985da17 GL |
1243 | break; |
1244 | default: | |
1245 | BUG(); | |
1246 | } | |
1247 | ||
5df460b1 GL |
1248 | if (wait) { |
1249 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
1250 | /* Wait for more data */ | |
8047310e | 1251 | mutex_unlock(&host->thread_lock); |
5df460b1 GL |
1252 | return IRQ_HANDLED; |
1253 | } | |
1254 | ||
f985da17 | 1255 | if (host->wait_for != MMCIF_WAIT_FOR_STOP) { |
91ab252a | 1256 | struct mmc_data *data = mrq->data; |
69983404 GL |
1257 | if (!mrq->cmd->error && data && !data->error) |
1258 | data->bytes_xfered = | |
1259 | data->blocks * data->blksz; | |
f985da17 | 1260 | |
69983404 | 1261 | if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { |
f985da17 | 1262 | sh_mmcif_stop_cmd(host, mrq); |
5df460b1 GL |
1263 | if (!mrq->stop->error) { |
1264 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
8047310e | 1265 | mutex_unlock(&host->thread_lock); |
f985da17 | 1266 | return IRQ_HANDLED; |
5df460b1 | 1267 | } |
f985da17 GL |
1268 | } |
1269 | } | |
1270 | ||
1271 | host->wait_for = MMCIF_WAIT_FOR_REQUEST; | |
1272 | host->state = STATE_IDLE; | |
69983404 | 1273 | host->mrq = NULL; |
f985da17 GL |
1274 | mmc_request_done(host->mmc, mrq); |
1275 | ||
8047310e GL |
1276 | mutex_unlock(&host->thread_lock); |
1277 | ||
f985da17 GL |
1278 | return IRQ_HANDLED; |
1279 | } | |
1280 | ||
fdc50a94 YG |
1281 | static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) |
1282 | { | |
1283 | struct sh_mmcif_host *host = dev_id; | |
967bcb77 | 1284 | u32 state, mask; |
fdc50a94 | 1285 | |
487d9fc5 | 1286 | state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); |
967bcb77 GL |
1287 | mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); |
1288 | if (host->ccs_enable) | |
1289 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); | |
1290 | else | |
1291 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); | |
8af50750 | 1292 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); |
fdc50a94 | 1293 | |
8af50750 GL |
1294 | if (state & ~MASK_CLEAN) |
1295 | dev_dbg(&host->pd->dev, "IRQ state = 0x%08x incompletely cleared\n", | |
1296 | state); | |
1297 | ||
1298 | if (state & INT_ERR_STS || state & ~INT_ALL) { | |
aa0787a9 | 1299 | host->sd_error = true; |
8af50750 | 1300 | dev_dbg(&host->pd->dev, "int err state = 0x%08x\n", state); |
fdc50a94 | 1301 | } |
f985da17 | 1302 | if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { |
8af50750 GL |
1303 | if (!host->mrq) |
1304 | dev_dbg(&host->pd->dev, "NULL IRQ state = 0x%08x\n", state); | |
f985da17 GL |
1305 | if (!host->dma_active) |
1306 | return IRQ_WAKE_THREAD; | |
1307 | else if (host->sd_error) | |
1308 | mmcif_dma_complete(host); | |
1309 | } else { | |
aa0787a9 | 1310 | dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); |
f985da17 | 1311 | } |
fdc50a94 YG |
1312 | |
1313 | return IRQ_HANDLED; | |
1314 | } | |
1315 | ||
f985da17 GL |
1316 | static void mmcif_timeout_work(struct work_struct *work) |
1317 | { | |
1318 | struct delayed_work *d = container_of(work, struct delayed_work, work); | |
1319 | struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); | |
1320 | struct mmc_request *mrq = host->mrq; | |
8047310e | 1321 | unsigned long flags; |
f985da17 GL |
1322 | |
1323 | if (host->dying) | |
1324 | /* Don't run after mmc_remove_host() */ | |
1325 | return; | |
1326 | ||
8047310e GL |
1327 | spin_lock_irqsave(&host->lock, flags); |
1328 | if (host->state == STATE_IDLE) { | |
1329 | spin_unlock_irqrestore(&host->lock, flags); | |
1330 | return; | |
1331 | } | |
1332 | ||
4cbd5224 KT |
1333 | dev_err(&host->pd->dev, "Timeout waiting for %u on CMD%u\n", |
1334 | host->wait_for, mrq->cmd->opcode); | |
1335 | ||
8047310e GL |
1336 | host->state = STATE_TIMEOUT; |
1337 | spin_unlock_irqrestore(&host->lock, flags); | |
1338 | ||
f985da17 GL |
1339 | /* |
1340 | * Handle races with cancel_delayed_work(), unless | |
1341 | * cancel_delayed_work_sync() is used | |
1342 | */ | |
1343 | switch (host->wait_for) { | |
1344 | case MMCIF_WAIT_FOR_CMD: | |
1345 | mrq->cmd->error = sh_mmcif_error_manage(host); | |
1346 | break; | |
1347 | case MMCIF_WAIT_FOR_STOP: | |
1348 | mrq->stop->error = sh_mmcif_error_manage(host); | |
1349 | break; | |
1350 | case MMCIF_WAIT_FOR_MREAD: | |
1351 | case MMCIF_WAIT_FOR_MWRITE: | |
1352 | case MMCIF_WAIT_FOR_READ: | |
1353 | case MMCIF_WAIT_FOR_WRITE: | |
1354 | case MMCIF_WAIT_FOR_READ_END: | |
1355 | case MMCIF_WAIT_FOR_WRITE_END: | |
69983404 | 1356 | mrq->data->error = sh_mmcif_error_manage(host); |
f985da17 GL |
1357 | break; |
1358 | default: | |
1359 | BUG(); | |
1360 | } | |
1361 | ||
1362 | host->state = STATE_IDLE; | |
1363 | host->wait_for = MMCIF_WAIT_FOR_REQUEST; | |
f985da17 GL |
1364 | host->mrq = NULL; |
1365 | mmc_request_done(host->mmc, mrq); | |
1366 | } | |
1367 | ||
7d17baa0 GL |
1368 | static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) |
1369 | { | |
1370 | struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; | |
1371 | struct mmc_host *mmc = host->mmc; | |
1372 | ||
1373 | mmc_regulator_get_supply(mmc); | |
1374 | ||
bf68a812 GL |
1375 | if (!pd) |
1376 | return; | |
1377 | ||
7d17baa0 GL |
1378 | if (!mmc->ocr_avail) |
1379 | mmc->ocr_avail = pd->ocr; | |
1380 | else if (pd->ocr) | |
1381 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); | |
1382 | } | |
1383 | ||
c3be1efd | 1384 | static int sh_mmcif_probe(struct platform_device *pdev) |
fdc50a94 YG |
1385 | { |
1386 | int ret = 0, irq[2]; | |
1387 | struct mmc_host *mmc; | |
e47bf32a | 1388 | struct sh_mmcif_host *host; |
e1aae2eb | 1389 | struct sh_mmcif_plat_data *pd = pdev->dev.platform_data; |
fdc50a94 YG |
1390 | struct resource *res; |
1391 | void __iomem *reg; | |
2cd5b3e0 | 1392 | const char *name; |
fdc50a94 YG |
1393 | |
1394 | irq[0] = platform_get_irq(pdev, 0); | |
1395 | irq[1] = platform_get_irq(pdev, 1); | |
2cd5b3e0 | 1396 | if (irq[0] < 0) { |
e47bf32a | 1397 | dev_err(&pdev->dev, "Get irq error\n"); |
fdc50a94 YG |
1398 | return -ENXIO; |
1399 | } | |
18f55fcc | 1400 | |
fdc50a94 | 1401 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
18f55fcc BD |
1402 | reg = devm_ioremap_resource(&pdev->dev, res); |
1403 | if (IS_ERR(reg)) | |
1404 | return PTR_ERR(reg); | |
e1aae2eb | 1405 | |
fdc50a94 | 1406 | mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); |
18f55fcc BD |
1407 | if (!mmc) |
1408 | return -ENOMEM; | |
2c9054dc SB |
1409 | |
1410 | ret = mmc_of_parse(mmc); | |
1411 | if (ret < 0) | |
46991005 | 1412 | goto err_host; |
2c9054dc | 1413 | |
fdc50a94 YG |
1414 | host = mmc_priv(mmc); |
1415 | host->mmc = mmc; | |
1416 | host->addr = reg; | |
bad4371d | 1417 | host->timeout = msecs_to_jiffies(10000); |
967bcb77 | 1418 | host->ccs_enable = !pd || !pd->ccs_unsupported; |
6d6fd367 | 1419 | host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; |
fdc50a94 | 1420 | |
fdc50a94 YG |
1421 | host->pd = pdev; |
1422 | ||
3b0beafc | 1423 | spin_lock_init(&host->lock); |
fdc50a94 YG |
1424 | |
1425 | mmc->ops = &sh_mmcif_ops; | |
7d17baa0 GL |
1426 | sh_mmcif_init_ocr(host); |
1427 | ||
eca889f6 | 1428 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; |
bf68a812 | 1429 | if (pd && pd->caps) |
fdc50a94 | 1430 | mmc->caps |= pd->caps; |
a782d688 | 1431 | mmc->max_segs = 32; |
fdc50a94 | 1432 | mmc->max_blk_size = 512; |
a782d688 GL |
1433 | mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; |
1434 | mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; | |
fdc50a94 YG |
1435 | mmc->max_seg_size = mmc->max_req_size; |
1436 | ||
fdc50a94 | 1437 | platform_set_drvdata(pdev, host); |
a782d688 | 1438 | |
faca6648 GL |
1439 | pm_runtime_enable(&pdev->dev); |
1440 | host->power = false; | |
1441 | ||
46991005 | 1442 | host->hclk = devm_clk_get(&pdev->dev, NULL); |
b289174f GL |
1443 | if (IS_ERR(host->hclk)) { |
1444 | ret = PTR_ERR(host->hclk); | |
047a9ce7 | 1445 | dev_err(&pdev->dev, "cannot get clock: %d\n", ret); |
46991005 | 1446 | goto err_pm; |
b289174f | 1447 | } |
a6609267 GL |
1448 | ret = sh_mmcif_clk_update(host); |
1449 | if (ret < 0) | |
46991005 | 1450 | goto err_pm; |
b289174f | 1451 | |
faca6648 GL |
1452 | ret = pm_runtime_resume(&pdev->dev); |
1453 | if (ret < 0) | |
46991005 | 1454 | goto err_clk; |
a782d688 | 1455 | |
5ba85d95 | 1456 | INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); |
fdc50a94 | 1457 | |
b289174f | 1458 | sh_mmcif_sync_reset(host); |
3b0beafc GL |
1459 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
1460 | ||
2cd5b3e0 | 1461 | name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error"; |
6f4789e6 BD |
1462 | ret = devm_request_threaded_irq(&pdev->dev, irq[0], sh_mmcif_intr, |
1463 | sh_mmcif_irqt, 0, name, host); | |
fdc50a94 | 1464 | if (ret) { |
2cd5b3e0 | 1465 | dev_err(&pdev->dev, "request_irq error (%s)\n", name); |
11a80852 | 1466 | goto err_clk; |
fdc50a94 | 1467 | } |
2cd5b3e0 | 1468 | if (irq[1] >= 0) { |
6f4789e6 BD |
1469 | ret = devm_request_threaded_irq(&pdev->dev, irq[1], |
1470 | sh_mmcif_intr, sh_mmcif_irqt, | |
1471 | 0, "sh_mmc:int", host); | |
2cd5b3e0 SK |
1472 | if (ret) { |
1473 | dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); | |
11a80852 | 1474 | goto err_clk; |
2cd5b3e0 | 1475 | } |
fdc50a94 YG |
1476 | } |
1477 | ||
e480606a | 1478 | if (pd && pd->use_cd_gpio) { |
214fc309 | 1479 | ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0); |
e480606a | 1480 | if (ret < 0) |
7f67f3a2 | 1481 | goto err_clk; |
e480606a GL |
1482 | } |
1483 | ||
8047310e GL |
1484 | mutex_init(&host->thread_lock); |
1485 | ||
5ba85d95 GL |
1486 | ret = mmc_add_host(mmc); |
1487 | if (ret < 0) | |
7f67f3a2 | 1488 | goto err_clk; |
fdc50a94 | 1489 | |
efe6a8ad RW |
1490 | dev_pm_qos_expose_latency_limit(&pdev->dev, 100); |
1491 | ||
ce7eb688 BD |
1492 | dev_info(&pdev->dev, "Chip version 0x%04x, clock rate %luMHz\n", |
1493 | sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, | |
1494 | clk_get_rate(host->hclk) / 1000000UL); | |
1495 | ||
1496 | clk_disable_unprepare(host->hclk); | |
fdc50a94 YG |
1497 | return ret; |
1498 | ||
46991005 | 1499 | err_clk: |
ac0a2e98 | 1500 | clk_disable_unprepare(host->hclk); |
46991005 | 1501 | err_pm: |
b289174f | 1502 | pm_runtime_disable(&pdev->dev); |
46991005 | 1503 | err_host: |
fdc50a94 | 1504 | mmc_free_host(mmc); |
fdc50a94 YG |
1505 | return ret; |
1506 | } | |
1507 | ||
6e0ee714 | 1508 | static int sh_mmcif_remove(struct platform_device *pdev) |
fdc50a94 YG |
1509 | { |
1510 | struct sh_mmcif_host *host = platform_get_drvdata(pdev); | |
fdc50a94 | 1511 | |
f985da17 | 1512 | host->dying = true; |
ac0a2e98 | 1513 | clk_prepare_enable(host->hclk); |
faca6648 | 1514 | pm_runtime_get_sync(&pdev->dev); |
fdc50a94 | 1515 | |
efe6a8ad RW |
1516 | dev_pm_qos_hide_latency_limit(&pdev->dev); |
1517 | ||
faca6648 | 1518 | mmc_remove_host(host->mmc); |
3b0beafc GL |
1519 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
1520 | ||
f985da17 GL |
1521 | /* |
1522 | * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the | |
1523 | * mmc_remove_host() call above. But swapping order doesn't help either | |
1524 | * (a query on the linux-mmc mailing list didn't bring any replies). | |
1525 | */ | |
1526 | cancel_delayed_work_sync(&host->timeout_work); | |
1527 | ||
ac0a2e98 | 1528 | clk_disable_unprepare(host->hclk); |
fdc50a94 | 1529 | mmc_free_host(host->mmc); |
faca6648 GL |
1530 | pm_runtime_put_sync(&pdev->dev); |
1531 | pm_runtime_disable(&pdev->dev); | |
fdc50a94 YG |
1532 | |
1533 | return 0; | |
1534 | } | |
1535 | ||
51129f31 | 1536 | #ifdef CONFIG_PM_SLEEP |
faca6648 GL |
1537 | static int sh_mmcif_suspend(struct device *dev) |
1538 | { | |
b289174f | 1539 | struct sh_mmcif_host *host = dev_get_drvdata(dev); |
faca6648 | 1540 | |
cb3ca1ae | 1541 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
faca6648 | 1542 | |
cb3ca1ae | 1543 | return 0; |
faca6648 GL |
1544 | } |
1545 | ||
1546 | static int sh_mmcif_resume(struct device *dev) | |
1547 | { | |
cb3ca1ae | 1548 | return 0; |
faca6648 | 1549 | } |
51129f31 | 1550 | #endif |
faca6648 GL |
1551 | |
1552 | static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { | |
51129f31 | 1553 | SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume) |
faca6648 GL |
1554 | }; |
1555 | ||
fdc50a94 YG |
1556 | static struct platform_driver sh_mmcif_driver = { |
1557 | .probe = sh_mmcif_probe, | |
1558 | .remove = sh_mmcif_remove, | |
1559 | .driver = { | |
1560 | .name = DRIVER_NAME, | |
faca6648 | 1561 | .pm = &sh_mmcif_dev_pm_ops, |
bf68a812 | 1562 | .of_match_table = mmcif_of_match, |
fdc50a94 YG |
1563 | }, |
1564 | }; | |
1565 | ||
d1f81a64 | 1566 | module_platform_driver(sh_mmcif_driver); |
fdc50a94 YG |
1567 | |
1568 | MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); | |
1569 | MODULE_LICENSE("GPL"); | |
aa0787a9 | 1570 | MODULE_ALIAS("platform:" DRIVER_NAME); |
fdc50a94 | 1571 | MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); |