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mmc: sh_mmcif: fix missing and consolidate IO completion timeouts
[linux-2.6-block.git] / drivers / mmc / host / sh_mmcif.c
CommitLineData
fdc50a94
YG		 1/*
2 * MMCIF eMMC driver.
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10 *
11 *
12 * TODO
13 * 1. DMA
14 * 2. Power management
15 * 3. Handle MMC errors better
16 *
17 */
18
f985da17
GL		 19/*
20 * The MMCIF driver is now processing MMC requests asynchronously, according
21 * to the Linux MMC API requirement.
22 *
23 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
24 * data, and optional stop. To achieve asynchronous processing each of these
25 * stages is split into two halves: a top and a bottom half. The top half
26 * initialises the hardware, installs a timeout handler to handle completion
27 * timeouts, and returns. In case of the command stage this immediately returns
28 * control to the caller, leaving all further processing to run asynchronously.
29 * All further request processing is performed by the bottom halves.
30 *
31 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
32 * thread, a DMA completion callback, if DMA is used, a timeout work, and
33 * request- and stage-specific handler methods.
34 *
35 * Each bottom half run begins with either a hardware interrupt, a DMA callback
36 * invocation, or a timeout work run. In case of an error or a successful
37 * processing completion, the MMC core is informed and the request processing is
38 * finished. In case processing has to continue, i.e., if data has to be read
39 * from or written to the card, or if a stop command has to be sent, the next
40 * top half is called, which performs the necessary hardware handling and
41 * reschedules the timeout work. This returns the driver state machine into the
42 * bottom half waiting state.
43 */
44
86df1745 45#include <linux/bitops.h>
aa0787a9
GL		 46#include <linux/clk.h>
47#include <linux/completion.h>
e47bf32a 48#include <linux/delay.h>
fdc50a94 49#include <linux/dma-mapping.h>
a782d688 50#include <linux/dmaengine.h>
fdc50a94
YG		 51#include <linux/mmc/card.h>
52#include <linux/mmc/core.h>
e47bf32a 53#include <linux/mmc/host.h>
fdc50a94
YG		 54#include <linux/mmc/mmc.h>
55#include <linux/mmc/sdio.h>
fdc50a94 56#include <linux/mmc/sh_mmcif.h>
e480606a 57#include <linux/mmc/slot-gpio.h>
bf68a812 58#include <linux/mod_devicetable.h>
a782d688 59#include <linux/pagemap.h>
e47bf32a 60#include <linux/platform_device.h>
efe6a8ad 61#include <linux/pm_qos.h>
faca6648 62#include <linux/pm_runtime.h>
3b0beafc 63#include <linux/spinlock.h>
88b47679 64#include <linux/module.h>
fdc50a94
YG		 65
66#define DRIVER_NAME "sh_mmcif"
67#define DRIVER_VERSION "2010-04-28"
68
fdc50a94
YG		 69/* CE_CMD_SET */
70#define CMD_MASK 0x3f000000
71#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
72#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
73#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
74#define CMD_SET_RBSY (1 << 21) /* R1b */
75#define CMD_SET_CCSEN (1 << 20)
76#define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
77#define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
78#define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
79#define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
80#define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
81#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
82#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
83#define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
84#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
85#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
86#define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
87#define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
88#define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
89#define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
90#define CMD_SET_CCSH (1 << 5)
555061f9 91#define CMD_SET_DARS (1 << 2) /* Dual Data Rate */
fdc50a94
YG		 92#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
93#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
94#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
95
96/* CE_CMD_CTRL */
97#define CMD_CTRL_BREAK (1 << 0)
98
99/* CE_BLOCK_SET */
100#define BLOCK_SIZE_MASK 0x0000ffff
101
fdc50a94
YG		 102/* CE_INT */
103#define INT_CCSDE (1 << 29)
104#define INT_CMD12DRE (1 << 26)
105#define INT_CMD12RBE (1 << 25)
106#define INT_CMD12CRE (1 << 24)
107#define INT_DTRANE (1 << 23)
108#define INT_BUFRE (1 << 22)
109#define INT_BUFWEN (1 << 21)
110#define INT_BUFREN (1 << 20)
111#define INT_CCSRCV (1 << 19)
112#define INT_RBSYE (1 << 17)
113#define INT_CRSPE (1 << 16)
114#define INT_CMDVIO (1 << 15)
115#define INT_BUFVIO (1 << 14)
116#define INT_WDATERR (1 << 11)
117#define INT_RDATERR (1 << 10)
118#define INT_RIDXERR (1 << 9)
119#define INT_RSPERR (1 << 8)
120#define INT_CCSTO (1 << 5)
121#define INT_CRCSTO (1 << 4)
122#define INT_WDATTO (1 << 3)
123#define INT_RDATTO (1 << 2)
124#define INT_RBSYTO (1 << 1)
125#define INT_RSPTO (1 << 0)
126#define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
127 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
128 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
129 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
130
131/* CE_INT_MASK */
132#define MASK_ALL 0x00000000
133#define MASK_MCCSDE (1 << 29)
134#define MASK_MCMD12DRE (1 << 26)
135#define MASK_MCMD12RBE (1 << 25)
136#define MASK_MCMD12CRE (1 << 24)
137#define MASK_MDTRANE (1 << 23)
138#define MASK_MBUFRE (1 << 22)
139#define MASK_MBUFWEN (1 << 21)
140#define MASK_MBUFREN (1 << 20)
141#define MASK_MCCSRCV (1 << 19)
142#define MASK_MRBSYE (1 << 17)
143#define MASK_MCRSPE (1 << 16)
144#define MASK_MCMDVIO (1 << 15)
145#define MASK_MBUFVIO (1 << 14)
146#define MASK_MWDATERR (1 << 11)
147#define MASK_MRDATERR (1 << 10)
148#define MASK_MRIDXERR (1 << 9)
149#define MASK_MRSPERR (1 << 8)
150#define MASK_MCCSTO (1 << 5)
151#define MASK_MCRCSTO (1 << 4)
152#define MASK_MWDATTO (1 << 3)
153#define MASK_MRDATTO (1 << 2)
154#define MASK_MRBSYTO (1 << 1)
155#define MASK_MRSPTO (1 << 0)
156
ee4b8887
GL		 157#define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
158 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
159 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
160 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
161
fdc50a94
YG		 162/* CE_HOST_STS1 */
163#define STS1_CMDSEQ (1 << 31)
164
165/* CE_HOST_STS2 */
166#define STS2_CRCSTE (1 << 31)
167#define STS2_CRC16E (1 << 30)
168#define STS2_AC12CRCE (1 << 29)
169#define STS2_RSPCRC7E (1 << 28)
170#define STS2_CRCSTEBE (1 << 27)
171#define STS2_RDATEBE (1 << 26)
172#define STS2_AC12REBE (1 << 25)
173#define STS2_RSPEBE (1 << 24)
174#define STS2_AC12IDXE (1 << 23)
175#define STS2_RSPIDXE (1 << 22)
176#define STS2_CCSTO (1 << 15)
177#define STS2_RDATTO (1 << 14)
178#define STS2_DATBSYTO (1 << 13)
179#define STS2_CRCSTTO (1 << 12)
180#define STS2_AC12BSYTO (1 << 11)
181#define STS2_RSPBSYTO (1 << 10)
182#define STS2_AC12RSPTO (1 << 9)
183#define STS2_RSPTO (1 << 8)
184#define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
185 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
186#define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
187 STS2_DATBSYTO | STS2_CRCSTTO | \
188 STS2_AC12BSYTO | STS2_RSPBSYTO | \
189 STS2_AC12RSPTO | STS2_RSPTO)
190
fdc50a94
YG		 191#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
192#define CLKDEV_MMC_DATA 20000000 /* 20MHz */
193#define CLKDEV_INIT 400000 /* 400 KHz */
194
3b0beafc
GL		 195enum mmcif_state {
196 STATE_IDLE,
197 STATE_REQUEST,
198 STATE_IOS,
199};
200
f985da17
GL		 201enum mmcif_wait_for {
202 MMCIF_WAIT_FOR_REQUEST,
203 MMCIF_WAIT_FOR_CMD,
204 MMCIF_WAIT_FOR_MREAD,
205 MMCIF_WAIT_FOR_MWRITE,
206 MMCIF_WAIT_FOR_READ,
207 MMCIF_WAIT_FOR_WRITE,
208 MMCIF_WAIT_FOR_READ_END,
209 MMCIF_WAIT_FOR_WRITE_END,
210 MMCIF_WAIT_FOR_STOP,
211};
212
fdc50a94
YG		 213struct sh_mmcif_host {
214 struct mmc_host *mmc;
f985da17 215 struct mmc_request *mrq;
fdc50a94
YG		 216 struct platform_device *pd;
217 struct clk *hclk;
218 unsigned int clk;
219 int bus_width;
555061f9 220 unsigned char timing;
aa0787a9 221 bool sd_error;
f985da17 222 bool dying;
fdc50a94
YG		 223 long timeout;
224 void __iomem *addr;
f985da17 225 u32 *pio_ptr;
ee4b8887 226 spinlock_t lock; /* protect sh_mmcif_host::state */
3b0beafc 227 enum mmcif_state state;
f985da17
GL		 228 enum mmcif_wait_for wait_for;
229 struct delayed_work timeout_work;
230 size_t blocksize;
231 int sg_idx;
232 int sg_blkidx;
faca6648 233 bool power;
c9b0cef2 234 bool card_present;
fdc50a94 235
a782d688
GL		 236 /* DMA support */
237 struct dma_chan *chan_rx;
238 struct dma_chan *chan_tx;
239 struct completion dma_complete;
f38f94c6 240 bool dma_active;
a782d688 241};
fdc50a94
YG		 242
243static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
244 unsigned int reg, u32 val)
245{
487d9fc5 246 writel(val | readl(host->addr + reg), host->addr + reg);
fdc50a94
YG		 247}
248
249static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
250 unsigned int reg, u32 val)
251{
487d9fc5 252 writel(~val & readl(host->addr + reg), host->addr + reg);
fdc50a94
YG		 253}
254
a782d688
GL		 255static void mmcif_dma_complete(void *arg)
256{
257 struct sh_mmcif_host *host = arg;
69983404
GL		 258 struct mmc_data *data = host->mrq->data;
259
a782d688
GL		 260 dev_dbg(&host->pd->dev, "Command completed\n");
261
69983404 262 if (WARN(!data, "%s: NULL data in DMA completion!\n",
a782d688
GL		 263 dev_name(&host->pd->dev)))
264 return;
265
69983404 266 if (data->flags & MMC_DATA_READ)
1ed828db 267 dma_unmap_sg(host->chan_rx->device->dev,
69983404 268 data->sg, data->sg_len,
a782d688
GL		 269 DMA_FROM_DEVICE);
270 else
1ed828db 271 dma_unmap_sg(host->chan_tx->device->dev,
69983404 272 data->sg, data->sg_len,
a782d688
GL		 273 DMA_TO_DEVICE);
274
275 complete(&host->dma_complete);
276}
277
278static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
279{
69983404
GL		 280 struct mmc_data *data = host->mrq->data;
281 struct scatterlist *sg = data->sg;
a782d688
GL		 282 struct dma_async_tx_descriptor *desc = NULL;
283 struct dma_chan *chan = host->chan_rx;
284 dma_cookie_t cookie = -EINVAL;
285 int ret;
286
69983404 287 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
1ed828db 288 DMA_FROM_DEVICE);
a782d688 289 if (ret > 0) {
f38f94c6 290 host->dma_active = true;
16052827 291 desc = dmaengine_prep_slave_sg(chan, sg, ret,
05f5799c 292 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
a782d688
GL		 293 }
294
295 if (desc) {
296 desc->callback = mmcif_dma_complete;
297 desc->callback_param = host;
a5ece7d2
LW		 298 cookie = dmaengine_submit(desc);
299 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
300 dma_async_issue_pending(chan);
a782d688
GL		 301 }
302 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
69983404 303 __func__, data->sg_len, ret, cookie);
a782d688
GL		 304
305 if (!desc) {
306 /* DMA failed, fall back to PIO */
307 if (ret >= 0)
308 ret = -EIO;
309 host->chan_rx = NULL;
f38f94c6 310 host->dma_active = false;
a782d688
GL		 311 dma_release_channel(chan);
312 /* Free the Tx channel too */
313 chan = host->chan_tx;
314 if (chan) {
315 host->chan_tx = NULL;
316 dma_release_channel(chan);
317 }
318 dev_warn(&host->pd->dev,
319 "DMA failed: %d, falling back to PIO\n", ret);
320 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
321 }
322
323 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
69983404 324 desc, cookie, data->sg_len);
a782d688
GL		 325}
326
327static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
328{
69983404
GL		 329 struct mmc_data *data = host->mrq->data;
330 struct scatterlist *sg = data->sg;
a782d688
GL		 331 struct dma_async_tx_descriptor *desc = NULL;
332 struct dma_chan *chan = host->chan_tx;
333 dma_cookie_t cookie = -EINVAL;
334 int ret;
335
69983404 336 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
1ed828db 337 DMA_TO_DEVICE);
a782d688 338 if (ret > 0) {
f38f94c6 339 host->dma_active = true;
16052827 340 desc = dmaengine_prep_slave_sg(chan, sg, ret,
05f5799c 341 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
a782d688
GL		 342 }
343
344 if (desc) {
345 desc->callback = mmcif_dma_complete;
346 desc->callback_param = host;
a5ece7d2
LW		 347 cookie = dmaengine_submit(desc);
348 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
349 dma_async_issue_pending(chan);
a782d688
GL		 350 }
351 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
69983404 352 __func__, data->sg_len, ret, cookie);
a782d688
GL		 353
354 if (!desc) {
355 /* DMA failed, fall back to PIO */
356 if (ret >= 0)
357 ret = -EIO;
358 host->chan_tx = NULL;
f38f94c6 359 host->dma_active = false;
a782d688
GL		 360 dma_release_channel(chan);
361 /* Free the Rx channel too */
362 chan = host->chan_rx;
363 if (chan) {
364 host->chan_rx = NULL;
365 dma_release_channel(chan);
366 }
367 dev_warn(&host->pd->dev,
368 "DMA failed: %d, falling back to PIO\n", ret);
369 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
370 }
371
372 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
373 desc, cookie);
374}
375
a782d688
GL		 376static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
377 struct sh_mmcif_plat_data *pdata)
378{
0e79f9ae
GL		 379 struct resource *res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);
380 struct dma_slave_config cfg;
381 dma_cap_mask_t mask;
382 int ret;
a782d688 383
f38f94c6 384 host->dma_active = false;
a782d688 385
bf68a812
GL		 386 if (!pdata)
387 return;
388
0e79f9ae
GL		 389 if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0)
390 return;
a782d688 391
0e79f9ae
GL		 392 /* We can only either use DMA for both Tx and Rx or not use it at all */
393 dma_cap_zero(mask);
394 dma_cap_set(DMA_SLAVE, mask);
a782d688 395
0e79f9ae
GL		 396 host->chan_tx = dma_request_channel(mask, shdma_chan_filter,
397 (void *)pdata->slave_id_tx);
398 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
399 host->chan_tx);
a782d688 400
0e79f9ae
GL		 401 if (!host->chan_tx)
402 return;
a782d688 403
0e79f9ae
GL		 404 cfg.slave_id = pdata->slave_id_tx;
405 cfg.direction = DMA_MEM_TO_DEV;
406 cfg.dst_addr = res->start + MMCIF_CE_DATA;
407 cfg.src_addr = 0;
408 ret = dmaengine_slave_config(host->chan_tx, &cfg);
409 if (ret < 0)
410 goto ecfgtx;
411
412 host->chan_rx = dma_request_channel(mask, shdma_chan_filter,
413 (void *)pdata->slave_id_rx);
414 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
415 host->chan_rx);
416
417 if (!host->chan_rx)
418 goto erqrx;
419
420 cfg.slave_id = pdata->slave_id_rx;
421 cfg.direction = DMA_DEV_TO_MEM;
422 cfg.dst_addr = 0;
423 cfg.src_addr = res->start + MMCIF_CE_DATA;
424 ret = dmaengine_slave_config(host->chan_rx, &cfg);
425 if (ret < 0)
426 goto ecfgrx;
427
428 init_completion(&host->dma_complete);
429
430 return;
431
432ecfgrx:
433 dma_release_channel(host->chan_rx);
434 host->chan_rx = NULL;
435erqrx:
436ecfgtx:
437 dma_release_channel(host->chan_tx);
438 host->chan_tx = NULL;
a782d688
GL		 439}
440
441static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
442{
443 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
444 /* Descriptors are freed automatically */
445 if (host->chan_tx) {
446 struct dma_chan *chan = host->chan_tx;
447 host->chan_tx = NULL;
448 dma_release_channel(chan);
449 }
450 if (host->chan_rx) {
451 struct dma_chan *chan = host->chan_rx;
452 host->chan_rx = NULL;
453 dma_release_channel(chan);
454 }
455
f38f94c6 456 host->dma_active = false;
a782d688 457}
fdc50a94
YG		 458
459static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
460{
461 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
bf68a812 462 bool sup_pclk = p ? p->sup_pclk : false;
fdc50a94
YG		 463
464 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
465 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
466
467 if (!clk)
468 return;
bf68a812 469 if (sup_pclk && clk == host->clk)
fdc50a94
YG		 470 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
471 else
472 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
f9388257
SH		 473 ((fls(DIV_ROUND_UP(host->clk,
474 clk) - 1) - 1) << 16));
fdc50a94
YG		 475
476 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
477}
478
479static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
480{
481 u32 tmp;
482
487d9fc5 483 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
fdc50a94 484
487d9fc5
MD		 485 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
486 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
fdc50a94
YG		 487 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
488 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
489 /* byte swap on */
490 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
491}
492
493static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
494{
495 u32 state1, state2;
ee4b8887 496 int ret, timeout;
fdc50a94 497
aa0787a9 498 host->sd_error = false;
fdc50a94 499
487d9fc5
MD		 500 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
501 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
e47bf32a
GL		 502 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
503 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
fdc50a94
YG		 504
505 if (state1 & STS1_CMDSEQ) {
506 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
507 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
ee4b8887 508 for (timeout = 10000000; timeout; timeout--) {
487d9fc5 509 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
ee4b8887 510 & STS1_CMDSEQ))
fdc50a94
YG		 511 break;
512 mdelay(1);
513 }
ee4b8887
GL		 514 if (!timeout) {
515 dev_err(&host->pd->dev,
516 "Forced end of command sequence timeout err\n");
517 return -EIO;
518 }
fdc50a94 519 sh_mmcif_sync_reset(host);
e47bf32a 520 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
fdc50a94
YG		 521 return -EIO;
522 }
523
524 if (state2 & STS2_CRC_ERR) {
ee4b8887 525 dev_dbg(&host->pd->dev, ": CRC error\n");
fdc50a94
YG		 526 ret = -EIO;
527 } else if (state2 & STS2_TIMEOUT_ERR) {
ee4b8887 528 dev_dbg(&host->pd->dev, ": Timeout\n");
fdc50a94
YG		 529 ret = -ETIMEDOUT;
530 } else {
ee4b8887 531 dev_dbg(&host->pd->dev, ": End/Index error\n");
fdc50a94
YG		 532 ret = -EIO;
533 }
534 return ret;
535}
536
f985da17 537static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
fdc50a94 538{
f985da17
GL		 539 struct mmc_data *data = host->mrq->data;
540
541 host->sg_blkidx += host->blocksize;
542
543 /* data->sg->length must be a multiple of host->blocksize? */
544 BUG_ON(host->sg_blkidx > data->sg->length);
545
546 if (host->sg_blkidx == data->sg->length) {
547 host->sg_blkidx = 0;
548 if (++host->sg_idx < data->sg_len)
549 host->pio_ptr = sg_virt(++data->sg);
550 } else {
551 host->pio_ptr = p;
552 }
553
554 if (host->sg_idx == data->sg_len)
555 return false;
556
557 return true;
558}
559
560static void sh_mmcif_single_read(struct sh_mmcif_host *host,
561 struct mmc_request *mrq)
562{
563 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
564 BLOCK_SIZE_MASK) + 3;
565
566 host->wait_for = MMCIF_WAIT_FOR_READ;
fdc50a94 567
fdc50a94
YG		 568 /* buf read enable */
569 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
f985da17
GL		 570}
571
572static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
573{
574 struct mmc_data *data = host->mrq->data;
575 u32 *p = sg_virt(data->sg);
576 int i;
577
578 if (host->sd_error) {
579 data->error = sh_mmcif_error_manage(host);
580 return false;
581 }
582
583 for (i = 0; i < host->blocksize / 4; i++)
487d9fc5 584 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
fdc50a94
YG		 585
586 /* buffer read end */
587 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
f985da17 588 host->wait_for = MMCIF_WAIT_FOR_READ_END;
fdc50a94 589
f985da17 590 return true;
fdc50a94
YG		 591}
592
f985da17
GL		 593static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
594 struct mmc_request *mrq)
fdc50a94
YG		 595{
596 struct mmc_data *data = mrq->data;
f985da17
GL		 597
598 if (!data->sg_len || !data->sg->length)
599 return;
600
601 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
602 BLOCK_SIZE_MASK;
603
604 host->wait_for = MMCIF_WAIT_FOR_MREAD;
605 host->sg_idx = 0;
606 host->sg_blkidx = 0;
607 host->pio_ptr = sg_virt(data->sg);
5df460b1 608
f985da17
GL		 609 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
610}
611
612static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
613{
614 struct mmc_data *data = host->mrq->data;
615 u32 *p = host->pio_ptr;
616 int i;
617
618 if (host->sd_error) {
619 data->error = sh_mmcif_error_manage(host);
620 return false;
fdc50a94 621 }
f985da17
GL		 622
623 BUG_ON(!data->sg->length);
624
625 for (i = 0; i < host->blocksize / 4; i++)
626 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
627
628 if (!sh_mmcif_next_block(host, p))
629 return false;
630
f985da17
GL		 631 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
632
633 return true;
fdc50a94
YG		 634}
635
f985da17 636static void sh_mmcif_single_write(struct sh_mmcif_host *host,
fdc50a94
YG		 637 struct mmc_request *mrq)
638{
f985da17
GL		 639 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
640 BLOCK_SIZE_MASK) + 3;
fdc50a94 641
f985da17 642 host->wait_for = MMCIF_WAIT_FOR_WRITE;
fdc50a94
YG		 643
644 /* buf write enable */
f985da17
GL		 645 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
646}
647
648static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
649{
650 struct mmc_data *data = host->mrq->data;
651 u32 *p = sg_virt(data->sg);
652 int i;
653
654 if (host->sd_error) {
655 data->error = sh_mmcif_error_manage(host);
656 return false;
657 }
658
659 for (i = 0; i < host->blocksize / 4; i++)
487d9fc5 660 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
fdc50a94
YG		 661
662 /* buffer write end */
663 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
f985da17 664 host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
fdc50a94 665
f985da17 666 return true;
fdc50a94
YG		 667}
668
f985da17
GL		 669static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
670 struct mmc_request *mrq)
fdc50a94
YG		 671{
672 struct mmc_data *data = mrq->data;
fdc50a94 673
f985da17
GL		 674 if (!data->sg_len || !data->sg->length)
675 return;
fdc50a94 676
f985da17
GL		 677 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
678 BLOCK_SIZE_MASK;
fdc50a94 679
f985da17
GL		 680 host->wait_for = MMCIF_WAIT_FOR_MWRITE;
681 host->sg_idx = 0;
682 host->sg_blkidx = 0;
683 host->pio_ptr = sg_virt(data->sg);
5df460b1 684
f985da17
GL		 685 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
686}
fdc50a94 687
f985da17
GL		 688static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
689{
690 struct mmc_data *data = host->mrq->data;
691 u32 *p = host->pio_ptr;
692 int i;
693
694 if (host->sd_error) {
695 data->error = sh_mmcif_error_manage(host);
696 return false;
fdc50a94 697 }
f985da17
GL		 698
699 BUG_ON(!data->sg->length);
700
701 for (i = 0; i < host->blocksize / 4; i++)
702 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
703
704 if (!sh_mmcif_next_block(host, p))
705 return false;
706
f985da17
GL		 707 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
708
709 return true;
fdc50a94
YG		 710}
711
712static void sh_mmcif_get_response(struct sh_mmcif_host *host,
713 struct mmc_command *cmd)
714{
715 if (cmd->flags & MMC_RSP_136) {
487d9fc5
MD		 716 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
717 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
718 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
719 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
fdc50a94 720 } else
487d9fc5 721 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
fdc50a94
YG		 722}
723
724static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
725 struct mmc_command *cmd)
726{
487d9fc5 727 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
fdc50a94
YG		 728}
729
730static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
69983404 731 struct mmc_request *mrq)
fdc50a94 732{
69983404
GL		 733 struct mmc_data *data = mrq->data;
734 struct mmc_command *cmd = mrq->cmd;
735 u32 opc = cmd->opcode;
fdc50a94
YG		 736 u32 tmp = 0;
737
738 /* Response Type check */
739 switch (mmc_resp_type(cmd)) {
740 case MMC_RSP_NONE:
741 tmp |= CMD_SET_RTYP_NO;
742 break;
743 case MMC_RSP_R1:
744 case MMC_RSP_R1B:
745 case MMC_RSP_R3:
746 tmp |= CMD_SET_RTYP_6B;
747 break;
748 case MMC_RSP_R2:
749 tmp |= CMD_SET_RTYP_17B;
750 break;
751 default:
e47bf32a 752 dev_err(&host->pd->dev, "Unsupported response type.\n");
fdc50a94
YG		 753 break;
754 }
755 switch (opc) {
756 /* RBSY */
a812ba0f 757 case MMC_SLEEP_AWAKE:
fdc50a94
YG		 758 case MMC_SWITCH:
759 case MMC_STOP_TRANSMISSION:
760 case MMC_SET_WRITE_PROT:
761 case MMC_CLR_WRITE_PROT:
762 case MMC_ERASE:
fdc50a94
YG		 763 tmp |= CMD_SET_RBSY;
764 break;
765 }
766 /* WDAT / DATW */
69983404 767 if (data) {
fdc50a94
YG		 768 tmp |= CMD_SET_WDAT;
769 switch (host->bus_width) {
770 case MMC_BUS_WIDTH_1:
771 tmp |= CMD_SET_DATW_1;
772 break;
773 case MMC_BUS_WIDTH_4:
774 tmp |= CMD_SET_DATW_4;
775 break;
776 case MMC_BUS_WIDTH_8:
777 tmp |= CMD_SET_DATW_8;
778 break;
779 default:
e47bf32a 780 dev_err(&host->pd->dev, "Unsupported bus width.\n");
fdc50a94
YG		 781 break;
782 }
555061f9
TK		 783 switch (host->timing) {
784 case MMC_TIMING_UHS_DDR50:
785 /*
786 * MMC core will only set this timing, if the host
787 * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF
788 * implementations with this capability, e.g. sh73a0,
789 * will have to set it in their platform data.
790 */
791 tmp |= CMD_SET_DARS;
792 break;
793 }
fdc50a94
YG		 794 }
795 /* DWEN */
796 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
797 tmp |= CMD_SET_DWEN;
798 /* CMLTE/CMD12EN */
799 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
800 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
801 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
69983404 802 data->blocks << 16);
fdc50a94
YG		 803 }
804 /* RIDXC[1:0] check bits */
805 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
806 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
807 tmp |= CMD_SET_RIDXC_BITS;
808 /* RCRC7C[1:0] check bits */
809 if (opc == MMC_SEND_OP_COND)
810 tmp |= CMD_SET_CRC7C_BITS;
811 /* RCRC7C[1:0] internal CRC7 */
812 if (opc == MMC_ALL_SEND_CID ||
813 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
814 tmp |= CMD_SET_CRC7C_INTERNAL;
815
69983404 816 return (opc << 24) | tmp;
fdc50a94
YG		 817}
818
e47bf32a 819static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
f985da17 820 struct mmc_request *mrq, u32 opc)
fdc50a94 821{
fdc50a94
YG		 822 switch (opc) {
823 case MMC_READ_MULTIPLE_BLOCK:
f985da17
GL		 824 sh_mmcif_multi_read(host, mrq);
825 return 0;
fdc50a94 826 case MMC_WRITE_MULTIPLE_BLOCK:
f985da17
GL		 827 sh_mmcif_multi_write(host, mrq);
828 return 0;
fdc50a94 829 case MMC_WRITE_BLOCK:
f985da17
GL		 830 sh_mmcif_single_write(host, mrq);
831 return 0;
fdc50a94
YG		 832 case MMC_READ_SINGLE_BLOCK:
833 case MMC_SEND_EXT_CSD:
f985da17
GL		 834 sh_mmcif_single_read(host, mrq);
835 return 0;
fdc50a94 836 default:
e47bf32a 837 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
ee4b8887 838 return -EINVAL;
fdc50a94 839 }
fdc50a94
YG		 840}
841
842static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
ee4b8887 843 struct mmc_request *mrq)
fdc50a94 844{
ee4b8887 845 struct mmc_command *cmd = mrq->cmd;
f985da17
GL		 846 u32 opc = cmd->opcode;
847 u32 mask;
fdc50a94 848
fdc50a94 849 switch (opc) {
ee4b8887 850 /* response busy check */
a812ba0f 851 case MMC_SLEEP_AWAKE:
fdc50a94
YG		 852 case MMC_SWITCH:
853 case MMC_STOP_TRANSMISSION:
854 case MMC_SET_WRITE_PROT:
855 case MMC_CLR_WRITE_PROT:
856 case MMC_ERASE:
ee4b8887 857 mask = MASK_START_CMD | MASK_MRBSYE;
fdc50a94
YG		 858 break;
859 default:
ee4b8887 860 mask = MASK_START_CMD | MASK_MCRSPE;
fdc50a94
YG		 861 break;
862 }
fdc50a94 863
69983404 864 if (mrq->data) {
487d9fc5
MD		 865 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
866 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
867 mrq->data->blksz);
fdc50a94 868 }
69983404 869 opc = sh_mmcif_set_cmd(host, mrq);
fdc50a94 870
487d9fc5
MD		 871 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
872 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
fdc50a94 873 /* set arg */
487d9fc5 874 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
fdc50a94 875 /* set cmd */
487d9fc5 876 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
fdc50a94 877
f985da17
GL		 878 host->wait_for = MMCIF_WAIT_FOR_CMD;
879 schedule_delayed_work(&host->timeout_work, host->timeout);
fdc50a94
YG		 880}
881
882static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
ee4b8887 883 struct mmc_request *mrq)
fdc50a94 884{
69983404
GL		 885 switch (mrq->cmd->opcode) {
886 case MMC_READ_MULTIPLE_BLOCK:
fdc50a94 887 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
69983404
GL		 888 break;
889 case MMC_WRITE_MULTIPLE_BLOCK:
fdc50a94 890 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
69983404
GL		 891 break;
892 default:
e47bf32a 893 dev_err(&host->pd->dev, "unsupported stop cmd\n");
69983404 894 mrq->stop->error = sh_mmcif_error_manage(host);
fdc50a94
YG		 895 return;
896 }
897
f985da17 898 host->wait_for = MMCIF_WAIT_FOR_STOP;
fdc50a94
YG		 899}
900
901static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
902{
903 struct sh_mmcif_host *host = mmc_priv(mmc);
3b0beafc
GL		 904 unsigned long flags;
905
906 spin_lock_irqsave(&host->lock, flags);
907 if (host->state != STATE_IDLE) {
908 spin_unlock_irqrestore(&host->lock, flags);
909 mrq->cmd->error = -EAGAIN;
910 mmc_request_done(mmc, mrq);
911 return;
912 }
913
914 host->state = STATE_REQUEST;
915 spin_unlock_irqrestore(&host->lock, flags);
fdc50a94
YG		 916
917 switch (mrq->cmd->opcode) {
918 /* MMCIF does not support SD/SDIO command */
7541ca98
LP		 919 case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */
920 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
921 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)
922 break;
fdc50a94 923 case MMC_APP_CMD:
92ff0c5b 924 case SD_IO_RW_DIRECT:
3b0beafc 925 host->state = STATE_IDLE;
fdc50a94
YG		 926 mrq->cmd->error = -ETIMEDOUT;
927 mmc_request_done(mmc, mrq);
928 return;
fdc50a94
YG		 929 default:
930 break;
931 }
f985da17
GL		 932
933 host->mrq = mrq;
fdc50a94 934
f985da17 935 sh_mmcif_start_cmd(host, mrq);
fdc50a94
YG		 936}
937
a6609267
GL		 938static int sh_mmcif_clk_update(struct sh_mmcif_host *host)
939{
940 int ret = clk_enable(host->hclk);
941
942 if (!ret) {
943 host->clk = clk_get_rate(host->hclk);
944 host->mmc->f_max = host->clk / 2;
945 host->mmc->f_min = host->clk / 512;
946 }
947
948 return ret;
949}
950
7d17baa0
GL		 951static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)
952{
953 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
954 struct mmc_host *mmc = host->mmc;
955
bf68a812 956 if (pd && pd->set_pwr)
7d17baa0
GL		 957 pd->set_pwr(host->pd, ios->power_mode != MMC_POWER_OFF);
958 if (!IS_ERR(mmc->supply.vmmc))
959 /* Errors ignored... */
960 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
961 ios->power_mode ? ios->vdd : 0);
962}
963
fdc50a94
YG		 964static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
965{
966 struct sh_mmcif_host *host = mmc_priv(mmc);
3b0beafc
GL		 967 unsigned long flags;
968
969 spin_lock_irqsave(&host->lock, flags);
970 if (host->state != STATE_IDLE) {
971 spin_unlock_irqrestore(&host->lock, flags);
972 return;
973 }
974
975 host->state = STATE_IOS;
976 spin_unlock_irqrestore(&host->lock, flags);
fdc50a94 977
f5e0cec4 978 if (ios->power_mode == MMC_POWER_UP) {
c9b0cef2 979 if (!host->card_present) {
faca6648
GL		 980 /* See if we also get DMA */
981 sh_mmcif_request_dma(host, host->pd->dev.platform_data);
c9b0cef2 982 host->card_present = true;
faca6648 983 }
7d17baa0 984 sh_mmcif_set_power(host, ios);
f5e0cec4 985 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
fdc50a94
YG		 986 /* clock stop */
987 sh_mmcif_clock_control(host, 0);
faca6648 988 if (ios->power_mode == MMC_POWER_OFF) {
c9b0cef2 989 if (host->card_present) {
faca6648 990 sh_mmcif_release_dma(host);
c9b0cef2 991 host->card_present = false;
faca6648 992 }
c9b0cef2
GL		 993 }
994 if (host->power) {
f8a8ced7 995 pm_runtime_put_sync(&host->pd->dev);
b289174f 996 clk_disable(host->hclk);
c9b0cef2 997 host->power = false;
7d17baa0
GL		 998 if (ios->power_mode == MMC_POWER_OFF)
999 sh_mmcif_set_power(host, ios);
faca6648 1000 }
3b0beafc 1001 host->state = STATE_IDLE;
fdc50a94 1002 return;
fdc50a94
YG		 1003 }
1004
c9b0cef2
GL		 1005 if (ios->clock) {
1006 if (!host->power) {
a6609267 1007 sh_mmcif_clk_update(host);
c9b0cef2
GL		 1008 pm_runtime_get_sync(&host->pd->dev);
1009 host->power = true;
1010 sh_mmcif_sync_reset(host);
1011 }
fdc50a94 1012 sh_mmcif_clock_control(host, ios->clock);
c9b0cef2 1013 }
fdc50a94 1014
555061f9 1015 host->timing = ios->timing;
fdc50a94 1016 host->bus_width = ios->bus_width;
3b0beafc 1017 host->state = STATE_IDLE;
fdc50a94
YG		 1018}
1019
777271d0
AH		 1020static int sh_mmcif_get_cd(struct mmc_host *mmc)
1021{
1022 struct sh_mmcif_host *host = mmc_priv(mmc);
1023 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
e480606a
GL		 1024 int ret = mmc_gpio_get_cd(mmc);
1025
1026 if (ret >= 0)
1027 return ret;
777271d0 1028
bf68a812 1029 if (!p || !p->get_cd)
777271d0
AH		 1030 return -ENOSYS;
1031 else
1032 return p->get_cd(host->pd);
1033}
1034
fdc50a94
YG		 1035static struct mmc_host_ops sh_mmcif_ops = {
1036 .request = sh_mmcif_request,
1037 .set_ios = sh_mmcif_set_ios,
777271d0 1038 .get_cd = sh_mmcif_get_cd,
fdc50a94
YG		 1039};
1040
f985da17
GL		 1041static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1042{
1043 struct mmc_command *cmd = host->mrq->cmd;
69983404 1044 struct mmc_data *data = host->mrq->data;
f985da17
GL		 1045 long time;
1046
1047 if (host->sd_error) {
1048 switch (cmd->opcode) {
1049 case MMC_ALL_SEND_CID:
1050 case MMC_SELECT_CARD:
1051 case MMC_APP_CMD:
1052 cmd->error = -ETIMEDOUT;
1053 host->sd_error = false;
1054 break;
1055 default:
1056 cmd->error = sh_mmcif_error_manage(host);
1057 dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n",
1058 cmd->opcode, cmd->error);
1059 break;
1060 }
1061 return false;
1062 }
1063 if (!(cmd->flags & MMC_RSP_PRESENT)) {
1064 cmd->error = 0;
1065 return false;
1066 }
1067
1068 sh_mmcif_get_response(host, cmd);
1069
69983404 1070 if (!data)
f985da17
GL		 1071 return false;
1072
69983404 1073 if (data->flags & MMC_DATA_READ) {
f985da17
GL		 1074 if (host->chan_rx)
1075 sh_mmcif_start_dma_rx(host);
1076 } else {
1077 if (host->chan_tx)
1078 sh_mmcif_start_dma_tx(host);
1079 }
1080
1081 if (!host->dma_active) {
69983404
GL		 1082 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1083 if (!data->error)
f985da17
GL		 1084 return true;
1085 return false;
1086 }
1087
1088 /* Running in the IRQ thread, can sleep */
1089 time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1090 host->timeout);
1091 if (host->sd_error) {
1092 dev_err(host->mmc->parent,
1093 "Error IRQ while waiting for DMA completion!\n");
1094 /* Woken up by an error IRQ: abort DMA */
69983404 1095 if (data->flags & MMC_DATA_READ)
f985da17
GL		 1096 dmaengine_terminate_all(host->chan_rx);
1097 else
1098 dmaengine_terminate_all(host->chan_tx);
69983404 1099 data->error = sh_mmcif_error_manage(host);
f985da17 1100 } else if (!time) {
69983404 1101 data->error = -ETIMEDOUT;
f985da17 1102 } else if (time < 0) {
69983404 1103 data->error = time;
f985da17
GL		 1104 }
1105 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1106 BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1107 host->dma_active = false;
1108
69983404
GL		 1109 if (data->error)
1110 data->bytes_xfered = 0;
f985da17
GL		 1111
1112 return false;
1113}
1114
1115static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1116{
1117 struct sh_mmcif_host *host = dev_id;
1118 struct mmc_request *mrq = host->mrq;
5df460b1 1119 bool wait = false;
f985da17
GL		 1120
1121 cancel_delayed_work_sync(&host->timeout_work);
1122
1123 /*
1124 * All handlers return true, if processing continues, and false, if the
1125 * request has to be completed - successfully or not
1126 */
1127 switch (host->wait_for) {
1128 case MMCIF_WAIT_FOR_REQUEST:
1129 /* We're too late, the timeout has already kicked in */
1130 return IRQ_HANDLED;
1131 case MMCIF_WAIT_FOR_CMD:
5df460b1
GL		 1132 /* Wait for data? */
1133 wait = sh_mmcif_end_cmd(host);
f985da17
GL		 1134 break;
1135 case MMCIF_WAIT_FOR_MREAD:
5df460b1
GL		 1136 /* Wait for more data? */
1137 wait = sh_mmcif_mread_block(host);
f985da17
GL		 1138 break;
1139 case MMCIF_WAIT_FOR_READ:
5df460b1
GL		 1140 /* Wait for data end? */
1141 wait = sh_mmcif_read_block(host);
f985da17
GL		 1142 break;
1143 case MMCIF_WAIT_FOR_MWRITE:
5df460b1
GL		 1144 /* Wait data to write? */
1145 wait = sh_mmcif_mwrite_block(host);
f985da17
GL		 1146 break;
1147 case MMCIF_WAIT_FOR_WRITE:
5df460b1
GL		 1148 /* Wait for data end? */
1149 wait = sh_mmcif_write_block(host);
f985da17
GL		 1150 break;
1151 case MMCIF_WAIT_FOR_STOP:
1152 if (host->sd_error) {
1153 mrq->stop->error = sh_mmcif_error_manage(host);
1154 break;
1155 }
1156 sh_mmcif_get_cmd12response(host, mrq->stop);
1157 mrq->stop->error = 0;
1158 break;
1159 case MMCIF_WAIT_FOR_READ_END:
1160 case MMCIF_WAIT_FOR_WRITE_END:
1161 if (host->sd_error)
91ab252a 1162 mrq->data->error = sh_mmcif_error_manage(host);
f985da17
GL		 1163 break;
1164 default:
1165 BUG();
1166 }
1167
5df460b1
GL		 1168 if (wait) {
1169 schedule_delayed_work(&host->timeout_work, host->timeout);
1170 /* Wait for more data */
1171 return IRQ_HANDLED;
1172 }
1173
f985da17 1174 if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
91ab252a 1175 struct mmc_data *data = mrq->data;
69983404
GL		 1176 if (!mrq->cmd->error && data && !data->error)
1177 data->bytes_xfered =
1178 data->blocks * data->blksz;
f985da17 1179
69983404 1180 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
f985da17 1181 sh_mmcif_stop_cmd(host, mrq);
5df460b1
GL		 1182 if (!mrq->stop->error) {
1183 schedule_delayed_work(&host->timeout_work, host->timeout);
f985da17 1184 return IRQ_HANDLED;
5df460b1 1185 }
f985da17
GL		 1186 }
1187 }
1188
1189 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1190 host->state = STATE_IDLE;
69983404 1191 host->mrq = NULL;
f985da17
GL		 1192 mmc_request_done(host->mmc, mrq);
1193
1194 return IRQ_HANDLED;
1195}
1196
fdc50a94
YG		 1197static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1198{
1199 struct sh_mmcif_host *host = dev_id;
aa0787a9 1200 u32 state;
fdc50a94
YG		 1201 int err = 0;
1202
487d9fc5 1203 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
fdc50a94 1204
8a8284a9
GL		 1205 if (state & INT_ERR_STS) {
1206 /* error interrupts - process first */
1207 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1208 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1209 err = 1;
1210 } else if (state & INT_RBSYE) {
487d9fc5
MD		 1211 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1212 ~(INT_RBSYE | INT_CRSPE));
fdc50a94
YG		 1213 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
1214 } else if (state & INT_CRSPE) {
487d9fc5 1215 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
fdc50a94
YG		 1216 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
1217 } else if (state & INT_BUFREN) {
487d9fc5 1218 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
fdc50a94
YG		 1219 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
1220 } else if (state & INT_BUFWEN) {
487d9fc5 1221 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
fdc50a94
YG		 1222 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
1223 } else if (state & INT_CMD12DRE) {
487d9fc5 1224 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
fdc50a94
YG		 1225 ~(INT_CMD12DRE | INT_CMD12RBE |
1226 INT_CMD12CRE | INT_BUFRE));
1227 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
1228 } else if (state & INT_BUFRE) {
487d9fc5 1229 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
fdc50a94
YG		 1230 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
1231 } else if (state & INT_DTRANE) {
7a7eb328
GL		 1232 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1233 ~(INT_CMD12DRE | INT_CMD12RBE |
1234 INT_CMD12CRE | INT_DTRANE));
fdc50a94
YG		 1235 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
1236 } else if (state & INT_CMD12RBE) {
487d9fc5 1237 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
fdc50a94
YG		 1238 ~(INT_CMD12RBE | INT_CMD12CRE));
1239 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
fdc50a94 1240 } else {
faca6648 1241 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
487d9fc5 1242 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
fdc50a94
YG		 1243 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1244 err = 1;
1245 }
1246 if (err) {
aa0787a9 1247 host->sd_error = true;
e47bf32a 1248 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
fdc50a94 1249 }
f985da17
GL		 1250 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1251 if (!host->dma_active)
1252 return IRQ_WAKE_THREAD;
1253 else if (host->sd_error)
1254 mmcif_dma_complete(host);
1255 } else {
aa0787a9 1256 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
f985da17 1257 }
fdc50a94
YG		 1258
1259 return IRQ_HANDLED;
1260}
1261
f985da17
GL		 1262static void mmcif_timeout_work(struct work_struct *work)
1263{
1264 struct delayed_work *d = container_of(work, struct delayed_work, work);
1265 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1266 struct mmc_request *mrq = host->mrq;
1267
1268 if (host->dying)
1269 /* Don't run after mmc_remove_host() */
1270 return;
1271
1272 /*
1273 * Handle races with cancel_delayed_work(), unless
1274 * cancel_delayed_work_sync() is used
1275 */
1276 switch (host->wait_for) {
1277 case MMCIF_WAIT_FOR_CMD:
1278 mrq->cmd->error = sh_mmcif_error_manage(host);
1279 break;
1280 case MMCIF_WAIT_FOR_STOP:
1281 mrq->stop->error = sh_mmcif_error_manage(host);
1282 break;
1283 case MMCIF_WAIT_FOR_MREAD:
1284 case MMCIF_WAIT_FOR_MWRITE:
1285 case MMCIF_WAIT_FOR_READ:
1286 case MMCIF_WAIT_FOR_WRITE:
1287 case MMCIF_WAIT_FOR_READ_END:
1288 case MMCIF_WAIT_FOR_WRITE_END:
69983404 1289 mrq->data->error = sh_mmcif_error_manage(host);
f985da17
GL		 1290 break;
1291 default:
1292 BUG();
1293 }
1294
1295 host->state = STATE_IDLE;
1296 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
f985da17
GL		 1297 host->mrq = NULL;
1298 mmc_request_done(host->mmc, mrq);
1299}
1300
7d17baa0
GL		 1301static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1302{
1303 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
1304 struct mmc_host *mmc = host->mmc;
1305
1306 mmc_regulator_get_supply(mmc);
1307
bf68a812
GL		 1308 if (!pd)
1309 return;
1310
7d17baa0
GL		 1311 if (!mmc->ocr_avail)
1312 mmc->ocr_avail = pd->ocr;
1313 else if (pd->ocr)
1314 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1315}
1316
c3be1efd 1317static int sh_mmcif_probe(struct platform_device *pdev)
fdc50a94
YG		 1318{
1319 int ret = 0, irq[2];
1320 struct mmc_host *mmc;
e47bf32a 1321 struct sh_mmcif_host *host;
e1aae2eb 1322 struct sh_mmcif_plat_data *pd = pdev->dev.platform_data;
fdc50a94
YG		 1323 struct resource *res;
1324 void __iomem *reg;
2cd5b3e0 1325 const char *name;
fdc50a94
YG		 1326
1327 irq[0] = platform_get_irq(pdev, 0);
1328 irq[1] = platform_get_irq(pdev, 1);
2cd5b3e0 1329 if (irq[0] < 0) {
e47bf32a 1330 dev_err(&pdev->dev, "Get irq error\n");
fdc50a94
YG		 1331 return -ENXIO;
1332 }
1333 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1334 if (!res) {
1335 dev_err(&pdev->dev, "platform_get_resource error.\n");
1336 return -ENXIO;
1337 }
1338 reg = ioremap(res->start, resource_size(res));
1339 if (!reg) {
1340 dev_err(&pdev->dev, "ioremap error.\n");
1341 return -ENOMEM;
1342 }
e1aae2eb 1343
fdc50a94
YG		 1344 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1345 if (!mmc) {
1346 ret = -ENOMEM;
e1aae2eb 1347 goto ealloch;
fdc50a94
YG		 1348 }
1349 host = mmc_priv(mmc);
1350 host->mmc = mmc;
1351 host->addr = reg;
f9fd54f2 1352 host->timeout = msecs_to_jiffies(1000);
fdc50a94 1353
fdc50a94
YG		 1354 host->pd = pdev;
1355
3b0beafc 1356 spin_lock_init(&host->lock);
fdc50a94
YG		 1357
1358 mmc->ops = &sh_mmcif_ops;
7d17baa0
GL		 1359 sh_mmcif_init_ocr(host);
1360
a812ba0f 1361 mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY;
bf68a812 1362 if (pd && pd->caps)
fdc50a94 1363 mmc->caps |= pd->caps;
a782d688 1364 mmc->max_segs = 32;
fdc50a94 1365 mmc->max_blk_size = 512;
a782d688
GL		 1366 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1367 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
fdc50a94
YG		 1368 mmc->max_seg_size = mmc->max_req_size;
1369
fdc50a94 1370 platform_set_drvdata(pdev, host);
a782d688 1371
faca6648
GL		 1372 pm_runtime_enable(&pdev->dev);
1373 host->power = false;
1374
047a9ce7 1375 host->hclk = clk_get(&pdev->dev, NULL);
b289174f
GL		 1376 if (IS_ERR(host->hclk)) {
1377 ret = PTR_ERR(host->hclk);
047a9ce7 1378 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
b289174f
GL		 1379 goto eclkget;
1380 }
a6609267
GL		 1381 ret = sh_mmcif_clk_update(host);
1382 if (ret < 0)
1383 goto eclkupdate;
b289174f 1384
faca6648
GL		 1385 ret = pm_runtime_resume(&pdev->dev);
1386 if (ret < 0)
e1aae2eb 1387 goto eresume;
a782d688 1388
5ba85d95 1389 INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
fdc50a94 1390
b289174f 1391 sh_mmcif_sync_reset(host);
3b0beafc
GL		 1392 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1393
2cd5b3e0
SK		 1394 name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error";
1395 ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, name, host);
fdc50a94 1396 if (ret) {
2cd5b3e0 1397 dev_err(&pdev->dev, "request_irq error (%s)\n", name);
e1aae2eb 1398 goto ereqirq0;
fdc50a94 1399 }
2cd5b3e0
SK		 1400 if (irq[1] >= 0) {
1401 ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt,
1402 0, "sh_mmc:int", host);
1403 if (ret) {
1404 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1405 goto ereqirq1;
1406 }
fdc50a94
YG		 1407 }
1408
e480606a
GL		 1409 if (pd && pd->use_cd_gpio) {
1410 ret = mmc_gpio_request_cd(mmc, pd->cd_gpio);
1411 if (ret < 0)
1412 goto erqcd;
1413 }
1414
b289174f 1415 clk_disable(host->hclk);
5ba85d95
GL		 1416 ret = mmc_add_host(mmc);
1417 if (ret < 0)
e1aae2eb 1418 goto emmcaddh;
fdc50a94 1419
efe6a8ad
RW		 1420 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1421
e47bf32a
GL		 1422 dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1423 dev_dbg(&pdev->dev, "chip ver H'%04x\n",
487d9fc5 1424 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
fdc50a94
YG		 1425 return ret;
1426
e1aae2eb 1427emmcaddh:
e480606a 1428erqcd:
2cd5b3e0
SK		 1429 if (irq[1] >= 0)
1430 free_irq(irq[1], host);
e1aae2eb 1431ereqirq1:
5ba85d95 1432 free_irq(irq[0], host);
e1aae2eb 1433ereqirq0:
faca6648 1434 pm_runtime_suspend(&pdev->dev);
e1aae2eb 1435eresume:
fdc50a94 1436 clk_disable(host->hclk);
a6609267 1437eclkupdate:
b289174f 1438 clk_put(host->hclk);
e1aae2eb 1439eclkget:
b289174f 1440 pm_runtime_disable(&pdev->dev);
fdc50a94 1441 mmc_free_host(mmc);
e1aae2eb
GL		 1442ealloch:
1443 iounmap(reg);
fdc50a94
YG		 1444 return ret;
1445}
1446
6e0ee714 1447static int sh_mmcif_remove(struct platform_device *pdev)
fdc50a94
YG		 1448{
1449 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1450 int irq[2];
1451
f985da17 1452 host->dying = true;
b289174f 1453 clk_enable(host->hclk);
faca6648 1454 pm_runtime_get_sync(&pdev->dev);
fdc50a94 1455
efe6a8ad
RW		 1456 dev_pm_qos_hide_latency_limit(&pdev->dev);
1457
faca6648 1458 mmc_remove_host(host->mmc);
3b0beafc
GL		 1459 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1460
f985da17
GL		 1461 /*
1462 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1463 * mmc_remove_host() call above. But swapping order doesn't help either
1464 * (a query on the linux-mmc mailing list didn't bring any replies).
1465 */
1466 cancel_delayed_work_sync(&host->timeout_work);
1467
fdc50a94
YG		 1468 if (host->addr)
1469 iounmap(host->addr);
1470
aa0787a9
GL		 1471 irq[0] = platform_get_irq(pdev, 0);
1472 irq[1] = platform_get_irq(pdev, 1);
fdc50a94
YG		 1473
1474 free_irq(irq[0], host);
2cd5b3e0
SK		 1475 if (irq[1] >= 0)
1476 free_irq(irq[1], host);
fdc50a94 1477
aa0787a9
GL		 1478 platform_set_drvdata(pdev, NULL);
1479
a0d28ba0 1480 clk_disable(host->hclk);
fdc50a94 1481 mmc_free_host(host->mmc);
faca6648
GL		 1482 pm_runtime_put_sync(&pdev->dev);
1483 pm_runtime_disable(&pdev->dev);
fdc50a94
YG		 1484
1485 return 0;
1486}
1487
faca6648
GL		 1488#ifdef CONFIG_PM
1489static int sh_mmcif_suspend(struct device *dev)
1490{
b289174f 1491 struct sh_mmcif_host *host = dev_get_drvdata(dev);
faca6648
GL		 1492 int ret = mmc_suspend_host(host->mmc);
1493
b289174f 1494 if (!ret)
faca6648 1495 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
faca6648
GL		 1496
1497 return ret;
1498}
1499
1500static int sh_mmcif_resume(struct device *dev)
1501{
b289174f 1502 struct sh_mmcif_host *host = dev_get_drvdata(dev);
faca6648
GL		 1503
1504 return mmc_resume_host(host->mmc);
1505}
1506#else
1507#define sh_mmcif_suspend NULL
1508#define sh_mmcif_resume NULL
1509#endif /* CONFIG_PM */
1510
bf68a812
GL		 1511static const struct of_device_id mmcif_of_match[] = {
1512 { .compatible = "renesas,sh-mmcif" },
1513 { }
1514};
1515MODULE_DEVICE_TABLE(of, mmcif_of_match);
1516
faca6648
GL		 1517static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1518 .suspend = sh_mmcif_suspend,
1519 .resume = sh_mmcif_resume,
1520};
1521
fdc50a94
YG		 1522static struct platform_driver sh_mmcif_driver = {
1523 .probe = sh_mmcif_probe,
1524 .remove = sh_mmcif_remove,
1525 .driver = {
1526 .name = DRIVER_NAME,
faca6648 1527 .pm = &sh_mmcif_dev_pm_ops,
bf68a812
GL		 1528 .owner = THIS_MODULE,
1529 .of_match_table = mmcif_of_match,
fdc50a94
YG		 1530 },
1531};
1532
d1f81a64 1533module_platform_driver(sh_mmcif_driver);
fdc50a94
YG		 1534
1535MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1536MODULE_LICENSE("GPL");
aa0787a9 1537MODULE_ALIAS("platform:" DRIVER_NAME);
fdc50a94 1538MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");
Linux 6.x block layer and io_uring tree(s)