Commit | Line | Data |
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fdc50a94 YG |
1 | /* |
2 | * MMCIF eMMC driver. | |
3 | * | |
4 | * Copyright (C) 2010 Renesas Solutions Corp. | |
5 | * Yusuke Goda <yusuke.goda.sx@renesas.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License. | |
10 | * | |
11 | * | |
12 | * TODO | |
13 | * 1. DMA | |
14 | * 2. Power management | |
15 | * 3. Handle MMC errors better | |
16 | * | |
17 | */ | |
18 | ||
f985da17 GL |
19 | /* |
20 | * The MMCIF driver is now processing MMC requests asynchronously, according | |
21 | * to the Linux MMC API requirement. | |
22 | * | |
23 | * The MMCIF driver processes MMC requests in up to 3 stages: command, optional | |
24 | * data, and optional stop. To achieve asynchronous processing each of these | |
25 | * stages is split into two halves: a top and a bottom half. The top half | |
26 | * initialises the hardware, installs a timeout handler to handle completion | |
27 | * timeouts, and returns. In case of the command stage this immediately returns | |
28 | * control to the caller, leaving all further processing to run asynchronously. | |
29 | * All further request processing is performed by the bottom halves. | |
30 | * | |
31 | * The bottom half further consists of a "hard" IRQ handler, an IRQ handler | |
32 | * thread, a DMA completion callback, if DMA is used, a timeout work, and | |
33 | * request- and stage-specific handler methods. | |
34 | * | |
35 | * Each bottom half run begins with either a hardware interrupt, a DMA callback | |
36 | * invocation, or a timeout work run. In case of an error or a successful | |
37 | * processing completion, the MMC core is informed and the request processing is | |
38 | * finished. In case processing has to continue, i.e., if data has to be read | |
39 | * from or written to the card, or if a stop command has to be sent, the next | |
40 | * top half is called, which performs the necessary hardware handling and | |
41 | * reschedules the timeout work. This returns the driver state machine into the | |
42 | * bottom half waiting state. | |
43 | */ | |
44 | ||
86df1745 | 45 | #include <linux/bitops.h> |
aa0787a9 GL |
46 | #include <linux/clk.h> |
47 | #include <linux/completion.h> | |
e47bf32a | 48 | #include <linux/delay.h> |
fdc50a94 | 49 | #include <linux/dma-mapping.h> |
a782d688 | 50 | #include <linux/dmaengine.h> |
fdc50a94 YG |
51 | #include <linux/mmc/card.h> |
52 | #include <linux/mmc/core.h> | |
e47bf32a | 53 | #include <linux/mmc/host.h> |
fdc50a94 YG |
54 | #include <linux/mmc/mmc.h> |
55 | #include <linux/mmc/sdio.h> | |
fdc50a94 | 56 | #include <linux/mmc/sh_mmcif.h> |
e480606a | 57 | #include <linux/mmc/slot-gpio.h> |
bf68a812 | 58 | #include <linux/mod_devicetable.h> |
8047310e | 59 | #include <linux/mutex.h> |
a782d688 | 60 | #include <linux/pagemap.h> |
e47bf32a | 61 | #include <linux/platform_device.h> |
efe6a8ad | 62 | #include <linux/pm_qos.h> |
faca6648 | 63 | #include <linux/pm_runtime.h> |
d00cadac | 64 | #include <linux/sh_dma.h> |
3b0beafc | 65 | #include <linux/spinlock.h> |
88b47679 | 66 | #include <linux/module.h> |
fdc50a94 YG |
67 | |
68 | #define DRIVER_NAME "sh_mmcif" | |
69 | #define DRIVER_VERSION "2010-04-28" | |
70 | ||
fdc50a94 YG |
71 | /* CE_CMD_SET */ |
72 | #define CMD_MASK 0x3f000000 | |
73 | #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) | |
74 | #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ | |
75 | #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ | |
76 | #define CMD_SET_RBSY (1 << 21) /* R1b */ | |
77 | #define CMD_SET_CCSEN (1 << 20) | |
78 | #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ | |
79 | #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ | |
80 | #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ | |
81 | #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ | |
82 | #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ | |
83 | #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ | |
84 | #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ | |
85 | #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ | |
86 | #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ | |
87 | #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ | |
88 | #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ | |
89 | #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ | |
90 | #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ | |
91 | #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ | |
92 | #define CMD_SET_CCSH (1 << 5) | |
555061f9 | 93 | #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ |
fdc50a94 YG |
94 | #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ |
95 | #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ | |
96 | #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ | |
97 | ||
98 | /* CE_CMD_CTRL */ | |
99 | #define CMD_CTRL_BREAK (1 << 0) | |
100 | ||
101 | /* CE_BLOCK_SET */ | |
102 | #define BLOCK_SIZE_MASK 0x0000ffff | |
103 | ||
fdc50a94 YG |
104 | /* CE_INT */ |
105 | #define INT_CCSDE (1 << 29) | |
106 | #define INT_CMD12DRE (1 << 26) | |
107 | #define INT_CMD12RBE (1 << 25) | |
108 | #define INT_CMD12CRE (1 << 24) | |
109 | #define INT_DTRANE (1 << 23) | |
110 | #define INT_BUFRE (1 << 22) | |
111 | #define INT_BUFWEN (1 << 21) | |
112 | #define INT_BUFREN (1 << 20) | |
113 | #define INT_CCSRCV (1 << 19) | |
114 | #define INT_RBSYE (1 << 17) | |
115 | #define INT_CRSPE (1 << 16) | |
116 | #define INT_CMDVIO (1 << 15) | |
117 | #define INT_BUFVIO (1 << 14) | |
118 | #define INT_WDATERR (1 << 11) | |
119 | #define INT_RDATERR (1 << 10) | |
120 | #define INT_RIDXERR (1 << 9) | |
121 | #define INT_RSPERR (1 << 8) | |
122 | #define INT_CCSTO (1 << 5) | |
123 | #define INT_CRCSTO (1 << 4) | |
124 | #define INT_WDATTO (1 << 3) | |
125 | #define INT_RDATTO (1 << 2) | |
126 | #define INT_RBSYTO (1 << 1) | |
127 | #define INT_RSPTO (1 << 0) | |
128 | #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ | |
129 | INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ | |
130 | INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ | |
131 | INT_RDATTO | INT_RBSYTO | INT_RSPTO) | |
132 | ||
8af50750 GL |
133 | #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ |
134 | INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ | |
135 | INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) | |
136 | ||
967bcb77 GL |
137 | #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) |
138 | ||
fdc50a94 YG |
139 | /* CE_INT_MASK */ |
140 | #define MASK_ALL 0x00000000 | |
141 | #define MASK_MCCSDE (1 << 29) | |
142 | #define MASK_MCMD12DRE (1 << 26) | |
143 | #define MASK_MCMD12RBE (1 << 25) | |
144 | #define MASK_MCMD12CRE (1 << 24) | |
145 | #define MASK_MDTRANE (1 << 23) | |
146 | #define MASK_MBUFRE (1 << 22) | |
147 | #define MASK_MBUFWEN (1 << 21) | |
148 | #define MASK_MBUFREN (1 << 20) | |
149 | #define MASK_MCCSRCV (1 << 19) | |
150 | #define MASK_MRBSYE (1 << 17) | |
151 | #define MASK_MCRSPE (1 << 16) | |
152 | #define MASK_MCMDVIO (1 << 15) | |
153 | #define MASK_MBUFVIO (1 << 14) | |
154 | #define MASK_MWDATERR (1 << 11) | |
155 | #define MASK_MRDATERR (1 << 10) | |
156 | #define MASK_MRIDXERR (1 << 9) | |
157 | #define MASK_MRSPERR (1 << 8) | |
158 | #define MASK_MCCSTO (1 << 5) | |
159 | #define MASK_MCRCSTO (1 << 4) | |
160 | #define MASK_MWDATTO (1 << 3) | |
161 | #define MASK_MRDATTO (1 << 2) | |
162 | #define MASK_MRBSYTO (1 << 1) | |
163 | #define MASK_MRSPTO (1 << 0) | |
164 | ||
ee4b8887 GL |
165 | #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ |
166 | MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ | |
967bcb77 | 167 | MASK_MCRCSTO | MASK_MWDATTO | \ |
ee4b8887 GL |
168 | MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) |
169 | ||
8af50750 GL |
170 | #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ |
171 | MASK_MBUFREN | MASK_MBUFWEN | \ | |
172 | MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ | |
173 | MASK_MCMD12RBE | MASK_MCMD12CRE) | |
174 | ||
fdc50a94 YG |
175 | /* CE_HOST_STS1 */ |
176 | #define STS1_CMDSEQ (1 << 31) | |
177 | ||
178 | /* CE_HOST_STS2 */ | |
179 | #define STS2_CRCSTE (1 << 31) | |
180 | #define STS2_CRC16E (1 << 30) | |
181 | #define STS2_AC12CRCE (1 << 29) | |
182 | #define STS2_RSPCRC7E (1 << 28) | |
183 | #define STS2_CRCSTEBE (1 << 27) | |
184 | #define STS2_RDATEBE (1 << 26) | |
185 | #define STS2_AC12REBE (1 << 25) | |
186 | #define STS2_RSPEBE (1 << 24) | |
187 | #define STS2_AC12IDXE (1 << 23) | |
188 | #define STS2_RSPIDXE (1 << 22) | |
189 | #define STS2_CCSTO (1 << 15) | |
190 | #define STS2_RDATTO (1 << 14) | |
191 | #define STS2_DATBSYTO (1 << 13) | |
192 | #define STS2_CRCSTTO (1 << 12) | |
193 | #define STS2_AC12BSYTO (1 << 11) | |
194 | #define STS2_RSPBSYTO (1 << 10) | |
195 | #define STS2_AC12RSPTO (1 << 9) | |
196 | #define STS2_RSPTO (1 << 8) | |
197 | #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ | |
198 | STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) | |
199 | #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ | |
200 | STS2_DATBSYTO | STS2_CRCSTTO | \ | |
201 | STS2_AC12BSYTO | STS2_RSPBSYTO | \ | |
202 | STS2_AC12RSPTO | STS2_RSPTO) | |
203 | ||
fdc50a94 YG |
204 | #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ |
205 | #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ | |
206 | #define CLKDEV_INIT 400000 /* 400 KHz */ | |
207 | ||
3b0beafc GL |
208 | enum mmcif_state { |
209 | STATE_IDLE, | |
210 | STATE_REQUEST, | |
211 | STATE_IOS, | |
8047310e | 212 | STATE_TIMEOUT, |
3b0beafc GL |
213 | }; |
214 | ||
f985da17 GL |
215 | enum mmcif_wait_for { |
216 | MMCIF_WAIT_FOR_REQUEST, | |
217 | MMCIF_WAIT_FOR_CMD, | |
218 | MMCIF_WAIT_FOR_MREAD, | |
219 | MMCIF_WAIT_FOR_MWRITE, | |
220 | MMCIF_WAIT_FOR_READ, | |
221 | MMCIF_WAIT_FOR_WRITE, | |
222 | MMCIF_WAIT_FOR_READ_END, | |
223 | MMCIF_WAIT_FOR_WRITE_END, | |
224 | MMCIF_WAIT_FOR_STOP, | |
225 | }; | |
226 | ||
fdc50a94 YG |
227 | struct sh_mmcif_host { |
228 | struct mmc_host *mmc; | |
f985da17 | 229 | struct mmc_request *mrq; |
fdc50a94 | 230 | struct platform_device *pd; |
6aed678b | 231 | struct clk *clk; |
fdc50a94 | 232 | int bus_width; |
555061f9 | 233 | unsigned char timing; |
aa0787a9 | 234 | bool sd_error; |
f985da17 | 235 | bool dying; |
fdc50a94 YG |
236 | long timeout; |
237 | void __iomem *addr; | |
f985da17 | 238 | u32 *pio_ptr; |
ee4b8887 | 239 | spinlock_t lock; /* protect sh_mmcif_host::state */ |
3b0beafc | 240 | enum mmcif_state state; |
f985da17 GL |
241 | enum mmcif_wait_for wait_for; |
242 | struct delayed_work timeout_work; | |
243 | size_t blocksize; | |
244 | int sg_idx; | |
245 | int sg_blkidx; | |
faca6648 | 246 | bool power; |
c9b0cef2 | 247 | bool card_present; |
967bcb77 | 248 | bool ccs_enable; /* Command Completion Signal support */ |
6d6fd367 | 249 | bool clk_ctrl2_enable; |
8047310e | 250 | struct mutex thread_lock; |
fdc50a94 | 251 | |
a782d688 GL |
252 | /* DMA support */ |
253 | struct dma_chan *chan_rx; | |
254 | struct dma_chan *chan_tx; | |
255 | struct completion dma_complete; | |
f38f94c6 | 256 | bool dma_active; |
a782d688 | 257 | }; |
fdc50a94 | 258 | |
70830b41 KM |
259 | static const struct of_device_id mmcif_of_match[] = { |
260 | { .compatible = "renesas,sh-mmcif" }, | |
261 | { } | |
262 | }; | |
263 | MODULE_DEVICE_TABLE(of, mmcif_of_match); | |
264 | ||
585c3a5a KM |
265 | #define sh_mmcif_host_to_dev(host) (&host->pd->dev) |
266 | ||
fdc50a94 YG |
267 | static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, |
268 | unsigned int reg, u32 val) | |
269 | { | |
487d9fc5 | 270 | writel(val | readl(host->addr + reg), host->addr + reg); |
fdc50a94 YG |
271 | } |
272 | ||
273 | static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, | |
274 | unsigned int reg, u32 val) | |
275 | { | |
487d9fc5 | 276 | writel(~val & readl(host->addr + reg), host->addr + reg); |
fdc50a94 YG |
277 | } |
278 | ||
a782d688 GL |
279 | static void mmcif_dma_complete(void *arg) |
280 | { | |
281 | struct sh_mmcif_host *host = arg; | |
8047310e | 282 | struct mmc_request *mrq = host->mrq; |
585c3a5a | 283 | struct device *dev = sh_mmcif_host_to_dev(host); |
69983404 | 284 | |
585c3a5a | 285 | dev_dbg(dev, "Command completed\n"); |
a782d688 | 286 | |
8047310e | 287 | if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", |
585c3a5a | 288 | dev_name(dev))) |
a782d688 GL |
289 | return; |
290 | ||
a782d688 GL |
291 | complete(&host->dma_complete); |
292 | } | |
293 | ||
294 | static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) | |
295 | { | |
69983404 GL |
296 | struct mmc_data *data = host->mrq->data; |
297 | struct scatterlist *sg = data->sg; | |
a782d688 GL |
298 | struct dma_async_tx_descriptor *desc = NULL; |
299 | struct dma_chan *chan = host->chan_rx; | |
585c3a5a | 300 | struct device *dev = sh_mmcif_host_to_dev(host); |
a782d688 GL |
301 | dma_cookie_t cookie = -EINVAL; |
302 | int ret; | |
303 | ||
69983404 | 304 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, |
1ed828db | 305 | DMA_FROM_DEVICE); |
a782d688 | 306 | if (ret > 0) { |
f38f94c6 | 307 | host->dma_active = true; |
16052827 | 308 | desc = dmaengine_prep_slave_sg(chan, sg, ret, |
05f5799c | 309 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
a782d688 GL |
310 | } |
311 | ||
312 | if (desc) { | |
313 | desc->callback = mmcif_dma_complete; | |
314 | desc->callback_param = host; | |
a5ece7d2 LW |
315 | cookie = dmaengine_submit(desc); |
316 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); | |
317 | dma_async_issue_pending(chan); | |
a782d688 | 318 | } |
585c3a5a | 319 | dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", |
69983404 | 320 | __func__, data->sg_len, ret, cookie); |
a782d688 GL |
321 | |
322 | if (!desc) { | |
323 | /* DMA failed, fall back to PIO */ | |
324 | if (ret >= 0) | |
325 | ret = -EIO; | |
326 | host->chan_rx = NULL; | |
f38f94c6 | 327 | host->dma_active = false; |
a782d688 GL |
328 | dma_release_channel(chan); |
329 | /* Free the Tx channel too */ | |
330 | chan = host->chan_tx; | |
331 | if (chan) { | |
332 | host->chan_tx = NULL; | |
333 | dma_release_channel(chan); | |
334 | } | |
585c3a5a | 335 | dev_warn(dev, |
a782d688 GL |
336 | "DMA failed: %d, falling back to PIO\n", ret); |
337 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
338 | } | |
339 | ||
585c3a5a | 340 | dev_dbg(dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, |
69983404 | 341 | desc, cookie, data->sg_len); |
a782d688 GL |
342 | } |
343 | ||
344 | static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) | |
345 | { | |
69983404 GL |
346 | struct mmc_data *data = host->mrq->data; |
347 | struct scatterlist *sg = data->sg; | |
a782d688 GL |
348 | struct dma_async_tx_descriptor *desc = NULL; |
349 | struct dma_chan *chan = host->chan_tx; | |
585c3a5a | 350 | struct device *dev = sh_mmcif_host_to_dev(host); |
a782d688 GL |
351 | dma_cookie_t cookie = -EINVAL; |
352 | int ret; | |
353 | ||
69983404 | 354 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, |
1ed828db | 355 | DMA_TO_DEVICE); |
a782d688 | 356 | if (ret > 0) { |
f38f94c6 | 357 | host->dma_active = true; |
16052827 | 358 | desc = dmaengine_prep_slave_sg(chan, sg, ret, |
05f5799c | 359 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
a782d688 GL |
360 | } |
361 | ||
362 | if (desc) { | |
363 | desc->callback = mmcif_dma_complete; | |
364 | desc->callback_param = host; | |
a5ece7d2 LW |
365 | cookie = dmaengine_submit(desc); |
366 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); | |
367 | dma_async_issue_pending(chan); | |
a782d688 | 368 | } |
585c3a5a | 369 | dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", |
69983404 | 370 | __func__, data->sg_len, ret, cookie); |
a782d688 GL |
371 | |
372 | if (!desc) { | |
373 | /* DMA failed, fall back to PIO */ | |
374 | if (ret >= 0) | |
375 | ret = -EIO; | |
376 | host->chan_tx = NULL; | |
f38f94c6 | 377 | host->dma_active = false; |
a782d688 GL |
378 | dma_release_channel(chan); |
379 | /* Free the Rx channel too */ | |
380 | chan = host->chan_rx; | |
381 | if (chan) { | |
382 | host->chan_rx = NULL; | |
383 | dma_release_channel(chan); | |
384 | } | |
585c3a5a | 385 | dev_warn(dev, |
a782d688 GL |
386 | "DMA failed: %d, falling back to PIO\n", ret); |
387 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
388 | } | |
389 | ||
585c3a5a | 390 | dev_dbg(dev, "%s(): desc %p, cookie %d\n", __func__, |
a782d688 GL |
391 | desc, cookie); |
392 | } | |
393 | ||
e5a233cb LP |
394 | static struct dma_chan * |
395 | sh_mmcif_request_dma_one(struct sh_mmcif_host *host, | |
396 | struct sh_mmcif_plat_data *pdata, | |
397 | enum dma_transfer_direction direction) | |
a782d688 | 398 | { |
d25006e7 | 399 | struct dma_slave_config cfg = { 0, }; |
e5a233cb | 400 | struct dma_chan *chan; |
5f48dd06 | 401 | void *slave_data = NULL; |
e5a233cb | 402 | struct resource *res; |
585c3a5a | 403 | struct device *dev = sh_mmcif_host_to_dev(host); |
0e79f9ae GL |
404 | dma_cap_mask_t mask; |
405 | int ret; | |
a782d688 | 406 | |
e5a233cb LP |
407 | dma_cap_zero(mask); |
408 | dma_cap_set(DMA_SLAVE, mask); | |
409 | ||
410 | if (pdata) | |
5f48dd06 KM |
411 | slave_data = direction == DMA_MEM_TO_DEV ? |
412 | (void *)pdata->slave_id_tx : | |
413 | (void *)pdata->slave_id_rx; | |
e5a233cb LP |
414 | |
415 | chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, | |
585c3a5a | 416 | slave_data, dev, |
e5a233cb LP |
417 | direction == DMA_MEM_TO_DEV ? "tx" : "rx"); |
418 | ||
585c3a5a | 419 | dev_dbg(dev, "%s: %s: got channel %p\n", __func__, |
e5a233cb LP |
420 | direction == DMA_MEM_TO_DEV ? "TX" : "RX", chan); |
421 | ||
422 | if (!chan) | |
423 | return NULL; | |
424 | ||
425 | res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); | |
426 | ||
e5a233cb | 427 | cfg.direction = direction; |
d25006e7 | 428 | |
e36152aa | 429 | if (direction == DMA_DEV_TO_MEM) { |
d25006e7 | 430 | cfg.src_addr = res->start + MMCIF_CE_DATA; |
e36152aa LP |
431 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
432 | } else { | |
d25006e7 | 433 | cfg.dst_addr = res->start + MMCIF_CE_DATA; |
e36152aa LP |
434 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
435 | } | |
d25006e7 | 436 | |
e5a233cb LP |
437 | ret = dmaengine_slave_config(chan, &cfg); |
438 | if (ret < 0) { | |
439 | dma_release_channel(chan); | |
440 | return NULL; | |
441 | } | |
442 | ||
443 | return chan; | |
444 | } | |
445 | ||
446 | static void sh_mmcif_request_dma(struct sh_mmcif_host *host, | |
447 | struct sh_mmcif_plat_data *pdata) | |
448 | { | |
585c3a5a | 449 | struct device *dev = sh_mmcif_host_to_dev(host); |
f38f94c6 | 450 | host->dma_active = false; |
a782d688 | 451 | |
acd6d772 GL |
452 | if (pdata) { |
453 | if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) | |
454 | return; | |
585c3a5a | 455 | } else if (!dev->of_node) { |
0e79f9ae | 456 | return; |
acd6d772 | 457 | } |
a782d688 | 458 | |
0e79f9ae | 459 | /* We can only either use DMA for both Tx and Rx or not use it at all */ |
e5a233cb | 460 | host->chan_tx = sh_mmcif_request_dma_one(host, pdata, DMA_MEM_TO_DEV); |
0e79f9ae GL |
461 | if (!host->chan_tx) |
462 | return; | |
a782d688 | 463 | |
e5a233cb LP |
464 | host->chan_rx = sh_mmcif_request_dma_one(host, pdata, DMA_DEV_TO_MEM); |
465 | if (!host->chan_rx) { | |
466 | dma_release_channel(host->chan_tx); | |
467 | host->chan_tx = NULL; | |
468 | } | |
a782d688 GL |
469 | } |
470 | ||
471 | static void sh_mmcif_release_dma(struct sh_mmcif_host *host) | |
472 | { | |
473 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
474 | /* Descriptors are freed automatically */ | |
475 | if (host->chan_tx) { | |
476 | struct dma_chan *chan = host->chan_tx; | |
477 | host->chan_tx = NULL; | |
478 | dma_release_channel(chan); | |
479 | } | |
480 | if (host->chan_rx) { | |
481 | struct dma_chan *chan = host->chan_rx; | |
482 | host->chan_rx = NULL; | |
483 | dma_release_channel(chan); | |
484 | } | |
485 | ||
f38f94c6 | 486 | host->dma_active = false; |
a782d688 | 487 | } |
fdc50a94 YG |
488 | |
489 | static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) | |
490 | { | |
585c3a5a KM |
491 | struct device *dev = sh_mmcif_host_to_dev(host); |
492 | struct sh_mmcif_plat_data *p = dev->platform_data; | |
bf68a812 | 493 | bool sup_pclk = p ? p->sup_pclk : false; |
6aed678b | 494 | unsigned int current_clk = clk_get_rate(host->clk); |
fdc50a94 YG |
495 | |
496 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); | |
497 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); | |
498 | ||
499 | if (!clk) | |
500 | return; | |
6aed678b | 501 | if (sup_pclk && clk == current_clk) |
fdc50a94 YG |
502 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); |
503 | else | |
504 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & | |
6aed678b | 505 | ((fls(DIV_ROUND_UP(current_clk, |
f9388257 | 506 | clk) - 1) - 1) << 16)); |
fdc50a94 YG |
507 | |
508 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); | |
509 | } | |
510 | ||
511 | static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) | |
512 | { | |
513 | u32 tmp; | |
514 | ||
487d9fc5 | 515 | tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); |
fdc50a94 | 516 | |
487d9fc5 MD |
517 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); |
518 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); | |
967bcb77 GL |
519 | if (host->ccs_enable) |
520 | tmp |= SCCSTO_29; | |
6d6fd367 GL |
521 | if (host->clk_ctrl2_enable) |
522 | sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); | |
fdc50a94 | 523 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | |
967bcb77 | 524 | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); |
fdc50a94 YG |
525 | /* byte swap on */ |
526 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); | |
527 | } | |
528 | ||
529 | static int sh_mmcif_error_manage(struct sh_mmcif_host *host) | |
530 | { | |
585c3a5a | 531 | struct device *dev = sh_mmcif_host_to_dev(host); |
fdc50a94 | 532 | u32 state1, state2; |
ee4b8887 | 533 | int ret, timeout; |
fdc50a94 | 534 | |
aa0787a9 | 535 | host->sd_error = false; |
fdc50a94 | 536 | |
487d9fc5 MD |
537 | state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); |
538 | state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); | |
585c3a5a KM |
539 | dev_dbg(dev, "ERR HOST_STS1 = %08x\n", state1); |
540 | dev_dbg(dev, "ERR HOST_STS2 = %08x\n", state2); | |
fdc50a94 YG |
541 | |
542 | if (state1 & STS1_CMDSEQ) { | |
543 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); | |
544 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); | |
ee4b8887 | 545 | for (timeout = 10000000; timeout; timeout--) { |
487d9fc5 | 546 | if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) |
ee4b8887 | 547 | & STS1_CMDSEQ)) |
fdc50a94 YG |
548 | break; |
549 | mdelay(1); | |
550 | } | |
ee4b8887 | 551 | if (!timeout) { |
585c3a5a | 552 | dev_err(dev, |
ee4b8887 GL |
553 | "Forced end of command sequence timeout err\n"); |
554 | return -EIO; | |
555 | } | |
fdc50a94 | 556 | sh_mmcif_sync_reset(host); |
585c3a5a | 557 | dev_dbg(dev, "Forced end of command sequence\n"); |
fdc50a94 YG |
558 | return -EIO; |
559 | } | |
560 | ||
561 | if (state2 & STS2_CRC_ERR) { | |
585c3a5a | 562 | dev_err(dev, " CRC error: state %u, wait %u\n", |
e475b270 | 563 | host->state, host->wait_for); |
fdc50a94 YG |
564 | ret = -EIO; |
565 | } else if (state2 & STS2_TIMEOUT_ERR) { | |
585c3a5a | 566 | dev_err(dev, " Timeout: state %u, wait %u\n", |
e475b270 | 567 | host->state, host->wait_for); |
fdc50a94 YG |
568 | ret = -ETIMEDOUT; |
569 | } else { | |
585c3a5a | 570 | dev_dbg(dev, " End/Index error: state %u, wait %u\n", |
e475b270 | 571 | host->state, host->wait_for); |
fdc50a94 YG |
572 | ret = -EIO; |
573 | } | |
574 | return ret; | |
575 | } | |
576 | ||
f985da17 | 577 | static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) |
fdc50a94 | 578 | { |
f985da17 GL |
579 | struct mmc_data *data = host->mrq->data; |
580 | ||
581 | host->sg_blkidx += host->blocksize; | |
582 | ||
583 | /* data->sg->length must be a multiple of host->blocksize? */ | |
584 | BUG_ON(host->sg_blkidx > data->sg->length); | |
585 | ||
586 | if (host->sg_blkidx == data->sg->length) { | |
587 | host->sg_blkidx = 0; | |
588 | if (++host->sg_idx < data->sg_len) | |
589 | host->pio_ptr = sg_virt(++data->sg); | |
590 | } else { | |
591 | host->pio_ptr = p; | |
592 | } | |
593 | ||
99eb9d8d | 594 | return host->sg_idx != data->sg_len; |
f985da17 GL |
595 | } |
596 | ||
597 | static void sh_mmcif_single_read(struct sh_mmcif_host *host, | |
598 | struct mmc_request *mrq) | |
599 | { | |
600 | host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & | |
601 | BLOCK_SIZE_MASK) + 3; | |
602 | ||
603 | host->wait_for = MMCIF_WAIT_FOR_READ; | |
fdc50a94 | 604 | |
fdc50a94 YG |
605 | /* buf read enable */ |
606 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); | |
f985da17 GL |
607 | } |
608 | ||
609 | static bool sh_mmcif_read_block(struct sh_mmcif_host *host) | |
610 | { | |
585c3a5a | 611 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
612 | struct mmc_data *data = host->mrq->data; |
613 | u32 *p = sg_virt(data->sg); | |
614 | int i; | |
615 | ||
616 | if (host->sd_error) { | |
617 | data->error = sh_mmcif_error_manage(host); | |
585c3a5a | 618 | dev_dbg(dev, "%s(): %d\n", __func__, data->error); |
f985da17 GL |
619 | return false; |
620 | } | |
621 | ||
622 | for (i = 0; i < host->blocksize / 4; i++) | |
487d9fc5 | 623 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); |
fdc50a94 YG |
624 | |
625 | /* buffer read end */ | |
626 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); | |
f985da17 | 627 | host->wait_for = MMCIF_WAIT_FOR_READ_END; |
fdc50a94 | 628 | |
f985da17 | 629 | return true; |
fdc50a94 YG |
630 | } |
631 | ||
f985da17 GL |
632 | static void sh_mmcif_multi_read(struct sh_mmcif_host *host, |
633 | struct mmc_request *mrq) | |
fdc50a94 YG |
634 | { |
635 | struct mmc_data *data = mrq->data; | |
f985da17 GL |
636 | |
637 | if (!data->sg_len || !data->sg->length) | |
638 | return; | |
639 | ||
640 | host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & | |
641 | BLOCK_SIZE_MASK; | |
642 | ||
643 | host->wait_for = MMCIF_WAIT_FOR_MREAD; | |
644 | host->sg_idx = 0; | |
645 | host->sg_blkidx = 0; | |
646 | host->pio_ptr = sg_virt(data->sg); | |
5df460b1 | 647 | |
f985da17 GL |
648 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
649 | } | |
650 | ||
651 | static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) | |
652 | { | |
585c3a5a | 653 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
654 | struct mmc_data *data = host->mrq->data; |
655 | u32 *p = host->pio_ptr; | |
656 | int i; | |
657 | ||
658 | if (host->sd_error) { | |
659 | data->error = sh_mmcif_error_manage(host); | |
585c3a5a | 660 | dev_dbg(dev, "%s(): %d\n", __func__, data->error); |
f985da17 | 661 | return false; |
fdc50a94 | 662 | } |
f985da17 GL |
663 | |
664 | BUG_ON(!data->sg->length); | |
665 | ||
666 | for (i = 0; i < host->blocksize / 4; i++) | |
667 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); | |
668 | ||
669 | if (!sh_mmcif_next_block(host, p)) | |
670 | return false; | |
671 | ||
f985da17 GL |
672 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
673 | ||
674 | return true; | |
fdc50a94 YG |
675 | } |
676 | ||
f985da17 | 677 | static void sh_mmcif_single_write(struct sh_mmcif_host *host, |
fdc50a94 YG |
678 | struct mmc_request *mrq) |
679 | { | |
f985da17 GL |
680 | host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
681 | BLOCK_SIZE_MASK) + 3; | |
fdc50a94 | 682 | |
f985da17 | 683 | host->wait_for = MMCIF_WAIT_FOR_WRITE; |
fdc50a94 YG |
684 | |
685 | /* buf write enable */ | |
f985da17 GL |
686 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
687 | } | |
688 | ||
689 | static bool sh_mmcif_write_block(struct sh_mmcif_host *host) | |
690 | { | |
585c3a5a | 691 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
692 | struct mmc_data *data = host->mrq->data; |
693 | u32 *p = sg_virt(data->sg); | |
694 | int i; | |
695 | ||
696 | if (host->sd_error) { | |
697 | data->error = sh_mmcif_error_manage(host); | |
585c3a5a | 698 | dev_dbg(dev, "%s(): %d\n", __func__, data->error); |
f985da17 GL |
699 | return false; |
700 | } | |
701 | ||
702 | for (i = 0; i < host->blocksize / 4; i++) | |
487d9fc5 | 703 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); |
fdc50a94 YG |
704 | |
705 | /* buffer write end */ | |
706 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); | |
f985da17 | 707 | host->wait_for = MMCIF_WAIT_FOR_WRITE_END; |
fdc50a94 | 708 | |
f985da17 | 709 | return true; |
fdc50a94 YG |
710 | } |
711 | ||
f985da17 GL |
712 | static void sh_mmcif_multi_write(struct sh_mmcif_host *host, |
713 | struct mmc_request *mrq) | |
fdc50a94 YG |
714 | { |
715 | struct mmc_data *data = mrq->data; | |
fdc50a94 | 716 | |
f985da17 GL |
717 | if (!data->sg_len || !data->sg->length) |
718 | return; | |
fdc50a94 | 719 | |
f985da17 GL |
720 | host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
721 | BLOCK_SIZE_MASK; | |
fdc50a94 | 722 | |
f985da17 GL |
723 | host->wait_for = MMCIF_WAIT_FOR_MWRITE; |
724 | host->sg_idx = 0; | |
725 | host->sg_blkidx = 0; | |
726 | host->pio_ptr = sg_virt(data->sg); | |
5df460b1 | 727 | |
f985da17 GL |
728 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
729 | } | |
fdc50a94 | 730 | |
f985da17 GL |
731 | static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) |
732 | { | |
585c3a5a | 733 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
734 | struct mmc_data *data = host->mrq->data; |
735 | u32 *p = host->pio_ptr; | |
736 | int i; | |
737 | ||
738 | if (host->sd_error) { | |
739 | data->error = sh_mmcif_error_manage(host); | |
585c3a5a | 740 | dev_dbg(dev, "%s(): %d\n", __func__, data->error); |
f985da17 | 741 | return false; |
fdc50a94 | 742 | } |
f985da17 GL |
743 | |
744 | BUG_ON(!data->sg->length); | |
745 | ||
746 | for (i = 0; i < host->blocksize / 4; i++) | |
747 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); | |
748 | ||
749 | if (!sh_mmcif_next_block(host, p)) | |
750 | return false; | |
751 | ||
f985da17 GL |
752 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
753 | ||
754 | return true; | |
fdc50a94 YG |
755 | } |
756 | ||
757 | static void sh_mmcif_get_response(struct sh_mmcif_host *host, | |
758 | struct mmc_command *cmd) | |
759 | { | |
760 | if (cmd->flags & MMC_RSP_136) { | |
487d9fc5 MD |
761 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); |
762 | cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); | |
763 | cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); | |
764 | cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); | |
fdc50a94 | 765 | } else |
487d9fc5 | 766 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); |
fdc50a94 YG |
767 | } |
768 | ||
769 | static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, | |
770 | struct mmc_command *cmd) | |
771 | { | |
487d9fc5 | 772 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); |
fdc50a94 YG |
773 | } |
774 | ||
775 | static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, | |
69983404 | 776 | struct mmc_request *mrq) |
fdc50a94 | 777 | { |
585c3a5a | 778 | struct device *dev = sh_mmcif_host_to_dev(host); |
69983404 GL |
779 | struct mmc_data *data = mrq->data; |
780 | struct mmc_command *cmd = mrq->cmd; | |
781 | u32 opc = cmd->opcode; | |
fdc50a94 YG |
782 | u32 tmp = 0; |
783 | ||
784 | /* Response Type check */ | |
785 | switch (mmc_resp_type(cmd)) { | |
786 | case MMC_RSP_NONE: | |
787 | tmp |= CMD_SET_RTYP_NO; | |
788 | break; | |
789 | case MMC_RSP_R1: | |
790 | case MMC_RSP_R1B: | |
791 | case MMC_RSP_R3: | |
792 | tmp |= CMD_SET_RTYP_6B; | |
793 | break; | |
794 | case MMC_RSP_R2: | |
795 | tmp |= CMD_SET_RTYP_17B; | |
796 | break; | |
797 | default: | |
585c3a5a | 798 | dev_err(dev, "Unsupported response type.\n"); |
fdc50a94 YG |
799 | break; |
800 | } | |
801 | switch (opc) { | |
802 | /* RBSY */ | |
a812ba0f | 803 | case MMC_SLEEP_AWAKE: |
fdc50a94 YG |
804 | case MMC_SWITCH: |
805 | case MMC_STOP_TRANSMISSION: | |
806 | case MMC_SET_WRITE_PROT: | |
807 | case MMC_CLR_WRITE_PROT: | |
808 | case MMC_ERASE: | |
fdc50a94 YG |
809 | tmp |= CMD_SET_RBSY; |
810 | break; | |
811 | } | |
812 | /* WDAT / DATW */ | |
69983404 | 813 | if (data) { |
fdc50a94 YG |
814 | tmp |= CMD_SET_WDAT; |
815 | switch (host->bus_width) { | |
816 | case MMC_BUS_WIDTH_1: | |
817 | tmp |= CMD_SET_DATW_1; | |
818 | break; | |
819 | case MMC_BUS_WIDTH_4: | |
820 | tmp |= CMD_SET_DATW_4; | |
821 | break; | |
822 | case MMC_BUS_WIDTH_8: | |
823 | tmp |= CMD_SET_DATW_8; | |
824 | break; | |
825 | default: | |
585c3a5a | 826 | dev_err(dev, "Unsupported bus width.\n"); |
fdc50a94 YG |
827 | break; |
828 | } | |
555061f9 | 829 | switch (host->timing) { |
4039ff47 | 830 | case MMC_TIMING_MMC_DDR52: |
555061f9 TK |
831 | /* |
832 | * MMC core will only set this timing, if the host | |
4039ff47 SJ |
833 | * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR |
834 | * capability. MMCIF implementations with this | |
835 | * capability, e.g. sh73a0, will have to set it | |
836 | * in their platform data. | |
555061f9 TK |
837 | */ |
838 | tmp |= CMD_SET_DARS; | |
839 | break; | |
840 | } | |
fdc50a94 YG |
841 | } |
842 | /* DWEN */ | |
843 | if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) | |
844 | tmp |= CMD_SET_DWEN; | |
845 | /* CMLTE/CMD12EN */ | |
846 | if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { | |
847 | tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; | |
848 | sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, | |
69983404 | 849 | data->blocks << 16); |
fdc50a94 YG |
850 | } |
851 | /* RIDXC[1:0] check bits */ | |
852 | if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || | |
853 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
854 | tmp |= CMD_SET_RIDXC_BITS; | |
855 | /* RCRC7C[1:0] check bits */ | |
856 | if (opc == MMC_SEND_OP_COND) | |
857 | tmp |= CMD_SET_CRC7C_BITS; | |
858 | /* RCRC7C[1:0] internal CRC7 */ | |
859 | if (opc == MMC_ALL_SEND_CID || | |
860 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
861 | tmp |= CMD_SET_CRC7C_INTERNAL; | |
862 | ||
69983404 | 863 | return (opc << 24) | tmp; |
fdc50a94 YG |
864 | } |
865 | ||
e47bf32a | 866 | static int sh_mmcif_data_trans(struct sh_mmcif_host *host, |
f985da17 | 867 | struct mmc_request *mrq, u32 opc) |
fdc50a94 | 868 | { |
585c3a5a KM |
869 | struct device *dev = sh_mmcif_host_to_dev(host); |
870 | ||
fdc50a94 YG |
871 | switch (opc) { |
872 | case MMC_READ_MULTIPLE_BLOCK: | |
f985da17 GL |
873 | sh_mmcif_multi_read(host, mrq); |
874 | return 0; | |
fdc50a94 | 875 | case MMC_WRITE_MULTIPLE_BLOCK: |
f985da17 GL |
876 | sh_mmcif_multi_write(host, mrq); |
877 | return 0; | |
fdc50a94 | 878 | case MMC_WRITE_BLOCK: |
f985da17 GL |
879 | sh_mmcif_single_write(host, mrq); |
880 | return 0; | |
fdc50a94 YG |
881 | case MMC_READ_SINGLE_BLOCK: |
882 | case MMC_SEND_EXT_CSD: | |
f985da17 GL |
883 | sh_mmcif_single_read(host, mrq); |
884 | return 0; | |
fdc50a94 | 885 | default: |
585c3a5a | 886 | dev_err(dev, "Unsupported CMD%d\n", opc); |
ee4b8887 | 887 | return -EINVAL; |
fdc50a94 | 888 | } |
fdc50a94 YG |
889 | } |
890 | ||
891 | static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, | |
ee4b8887 | 892 | struct mmc_request *mrq) |
fdc50a94 | 893 | { |
ee4b8887 | 894 | struct mmc_command *cmd = mrq->cmd; |
f985da17 GL |
895 | u32 opc = cmd->opcode; |
896 | u32 mask; | |
dbb42d96 | 897 | unsigned long flags; |
fdc50a94 | 898 | |
fdc50a94 | 899 | switch (opc) { |
ee4b8887 | 900 | /* response busy check */ |
a812ba0f | 901 | case MMC_SLEEP_AWAKE: |
fdc50a94 YG |
902 | case MMC_SWITCH: |
903 | case MMC_STOP_TRANSMISSION: | |
904 | case MMC_SET_WRITE_PROT: | |
905 | case MMC_CLR_WRITE_PROT: | |
906 | case MMC_ERASE: | |
ee4b8887 | 907 | mask = MASK_START_CMD | MASK_MRBSYE; |
fdc50a94 YG |
908 | break; |
909 | default: | |
ee4b8887 | 910 | mask = MASK_START_CMD | MASK_MCRSPE; |
fdc50a94 YG |
911 | break; |
912 | } | |
fdc50a94 | 913 | |
967bcb77 GL |
914 | if (host->ccs_enable) |
915 | mask |= MASK_MCCSTO; | |
916 | ||
69983404 | 917 | if (mrq->data) { |
487d9fc5 MD |
918 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); |
919 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, | |
920 | mrq->data->blksz); | |
fdc50a94 | 921 | } |
69983404 | 922 | opc = sh_mmcif_set_cmd(host, mrq); |
fdc50a94 | 923 | |
967bcb77 GL |
924 | if (host->ccs_enable) |
925 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); | |
926 | else | |
927 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); | |
487d9fc5 | 928 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); |
fdc50a94 | 929 | /* set arg */ |
487d9fc5 | 930 | sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); |
fdc50a94 | 931 | /* set cmd */ |
dbb42d96 | 932 | spin_lock_irqsave(&host->lock, flags); |
487d9fc5 | 933 | sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); |
fdc50a94 | 934 | |
f985da17 GL |
935 | host->wait_for = MMCIF_WAIT_FOR_CMD; |
936 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
dbb42d96 | 937 | spin_unlock_irqrestore(&host->lock, flags); |
fdc50a94 YG |
938 | } |
939 | ||
940 | static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, | |
ee4b8887 | 941 | struct mmc_request *mrq) |
fdc50a94 | 942 | { |
585c3a5a KM |
943 | struct device *dev = sh_mmcif_host_to_dev(host); |
944 | ||
69983404 GL |
945 | switch (mrq->cmd->opcode) { |
946 | case MMC_READ_MULTIPLE_BLOCK: | |
fdc50a94 | 947 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); |
69983404 GL |
948 | break; |
949 | case MMC_WRITE_MULTIPLE_BLOCK: | |
fdc50a94 | 950 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); |
69983404 GL |
951 | break; |
952 | default: | |
585c3a5a | 953 | dev_err(dev, "unsupported stop cmd\n"); |
69983404 | 954 | mrq->stop->error = sh_mmcif_error_manage(host); |
fdc50a94 YG |
955 | return; |
956 | } | |
957 | ||
f985da17 | 958 | host->wait_for = MMCIF_WAIT_FOR_STOP; |
fdc50a94 YG |
959 | } |
960 | ||
961 | static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
962 | { | |
963 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
585c3a5a | 964 | struct device *dev = sh_mmcif_host_to_dev(host); |
3b0beafc GL |
965 | unsigned long flags; |
966 | ||
967 | spin_lock_irqsave(&host->lock, flags); | |
968 | if (host->state != STATE_IDLE) { | |
585c3a5a KM |
969 | dev_dbg(dev, "%s() rejected, state %u\n", |
970 | __func__, host->state); | |
3b0beafc GL |
971 | spin_unlock_irqrestore(&host->lock, flags); |
972 | mrq->cmd->error = -EAGAIN; | |
973 | mmc_request_done(mmc, mrq); | |
974 | return; | |
975 | } | |
976 | ||
977 | host->state = STATE_REQUEST; | |
978 | spin_unlock_irqrestore(&host->lock, flags); | |
fdc50a94 YG |
979 | |
980 | switch (mrq->cmd->opcode) { | |
981 | /* MMCIF does not support SD/SDIO command */ | |
7541ca98 LP |
982 | case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ |
983 | case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ | |
984 | if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) | |
985 | break; | |
fdc50a94 | 986 | case MMC_APP_CMD: |
92ff0c5b | 987 | case SD_IO_RW_DIRECT: |
3b0beafc | 988 | host->state = STATE_IDLE; |
fdc50a94 YG |
989 | mrq->cmd->error = -ETIMEDOUT; |
990 | mmc_request_done(mmc, mrq); | |
991 | return; | |
fdc50a94 YG |
992 | default: |
993 | break; | |
994 | } | |
f985da17 GL |
995 | |
996 | host->mrq = mrq; | |
fdc50a94 | 997 | |
f985da17 | 998 | sh_mmcif_start_cmd(host, mrq); |
fdc50a94 YG |
999 | } |
1000 | ||
9bb09a30 | 1001 | static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) |
a6609267 | 1002 | { |
9bb09a30 | 1003 | unsigned int clk = clk_get_rate(host->clk); |
a6609267 | 1004 | |
9bb09a30 KM |
1005 | host->mmc->f_max = clk / 2; |
1006 | host->mmc->f_min = clk / 512; | |
a6609267 GL |
1007 | } |
1008 | ||
7d17baa0 GL |
1009 | static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) |
1010 | { | |
7d17baa0 GL |
1011 | struct mmc_host *mmc = host->mmc; |
1012 | ||
7d17baa0 GL |
1013 | if (!IS_ERR(mmc->supply.vmmc)) |
1014 | /* Errors ignored... */ | |
1015 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, | |
1016 | ios->power_mode ? ios->vdd : 0); | |
1017 | } | |
1018 | ||
fdc50a94 YG |
1019 | static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
1020 | { | |
1021 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
585c3a5a | 1022 | struct device *dev = sh_mmcif_host_to_dev(host); |
3b0beafc GL |
1023 | unsigned long flags; |
1024 | ||
1025 | spin_lock_irqsave(&host->lock, flags); | |
1026 | if (host->state != STATE_IDLE) { | |
585c3a5a KM |
1027 | dev_dbg(dev, "%s() rejected, state %u\n", |
1028 | __func__, host->state); | |
3b0beafc GL |
1029 | spin_unlock_irqrestore(&host->lock, flags); |
1030 | return; | |
1031 | } | |
1032 | ||
1033 | host->state = STATE_IOS; | |
1034 | spin_unlock_irqrestore(&host->lock, flags); | |
fdc50a94 | 1035 | |
f5e0cec4 | 1036 | if (ios->power_mode == MMC_POWER_UP) { |
c9b0cef2 | 1037 | if (!host->card_present) { |
faca6648 | 1038 | /* See if we also get DMA */ |
585c3a5a | 1039 | sh_mmcif_request_dma(host, dev->platform_data); |
c9b0cef2 | 1040 | host->card_present = true; |
faca6648 | 1041 | } |
7d17baa0 | 1042 | sh_mmcif_set_power(host, ios); |
f5e0cec4 | 1043 | } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { |
fdc50a94 YG |
1044 | /* clock stop */ |
1045 | sh_mmcif_clock_control(host, 0); | |
faca6648 | 1046 | if (ios->power_mode == MMC_POWER_OFF) { |
c9b0cef2 | 1047 | if (host->card_present) { |
faca6648 | 1048 | sh_mmcif_release_dma(host); |
c9b0cef2 | 1049 | host->card_present = false; |
faca6648 | 1050 | } |
c9b0cef2 GL |
1051 | } |
1052 | if (host->power) { | |
585c3a5a | 1053 | pm_runtime_put_sync(dev); |
6aed678b | 1054 | clk_disable_unprepare(host->clk); |
c9b0cef2 | 1055 | host->power = false; |
7d17baa0 GL |
1056 | if (ios->power_mode == MMC_POWER_OFF) |
1057 | sh_mmcif_set_power(host, ios); | |
faca6648 | 1058 | } |
3b0beafc | 1059 | host->state = STATE_IDLE; |
fdc50a94 | 1060 | return; |
fdc50a94 YG |
1061 | } |
1062 | ||
c9b0cef2 GL |
1063 | if (ios->clock) { |
1064 | if (!host->power) { | |
9bb09a30 KM |
1065 | clk_prepare_enable(host->clk); |
1066 | ||
585c3a5a | 1067 | pm_runtime_get_sync(dev); |
c9b0cef2 GL |
1068 | host->power = true; |
1069 | sh_mmcif_sync_reset(host); | |
1070 | } | |
fdc50a94 | 1071 | sh_mmcif_clock_control(host, ios->clock); |
c9b0cef2 | 1072 | } |
fdc50a94 | 1073 | |
555061f9 | 1074 | host->timing = ios->timing; |
fdc50a94 | 1075 | host->bus_width = ios->bus_width; |
3b0beafc | 1076 | host->state = STATE_IDLE; |
fdc50a94 YG |
1077 | } |
1078 | ||
777271d0 AH |
1079 | static int sh_mmcif_get_cd(struct mmc_host *mmc) |
1080 | { | |
1081 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
585c3a5a KM |
1082 | struct device *dev = sh_mmcif_host_to_dev(host); |
1083 | struct sh_mmcif_plat_data *p = dev->platform_data; | |
e480606a GL |
1084 | int ret = mmc_gpio_get_cd(mmc); |
1085 | ||
1086 | if (ret >= 0) | |
1087 | return ret; | |
777271d0 | 1088 | |
bf68a812 | 1089 | if (!p || !p->get_cd) |
777271d0 AH |
1090 | return -ENOSYS; |
1091 | else | |
1092 | return p->get_cd(host->pd); | |
1093 | } | |
1094 | ||
fdc50a94 YG |
1095 | static struct mmc_host_ops sh_mmcif_ops = { |
1096 | .request = sh_mmcif_request, | |
1097 | .set_ios = sh_mmcif_set_ios, | |
777271d0 | 1098 | .get_cd = sh_mmcif_get_cd, |
fdc50a94 YG |
1099 | }; |
1100 | ||
f985da17 GL |
1101 | static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) |
1102 | { | |
1103 | struct mmc_command *cmd = host->mrq->cmd; | |
69983404 | 1104 | struct mmc_data *data = host->mrq->data; |
585c3a5a | 1105 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
1106 | long time; |
1107 | ||
1108 | if (host->sd_error) { | |
1109 | switch (cmd->opcode) { | |
1110 | case MMC_ALL_SEND_CID: | |
1111 | case MMC_SELECT_CARD: | |
1112 | case MMC_APP_CMD: | |
1113 | cmd->error = -ETIMEDOUT; | |
f985da17 GL |
1114 | break; |
1115 | default: | |
1116 | cmd->error = sh_mmcif_error_manage(host); | |
f985da17 GL |
1117 | break; |
1118 | } | |
585c3a5a | 1119 | dev_dbg(dev, "CMD%d error %d\n", |
e475b270 | 1120 | cmd->opcode, cmd->error); |
aba9d646 | 1121 | host->sd_error = false; |
f985da17 GL |
1122 | return false; |
1123 | } | |
1124 | if (!(cmd->flags & MMC_RSP_PRESENT)) { | |
1125 | cmd->error = 0; | |
1126 | return false; | |
1127 | } | |
1128 | ||
1129 | sh_mmcif_get_response(host, cmd); | |
1130 | ||
69983404 | 1131 | if (!data) |
f985da17 GL |
1132 | return false; |
1133 | ||
90f1cb43 GL |
1134 | /* |
1135 | * Completion can be signalled from DMA callback and error, so, have to | |
1136 | * reset here, before setting .dma_active | |
1137 | */ | |
1138 | init_completion(&host->dma_complete); | |
1139 | ||
69983404 | 1140 | if (data->flags & MMC_DATA_READ) { |
f985da17 GL |
1141 | if (host->chan_rx) |
1142 | sh_mmcif_start_dma_rx(host); | |
1143 | } else { | |
1144 | if (host->chan_tx) | |
1145 | sh_mmcif_start_dma_tx(host); | |
1146 | } | |
1147 | ||
1148 | if (!host->dma_active) { | |
69983404 | 1149 | data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); |
99eb9d8d | 1150 | return !data->error; |
f985da17 GL |
1151 | } |
1152 | ||
1153 | /* Running in the IRQ thread, can sleep */ | |
1154 | time = wait_for_completion_interruptible_timeout(&host->dma_complete, | |
1155 | host->timeout); | |
eae30983 TK |
1156 | |
1157 | if (data->flags & MMC_DATA_READ) | |
1158 | dma_unmap_sg(host->chan_rx->device->dev, | |
1159 | data->sg, data->sg_len, | |
1160 | DMA_FROM_DEVICE); | |
1161 | else | |
1162 | dma_unmap_sg(host->chan_tx->device->dev, | |
1163 | data->sg, data->sg_len, | |
1164 | DMA_TO_DEVICE); | |
1165 | ||
f985da17 GL |
1166 | if (host->sd_error) { |
1167 | dev_err(host->mmc->parent, | |
1168 | "Error IRQ while waiting for DMA completion!\n"); | |
1169 | /* Woken up by an error IRQ: abort DMA */ | |
69983404 | 1170 | data->error = sh_mmcif_error_manage(host); |
f985da17 | 1171 | } else if (!time) { |
e475b270 | 1172 | dev_err(host->mmc->parent, "DMA timeout!\n"); |
69983404 | 1173 | data->error = -ETIMEDOUT; |
f985da17 | 1174 | } else if (time < 0) { |
e475b270 TK |
1175 | dev_err(host->mmc->parent, |
1176 | "wait_for_completion_...() error %ld!\n", time); | |
69983404 | 1177 | data->error = time; |
f985da17 GL |
1178 | } |
1179 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, | |
1180 | BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
1181 | host->dma_active = false; | |
1182 | ||
eae30983 | 1183 | if (data->error) { |
69983404 | 1184 | data->bytes_xfered = 0; |
eae30983 TK |
1185 | /* Abort DMA */ |
1186 | if (data->flags & MMC_DATA_READ) | |
1187 | dmaengine_terminate_all(host->chan_rx); | |
1188 | else | |
1189 | dmaengine_terminate_all(host->chan_tx); | |
1190 | } | |
f985da17 GL |
1191 | |
1192 | return false; | |
1193 | } | |
1194 | ||
1195 | static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) | |
1196 | { | |
1197 | struct sh_mmcif_host *host = dev_id; | |
8047310e | 1198 | struct mmc_request *mrq; |
585c3a5a | 1199 | struct device *dev = sh_mmcif_host_to_dev(host); |
5df460b1 | 1200 | bool wait = false; |
dbb42d96 KT |
1201 | unsigned long flags; |
1202 | int wait_work; | |
1203 | ||
1204 | spin_lock_irqsave(&host->lock, flags); | |
1205 | wait_work = host->wait_for; | |
1206 | spin_unlock_irqrestore(&host->lock, flags); | |
f985da17 GL |
1207 | |
1208 | cancel_delayed_work_sync(&host->timeout_work); | |
1209 | ||
8047310e GL |
1210 | mutex_lock(&host->thread_lock); |
1211 | ||
1212 | mrq = host->mrq; | |
1213 | if (!mrq) { | |
585c3a5a | 1214 | dev_dbg(dev, "IRQ thread state %u, wait %u: NULL mrq!\n", |
8047310e GL |
1215 | host->state, host->wait_for); |
1216 | mutex_unlock(&host->thread_lock); | |
1217 | return IRQ_HANDLED; | |
1218 | } | |
1219 | ||
f985da17 GL |
1220 | /* |
1221 | * All handlers return true, if processing continues, and false, if the | |
1222 | * request has to be completed - successfully or not | |
1223 | */ | |
dbb42d96 | 1224 | switch (wait_work) { |
f985da17 GL |
1225 | case MMCIF_WAIT_FOR_REQUEST: |
1226 | /* We're too late, the timeout has already kicked in */ | |
8047310e | 1227 | mutex_unlock(&host->thread_lock); |
f985da17 GL |
1228 | return IRQ_HANDLED; |
1229 | case MMCIF_WAIT_FOR_CMD: | |
5df460b1 GL |
1230 | /* Wait for data? */ |
1231 | wait = sh_mmcif_end_cmd(host); | |
f985da17 GL |
1232 | break; |
1233 | case MMCIF_WAIT_FOR_MREAD: | |
5df460b1 GL |
1234 | /* Wait for more data? */ |
1235 | wait = sh_mmcif_mread_block(host); | |
f985da17 GL |
1236 | break; |
1237 | case MMCIF_WAIT_FOR_READ: | |
5df460b1 GL |
1238 | /* Wait for data end? */ |
1239 | wait = sh_mmcif_read_block(host); | |
f985da17 GL |
1240 | break; |
1241 | case MMCIF_WAIT_FOR_MWRITE: | |
5df460b1 GL |
1242 | /* Wait data to write? */ |
1243 | wait = sh_mmcif_mwrite_block(host); | |
f985da17 GL |
1244 | break; |
1245 | case MMCIF_WAIT_FOR_WRITE: | |
5df460b1 GL |
1246 | /* Wait for data end? */ |
1247 | wait = sh_mmcif_write_block(host); | |
f985da17 GL |
1248 | break; |
1249 | case MMCIF_WAIT_FOR_STOP: | |
1250 | if (host->sd_error) { | |
1251 | mrq->stop->error = sh_mmcif_error_manage(host); | |
585c3a5a | 1252 | dev_dbg(dev, "%s(): %d\n", __func__, mrq->stop->error); |
f985da17 GL |
1253 | break; |
1254 | } | |
1255 | sh_mmcif_get_cmd12response(host, mrq->stop); | |
1256 | mrq->stop->error = 0; | |
1257 | break; | |
1258 | case MMCIF_WAIT_FOR_READ_END: | |
1259 | case MMCIF_WAIT_FOR_WRITE_END: | |
e475b270 | 1260 | if (host->sd_error) { |
91ab252a | 1261 | mrq->data->error = sh_mmcif_error_manage(host); |
585c3a5a | 1262 | dev_dbg(dev, "%s(): %d\n", __func__, mrq->data->error); |
e475b270 | 1263 | } |
f985da17 GL |
1264 | break; |
1265 | default: | |
1266 | BUG(); | |
1267 | } | |
1268 | ||
5df460b1 GL |
1269 | if (wait) { |
1270 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
1271 | /* Wait for more data */ | |
8047310e | 1272 | mutex_unlock(&host->thread_lock); |
5df460b1 GL |
1273 | return IRQ_HANDLED; |
1274 | } | |
1275 | ||
f985da17 | 1276 | if (host->wait_for != MMCIF_WAIT_FOR_STOP) { |
91ab252a | 1277 | struct mmc_data *data = mrq->data; |
69983404 GL |
1278 | if (!mrq->cmd->error && data && !data->error) |
1279 | data->bytes_xfered = | |
1280 | data->blocks * data->blksz; | |
f985da17 | 1281 | |
69983404 | 1282 | if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { |
f985da17 | 1283 | sh_mmcif_stop_cmd(host, mrq); |
5df460b1 GL |
1284 | if (!mrq->stop->error) { |
1285 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
8047310e | 1286 | mutex_unlock(&host->thread_lock); |
f985da17 | 1287 | return IRQ_HANDLED; |
5df460b1 | 1288 | } |
f985da17 GL |
1289 | } |
1290 | } | |
1291 | ||
1292 | host->wait_for = MMCIF_WAIT_FOR_REQUEST; | |
1293 | host->state = STATE_IDLE; | |
69983404 | 1294 | host->mrq = NULL; |
f985da17 GL |
1295 | mmc_request_done(host->mmc, mrq); |
1296 | ||
8047310e GL |
1297 | mutex_unlock(&host->thread_lock); |
1298 | ||
f985da17 GL |
1299 | return IRQ_HANDLED; |
1300 | } | |
1301 | ||
fdc50a94 YG |
1302 | static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) |
1303 | { | |
1304 | struct sh_mmcif_host *host = dev_id; | |
585c3a5a | 1305 | struct device *dev = sh_mmcif_host_to_dev(host); |
967bcb77 | 1306 | u32 state, mask; |
fdc50a94 | 1307 | |
487d9fc5 | 1308 | state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); |
967bcb77 GL |
1309 | mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); |
1310 | if (host->ccs_enable) | |
1311 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); | |
1312 | else | |
1313 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); | |
8af50750 | 1314 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); |
fdc50a94 | 1315 | |
8af50750 | 1316 | if (state & ~MASK_CLEAN) |
585c3a5a | 1317 | dev_dbg(dev, "IRQ state = 0x%08x incompletely cleared\n", |
8af50750 GL |
1318 | state); |
1319 | ||
1320 | if (state & INT_ERR_STS || state & ~INT_ALL) { | |
aa0787a9 | 1321 | host->sd_error = true; |
585c3a5a | 1322 | dev_dbg(dev, "int err state = 0x%08x\n", state); |
fdc50a94 | 1323 | } |
f985da17 | 1324 | if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { |
8af50750 | 1325 | if (!host->mrq) |
585c3a5a | 1326 | dev_dbg(dev, "NULL IRQ state = 0x%08x\n", state); |
f985da17 GL |
1327 | if (!host->dma_active) |
1328 | return IRQ_WAKE_THREAD; | |
1329 | else if (host->sd_error) | |
1330 | mmcif_dma_complete(host); | |
1331 | } else { | |
585c3a5a | 1332 | dev_dbg(dev, "Unexpected IRQ 0x%x\n", state); |
f985da17 | 1333 | } |
fdc50a94 YG |
1334 | |
1335 | return IRQ_HANDLED; | |
1336 | } | |
1337 | ||
f985da17 GL |
1338 | static void mmcif_timeout_work(struct work_struct *work) |
1339 | { | |
1340 | struct delayed_work *d = container_of(work, struct delayed_work, work); | |
1341 | struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); | |
1342 | struct mmc_request *mrq = host->mrq; | |
585c3a5a | 1343 | struct device *dev = sh_mmcif_host_to_dev(host); |
8047310e | 1344 | unsigned long flags; |
f985da17 GL |
1345 | |
1346 | if (host->dying) | |
1347 | /* Don't run after mmc_remove_host() */ | |
1348 | return; | |
1349 | ||
8047310e GL |
1350 | spin_lock_irqsave(&host->lock, flags); |
1351 | if (host->state == STATE_IDLE) { | |
1352 | spin_unlock_irqrestore(&host->lock, flags); | |
1353 | return; | |
1354 | } | |
1355 | ||
585c3a5a | 1356 | dev_err(dev, "Timeout waiting for %u on CMD%u\n", |
4cbd5224 KT |
1357 | host->wait_for, mrq->cmd->opcode); |
1358 | ||
8047310e GL |
1359 | host->state = STATE_TIMEOUT; |
1360 | spin_unlock_irqrestore(&host->lock, flags); | |
1361 | ||
f985da17 GL |
1362 | /* |
1363 | * Handle races with cancel_delayed_work(), unless | |
1364 | * cancel_delayed_work_sync() is used | |
1365 | */ | |
1366 | switch (host->wait_for) { | |
1367 | case MMCIF_WAIT_FOR_CMD: | |
1368 | mrq->cmd->error = sh_mmcif_error_manage(host); | |
1369 | break; | |
1370 | case MMCIF_WAIT_FOR_STOP: | |
1371 | mrq->stop->error = sh_mmcif_error_manage(host); | |
1372 | break; | |
1373 | case MMCIF_WAIT_FOR_MREAD: | |
1374 | case MMCIF_WAIT_FOR_MWRITE: | |
1375 | case MMCIF_WAIT_FOR_READ: | |
1376 | case MMCIF_WAIT_FOR_WRITE: | |
1377 | case MMCIF_WAIT_FOR_READ_END: | |
1378 | case MMCIF_WAIT_FOR_WRITE_END: | |
69983404 | 1379 | mrq->data->error = sh_mmcif_error_manage(host); |
f985da17 GL |
1380 | break; |
1381 | default: | |
1382 | BUG(); | |
1383 | } | |
1384 | ||
1385 | host->state = STATE_IDLE; | |
1386 | host->wait_for = MMCIF_WAIT_FOR_REQUEST; | |
f985da17 GL |
1387 | host->mrq = NULL; |
1388 | mmc_request_done(host->mmc, mrq); | |
1389 | } | |
1390 | ||
7d17baa0 GL |
1391 | static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) |
1392 | { | |
585c3a5a KM |
1393 | struct device *dev = sh_mmcif_host_to_dev(host); |
1394 | struct sh_mmcif_plat_data *pd = dev->platform_data; | |
7d17baa0 GL |
1395 | struct mmc_host *mmc = host->mmc; |
1396 | ||
1397 | mmc_regulator_get_supply(mmc); | |
1398 | ||
bf68a812 GL |
1399 | if (!pd) |
1400 | return; | |
1401 | ||
7d17baa0 GL |
1402 | if (!mmc->ocr_avail) |
1403 | mmc->ocr_avail = pd->ocr; | |
1404 | else if (pd->ocr) | |
1405 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); | |
1406 | } | |
1407 | ||
c3be1efd | 1408 | static int sh_mmcif_probe(struct platform_device *pdev) |
fdc50a94 YG |
1409 | { |
1410 | int ret = 0, irq[2]; | |
1411 | struct mmc_host *mmc; | |
e47bf32a | 1412 | struct sh_mmcif_host *host; |
60985c39 KM |
1413 | struct device *dev = &pdev->dev; |
1414 | struct sh_mmcif_plat_data *pd = dev->platform_data; | |
fdc50a94 YG |
1415 | struct resource *res; |
1416 | void __iomem *reg; | |
2cd5b3e0 | 1417 | const char *name; |
fdc50a94 YG |
1418 | |
1419 | irq[0] = platform_get_irq(pdev, 0); | |
1420 | irq[1] = platform_get_irq(pdev, 1); | |
2cd5b3e0 | 1421 | if (irq[0] < 0) { |
60985c39 | 1422 | dev_err(dev, "Get irq error\n"); |
fdc50a94 YG |
1423 | return -ENXIO; |
1424 | } | |
18f55fcc | 1425 | |
fdc50a94 | 1426 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
60985c39 | 1427 | reg = devm_ioremap_resource(dev, res); |
18f55fcc BD |
1428 | if (IS_ERR(reg)) |
1429 | return PTR_ERR(reg); | |
e1aae2eb | 1430 | |
60985c39 | 1431 | mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev); |
18f55fcc BD |
1432 | if (!mmc) |
1433 | return -ENOMEM; | |
2c9054dc SB |
1434 | |
1435 | ret = mmc_of_parse(mmc); | |
1436 | if (ret < 0) | |
46991005 | 1437 | goto err_host; |
2c9054dc | 1438 | |
fdc50a94 YG |
1439 | host = mmc_priv(mmc); |
1440 | host->mmc = mmc; | |
1441 | host->addr = reg; | |
bad4371d | 1442 | host->timeout = msecs_to_jiffies(10000); |
967bcb77 | 1443 | host->ccs_enable = !pd || !pd->ccs_unsupported; |
6d6fd367 | 1444 | host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; |
fdc50a94 | 1445 | |
fdc50a94 YG |
1446 | host->pd = pdev; |
1447 | ||
3b0beafc | 1448 | spin_lock_init(&host->lock); |
fdc50a94 YG |
1449 | |
1450 | mmc->ops = &sh_mmcif_ops; | |
7d17baa0 GL |
1451 | sh_mmcif_init_ocr(host); |
1452 | ||
eca889f6 | 1453 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; |
bf68a812 | 1454 | if (pd && pd->caps) |
fdc50a94 | 1455 | mmc->caps |= pd->caps; |
a782d688 | 1456 | mmc->max_segs = 32; |
fdc50a94 | 1457 | mmc->max_blk_size = 512; |
a782d688 GL |
1458 | mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; |
1459 | mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; | |
fdc50a94 YG |
1460 | mmc->max_seg_size = mmc->max_req_size; |
1461 | ||
fdc50a94 | 1462 | platform_set_drvdata(pdev, host); |
a782d688 | 1463 | |
60985c39 | 1464 | pm_runtime_enable(dev); |
faca6648 GL |
1465 | host->power = false; |
1466 | ||
6aed678b KM |
1467 | host->clk = devm_clk_get(dev, NULL); |
1468 | if (IS_ERR(host->clk)) { | |
1469 | ret = PTR_ERR(host->clk); | |
60985c39 | 1470 | dev_err(dev, "cannot get clock: %d\n", ret); |
46991005 | 1471 | goto err_pm; |
b289174f | 1472 | } |
9bb09a30 KM |
1473 | |
1474 | ret = clk_prepare_enable(host->clk); | |
a6609267 | 1475 | if (ret < 0) |
46991005 | 1476 | goto err_pm; |
b289174f | 1477 | |
9bb09a30 KM |
1478 | sh_mmcif_clk_setup(host); |
1479 | ||
60985c39 | 1480 | ret = pm_runtime_resume(dev); |
faca6648 | 1481 | if (ret < 0) |
46991005 | 1482 | goto err_clk; |
a782d688 | 1483 | |
5ba85d95 | 1484 | INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); |
fdc50a94 | 1485 | |
b289174f | 1486 | sh_mmcif_sync_reset(host); |
3b0beafc GL |
1487 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
1488 | ||
60985c39 KM |
1489 | name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error"; |
1490 | ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr, | |
6f4789e6 | 1491 | sh_mmcif_irqt, 0, name, host); |
fdc50a94 | 1492 | if (ret) { |
60985c39 | 1493 | dev_err(dev, "request_irq error (%s)\n", name); |
11a80852 | 1494 | goto err_clk; |
fdc50a94 | 1495 | } |
2cd5b3e0 | 1496 | if (irq[1] >= 0) { |
60985c39 | 1497 | ret = devm_request_threaded_irq(dev, irq[1], |
6f4789e6 BD |
1498 | sh_mmcif_intr, sh_mmcif_irqt, |
1499 | 0, "sh_mmc:int", host); | |
2cd5b3e0 | 1500 | if (ret) { |
60985c39 | 1501 | dev_err(dev, "request_irq error (sh_mmc:int)\n"); |
11a80852 | 1502 | goto err_clk; |
2cd5b3e0 | 1503 | } |
fdc50a94 YG |
1504 | } |
1505 | ||
e480606a | 1506 | if (pd && pd->use_cd_gpio) { |
214fc309 | 1507 | ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0); |
e480606a | 1508 | if (ret < 0) |
7f67f3a2 | 1509 | goto err_clk; |
e480606a GL |
1510 | } |
1511 | ||
8047310e GL |
1512 | mutex_init(&host->thread_lock); |
1513 | ||
5ba85d95 GL |
1514 | ret = mmc_add_host(mmc); |
1515 | if (ret < 0) | |
7f67f3a2 | 1516 | goto err_clk; |
fdc50a94 | 1517 | |
60985c39 | 1518 | dev_pm_qos_expose_latency_limit(dev, 100); |
efe6a8ad | 1519 | |
60985c39 | 1520 | dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n", |
ce7eb688 | 1521 | sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, |
6aed678b | 1522 | clk_get_rate(host->clk) / 1000000UL); |
ce7eb688 | 1523 | |
6aed678b | 1524 | clk_disable_unprepare(host->clk); |
fdc50a94 YG |
1525 | return ret; |
1526 | ||
46991005 | 1527 | err_clk: |
6aed678b | 1528 | clk_disable_unprepare(host->clk); |
46991005 | 1529 | err_pm: |
60985c39 | 1530 | pm_runtime_disable(dev); |
46991005 | 1531 | err_host: |
fdc50a94 | 1532 | mmc_free_host(mmc); |
fdc50a94 YG |
1533 | return ret; |
1534 | } | |
1535 | ||
6e0ee714 | 1536 | static int sh_mmcif_remove(struct platform_device *pdev) |
fdc50a94 YG |
1537 | { |
1538 | struct sh_mmcif_host *host = platform_get_drvdata(pdev); | |
fdc50a94 | 1539 | |
f985da17 | 1540 | host->dying = true; |
6aed678b | 1541 | clk_prepare_enable(host->clk); |
faca6648 | 1542 | pm_runtime_get_sync(&pdev->dev); |
fdc50a94 | 1543 | |
efe6a8ad RW |
1544 | dev_pm_qos_hide_latency_limit(&pdev->dev); |
1545 | ||
faca6648 | 1546 | mmc_remove_host(host->mmc); |
3b0beafc GL |
1547 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
1548 | ||
f985da17 GL |
1549 | /* |
1550 | * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the | |
1551 | * mmc_remove_host() call above. But swapping order doesn't help either | |
1552 | * (a query on the linux-mmc mailing list didn't bring any replies). | |
1553 | */ | |
1554 | cancel_delayed_work_sync(&host->timeout_work); | |
1555 | ||
6aed678b | 1556 | clk_disable_unprepare(host->clk); |
fdc50a94 | 1557 | mmc_free_host(host->mmc); |
faca6648 GL |
1558 | pm_runtime_put_sync(&pdev->dev); |
1559 | pm_runtime_disable(&pdev->dev); | |
fdc50a94 YG |
1560 | |
1561 | return 0; | |
1562 | } | |
1563 | ||
51129f31 | 1564 | #ifdef CONFIG_PM_SLEEP |
faca6648 GL |
1565 | static int sh_mmcif_suspend(struct device *dev) |
1566 | { | |
b289174f | 1567 | struct sh_mmcif_host *host = dev_get_drvdata(dev); |
faca6648 | 1568 | |
cb3ca1ae | 1569 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
faca6648 | 1570 | |
cb3ca1ae | 1571 | return 0; |
faca6648 GL |
1572 | } |
1573 | ||
1574 | static int sh_mmcif_resume(struct device *dev) | |
1575 | { | |
cb3ca1ae | 1576 | return 0; |
faca6648 | 1577 | } |
51129f31 | 1578 | #endif |
faca6648 GL |
1579 | |
1580 | static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { | |
51129f31 | 1581 | SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume) |
faca6648 GL |
1582 | }; |
1583 | ||
fdc50a94 YG |
1584 | static struct platform_driver sh_mmcif_driver = { |
1585 | .probe = sh_mmcif_probe, | |
1586 | .remove = sh_mmcif_remove, | |
1587 | .driver = { | |
1588 | .name = DRIVER_NAME, | |
faca6648 | 1589 | .pm = &sh_mmcif_dev_pm_ops, |
bf68a812 | 1590 | .of_match_table = mmcif_of_match, |
fdc50a94 YG |
1591 | }, |
1592 | }; | |
1593 | ||
d1f81a64 | 1594 | module_platform_driver(sh_mmcif_driver); |
fdc50a94 YG |
1595 | |
1596 | MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); | |
1597 | MODULE_LICENSE("GPL"); | |
aa0787a9 | 1598 | MODULE_ALIAS("platform:" DRIVER_NAME); |
fdc50a94 | 1599 | MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); |