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mmc: using module_param requires the inclusion of moduleparam.h
[linux-2.6-block.git] / drivers / mmc / host / sh_mmcif.c
CommitLineData
fdc50a94
YG		 1/*
2 * MMCIF eMMC driver.
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10 *
11 *
12 * TODO
13 * 1. DMA
14 * 2. Power management
15 * 3. Handle MMC errors better
16 *
17 */
18
aa0787a9
GL		 19#include <linux/clk.h>
20#include <linux/completion.h>
e47bf32a 21#include <linux/delay.h>
fdc50a94 22#include <linux/dma-mapping.h>
a782d688 23#include <linux/dmaengine.h>
fdc50a94
YG		 24#include <linux/mmc/card.h>
25#include <linux/mmc/core.h>
e47bf32a 26#include <linux/mmc/host.h>
fdc50a94
YG		 27#include <linux/mmc/mmc.h>
28#include <linux/mmc/sdio.h>
fdc50a94 29#include <linux/mmc/sh_mmcif.h>
a782d688 30#include <linux/pagemap.h>
e47bf32a 31#include <linux/platform_device.h>
faca6648 32#include <linux/pm_runtime.h>
3b0beafc 33#include <linux/spinlock.h>
fdc50a94
YG		 34
35#define DRIVER_NAME "sh_mmcif"
36#define DRIVER_VERSION "2010-04-28"
37
fdc50a94
YG		 38/* CE_CMD_SET */
39#define CMD_MASK 0x3f000000
40#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
41#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
42#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
43#define CMD_SET_RBSY (1 << 21) /* R1b */
44#define CMD_SET_CCSEN (1 << 20)
45#define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
46#define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
47#define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
48#define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
49#define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
50#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
51#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
52#define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
53#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
54#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
55#define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
56#define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
57#define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
58#define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
59#define CMD_SET_CCSH (1 << 5)
60#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
61#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
62#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
63
64/* CE_CMD_CTRL */
65#define CMD_CTRL_BREAK (1 << 0)
66
67/* CE_BLOCK_SET */
68#define BLOCK_SIZE_MASK 0x0000ffff
69
fdc50a94
YG		 70/* CE_INT */
71#define INT_CCSDE (1 << 29)
72#define INT_CMD12DRE (1 << 26)
73#define INT_CMD12RBE (1 << 25)
74#define INT_CMD12CRE (1 << 24)
75#define INT_DTRANE (1 << 23)
76#define INT_BUFRE (1 << 22)
77#define INT_BUFWEN (1 << 21)
78#define INT_BUFREN (1 << 20)
79#define INT_CCSRCV (1 << 19)
80#define INT_RBSYE (1 << 17)
81#define INT_CRSPE (1 << 16)
82#define INT_CMDVIO (1 << 15)
83#define INT_BUFVIO (1 << 14)
84#define INT_WDATERR (1 << 11)
85#define INT_RDATERR (1 << 10)
86#define INT_RIDXERR (1 << 9)
87#define INT_RSPERR (1 << 8)
88#define INT_CCSTO (1 << 5)
89#define INT_CRCSTO (1 << 4)
90#define INT_WDATTO (1 << 3)
91#define INT_RDATTO (1 << 2)
92#define INT_RBSYTO (1 << 1)
93#define INT_RSPTO (1 << 0)
94#define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
95 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
96 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
97 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
98
99/* CE_INT_MASK */
100#define MASK_ALL 0x00000000
101#define MASK_MCCSDE (1 << 29)
102#define MASK_MCMD12DRE (1 << 26)
103#define MASK_MCMD12RBE (1 << 25)
104#define MASK_MCMD12CRE (1 << 24)
105#define MASK_MDTRANE (1 << 23)
106#define MASK_MBUFRE (1 << 22)
107#define MASK_MBUFWEN (1 << 21)
108#define MASK_MBUFREN (1 << 20)
109#define MASK_MCCSRCV (1 << 19)
110#define MASK_MRBSYE (1 << 17)
111#define MASK_MCRSPE (1 << 16)
112#define MASK_MCMDVIO (1 << 15)
113#define MASK_MBUFVIO (1 << 14)
114#define MASK_MWDATERR (1 << 11)
115#define MASK_MRDATERR (1 << 10)
116#define MASK_MRIDXERR (1 << 9)
117#define MASK_MRSPERR (1 << 8)
118#define MASK_MCCSTO (1 << 5)
119#define MASK_MCRCSTO (1 << 4)
120#define MASK_MWDATTO (1 << 3)
121#define MASK_MRDATTO (1 << 2)
122#define MASK_MRBSYTO (1 << 1)
123#define MASK_MRSPTO (1 << 0)
124
125/* CE_HOST_STS1 */
126#define STS1_CMDSEQ (1 << 31)
127
128/* CE_HOST_STS2 */
129#define STS2_CRCSTE (1 << 31)
130#define STS2_CRC16E (1 << 30)
131#define STS2_AC12CRCE (1 << 29)
132#define STS2_RSPCRC7E (1 << 28)
133#define STS2_CRCSTEBE (1 << 27)
134#define STS2_RDATEBE (1 << 26)
135#define STS2_AC12REBE (1 << 25)
136#define STS2_RSPEBE (1 << 24)
137#define STS2_AC12IDXE (1 << 23)
138#define STS2_RSPIDXE (1 << 22)
139#define STS2_CCSTO (1 << 15)
140#define STS2_RDATTO (1 << 14)
141#define STS2_DATBSYTO (1 << 13)
142#define STS2_CRCSTTO (1 << 12)
143#define STS2_AC12BSYTO (1 << 11)
144#define STS2_RSPBSYTO (1 << 10)
145#define STS2_AC12RSPTO (1 << 9)
146#define STS2_RSPTO (1 << 8)
147#define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
148 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
149#define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
150 STS2_DATBSYTO | STS2_CRCSTTO | \
151 STS2_AC12BSYTO | STS2_RSPBSYTO | \
152 STS2_AC12RSPTO | STS2_RSPTO)
153
fdc50a94
YG		 154#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
155#define CLKDEV_MMC_DATA 20000000 /* 20MHz */
156#define CLKDEV_INIT 400000 /* 400 KHz */
157
3b0beafc
GL		 158enum mmcif_state {
159 STATE_IDLE,
160 STATE_REQUEST,
161 STATE_IOS,
162};
163
fdc50a94
YG		 164struct sh_mmcif_host {
165 struct mmc_host *mmc;
166 struct mmc_data *data;
fdc50a94 167 struct platform_device *pd;
714c4a6e
GL		 168 struct sh_dmae_slave dma_slave_tx;
169 struct sh_dmae_slave dma_slave_rx;
fdc50a94
YG		 170 struct clk *hclk;
171 unsigned int clk;
172 int bus_width;
aa0787a9 173 bool sd_error;
fdc50a94
YG		 174 long timeout;
175 void __iomem *addr;
aa0787a9 176 struct completion intr_wait;
3b0beafc
GL		 177 enum mmcif_state state;
178 spinlock_t lock;
faca6648 179 bool power;
c9b0cef2 180 bool card_present;
fdc50a94 181
a782d688
GL		 182 /* DMA support */
183 struct dma_chan *chan_rx;
184 struct dma_chan *chan_tx;
185 struct completion dma_complete;
f38f94c6 186 bool dma_active;
a782d688 187};
fdc50a94
YG		 188
189static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
190 unsigned int reg, u32 val)
191{
487d9fc5 192 writel(val | readl(host->addr + reg), host->addr + reg);
fdc50a94
YG		 193}
194
195static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
196 unsigned int reg, u32 val)
197{
487d9fc5 198 writel(~val & readl(host->addr + reg), host->addr + reg);
fdc50a94
YG		 199}
200
a782d688
GL		 201static void mmcif_dma_complete(void *arg)
202{
203 struct sh_mmcif_host *host = arg;
204 dev_dbg(&host->pd->dev, "Command completed\n");
205
206 if (WARN(!host->data, "%s: NULL data in DMA completion!\n",
207 dev_name(&host->pd->dev)))
208 return;
209
210 if (host->data->flags & MMC_DATA_READ)
1ed828db 211 dma_unmap_sg(host->chan_rx->device->dev,
9dc3fb5e 212 host->data->sg, host->data->sg_len,
a782d688
GL		 213 DMA_FROM_DEVICE);
214 else
1ed828db 215 dma_unmap_sg(host->chan_tx->device->dev,
9dc3fb5e 216 host->data->sg, host->data->sg_len,
a782d688
GL		 217 DMA_TO_DEVICE);
218
219 complete(&host->dma_complete);
220}
221
222static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
223{
224 struct scatterlist *sg = host->data->sg;
225 struct dma_async_tx_descriptor *desc = NULL;
226 struct dma_chan *chan = host->chan_rx;
227 dma_cookie_t cookie = -EINVAL;
228 int ret;
229
1ed828db
LW		 230 ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
231 DMA_FROM_DEVICE);
a782d688 232 if (ret > 0) {
f38f94c6 233 host->dma_active = true;
a782d688
GL		 234 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
235 DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
236 }
237
238 if (desc) {
239 desc->callback = mmcif_dma_complete;
240 desc->callback_param = host;
a5ece7d2
LW		 241 cookie = dmaengine_submit(desc);
242 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
243 dma_async_issue_pending(chan);
a782d688
GL		 244 }
245 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
246 __func__, host->data->sg_len, ret, cookie);
247
248 if (!desc) {
249 /* DMA failed, fall back to PIO */
250 if (ret >= 0)
251 ret = -EIO;
252 host->chan_rx = NULL;
f38f94c6 253 host->dma_active = false;
a782d688
GL		 254 dma_release_channel(chan);
255 /* Free the Tx channel too */
256 chan = host->chan_tx;
257 if (chan) {
258 host->chan_tx = NULL;
259 dma_release_channel(chan);
260 }
261 dev_warn(&host->pd->dev,
262 "DMA failed: %d, falling back to PIO\n", ret);
263 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
264 }
265
266 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
267 desc, cookie, host->data->sg_len);
268}
269
270static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
271{
272 struct scatterlist *sg = host->data->sg;
273 struct dma_async_tx_descriptor *desc = NULL;
274 struct dma_chan *chan = host->chan_tx;
275 dma_cookie_t cookie = -EINVAL;
276 int ret;
277
1ed828db
LW		 278 ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
279 DMA_TO_DEVICE);
a782d688 280 if (ret > 0) {
f38f94c6 281 host->dma_active = true;
a782d688
GL		 282 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
283 DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
284 }
285
286 if (desc) {
287 desc->callback = mmcif_dma_complete;
288 desc->callback_param = host;
a5ece7d2
LW		 289 cookie = dmaengine_submit(desc);
290 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
291 dma_async_issue_pending(chan);
a782d688
GL		 292 }
293 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
294 __func__, host->data->sg_len, ret, cookie);
295
296 if (!desc) {
297 /* DMA failed, fall back to PIO */
298 if (ret >= 0)
299 ret = -EIO;
300 host->chan_tx = NULL;
f38f94c6 301 host->dma_active = false;
a782d688
GL		 302 dma_release_channel(chan);
303 /* Free the Rx channel too */
304 chan = host->chan_rx;
305 if (chan) {
306 host->chan_rx = NULL;
307 dma_release_channel(chan);
308 }
309 dev_warn(&host->pd->dev,
310 "DMA failed: %d, falling back to PIO\n", ret);
311 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
312 }
313
314 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
315 desc, cookie);
316}
317
318static bool sh_mmcif_filter(struct dma_chan *chan, void *arg)
319{
320 dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
321 chan->private = arg;
322 return true;
323}
324
325static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
326 struct sh_mmcif_plat_data *pdata)
327{
714c4a6e 328 struct sh_dmae_slave *tx, *rx;
f38f94c6 329 host->dma_active = false;
a782d688
GL		 330
331 /* We can only either use DMA for both Tx and Rx or not use it at all */
332 if (pdata->dma) {
714c4a6e
GL		 333 dev_warn(&host->pd->dev,
334 "Update your platform to use embedded DMA slave IDs\n");
335 tx = &pdata->dma->chan_priv_tx;
336 rx = &pdata->dma->chan_priv_rx;
337 } else {
338 tx = &host->dma_slave_tx;
339 tx->slave_id = pdata->slave_id_tx;
340 rx = &host->dma_slave_rx;
341 rx->slave_id = pdata->slave_id_rx;
342 }
343 if (tx->slave_id > 0 && rx->slave_id > 0) {
a782d688
GL		 344 dma_cap_mask_t mask;
345
346 dma_cap_zero(mask);
347 dma_cap_set(DMA_SLAVE, mask);
348
714c4a6e 349 host->chan_tx = dma_request_channel(mask, sh_mmcif_filter, tx);
a782d688
GL		 350 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
351 host->chan_tx);
352
353 if (!host->chan_tx)
354 return;
355
714c4a6e 356 host->chan_rx = dma_request_channel(mask, sh_mmcif_filter, rx);
a782d688
GL		 357 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
358 host->chan_rx);
359
360 if (!host->chan_rx) {
361 dma_release_channel(host->chan_tx);
362 host->chan_tx = NULL;
363 return;
364 }
365
366 init_completion(&host->dma_complete);
367 }
368}
369
370static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
371{
372 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
373 /* Descriptors are freed automatically */
374 if (host->chan_tx) {
375 struct dma_chan *chan = host->chan_tx;
376 host->chan_tx = NULL;
377 dma_release_channel(chan);
378 }
379 if (host->chan_rx) {
380 struct dma_chan *chan = host->chan_rx;
381 host->chan_rx = NULL;
382 dma_release_channel(chan);
383 }
384
f38f94c6 385 host->dma_active = false;
a782d688 386}
fdc50a94
YG		 387
388static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
389{
390 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
391
392 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
393 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
394
395 if (!clk)
396 return;
397 if (p->sup_pclk && clk == host->clk)
398 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
399 else
400 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
401 (ilog2(__rounddown_pow_of_two(host->clk / clk)) << 16));
402
403 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
404}
405
406static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
407{
408 u32 tmp;
409
487d9fc5 410 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
fdc50a94 411
487d9fc5
MD		 412 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
413 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
fdc50a94
YG		 414 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
415 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
416 /* byte swap on */
417 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
418}
419
420static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
421{
422 u32 state1, state2;
423 int ret, timeout = 10000000;
424
aa0787a9 425 host->sd_error = false;
fdc50a94 426
487d9fc5
MD		 427 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
428 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
e47bf32a
GL		 429 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
430 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
fdc50a94
YG		 431
432 if (state1 & STS1_CMDSEQ) {
433 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
434 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
435 while (1) {
436 timeout--;
437 if (timeout < 0) {
e47bf32a
GL		 438 dev_err(&host->pd->dev,
439 "Forceed end of command sequence timeout err\n");
fdc50a94
YG		 440 return -EIO;
441 }
487d9fc5 442 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
fdc50a94
YG		 443 & STS1_CMDSEQ))
444 break;
445 mdelay(1);
446 }
447 sh_mmcif_sync_reset(host);
e47bf32a 448 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
fdc50a94
YG		 449 return -EIO;
450 }
451
452 if (state2 & STS2_CRC_ERR) {
e47bf32a 453 dev_dbg(&host->pd->dev, ": Happened CRC error\n");
fdc50a94
YG		 454 ret = -EIO;
455 } else if (state2 & STS2_TIMEOUT_ERR) {
e47bf32a 456 dev_dbg(&host->pd->dev, ": Happened Timeout error\n");
fdc50a94
YG		 457 ret = -ETIMEDOUT;
458 } else {
e47bf32a 459 dev_dbg(&host->pd->dev, ": Happened End/Index error\n");
fdc50a94
YG		 460 ret = -EIO;
461 }
462 return ret;
463}
464
465static int sh_mmcif_single_read(struct sh_mmcif_host *host,
466 struct mmc_request *mrq)
467{
468 struct mmc_data *data = mrq->data;
469 long time;
470 u32 blocksize, i, *p = sg_virt(data->sg);
471
fdc50a94
YG		 472 /* buf read enable */
473 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
aa0787a9
GL		 474 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
475 host->timeout);
476 if (time <= 0 || host->sd_error)
fdc50a94
YG		 477 return sh_mmcif_error_manage(host);
478
fdc50a94 479 blocksize = (BLOCK_SIZE_MASK &
487d9fc5 480 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
fdc50a94 481 for (i = 0; i < blocksize / 4; i++)
487d9fc5 482 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
fdc50a94
YG		 483
484 /* buffer read end */
485 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
aa0787a9
GL		 486 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
487 host->timeout);
488 if (time <= 0 || host->sd_error)
fdc50a94
YG		 489 return sh_mmcif_error_manage(host);
490
fdc50a94
YG		 491 return 0;
492}
493
494static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
495 struct mmc_request *mrq)
496{
497 struct mmc_data *data = mrq->data;
498 long time;
499 u32 blocksize, i, j, sec, *p;
500
487d9fc5
MD		 501 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
502 MMCIF_CE_BLOCK_SET);
fdc50a94
YG		 503 for (j = 0; j < data->sg_len; j++) {
504 p = sg_virt(data->sg);
fdc50a94
YG		 505 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
506 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
507 /* buf read enable */
aa0787a9
GL		 508 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
509 host->timeout);
fdc50a94 510
aa0787a9 511 if (time <= 0 || host->sd_error)
fdc50a94
YG		 512 return sh_mmcif_error_manage(host);
513
fdc50a94 514 for (i = 0; i < blocksize / 4; i++)
487d9fc5
MD		 515 *p++ = sh_mmcif_readl(host->addr,
516 MMCIF_CE_DATA);
fdc50a94
YG		 517 }
518 if (j < data->sg_len - 1)
519 data->sg++;
520 }
521 return 0;
522}
523
524static int sh_mmcif_single_write(struct sh_mmcif_host *host,
525 struct mmc_request *mrq)
526{
527 struct mmc_data *data = mrq->data;
528 long time;
529 u32 blocksize, i, *p = sg_virt(data->sg);
530
fdc50a94
YG		 531 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
532
533 /* buf write enable */
aa0787a9
GL		 534 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
535 host->timeout);
536 if (time <= 0 || host->sd_error)
fdc50a94
YG		 537 return sh_mmcif_error_manage(host);
538
fdc50a94 539 blocksize = (BLOCK_SIZE_MASK &
487d9fc5 540 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
fdc50a94 541 for (i = 0; i < blocksize / 4; i++)
487d9fc5 542 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
fdc50a94
YG		 543
544 /* buffer write end */
545 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
546
aa0787a9
GL		 547 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
548 host->timeout);
549 if (time <= 0 || host->sd_error)
fdc50a94
YG		 550 return sh_mmcif_error_manage(host);
551
fdc50a94
YG		 552 return 0;
553}
554
555static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
556 struct mmc_request *mrq)
557{
558 struct mmc_data *data = mrq->data;
559 long time;
560 u32 i, sec, j, blocksize, *p;
561
487d9fc5
MD		 562 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
563 MMCIF_CE_BLOCK_SET);
fdc50a94
YG		 564
565 for (j = 0; j < data->sg_len; j++) {
566 p = sg_virt(data->sg);
fdc50a94
YG		 567 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
568 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
569 /* buf write enable*/
aa0787a9
GL		 570 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
571 host->timeout);
fdc50a94 572
aa0787a9 573 if (time <= 0 || host->sd_error)
fdc50a94
YG		 574 return sh_mmcif_error_manage(host);
575
fdc50a94 576 for (i = 0; i < blocksize / 4; i++)
487d9fc5
MD		 577 sh_mmcif_writel(host->addr,
578 MMCIF_CE_DATA, *p++);
fdc50a94
YG		 579 }
580 if (j < data->sg_len - 1)
581 data->sg++;
582 }
583 return 0;
584}
585
586static void sh_mmcif_get_response(struct sh_mmcif_host *host,
587 struct mmc_command *cmd)
588{
589 if (cmd->flags & MMC_RSP_136) {
487d9fc5
MD		 590 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
591 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
592 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
593 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
fdc50a94 594 } else
487d9fc5 595 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
fdc50a94
YG		 596}
597
598static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
599 struct mmc_command *cmd)
600{
487d9fc5 601 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
fdc50a94
YG		 602}
603
604static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
605 struct mmc_request *mrq, struct mmc_command *cmd, u32 opc)
606{
607 u32 tmp = 0;
608
609 /* Response Type check */
610 switch (mmc_resp_type(cmd)) {
611 case MMC_RSP_NONE:
612 tmp |= CMD_SET_RTYP_NO;
613 break;
614 case MMC_RSP_R1:
615 case MMC_RSP_R1B:
616 case MMC_RSP_R3:
617 tmp |= CMD_SET_RTYP_6B;
618 break;
619 case MMC_RSP_R2:
620 tmp |= CMD_SET_RTYP_17B;
621 break;
622 default:
e47bf32a 623 dev_err(&host->pd->dev, "Unsupported response type.\n");
fdc50a94
YG		 624 break;
625 }
626 switch (opc) {
627 /* RBSY */
628 case MMC_SWITCH:
629 case MMC_STOP_TRANSMISSION:
630 case MMC_SET_WRITE_PROT:
631 case MMC_CLR_WRITE_PROT:
632 case MMC_ERASE:
633 case MMC_GEN_CMD:
634 tmp |= CMD_SET_RBSY;
635 break;
636 }
637 /* WDAT / DATW */
638 if (host->data) {
639 tmp |= CMD_SET_WDAT;
640 switch (host->bus_width) {
641 case MMC_BUS_WIDTH_1:
642 tmp |= CMD_SET_DATW_1;
643 break;
644 case MMC_BUS_WIDTH_4:
645 tmp |= CMD_SET_DATW_4;
646 break;
647 case MMC_BUS_WIDTH_8:
648 tmp |= CMD_SET_DATW_8;
649 break;
650 default:
e47bf32a 651 dev_err(&host->pd->dev, "Unsupported bus width.\n");
fdc50a94
YG		 652 break;
653 }
654 }
655 /* DWEN */
656 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
657 tmp |= CMD_SET_DWEN;
658 /* CMLTE/CMD12EN */
659 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
660 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
661 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
662 mrq->data->blocks << 16);
663 }
664 /* RIDXC[1:0] check bits */
665 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
666 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
667 tmp |= CMD_SET_RIDXC_BITS;
668 /* RCRC7C[1:0] check bits */
669 if (opc == MMC_SEND_OP_COND)
670 tmp |= CMD_SET_CRC7C_BITS;
671 /* RCRC7C[1:0] internal CRC7 */
672 if (opc == MMC_ALL_SEND_CID ||
673 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
674 tmp |= CMD_SET_CRC7C_INTERNAL;
675
676 return opc = ((opc << 24) | tmp);
677}
678
e47bf32a 679static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
fdc50a94
YG		 680 struct mmc_request *mrq, u32 opc)
681{
e47bf32a 682 int ret;
fdc50a94
YG		 683
684 switch (opc) {
685 case MMC_READ_MULTIPLE_BLOCK:
686 ret = sh_mmcif_multi_read(host, mrq);
687 break;
688 case MMC_WRITE_MULTIPLE_BLOCK:
689 ret = sh_mmcif_multi_write(host, mrq);
690 break;
691 case MMC_WRITE_BLOCK:
692 ret = sh_mmcif_single_write(host, mrq);
693 break;
694 case MMC_READ_SINGLE_BLOCK:
695 case MMC_SEND_EXT_CSD:
696 ret = sh_mmcif_single_read(host, mrq);
697 break;
698 default:
e47bf32a 699 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
fdc50a94
YG		 700 ret = -EINVAL;
701 break;
702 }
703 return ret;
704}
705
706static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
707 struct mmc_request *mrq, struct mmc_command *cmd)
708{
709 long time;
710 int ret = 0, mask = 0;
711 u32 opc = cmd->opcode;
712
fdc50a94
YG		 713 switch (opc) {
714 /* respons busy check */
715 case MMC_SWITCH:
716 case MMC_STOP_TRANSMISSION:
717 case MMC_SET_WRITE_PROT:
718 case MMC_CLR_WRITE_PROT:
719 case MMC_ERASE:
720 case MMC_GEN_CMD:
721 mask = MASK_MRBSYE;
722 break;
723 default:
724 mask = MASK_MCRSPE;
725 break;
726 }
727 mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
728 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
729 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
730 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
731
732 if (host->data) {
487d9fc5
MD		 733 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
734 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
735 mrq->data->blksz);
fdc50a94
YG		 736 }
737 opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
738
487d9fc5
MD		 739 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
740 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
fdc50a94 741 /* set arg */
487d9fc5 742 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
fdc50a94 743 /* set cmd */
487d9fc5 744 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
fdc50a94 745
aa0787a9
GL		 746 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
747 host->timeout);
748 if (time <= 0) {
fdc50a94
YG		 749 cmd->error = sh_mmcif_error_manage(host);
750 return;
751 }
752 if (host->sd_error) {
753 switch (cmd->opcode) {
754 case MMC_ALL_SEND_CID:
755 case MMC_SELECT_CARD:
756 case MMC_APP_CMD:
757 cmd->error = -ETIMEDOUT;
758 break;
759 default:
e47bf32a
GL		 760 dev_dbg(&host->pd->dev, "Cmd(d'%d) err\n",
761 cmd->opcode);
fdc50a94
YG		 762 cmd->error = sh_mmcif_error_manage(host);
763 break;
764 }
aa0787a9 765 host->sd_error = false;
fdc50a94
YG		 766 return;
767 }
768 if (!(cmd->flags & MMC_RSP_PRESENT)) {
e47bf32a 769 cmd->error = 0;
fdc50a94
YG		 770 return;
771 }
aa0787a9 772 sh_mmcif_get_response(host, cmd);
fdc50a94 773 if (host->data) {
f38f94c6 774 if (!host->dma_active) {
a782d688
GL		 775 ret = sh_mmcif_data_trans(host, mrq, cmd->opcode);
776 } else {
777 long time =
778 wait_for_completion_interruptible_timeout(&host->dma_complete,
779 host->timeout);
780 if (!time)
781 ret = -ETIMEDOUT;
782 else if (time < 0)
783 ret = time;
784 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
785 BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
f38f94c6 786 host->dma_active = false;
a782d688 787 }
fdc50a94
YG		 788 if (ret < 0)
789 mrq->data->bytes_xfered = 0;
790 else
791 mrq->data->bytes_xfered =
792 mrq->data->blocks * mrq->data->blksz;
793 }
794 cmd->error = ret;
795}
796
797static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
798 struct mmc_request *mrq, struct mmc_command *cmd)
799{
800 long time;
801
802 if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK)
803 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
804 else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
805 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
806 else {
e47bf32a 807 dev_err(&host->pd->dev, "unsupported stop cmd\n");
fdc50a94
YG		 808 cmd->error = sh_mmcif_error_manage(host);
809 return;
810 }
811
aa0787a9
GL		 812 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
813 host->timeout);
814 if (time <= 0 || host->sd_error) {
fdc50a94
YG		 815 cmd->error = sh_mmcif_error_manage(host);
816 return;
817 }
818 sh_mmcif_get_cmd12response(host, cmd);
fdc50a94
YG		 819 cmd->error = 0;
820}
821
822static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
823{
824 struct sh_mmcif_host *host = mmc_priv(mmc);
3b0beafc
GL		 825 unsigned long flags;
826
827 spin_lock_irqsave(&host->lock, flags);
828 if (host->state != STATE_IDLE) {
829 spin_unlock_irqrestore(&host->lock, flags);
830 mrq->cmd->error = -EAGAIN;
831 mmc_request_done(mmc, mrq);
832 return;
833 }
834
835 host->state = STATE_REQUEST;
836 spin_unlock_irqrestore(&host->lock, flags);
fdc50a94
YG		 837
838 switch (mrq->cmd->opcode) {
839 /* MMCIF does not support SD/SDIO command */
840 case SD_IO_SEND_OP_COND:
841 case MMC_APP_CMD:
3b0beafc 842 host->state = STATE_IDLE;
fdc50a94
YG		 843 mrq->cmd->error = -ETIMEDOUT;
844 mmc_request_done(mmc, mrq);
845 return;
846 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
847 if (!mrq->data) {
848 /* send_if_cond cmd (not support) */
3b0beafc 849 host->state = STATE_IDLE;
fdc50a94
YG		 850 mrq->cmd->error = -ETIMEDOUT;
851 mmc_request_done(mmc, mrq);
852 return;
853 }
854 break;
855 default:
856 break;
857 }
858 host->data = mrq->data;
a782d688
GL		 859 if (mrq->data) {
860 if (mrq->data->flags & MMC_DATA_READ) {
861 if (host->chan_rx)
862 sh_mmcif_start_dma_rx(host);
863 } else {
864 if (host->chan_tx)
865 sh_mmcif_start_dma_tx(host);
866 }
867 }
fdc50a94
YG		 868 sh_mmcif_start_cmd(host, mrq, mrq->cmd);
869 host->data = NULL;
870
3b0beafc 871 if (!mrq->cmd->error && mrq->stop)
fdc50a94 872 sh_mmcif_stop_cmd(host, mrq, mrq->stop);
3b0beafc 873 host->state = STATE_IDLE;
fdc50a94
YG		 874 mmc_request_done(mmc, mrq);
875}
876
877static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
878{
879 struct sh_mmcif_host *host = mmc_priv(mmc);
880 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
3b0beafc
GL		 881 unsigned long flags;
882
883 spin_lock_irqsave(&host->lock, flags);
884 if (host->state != STATE_IDLE) {
885 spin_unlock_irqrestore(&host->lock, flags);
886 return;
887 }
888
889 host->state = STATE_IOS;
890 spin_unlock_irqrestore(&host->lock, flags);
fdc50a94 891
f5e0cec4 892 if (ios->power_mode == MMC_POWER_UP) {
c9b0cef2 893 if (!host->card_present) {
faca6648
GL		 894 /* See if we also get DMA */
895 sh_mmcif_request_dma(host, host->pd->dev.platform_data);
c9b0cef2 896 host->card_present = true;
faca6648 897 }
f5e0cec4 898 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
fdc50a94
YG		 899 /* clock stop */
900 sh_mmcif_clock_control(host, 0);
faca6648 901 if (ios->power_mode == MMC_POWER_OFF) {
c9b0cef2 902 if (host->card_present) {
faca6648 903 sh_mmcif_release_dma(host);
c9b0cef2 904 host->card_present = false;
faca6648 905 }
c9b0cef2
GL		 906 }
907 if (host->power) {
908 pm_runtime_put(&host->pd->dev);
909 host->power = false;
faca6648
GL		 910 if (p->down_pwr)
911 p->down_pwr(host->pd);
912 }
3b0beafc 913 host->state = STATE_IDLE;
fdc50a94 914 return;
fdc50a94
YG		 915 }
916
c9b0cef2
GL		 917 if (ios->clock) {
918 if (!host->power) {
919 if (p->set_pwr)
920 p->set_pwr(host->pd, ios->power_mode);
921 pm_runtime_get_sync(&host->pd->dev);
922 host->power = true;
923 sh_mmcif_sync_reset(host);
924 }
fdc50a94 925 sh_mmcif_clock_control(host, ios->clock);
c9b0cef2 926 }
fdc50a94
YG		 927
928 host->bus_width = ios->bus_width;
3b0beafc 929 host->state = STATE_IDLE;
fdc50a94
YG		 930}
931
777271d0
AH		 932static int sh_mmcif_get_cd(struct mmc_host *mmc)
933{
934 struct sh_mmcif_host *host = mmc_priv(mmc);
935 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
936
937 if (!p->get_cd)
938 return -ENOSYS;
939 else
940 return p->get_cd(host->pd);
941}
942
fdc50a94
YG		 943static struct mmc_host_ops sh_mmcif_ops = {
944 .request = sh_mmcif_request,
945 .set_ios = sh_mmcif_set_ios,
777271d0 946 .get_cd = sh_mmcif_get_cd,
fdc50a94
YG		 947};
948
949static void sh_mmcif_detect(struct mmc_host *mmc)
950{
951 mmc_detect_change(mmc, 0);
952}
953
954static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
955{
956 struct sh_mmcif_host *host = dev_id;
aa0787a9 957 u32 state;
fdc50a94
YG		 958 int err = 0;
959
487d9fc5 960 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
fdc50a94
YG		 961
962 if (state & INT_RBSYE) {
487d9fc5
MD		 963 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
964 ~(INT_RBSYE | INT_CRSPE));
fdc50a94
YG		 965 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
966 } else if (state & INT_CRSPE) {
487d9fc5 967 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
fdc50a94
YG		 968 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
969 } else if (state & INT_BUFREN) {
487d9fc5 970 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
fdc50a94
YG		 971 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
972 } else if (state & INT_BUFWEN) {
487d9fc5 973 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
fdc50a94
YG		 974 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
975 } else if (state & INT_CMD12DRE) {
487d9fc5 976 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
fdc50a94
YG		 977 ~(INT_CMD12DRE | INT_CMD12RBE |
978 INT_CMD12CRE | INT_BUFRE));
979 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
980 } else if (state & INT_BUFRE) {
487d9fc5 981 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
fdc50a94
YG		 982 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
983 } else if (state & INT_DTRANE) {
487d9fc5 984 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
fdc50a94
YG		 985 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
986 } else if (state & INT_CMD12RBE) {
487d9fc5 987 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
fdc50a94
YG		 988 ~(INT_CMD12RBE | INT_CMD12CRE));
989 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
990 } else if (state & INT_ERR_STS) {
991 /* err interrupts */
487d9fc5 992 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
fdc50a94
YG		 993 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
994 err = 1;
995 } else {
faca6648 996 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
487d9fc5 997 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
fdc50a94
YG		 998 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
999 err = 1;
1000 }
1001 if (err) {
aa0787a9 1002 host->sd_error = true;
e47bf32a 1003 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
fdc50a94 1004 }
aa0787a9
GL		 1005 if (state & ~(INT_CMD12RBE | INT_CMD12CRE))
1006 complete(&host->intr_wait);
1007 else
1008 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
fdc50a94
YG		 1009
1010 return IRQ_HANDLED;
1011}
1012
1013static int __devinit sh_mmcif_probe(struct platform_device *pdev)
1014{
1015 int ret = 0, irq[2];
1016 struct mmc_host *mmc;
e47bf32a
GL		 1017 struct sh_mmcif_host *host;
1018 struct sh_mmcif_plat_data *pd;
fdc50a94
YG		 1019 struct resource *res;
1020 void __iomem *reg;
1021 char clk_name[8];
1022
1023 irq[0] = platform_get_irq(pdev, 0);
1024 irq[1] = platform_get_irq(pdev, 1);
1025 if (irq[0] < 0 || irq[1] < 0) {
e47bf32a 1026 dev_err(&pdev->dev, "Get irq error\n");
fdc50a94
YG		 1027 return -ENXIO;
1028 }
1029 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1030 if (!res) {
1031 dev_err(&pdev->dev, "platform_get_resource error.\n");
1032 return -ENXIO;
1033 }
1034 reg = ioremap(res->start, resource_size(res));
1035 if (!reg) {
1036 dev_err(&pdev->dev, "ioremap error.\n");
1037 return -ENOMEM;
1038 }
e47bf32a 1039 pd = pdev->dev.platform_data;
fdc50a94
YG		 1040 if (!pd) {
1041 dev_err(&pdev->dev, "sh_mmcif plat data error.\n");
1042 ret = -ENXIO;
1043 goto clean_up;
1044 }
1045 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1046 if (!mmc) {
1047 ret = -ENOMEM;
1048 goto clean_up;
1049 }
1050 host = mmc_priv(mmc);
1051 host->mmc = mmc;
1052 host->addr = reg;
1053 host->timeout = 1000;
1054
1055 snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
1056 host->hclk = clk_get(&pdev->dev, clk_name);
1057 if (IS_ERR(host->hclk)) {
1058 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
1059 ret = PTR_ERR(host->hclk);
1060 goto clean_up1;
1061 }
1062 clk_enable(host->hclk);
1063 host->clk = clk_get_rate(host->hclk);
1064 host->pd = pdev;
1065
aa0787a9 1066 init_completion(&host->intr_wait);
3b0beafc 1067 spin_lock_init(&host->lock);
fdc50a94
YG		 1068
1069 mmc->ops = &sh_mmcif_ops;
1070 mmc->f_max = host->clk;
1071 /* close to 400KHz */
1072 if (mmc->f_max < 51200000)
1073 mmc->f_min = mmc->f_max / 128;
1074 else if (mmc->f_max < 102400000)
1075 mmc->f_min = mmc->f_max / 256;
1076 else
1077 mmc->f_min = mmc->f_max / 512;
1078 if (pd->ocr)
1079 mmc->ocr_avail = pd->ocr;
1080 mmc->caps = MMC_CAP_MMC_HIGHSPEED;
1081 if (pd->caps)
1082 mmc->caps |= pd->caps;
a782d688 1083 mmc->max_segs = 32;
fdc50a94 1084 mmc->max_blk_size = 512;
a782d688
GL		 1085 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1086 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
fdc50a94
YG		 1087 mmc->max_seg_size = mmc->max_req_size;
1088
1089 sh_mmcif_sync_reset(host);
1090 platform_set_drvdata(pdev, host);
a782d688 1091
faca6648
GL		 1092 pm_runtime_enable(&pdev->dev);
1093 host->power = false;
1094
1095 ret = pm_runtime_resume(&pdev->dev);
1096 if (ret < 0)
1097 goto clean_up2;
a782d688 1098
fdc50a94
YG		 1099 mmc_add_host(mmc);
1100
3b0beafc
GL		 1101 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1102
fdc50a94
YG		 1103 ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host);
1104 if (ret) {
e47bf32a 1105 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
faca6648 1106 goto clean_up3;
fdc50a94
YG		 1107 }
1108 ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host);
1109 if (ret) {
1110 free_irq(irq[0], host);
e47bf32a 1111 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
faca6648 1112 goto clean_up3;
fdc50a94
YG		 1113 }
1114
fdc50a94
YG		 1115 sh_mmcif_detect(host->mmc);
1116
e47bf32a
GL		 1117 dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1118 dev_dbg(&pdev->dev, "chip ver H'%04x\n",
487d9fc5 1119 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
fdc50a94
YG		 1120 return ret;
1121
faca6648
GL		 1122clean_up3:
1123 mmc_remove_host(mmc);
1124 pm_runtime_suspend(&pdev->dev);
fdc50a94 1125clean_up2:
faca6648 1126 pm_runtime_disable(&pdev->dev);
fdc50a94
YG		 1127 clk_disable(host->hclk);
1128clean_up1:
1129 mmc_free_host(mmc);
1130clean_up:
1131 if (reg)
1132 iounmap(reg);
1133 return ret;
1134}
1135
1136static int __devexit sh_mmcif_remove(struct platform_device *pdev)
1137{
1138 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1139 int irq[2];
1140
faca6648 1141 pm_runtime_get_sync(&pdev->dev);
fdc50a94 1142
faca6648 1143 mmc_remove_host(host->mmc);
3b0beafc
GL		 1144 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1145
fdc50a94
YG		 1146 if (host->addr)
1147 iounmap(host->addr);
1148
aa0787a9
GL		 1149 irq[0] = platform_get_irq(pdev, 0);
1150 irq[1] = platform_get_irq(pdev, 1);
fdc50a94
YG		 1151
1152 free_irq(irq[0], host);
1153 free_irq(irq[1], host);
1154
aa0787a9
GL		 1155 platform_set_drvdata(pdev, NULL);
1156
fdc50a94
YG		 1157 clk_disable(host->hclk);
1158 mmc_free_host(host->mmc);
faca6648
GL		 1159 pm_runtime_put_sync(&pdev->dev);
1160 pm_runtime_disable(&pdev->dev);
fdc50a94
YG		 1161
1162 return 0;
1163}
1164
faca6648
GL		 1165#ifdef CONFIG_PM
1166static int sh_mmcif_suspend(struct device *dev)
1167{
1168 struct platform_device *pdev = to_platform_device(dev);
1169 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1170 int ret = mmc_suspend_host(host->mmc);
1171
1172 if (!ret) {
1173 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1174 clk_disable(host->hclk);
1175 }
1176
1177 return ret;
1178}
1179
1180static int sh_mmcif_resume(struct device *dev)
1181{
1182 struct platform_device *pdev = to_platform_device(dev);
1183 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1184
1185 clk_enable(host->hclk);
1186
1187 return mmc_resume_host(host->mmc);
1188}
1189#else
1190#define sh_mmcif_suspend NULL
1191#define sh_mmcif_resume NULL
1192#endif /* CONFIG_PM */
1193
1194static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1195 .suspend = sh_mmcif_suspend,
1196 .resume = sh_mmcif_resume,
1197};
1198
fdc50a94
YG		 1199static struct platform_driver sh_mmcif_driver = {
1200 .probe = sh_mmcif_probe,
1201 .remove = sh_mmcif_remove,
1202 .driver = {
1203 .name = DRIVER_NAME,
faca6648 1204 .pm = &sh_mmcif_dev_pm_ops,
fdc50a94
YG		 1205 },
1206};
1207
1208static int __init sh_mmcif_init(void)
1209{
1210 return platform_driver_register(&sh_mmcif_driver);
1211}
1212
1213static void __exit sh_mmcif_exit(void)
1214{
1215 platform_driver_unregister(&sh_mmcif_driver);
1216}
1217
1218module_init(sh_mmcif_init);
1219module_exit(sh_mmcif_exit);
1220
1221
1222MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1223MODULE_LICENSE("GPL");
aa0787a9 1224MODULE_ALIAS("platform:" DRIVER_NAME);
fdc50a94 1225MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");
Linux 6.x block layer and io_uring tree(s)