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Merge branch 'common/mmcif' into rmobile/mmcif
[linux-2.6-block.git] / drivers / mmc / host / sh_mmcif.c
CommitLineData
fdc50a94
YG		 1/*
2 * MMCIF eMMC driver.
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10 *
11 *
12 * TODO
13 * 1. DMA
14 * 2. Power management
15 * 3. Handle MMC errors better
16 *
17 */
18
19#include <linux/dma-mapping.h>
20#include <linux/mmc/host.h>
21#include <linux/mmc/card.h>
22#include <linux/mmc/core.h>
23#include <linux/mmc/mmc.h>
24#include <linux/mmc/sdio.h>
25#include <linux/delay.h>
26#include <linux/platform_device.h>
27#include <linux/clk.h>
28#include <linux/mmc/sh_mmcif.h>
29
30#define DRIVER_NAME "sh_mmcif"
31#define DRIVER_VERSION "2010-04-28"
32
fdc50a94
YG		 33/* CE_CMD_SET */
34#define CMD_MASK 0x3f000000
35#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
36#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
37#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
38#define CMD_SET_RBSY (1 << 21) /* R1b */
39#define CMD_SET_CCSEN (1 << 20)
40#define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
41#define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
42#define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
43#define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
44#define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
45#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
46#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
47#define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
48#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
49#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
50#define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
51#define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
52#define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
53#define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
54#define CMD_SET_CCSH (1 << 5)
55#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
56#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
57#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
58
59/* CE_CMD_CTRL */
60#define CMD_CTRL_BREAK (1 << 0)
61
62/* CE_BLOCK_SET */
63#define BLOCK_SIZE_MASK 0x0000ffff
64
fdc50a94
YG		 65/* CE_INT */
66#define INT_CCSDE (1 << 29)
67#define INT_CMD12DRE (1 << 26)
68#define INT_CMD12RBE (1 << 25)
69#define INT_CMD12CRE (1 << 24)
70#define INT_DTRANE (1 << 23)
71#define INT_BUFRE (1 << 22)
72#define INT_BUFWEN (1 << 21)
73#define INT_BUFREN (1 << 20)
74#define INT_CCSRCV (1 << 19)
75#define INT_RBSYE (1 << 17)
76#define INT_CRSPE (1 << 16)
77#define INT_CMDVIO (1 << 15)
78#define INT_BUFVIO (1 << 14)
79#define INT_WDATERR (1 << 11)
80#define INT_RDATERR (1 << 10)
81#define INT_RIDXERR (1 << 9)
82#define INT_RSPERR (1 << 8)
83#define INT_CCSTO (1 << 5)
84#define INT_CRCSTO (1 << 4)
85#define INT_WDATTO (1 << 3)
86#define INT_RDATTO (1 << 2)
87#define INT_RBSYTO (1 << 1)
88#define INT_RSPTO (1 << 0)
89#define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
90 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
91 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
92 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
93
94/* CE_INT_MASK */
95#define MASK_ALL 0x00000000
96#define MASK_MCCSDE (1 << 29)
97#define MASK_MCMD12DRE (1 << 26)
98#define MASK_MCMD12RBE (1 << 25)
99#define MASK_MCMD12CRE (1 << 24)
100#define MASK_MDTRANE (1 << 23)
101#define MASK_MBUFRE (1 << 22)
102#define MASK_MBUFWEN (1 << 21)
103#define MASK_MBUFREN (1 << 20)
104#define MASK_MCCSRCV (1 << 19)
105#define MASK_MRBSYE (1 << 17)
106#define MASK_MCRSPE (1 << 16)
107#define MASK_MCMDVIO (1 << 15)
108#define MASK_MBUFVIO (1 << 14)
109#define MASK_MWDATERR (1 << 11)
110#define MASK_MRDATERR (1 << 10)
111#define MASK_MRIDXERR (1 << 9)
112#define MASK_MRSPERR (1 << 8)
113#define MASK_MCCSTO (1 << 5)
114#define MASK_MCRCSTO (1 << 4)
115#define MASK_MWDATTO (1 << 3)
116#define MASK_MRDATTO (1 << 2)
117#define MASK_MRBSYTO (1 << 1)
118#define MASK_MRSPTO (1 << 0)
119
120/* CE_HOST_STS1 */
121#define STS1_CMDSEQ (1 << 31)
122
123/* CE_HOST_STS2 */
124#define STS2_CRCSTE (1 << 31)
125#define STS2_CRC16E (1 << 30)
126#define STS2_AC12CRCE (1 << 29)
127#define STS2_RSPCRC7E (1 << 28)
128#define STS2_CRCSTEBE (1 << 27)
129#define STS2_RDATEBE (1 << 26)
130#define STS2_AC12REBE (1 << 25)
131#define STS2_RSPEBE (1 << 24)
132#define STS2_AC12IDXE (1 << 23)
133#define STS2_RSPIDXE (1 << 22)
134#define STS2_CCSTO (1 << 15)
135#define STS2_RDATTO (1 << 14)
136#define STS2_DATBSYTO (1 << 13)
137#define STS2_CRCSTTO (1 << 12)
138#define STS2_AC12BSYTO (1 << 11)
139#define STS2_RSPBSYTO (1 << 10)
140#define STS2_AC12RSPTO (1 << 9)
141#define STS2_RSPTO (1 << 8)
142#define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
143 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
144#define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
145 STS2_DATBSYTO | STS2_CRCSTTO | \
146 STS2_AC12BSYTO | STS2_RSPBSYTO | \
147 STS2_AC12RSPTO | STS2_RSPTO)
148
fdc50a94
YG		 149#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
150#define CLKDEV_MMC_DATA 20000000 /* 20MHz */
151#define CLKDEV_INIT 400000 /* 400 KHz */
152
153struct sh_mmcif_host {
154 struct mmc_host *mmc;
155 struct mmc_data *data;
156 struct mmc_command *cmd;
157 struct platform_device *pd;
158 struct clk *hclk;
159 unsigned int clk;
160 int bus_width;
161 u16 wait_int;
162 u16 sd_error;
163 long timeout;
164 void __iomem *addr;
165 wait_queue_head_t intr_wait;
166};
167
fdc50a94
YG		 168
169static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
170 unsigned int reg, u32 val)
171{
487d9fc5 172 writel(val | readl(host->addr + reg), host->addr + reg);
fdc50a94
YG		 173}
174
175static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
176 unsigned int reg, u32 val)
177{
487d9fc5 178 writel(~val & readl(host->addr + reg), host->addr + reg);
fdc50a94
YG		 179}
180
181
182static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
183{
184 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
185
186 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
187 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
188
189 if (!clk)
190 return;
191 if (p->sup_pclk && clk == host->clk)
192 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
193 else
194 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
195 (ilog2(__rounddown_pow_of_two(host->clk / clk)) << 16));
196
197 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
198}
199
200static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
201{
202 u32 tmp;
203
487d9fc5 204 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
fdc50a94 205
487d9fc5
MD		 206 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
207 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
fdc50a94
YG		 208 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
209 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
210 /* byte swap on */
211 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
212}
213
214static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
215{
216 u32 state1, state2;
217 int ret, timeout = 10000000;
218
219 host->sd_error = 0;
220 host->wait_int = 0;
221
487d9fc5
MD		 222 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
223 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
224 pr_debug("%s: ERR HOST_STS1 = %08x\n", DRIVER_NAME, state1);
225 pr_debug("%s: ERR HOST_STS2 = %08x\n", DRIVER_NAME, state2);
fdc50a94
YG		 226
227 if (state1 & STS1_CMDSEQ) {
228 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
229 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
230 while (1) {
231 timeout--;
232 if (timeout < 0) {
233 pr_err(DRIVER_NAME": Forceed end of " \
234 "command sequence timeout err\n");
235 return -EIO;
236 }
487d9fc5 237 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
fdc50a94
YG		 238 & STS1_CMDSEQ))
239 break;
240 mdelay(1);
241 }
242 sh_mmcif_sync_reset(host);
243 pr_debug(DRIVER_NAME": Forced end of command sequence\n");
244 return -EIO;
245 }
246
247 if (state2 & STS2_CRC_ERR) {
248 pr_debug(DRIVER_NAME": Happened CRC error\n");
249 ret = -EIO;
250 } else if (state2 & STS2_TIMEOUT_ERR) {
251 pr_debug(DRIVER_NAME": Happened Timeout error\n");
252 ret = -ETIMEDOUT;
253 } else {
254 pr_debug(DRIVER_NAME": Happened End/Index error\n");
255 ret = -EIO;
256 }
257 return ret;
258}
259
260static int sh_mmcif_single_read(struct sh_mmcif_host *host,
261 struct mmc_request *mrq)
262{
263 struct mmc_data *data = mrq->data;
264 long time;
265 u32 blocksize, i, *p = sg_virt(data->sg);
266
267 host->wait_int = 0;
268
269 /* buf read enable */
270 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
271 time = wait_event_interruptible_timeout(host->intr_wait,
272 host->wait_int == 1 ||
273 host->sd_error == 1, host->timeout);
274 if (host->wait_int != 1 && (time == 0 || host->sd_error != 0))
275 return sh_mmcif_error_manage(host);
276
277 host->wait_int = 0;
278 blocksize = (BLOCK_SIZE_MASK &
487d9fc5 279 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
fdc50a94 280 for (i = 0; i < blocksize / 4; i++)
487d9fc5 281 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
fdc50a94
YG		 282
283 /* buffer read end */
284 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
285 time = wait_event_interruptible_timeout(host->intr_wait,
286 host->wait_int == 1 ||
287 host->sd_error == 1, host->timeout);
288 if (host->wait_int != 1 && (time == 0 || host->sd_error != 0))
289 return sh_mmcif_error_manage(host);
290
291 host->wait_int = 0;
292 return 0;
293}
294
295static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
296 struct mmc_request *mrq)
297{
298 struct mmc_data *data = mrq->data;
299 long time;
300 u32 blocksize, i, j, sec, *p;
301
487d9fc5
MD		 302 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
303 MMCIF_CE_BLOCK_SET);
fdc50a94
YG		 304 for (j = 0; j < data->sg_len; j++) {
305 p = sg_virt(data->sg);
306 host->wait_int = 0;
307 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
308 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
309 /* buf read enable */
310 time = wait_event_interruptible_timeout(host->intr_wait,
311 host->wait_int == 1 ||
312 host->sd_error == 1, host->timeout);
313
314 if (host->wait_int != 1 &&
315 (time == 0 || host->sd_error != 0))
316 return sh_mmcif_error_manage(host);
317
318 host->wait_int = 0;
319 for (i = 0; i < blocksize / 4; i++)
487d9fc5
MD		 320 *p++ = sh_mmcif_readl(host->addr,
321 MMCIF_CE_DATA);
fdc50a94
YG		 322 }
323 if (j < data->sg_len - 1)
324 data->sg++;
325 }
326 return 0;
327}
328
329static int sh_mmcif_single_write(struct sh_mmcif_host *host,
330 struct mmc_request *mrq)
331{
332 struct mmc_data *data = mrq->data;
333 long time;
334 u32 blocksize, i, *p = sg_virt(data->sg);
335
336 host->wait_int = 0;
337 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
338
339 /* buf write enable */
340 time = wait_event_interruptible_timeout(host->intr_wait,
341 host->wait_int == 1 ||
342 host->sd_error == 1, host->timeout);
343 if (host->wait_int != 1 && (time == 0 || host->sd_error != 0))
344 return sh_mmcif_error_manage(host);
345
346 host->wait_int = 0;
347 blocksize = (BLOCK_SIZE_MASK &
487d9fc5 348 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
fdc50a94 349 for (i = 0; i < blocksize / 4; i++)
487d9fc5 350 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
fdc50a94
YG		 351
352 /* buffer write end */
353 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
354
355 time = wait_event_interruptible_timeout(host->intr_wait,
356 host->wait_int == 1 ||
357 host->sd_error == 1, host->timeout);
358 if (host->wait_int != 1 && (time == 0 || host->sd_error != 0))
359 return sh_mmcif_error_manage(host);
360
361 host->wait_int = 0;
362 return 0;
363}
364
365static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
366 struct mmc_request *mrq)
367{
368 struct mmc_data *data = mrq->data;
369 long time;
370 u32 i, sec, j, blocksize, *p;
371
487d9fc5
MD		 372 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
373 MMCIF_CE_BLOCK_SET);
fdc50a94
YG		 374
375 for (j = 0; j < data->sg_len; j++) {
376 p = sg_virt(data->sg);
377 host->wait_int = 0;
378 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
379 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
380 /* buf write enable*/
381 time = wait_event_interruptible_timeout(host->intr_wait,
382 host->wait_int == 1 ||
383 host->sd_error == 1, host->timeout);
384
385 if (host->wait_int != 1 &&
386 (time == 0 || host->sd_error != 0))
387 return sh_mmcif_error_manage(host);
388
389 host->wait_int = 0;
390 for (i = 0; i < blocksize / 4; i++)
487d9fc5
MD		 391 sh_mmcif_writel(host->addr,
392 MMCIF_CE_DATA, *p++);
fdc50a94
YG		 393 }
394 if (j < data->sg_len - 1)
395 data->sg++;
396 }
397 return 0;
398}
399
400static void sh_mmcif_get_response(struct sh_mmcif_host *host,
401 struct mmc_command *cmd)
402{
403 if (cmd->flags & MMC_RSP_136) {
487d9fc5
MD		 404 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
405 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
406 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
407 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
fdc50a94 408 } else
487d9fc5 409 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
fdc50a94
YG		 410}
411
412static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
413 struct mmc_command *cmd)
414{
487d9fc5 415 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
fdc50a94
YG		 416}
417
418static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
419 struct mmc_request *mrq, struct mmc_command *cmd, u32 opc)
420{
421 u32 tmp = 0;
422
423 /* Response Type check */
424 switch (mmc_resp_type(cmd)) {
425 case MMC_RSP_NONE:
426 tmp |= CMD_SET_RTYP_NO;
427 break;
428 case MMC_RSP_R1:
429 case MMC_RSP_R1B:
430 case MMC_RSP_R3:
431 tmp |= CMD_SET_RTYP_6B;
432 break;
433 case MMC_RSP_R2:
434 tmp |= CMD_SET_RTYP_17B;
435 break;
436 default:
437 pr_err(DRIVER_NAME": Not support type response.\n");
438 break;
439 }
440 switch (opc) {
441 /* RBSY */
442 case MMC_SWITCH:
443 case MMC_STOP_TRANSMISSION:
444 case MMC_SET_WRITE_PROT:
445 case MMC_CLR_WRITE_PROT:
446 case MMC_ERASE:
447 case MMC_GEN_CMD:
448 tmp |= CMD_SET_RBSY;
449 break;
450 }
451 /* WDAT / DATW */
452 if (host->data) {
453 tmp |= CMD_SET_WDAT;
454 switch (host->bus_width) {
455 case MMC_BUS_WIDTH_1:
456 tmp |= CMD_SET_DATW_1;
457 break;
458 case MMC_BUS_WIDTH_4:
459 tmp |= CMD_SET_DATW_4;
460 break;
461 case MMC_BUS_WIDTH_8:
462 tmp |= CMD_SET_DATW_8;
463 break;
464 default:
465 pr_err(DRIVER_NAME": Not support bus width.\n");
466 break;
467 }
468 }
469 /* DWEN */
470 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
471 tmp |= CMD_SET_DWEN;
472 /* CMLTE/CMD12EN */
473 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
474 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
475 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
476 mrq->data->blocks << 16);
477 }
478 /* RIDXC[1:0] check bits */
479 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
480 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
481 tmp |= CMD_SET_RIDXC_BITS;
482 /* RCRC7C[1:0] check bits */
483 if (opc == MMC_SEND_OP_COND)
484 tmp |= CMD_SET_CRC7C_BITS;
485 /* RCRC7C[1:0] internal CRC7 */
486 if (opc == MMC_ALL_SEND_CID ||
487 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
488 tmp |= CMD_SET_CRC7C_INTERNAL;
489
490 return opc = ((opc << 24) | tmp);
491}
492
493static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
494 struct mmc_request *mrq, u32 opc)
495{
496 u32 ret;
497
498 switch (opc) {
499 case MMC_READ_MULTIPLE_BLOCK:
500 ret = sh_mmcif_multi_read(host, mrq);
501 break;
502 case MMC_WRITE_MULTIPLE_BLOCK:
503 ret = sh_mmcif_multi_write(host, mrq);
504 break;
505 case MMC_WRITE_BLOCK:
506 ret = sh_mmcif_single_write(host, mrq);
507 break;
508 case MMC_READ_SINGLE_BLOCK:
509 case MMC_SEND_EXT_CSD:
510 ret = sh_mmcif_single_read(host, mrq);
511 break;
512 default:
513 pr_err(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
514 ret = -EINVAL;
515 break;
516 }
517 return ret;
518}
519
520static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
521 struct mmc_request *mrq, struct mmc_command *cmd)
522{
523 long time;
524 int ret = 0, mask = 0;
525 u32 opc = cmd->opcode;
526
527 host->cmd = cmd;
528
529 switch (opc) {
530 /* respons busy check */
531 case MMC_SWITCH:
532 case MMC_STOP_TRANSMISSION:
533 case MMC_SET_WRITE_PROT:
534 case MMC_CLR_WRITE_PROT:
535 case MMC_ERASE:
536 case MMC_GEN_CMD:
537 mask = MASK_MRBSYE;
538 break;
539 default:
540 mask = MASK_MCRSPE;
541 break;
542 }
543 mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
544 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
545 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
546 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
547
548 if (host->data) {
487d9fc5
MD		 549 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
550 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
551 mrq->data->blksz);
fdc50a94
YG		 552 }
553 opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
554
487d9fc5
MD		 555 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
556 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
fdc50a94 557 /* set arg */
487d9fc5 558 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
fdc50a94
YG		 559 host->wait_int = 0;
560 /* set cmd */
487d9fc5 561 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
fdc50a94
YG		 562
563 time = wait_event_interruptible_timeout(host->intr_wait,
564 host->wait_int == 1 || host->sd_error == 1, host->timeout);
565 if (host->wait_int != 1 && time == 0) {
566 cmd->error = sh_mmcif_error_manage(host);
567 return;
568 }
569 if (host->sd_error) {
570 switch (cmd->opcode) {
571 case MMC_ALL_SEND_CID:
572 case MMC_SELECT_CARD:
573 case MMC_APP_CMD:
574 cmd->error = -ETIMEDOUT;
575 break;
576 default:
577 pr_debug("%s: Cmd(d'%d) err\n",
578 DRIVER_NAME, cmd->opcode);
579 cmd->error = sh_mmcif_error_manage(host);
580 break;
581 }
582 host->sd_error = 0;
583 host->wait_int = 0;
584 return;
585 }
586 if (!(cmd->flags & MMC_RSP_PRESENT)) {
587 cmd->error = ret;
588 host->wait_int = 0;
589 return;
590 }
591 if (host->wait_int == 1) {
592 sh_mmcif_get_response(host, cmd);
593 host->wait_int = 0;
594 }
595 if (host->data) {
596 ret = sh_mmcif_data_trans(host, mrq, cmd->opcode);
597 if (ret < 0)
598 mrq->data->bytes_xfered = 0;
599 else
600 mrq->data->bytes_xfered =
601 mrq->data->blocks * mrq->data->blksz;
602 }
603 cmd->error = ret;
604}
605
606static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
607 struct mmc_request *mrq, struct mmc_command *cmd)
608{
609 long time;
610
611 if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK)
612 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
613 else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
614 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
615 else {
616 pr_err(DRIVER_NAME": not support stop cmd\n");
617 cmd->error = sh_mmcif_error_manage(host);
618 return;
619 }
620
621 time = wait_event_interruptible_timeout(host->intr_wait,
622 host->wait_int == 1 ||
623 host->sd_error == 1, host->timeout);
624 if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) {
625 cmd->error = sh_mmcif_error_manage(host);
626 return;
627 }
628 sh_mmcif_get_cmd12response(host, cmd);
629 host->wait_int = 0;
630 cmd->error = 0;
631}
632
633static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
634{
635 struct sh_mmcif_host *host = mmc_priv(mmc);
636
637 switch (mrq->cmd->opcode) {
638 /* MMCIF does not support SD/SDIO command */
639 case SD_IO_SEND_OP_COND:
640 case MMC_APP_CMD:
641 mrq->cmd->error = -ETIMEDOUT;
642 mmc_request_done(mmc, mrq);
643 return;
644 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
645 if (!mrq->data) {
646 /* send_if_cond cmd (not support) */
647 mrq->cmd->error = -ETIMEDOUT;
648 mmc_request_done(mmc, mrq);
649 return;
650 }
651 break;
652 default:
653 break;
654 }
655 host->data = mrq->data;
656 sh_mmcif_start_cmd(host, mrq, mrq->cmd);
657 host->data = NULL;
658
659 if (mrq->cmd->error != 0) {
660 mmc_request_done(mmc, mrq);
661 return;
662 }
663 if (mrq->stop)
664 sh_mmcif_stop_cmd(host, mrq, mrq->stop);
665 mmc_request_done(mmc, mrq);
666}
667
668static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
669{
670 struct sh_mmcif_host *host = mmc_priv(mmc);
671 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
672
673 if (ios->power_mode == MMC_POWER_OFF) {
674 /* clock stop */
675 sh_mmcif_clock_control(host, 0);
676 if (p->down_pwr)
677 p->down_pwr(host->pd);
678 return;
679 } else if (ios->power_mode == MMC_POWER_UP) {
680 if (p->set_pwr)
681 p->set_pwr(host->pd, ios->power_mode);
682 }
683
684 if (ios->clock)
685 sh_mmcif_clock_control(host, ios->clock);
686
687 host->bus_width = ios->bus_width;
688}
689
777271d0
AH		 690static int sh_mmcif_get_cd(struct mmc_host *mmc)
691{
692 struct sh_mmcif_host *host = mmc_priv(mmc);
693 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
694
695 if (!p->get_cd)
696 return -ENOSYS;
697 else
698 return p->get_cd(host->pd);
699}
700
fdc50a94
YG		 701static struct mmc_host_ops sh_mmcif_ops = {
702 .request = sh_mmcif_request,
703 .set_ios = sh_mmcif_set_ios,
777271d0 704 .get_cd = sh_mmcif_get_cd,
fdc50a94
YG		 705};
706
707static void sh_mmcif_detect(struct mmc_host *mmc)
708{
709 mmc_detect_change(mmc, 0);
710}
711
712static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
713{
714 struct sh_mmcif_host *host = dev_id;
715 u32 state = 0;
716 int err = 0;
717
487d9fc5 718 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
fdc50a94
YG		 719
720 if (state & INT_RBSYE) {
487d9fc5
MD		 721 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
722 ~(INT_RBSYE | INT_CRSPE));
fdc50a94
YG		 723 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
724 } else if (state & INT_CRSPE) {
487d9fc5 725 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
fdc50a94
YG		 726 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
727 } else if (state & INT_BUFREN) {
487d9fc5 728 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
fdc50a94
YG		 729 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
730 } else if (state & INT_BUFWEN) {
487d9fc5 731 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
fdc50a94
YG		 732 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
733 } else if (state & INT_CMD12DRE) {
487d9fc5 734 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
fdc50a94
YG		 735 ~(INT_CMD12DRE | INT_CMD12RBE |
736 INT_CMD12CRE | INT_BUFRE));
737 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
738 } else if (state & INT_BUFRE) {
487d9fc5 739 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
fdc50a94
YG		 740 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
741 } else if (state & INT_DTRANE) {
487d9fc5 742 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
fdc50a94
YG		 743 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
744 } else if (state & INT_CMD12RBE) {
487d9fc5 745 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
fdc50a94
YG		 746 ~(INT_CMD12RBE | INT_CMD12CRE));
747 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
748 } else if (state & INT_ERR_STS) {
749 /* err interrupts */
487d9fc5 750 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
fdc50a94
YG		 751 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
752 err = 1;
753 } else {
754 pr_debug("%s: Not support int\n", DRIVER_NAME);
487d9fc5 755 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
fdc50a94
YG		 756 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
757 err = 1;
758 }
759 if (err) {
760 host->sd_error = 1;
761 pr_debug("%s: int err state = %08x\n", DRIVER_NAME, state);
762 }
763 host->wait_int = 1;
764 wake_up(&host->intr_wait);
765
766 return IRQ_HANDLED;
767}
768
769static int __devinit sh_mmcif_probe(struct platform_device *pdev)
770{
771 int ret = 0, irq[2];
772 struct mmc_host *mmc;
773 struct sh_mmcif_host *host = NULL;
774 struct sh_mmcif_plat_data *pd = NULL;
775 struct resource *res;
776 void __iomem *reg;
777 char clk_name[8];
778
779 irq[0] = platform_get_irq(pdev, 0);
780 irq[1] = platform_get_irq(pdev, 1);
781 if (irq[0] < 0 || irq[1] < 0) {
782 pr_err(DRIVER_NAME": Get irq error\n");
783 return -ENXIO;
784 }
785 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
786 if (!res) {
787 dev_err(&pdev->dev, "platform_get_resource error.\n");
788 return -ENXIO;
789 }
790 reg = ioremap(res->start, resource_size(res));
791 if (!reg) {
792 dev_err(&pdev->dev, "ioremap error.\n");
793 return -ENOMEM;
794 }
795 pd = (struct sh_mmcif_plat_data *)(pdev->dev.platform_data);
796 if (!pd) {
797 dev_err(&pdev->dev, "sh_mmcif plat data error.\n");
798 ret = -ENXIO;
799 goto clean_up;
800 }
801 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
802 if (!mmc) {
803 ret = -ENOMEM;
804 goto clean_up;
805 }
806 host = mmc_priv(mmc);
807 host->mmc = mmc;
808 host->addr = reg;
809 host->timeout = 1000;
810
811 snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
812 host->hclk = clk_get(&pdev->dev, clk_name);
813 if (IS_ERR(host->hclk)) {
814 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
815 ret = PTR_ERR(host->hclk);
816 goto clean_up1;
817 }
818 clk_enable(host->hclk);
819 host->clk = clk_get_rate(host->hclk);
820 host->pd = pdev;
821
822 init_waitqueue_head(&host->intr_wait);
823
824 mmc->ops = &sh_mmcif_ops;
825 mmc->f_max = host->clk;
826 /* close to 400KHz */
827 if (mmc->f_max < 51200000)
828 mmc->f_min = mmc->f_max / 128;
829 else if (mmc->f_max < 102400000)
830 mmc->f_min = mmc->f_max / 256;
831 else
832 mmc->f_min = mmc->f_max / 512;
833 if (pd->ocr)
834 mmc->ocr_avail = pd->ocr;
835 mmc->caps = MMC_CAP_MMC_HIGHSPEED;
836 if (pd->caps)
837 mmc->caps |= pd->caps;
a36274e0 838 mmc->max_segs = 128;
fdc50a94
YG		 839 mmc->max_blk_size = 512;
840 mmc->max_blk_count = 65535;
841 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
842 mmc->max_seg_size = mmc->max_req_size;
843
844 sh_mmcif_sync_reset(host);
845 platform_set_drvdata(pdev, host);
846 mmc_add_host(mmc);
847
848 ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host);
849 if (ret) {
850 pr_err(DRIVER_NAME": request_irq error (sh_mmc:error)\n");
851 goto clean_up2;
852 }
853 ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host);
854 if (ret) {
855 free_irq(irq[0], host);
856 pr_err(DRIVER_NAME": request_irq error (sh_mmc:int)\n");
857 goto clean_up2;
858 }
859
487d9fc5 860 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
fdc50a94
YG		 861 sh_mmcif_detect(host->mmc);
862
863 pr_info("%s: driver version %s\n", DRIVER_NAME, DRIVER_VERSION);
864 pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME,
487d9fc5 865 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
fdc50a94
YG		 866 return ret;
867
868clean_up2:
869 clk_disable(host->hclk);
870clean_up1:
871 mmc_free_host(mmc);
872clean_up:
873 if (reg)
874 iounmap(reg);
875 return ret;
876}
877
878static int __devexit sh_mmcif_remove(struct platform_device *pdev)
879{
880 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
881 int irq[2];
882
487d9fc5 883 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
fdc50a94
YG		 884
885 irq[0] = platform_get_irq(pdev, 0);
886 irq[1] = platform_get_irq(pdev, 1);
887
888 if (host->addr)
889 iounmap(host->addr);
890
891 platform_set_drvdata(pdev, NULL);
892 mmc_remove_host(host->mmc);
893
894 free_irq(irq[0], host);
895 free_irq(irq[1], host);
896
897 clk_disable(host->hclk);
898 mmc_free_host(host->mmc);
899
900 return 0;
901}
902
903static struct platform_driver sh_mmcif_driver = {
904 .probe = sh_mmcif_probe,
905 .remove = sh_mmcif_remove,
906 .driver = {
907 .name = DRIVER_NAME,
908 },
909};
910
911static int __init sh_mmcif_init(void)
912{
913 return platform_driver_register(&sh_mmcif_driver);
914}
915
916static void __exit sh_mmcif_exit(void)
917{
918 platform_driver_unregister(&sh_mmcif_driver);
919}
920
921module_init(sh_mmcif_init);
922module_exit(sh_mmcif_exit);
923
924
925MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
926MODULE_LICENSE("GPL");
927MODULE_ALIAS(DRIVER_NAME);
928MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");
Linux 6.x block layer and io_uring tree(s)