Commit | Line | Data |
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a702c8ab ZG |
1 | /* |
2 | * Copyright (C) 2010 Marvell International Ltd. | |
3 | * Zhangfei Gao <zhangfei.gao@marvell.com> | |
4 | * Kevin Wang <dwang4@marvell.com> | |
5 | * Mingwei Wang <mwwang@marvell.com> | |
6 | * Philip Rakity <prakity@marvell.com> | |
7 | * Mark Brown <markb@marvell.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | #include <linux/err.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/gpio.h> | |
25 | #include <linux/mmc/card.h> | |
26 | #include <linux/mmc/host.h> | |
8f63795c | 27 | #include <linux/mmc/slot-gpio.h> |
bfed345e | 28 | #include <linux/platform_data/pxa_sdhci.h> |
a702c8ab ZG |
29 | #include <linux/slab.h> |
30 | #include <linux/delay.h> | |
88b47679 | 31 | #include <linux/module.h> |
b650352d CB |
32 | #include <linux/of.h> |
33 | #include <linux/of_device.h> | |
8f63795c | 34 | #include <linux/of_gpio.h> |
bb691ae4 KL |
35 | #include <linux/pm.h> |
36 | #include <linux/pm_runtime.h> | |
5491ce3f | 37 | #include <linux/mbus.h> |
b650352d | 38 | |
a702c8ab ZG |
39 | #include "sdhci.h" |
40 | #include "sdhci-pltfm.h" | |
41 | ||
bb691ae4 KL |
42 | #define PXAV3_RPM_DELAY_MS 50 |
43 | ||
a702c8ab ZG |
44 | #define SD_CLOCK_BURST_SIZE_SETUP 0x10A |
45 | #define SDCLK_SEL 0x100 | |
46 | #define SDCLK_DELAY_SHIFT 9 | |
47 | #define SDCLK_DELAY_MASK 0x1f | |
48 | ||
49 | #define SD_CFG_FIFO_PARAM 0x100 | |
50 | #define SDCFG_GEN_PAD_CLK_ON (1<<6) | |
51 | #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF | |
52 | #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24 | |
53 | ||
54 | #define SD_SPI_MODE 0x108 | |
55 | #define SD_CE_ATA_1 0x10C | |
56 | ||
57 | #define SD_CE_ATA_2 0x10E | |
58 | #define SDCE_MISC_INT (1<<2) | |
59 | #define SDCE_MISC_INT_EN (1<<1) | |
60 | ||
cc9571e8 | 61 | struct sdhci_pxa { |
8afdc9cc | 62 | struct clk *clk_core; |
8c96a7a3 | 63 | struct clk *clk_io; |
cc9571e8 | 64 | u8 power_mode; |
1140011e | 65 | void __iomem *sdio3_conf_reg; |
cc9571e8 SH |
66 | }; |
67 | ||
5491ce3f MW |
68 | /* |
69 | * These registers are relative to the second register region, for the | |
70 | * MBus bridge. | |
71 | */ | |
72 | #define SDHCI_WINDOW_CTRL(i) (0x80 + ((i) << 3)) | |
73 | #define SDHCI_WINDOW_BASE(i) (0x84 + ((i) << 3)) | |
74 | #define SDHCI_MAX_WIN_NUM 8 | |
75 | ||
1140011e MW |
76 | /* |
77 | * Fields below belong to SDIO3 Configuration Register (third register | |
78 | * region for the Armada 38x flavor) | |
79 | */ | |
80 | ||
81 | #define SDIO3_CONF_CLK_INV BIT(0) | |
82 | #define SDIO3_CONF_SD_FB_CLK BIT(2) | |
83 | ||
5491ce3f MW |
84 | static int mv_conf_mbus_windows(struct platform_device *pdev, |
85 | const struct mbus_dram_target_info *dram) | |
86 | { | |
87 | int i; | |
88 | void __iomem *regs; | |
89 | struct resource *res; | |
90 | ||
91 | if (!dram) { | |
92 | dev_err(&pdev->dev, "no mbus dram info\n"); | |
93 | return -EINVAL; | |
94 | } | |
95 | ||
96 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
97 | if (!res) { | |
98 | dev_err(&pdev->dev, "cannot get mbus registers\n"); | |
99 | return -EINVAL; | |
100 | } | |
101 | ||
102 | regs = ioremap(res->start, resource_size(res)); | |
103 | if (!regs) { | |
104 | dev_err(&pdev->dev, "cannot map mbus registers\n"); | |
105 | return -ENOMEM; | |
106 | } | |
107 | ||
108 | for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) { | |
109 | writel(0, regs + SDHCI_WINDOW_CTRL(i)); | |
110 | writel(0, regs + SDHCI_WINDOW_BASE(i)); | |
111 | } | |
112 | ||
113 | for (i = 0; i < dram->num_cs; i++) { | |
114 | const struct mbus_dram_window *cs = dram->cs + i; | |
115 | ||
116 | /* Write size, attributes and target id to control register */ | |
117 | writel(((cs->size - 1) & 0xffff0000) | | |
118 | (cs->mbus_attr << 8) | | |
119 | (dram->mbus_dram_target_id << 4) | 1, | |
120 | regs + SDHCI_WINDOW_CTRL(i)); | |
121 | /* Write base address to base register */ | |
122 | writel(cs->base, regs + SDHCI_WINDOW_BASE(i)); | |
123 | } | |
124 | ||
125 | iounmap(regs); | |
126 | ||
127 | return 0; | |
128 | } | |
129 | ||
a39128bc MW |
130 | static int armada_38x_quirks(struct platform_device *pdev, |
131 | struct sdhci_host *host) | |
d4b803c5 | 132 | { |
a39128bc | 133 | struct device_node *np = pdev->dev.of_node; |
1140011e MW |
134 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
135 | struct sdhci_pxa *pxa = pltfm_host->priv; | |
136 | struct resource *res; | |
a39128bc | 137 | |
5de76bfc | 138 | host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; |
d4b803c5 | 139 | host->quirks |= SDHCI_QUIRK_MISSING_CAPS; |
1140011e MW |
140 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
141 | "conf-sdio3"); | |
142 | if (res) { | |
143 | pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res); | |
144 | if (IS_ERR(pxa->sdio3_conf_reg)) | |
145 | return PTR_ERR(pxa->sdio3_conf_reg); | |
146 | } else { | |
147 | /* | |
148 | * According to erratum 'FE-2946959' both SDR50 and DDR50 | |
149 | * modes require specific clock adjustments in SDIO3 | |
150 | * Configuration register, if the adjustment is not done, | |
151 | * remove them from the capabilities. | |
152 | */ | |
153 | host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); | |
154 | host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); | |
155 | ||
156 | dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n"); | |
157 | } | |
a39128bc MW |
158 | |
159 | /* | |
160 | * According to erratum 'ERR-7878951' Armada 38x SDHCI | |
161 | * controller has different capabilities than the ones shown | |
162 | * in its registers | |
163 | */ | |
164 | host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); | |
165 | if (of_property_read_bool(np, "no-1-8-v")) { | |
166 | host->caps &= ~SDHCI_CAN_VDD_180; | |
167 | host->mmc->caps &= ~MMC_CAP_1_8V_DDR; | |
168 | } else { | |
169 | host->caps &= ~SDHCI_CAN_VDD_330; | |
170 | } | |
171 | host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING); | |
172 | ||
d4b803c5 GC |
173 | return 0; |
174 | } | |
175 | ||
03231f9b | 176 | static void pxav3_reset(struct sdhci_host *host, u8 mask) |
a702c8ab ZG |
177 | { |
178 | struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); | |
179 | struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; | |
180 | ||
03231f9b RK |
181 | sdhci_reset(host, mask); |
182 | ||
a702c8ab ZG |
183 | if (mask == SDHCI_RESET_ALL) { |
184 | /* | |
185 | * tune timing of read data/command when crc error happen | |
186 | * no performance impact | |
187 | */ | |
188 | if (pdata && 0 != pdata->clk_delay_cycles) { | |
189 | u16 tmp; | |
190 | ||
191 | tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); | |
192 | tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) | |
193 | << SDCLK_DELAY_SHIFT; | |
194 | tmp |= SDCLK_SEL; | |
195 | writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); | |
196 | } | |
197 | } | |
198 | } | |
199 | ||
200 | #define MAX_WAIT_COUNT 5 | |
201 | static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode) | |
202 | { | |
203 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
204 | struct sdhci_pxa *pxa = pltfm_host->priv; | |
205 | u16 tmp; | |
206 | int count; | |
207 | ||
208 | if (pxa->power_mode == MMC_POWER_UP | |
209 | && power_mode == MMC_POWER_ON) { | |
210 | ||
211 | dev_dbg(mmc_dev(host->mmc), | |
212 | "%s: slot->power_mode = %d," | |
213 | "ios->power_mode = %d\n", | |
214 | __func__, | |
215 | pxa->power_mode, | |
216 | power_mode); | |
217 | ||
218 | /* set we want notice of when 74 clocks are sent */ | |
219 | tmp = readw(host->ioaddr + SD_CE_ATA_2); | |
220 | tmp |= SDCE_MISC_INT_EN; | |
221 | writew(tmp, host->ioaddr + SD_CE_ATA_2); | |
222 | ||
223 | /* start sending the 74 clocks */ | |
224 | tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM); | |
225 | tmp |= SDCFG_GEN_PAD_CLK_ON; | |
226 | writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM); | |
227 | ||
228 | /* slowest speed is about 100KHz or 10usec per clock */ | |
229 | udelay(740); | |
230 | count = 0; | |
231 | ||
232 | while (count++ < MAX_WAIT_COUNT) { | |
233 | if ((readw(host->ioaddr + SD_CE_ATA_2) | |
234 | & SDCE_MISC_INT) == 0) | |
235 | break; | |
236 | udelay(10); | |
237 | } | |
238 | ||
239 | if (count == MAX_WAIT_COUNT) | |
240 | dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n"); | |
241 | ||
242 | /* clear the interrupt bit if posted */ | |
243 | tmp = readw(host->ioaddr + SD_CE_ATA_2); | |
244 | tmp |= SDCE_MISC_INT; | |
245 | writew(tmp, host->ioaddr + SD_CE_ATA_2); | |
246 | } | |
247 | pxa->power_mode = power_mode; | |
248 | } | |
249 | ||
13e64501 | 250 | static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) |
a702c8ab | 251 | { |
1140011e MW |
252 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
253 | struct sdhci_pxa *pxa = pltfm_host->priv; | |
a702c8ab ZG |
254 | u16 ctrl_2; |
255 | ||
256 | /* | |
257 | * Set V18_EN -- UHS modes do not work without this. | |
258 | * does not change signaling voltage | |
259 | */ | |
260 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
261 | ||
262 | /* Select Bus Speed Mode for host */ | |
263 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
264 | switch (uhs) { | |
265 | case MMC_TIMING_UHS_SDR12: | |
266 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | |
267 | break; | |
268 | case MMC_TIMING_UHS_SDR25: | |
269 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
270 | break; | |
271 | case MMC_TIMING_UHS_SDR50: | |
272 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180; | |
273 | break; | |
274 | case MMC_TIMING_UHS_SDR104: | |
275 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; | |
276 | break; | |
668e84b2 | 277 | case MMC_TIMING_MMC_DDR52: |
a702c8ab ZG |
278 | case MMC_TIMING_UHS_DDR50: |
279 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; | |
280 | break; | |
281 | } | |
282 | ||
1140011e MW |
283 | /* |
284 | * Update SDIO3 Configuration register according to erratum | |
285 | * FE-2946959 | |
286 | */ | |
287 | if (pxa->sdio3_conf_reg) { | |
288 | u8 reg_val = readb(pxa->sdio3_conf_reg); | |
289 | ||
290 | if (uhs == MMC_TIMING_UHS_SDR50 || | |
291 | uhs == MMC_TIMING_UHS_DDR50) { | |
292 | reg_val &= ~SDIO3_CONF_CLK_INV; | |
293 | reg_val |= SDIO3_CONF_SD_FB_CLK; | |
fa796414 NH |
294 | } else if (uhs == MMC_TIMING_MMC_HS) { |
295 | reg_val &= ~SDIO3_CONF_CLK_INV; | |
296 | reg_val &= ~SDIO3_CONF_SD_FB_CLK; | |
1140011e MW |
297 | } else { |
298 | reg_val |= SDIO3_CONF_CLK_INV; | |
299 | reg_val &= ~SDIO3_CONF_SD_FB_CLK; | |
300 | } | |
301 | writeb(reg_val, pxa->sdio3_conf_reg); | |
302 | } | |
303 | ||
a702c8ab ZG |
304 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
305 | dev_dbg(mmc_dev(host->mmc), | |
306 | "%s uhs = %d, ctrl_2 = %04X\n", | |
307 | __func__, uhs, ctrl_2); | |
a702c8ab ZG |
308 | } |
309 | ||
c915568d | 310 | static const struct sdhci_ops pxav3_sdhci_ops = { |
1771059c | 311 | .set_clock = sdhci_set_clock, |
a702c8ab | 312 | .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, |
d005d943 | 313 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
2317f56c | 314 | .set_bus_width = sdhci_set_bus_width, |
03231f9b | 315 | .reset = pxav3_reset, |
b3153765 | 316 | .set_uhs_signaling = pxav3_set_uhs_signaling, |
a702c8ab ZG |
317 | }; |
318 | ||
73b7afb9 | 319 | static struct sdhci_pltfm_data sdhci_pxav3_pdata = { |
e065162a | 320 | .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
73b7afb9 KL |
321 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
322 | | SDHCI_QUIRK_32BIT_ADMA_SIZE | |
323 | | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | |
324 | .ops = &pxav3_sdhci_ops, | |
325 | }; | |
326 | ||
b650352d CB |
327 | #ifdef CONFIG_OF |
328 | static const struct of_device_id sdhci_pxav3_of_match[] = { | |
329 | { | |
330 | .compatible = "mrvl,pxav3-mmc", | |
331 | }, | |
5491ce3f MW |
332 | { |
333 | .compatible = "marvell,armada-380-sdhci", | |
334 | }, | |
b650352d CB |
335 | {}, |
336 | }; | |
337 | MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match); | |
338 | ||
339 | static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev) | |
340 | { | |
341 | struct sdhci_pxa_platdata *pdata; | |
342 | struct device_node *np = dev->of_node; | |
b650352d CB |
343 | u32 clk_delay_cycles; |
344 | ||
345 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
346 | if (!pdata) | |
347 | return NULL; | |
348 | ||
14460dba JZ |
349 | if (!of_property_read_u32(np, "mrvl,clk-delay-cycles", |
350 | &clk_delay_cycles)) | |
b650352d CB |
351 | pdata->clk_delay_cycles = clk_delay_cycles; |
352 | ||
353 | return pdata; | |
354 | } | |
355 | #else | |
356 | static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev) | |
357 | { | |
358 | return NULL; | |
359 | } | |
360 | #endif | |
361 | ||
c3be1efd | 362 | static int sdhci_pxav3_probe(struct platform_device *pdev) |
a702c8ab ZG |
363 | { |
364 | struct sdhci_pltfm_host *pltfm_host; | |
365 | struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; | |
366 | struct device *dev = &pdev->dev; | |
5491ce3f | 367 | struct device_node *np = pdev->dev.of_node; |
a702c8ab ZG |
368 | struct sdhci_host *host = NULL; |
369 | struct sdhci_pxa *pxa = NULL; | |
b650352d | 370 | const struct of_device_id *match; |
a702c8ab | 371 | int ret; |
a702c8ab | 372 | |
3df5b281 | 373 | pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL); |
a702c8ab ZG |
374 | if (!pxa) |
375 | return -ENOMEM; | |
376 | ||
0e748234 | 377 | host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0); |
3df5b281 | 378 | if (IS_ERR(host)) |
a702c8ab | 379 | return PTR_ERR(host); |
5491ce3f | 380 | |
a702c8ab ZG |
381 | pltfm_host = sdhci_priv(host); |
382 | pltfm_host->priv = pxa; | |
383 | ||
01ae1070 SH |
384 | pxa->clk_io = devm_clk_get(dev, "io"); |
385 | if (IS_ERR(pxa->clk_io)) | |
386 | pxa->clk_io = devm_clk_get(dev, NULL); | |
8c96a7a3 | 387 | if (IS_ERR(pxa->clk_io)) { |
a702c8ab | 388 | dev_err(dev, "failed to get io clock\n"); |
8c96a7a3 | 389 | ret = PTR_ERR(pxa->clk_io); |
a702c8ab ZG |
390 | goto err_clk_get; |
391 | } | |
8c96a7a3 SH |
392 | pltfm_host->clk = pxa->clk_io; |
393 | clk_prepare_enable(pxa->clk_io); | |
a702c8ab | 394 | |
8afdc9cc SH |
395 | pxa->clk_core = devm_clk_get(dev, "core"); |
396 | if (!IS_ERR(pxa->clk_core)) | |
397 | clk_prepare_enable(pxa->clk_core); | |
398 | ||
a39128bc MW |
399 | /* enable 1/8V DDR capable */ |
400 | host->mmc->caps |= MMC_CAP_1_8V_DDR; | |
401 | ||
aa8165f9 | 402 | if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) { |
a39128bc | 403 | ret = armada_38x_quirks(pdev, host); |
d4b803c5 GC |
404 | if (ret < 0) |
405 | goto err_clk_get; | |
aa8165f9 TP |
406 | ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info()); |
407 | if (ret < 0) | |
408 | goto err_mbus_win; | |
409 | } | |
410 | ||
b650352d | 411 | match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev); |
943647f6 | 412 | if (match) { |
d2cf6071 SB |
413 | ret = mmc_of_parse(host->mmc); |
414 | if (ret) | |
415 | goto err_of_parse; | |
943647f6 | 416 | sdhci_get_of_property(pdev); |
b650352d | 417 | pdata = pxav3_get_mmc_pdata(dev); |
9cd76049 | 418 | pdev->dev.platform_data = pdata; |
943647f6 | 419 | } else if (pdata) { |
c844a46f KL |
420 | /* on-chip device */ |
421 | if (pdata->flags & PXA_FLAG_CARD_PERMANENT) | |
a702c8ab | 422 | host->mmc->caps |= MMC_CAP_NONREMOVABLE; |
a702c8ab ZG |
423 | |
424 | /* If slot design supports 8 bit data, indicate this to MMC. */ | |
425 | if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) | |
426 | host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
427 | ||
428 | if (pdata->quirks) | |
429 | host->quirks |= pdata->quirks; | |
7c52d7bb KL |
430 | if (pdata->quirks2) |
431 | host->quirks2 |= pdata->quirks2; | |
a702c8ab ZG |
432 | if (pdata->host_caps) |
433 | host->mmc->caps |= pdata->host_caps; | |
8f63795c CB |
434 | if (pdata->host_caps2) |
435 | host->mmc->caps2 |= pdata->host_caps2; | |
a702c8ab ZG |
436 | if (pdata->pm_caps) |
437 | host->mmc->pm_caps |= pdata->pm_caps; | |
8f63795c CB |
438 | |
439 | if (gpio_is_valid(pdata->ext_cd_gpio)) { | |
214fc309 LP |
440 | ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio, |
441 | 0); | |
8f63795c CB |
442 | if (ret) { |
443 | dev_err(mmc_dev(host->mmc), | |
444 | "failed to allocate card detect gpio\n"); | |
445 | goto err_cd_req; | |
446 | } | |
447 | } | |
a702c8ab ZG |
448 | } |
449 | ||
62cf983a JZ |
450 | pm_runtime_get_noresume(&pdev->dev); |
451 | pm_runtime_set_active(&pdev->dev); | |
bb691ae4 KL |
452 | pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS); |
453 | pm_runtime_use_autosuspend(&pdev->dev); | |
62cf983a | 454 | pm_runtime_enable(&pdev->dev); |
bb691ae4 | 455 | pm_suspend_ignore_children(&pdev->dev, 1); |
bb691ae4 | 456 | |
a702c8ab ZG |
457 | ret = sdhci_add_host(host); |
458 | if (ret) { | |
459 | dev_err(&pdev->dev, "failed to add host\n"); | |
460 | goto err_add_host; | |
461 | } | |
462 | ||
463 | platform_set_drvdata(pdev, host); | |
464 | ||
83dc9fec | 465 | if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) |
740b7a44 | 466 | device_init_wakeup(&pdev->dev, 1); |
740b7a44 | 467 | |
bb691ae4 KL |
468 | pm_runtime_put_autosuspend(&pdev->dev); |
469 | ||
a702c8ab ZG |
470 | return 0; |
471 | ||
472 | err_add_host: | |
0dcaa249 | 473 | pm_runtime_disable(&pdev->dev); |
62cf983a | 474 | pm_runtime_put_noidle(&pdev->dev); |
87d2163d XW |
475 | err_of_parse: |
476 | err_cd_req: | |
aa8165f9 | 477 | err_mbus_win: |
8c96a7a3 | 478 | clk_disable_unprepare(pxa->clk_io); |
c25d9e1b | 479 | clk_disable_unprepare(pxa->clk_core); |
a702c8ab ZG |
480 | err_clk_get: |
481 | sdhci_pltfm_free(pdev); | |
a702c8ab ZG |
482 | return ret; |
483 | } | |
484 | ||
6e0ee714 | 485 | static int sdhci_pxav3_remove(struct platform_device *pdev) |
a702c8ab ZG |
486 | { |
487 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
488 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
8c96a7a3 | 489 | struct sdhci_pxa *pxa = pltfm_host->priv; |
a702c8ab | 490 | |
bb691ae4 | 491 | pm_runtime_get_sync(&pdev->dev); |
bb691ae4 | 492 | pm_runtime_disable(&pdev->dev); |
20f1f2d7 JZ |
493 | pm_runtime_put_noidle(&pdev->dev); |
494 | ||
495 | sdhci_remove_host(host, 1); | |
a702c8ab | 496 | |
8c96a7a3 | 497 | clk_disable_unprepare(pxa->clk_io); |
c25d9e1b | 498 | clk_disable_unprepare(pxa->clk_core); |
8f63795c | 499 | |
a702c8ab | 500 | sdhci_pltfm_free(pdev); |
a702c8ab | 501 | |
a702c8ab ZG |
502 | return 0; |
503 | } | |
504 | ||
bb691ae4 KL |
505 | #ifdef CONFIG_PM_SLEEP |
506 | static int sdhci_pxav3_suspend(struct device *dev) | |
507 | { | |
508 | int ret; | |
509 | struct sdhci_host *host = dev_get_drvdata(dev); | |
510 | ||
511 | pm_runtime_get_sync(dev); | |
512 | ret = sdhci_suspend_host(host); | |
513 | pm_runtime_mark_last_busy(dev); | |
514 | pm_runtime_put_autosuspend(dev); | |
515 | ||
516 | return ret; | |
517 | } | |
518 | ||
519 | static int sdhci_pxav3_resume(struct device *dev) | |
520 | { | |
521 | int ret; | |
522 | struct sdhci_host *host = dev_get_drvdata(dev); | |
523 | ||
524 | pm_runtime_get_sync(dev); | |
525 | ret = sdhci_resume_host(host); | |
526 | pm_runtime_mark_last_busy(dev); | |
527 | pm_runtime_put_autosuspend(dev); | |
528 | ||
529 | return ret; | |
530 | } | |
531 | #endif | |
532 | ||
162d6f98 | 533 | #ifdef CONFIG_PM |
bb691ae4 KL |
534 | static int sdhci_pxav3_runtime_suspend(struct device *dev) |
535 | { | |
536 | struct sdhci_host *host = dev_get_drvdata(dev); | |
537 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
8c96a7a3 | 538 | struct sdhci_pxa *pxa = pltfm_host->priv; |
3bb10f60 | 539 | int ret; |
bb691ae4 | 540 | |
3bb10f60 JZ |
541 | ret = sdhci_runtime_suspend_host(host); |
542 | if (ret) | |
543 | return ret; | |
bb691ae4 | 544 | |
8c96a7a3 | 545 | clk_disable_unprepare(pxa->clk_io); |
8afdc9cc SH |
546 | if (!IS_ERR(pxa->clk_core)) |
547 | clk_disable_unprepare(pxa->clk_core); | |
bb691ae4 KL |
548 | |
549 | return 0; | |
550 | } | |
551 | ||
552 | static int sdhci_pxav3_runtime_resume(struct device *dev) | |
553 | { | |
554 | struct sdhci_host *host = dev_get_drvdata(dev); | |
555 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
8c96a7a3 | 556 | struct sdhci_pxa *pxa = pltfm_host->priv; |
bb691ae4 | 557 | |
8c96a7a3 | 558 | clk_prepare_enable(pxa->clk_io); |
8afdc9cc SH |
559 | if (!IS_ERR(pxa->clk_core)) |
560 | clk_prepare_enable(pxa->clk_core); | |
bb691ae4 | 561 | |
3bb10f60 | 562 | return sdhci_runtime_resume_host(host); |
bb691ae4 KL |
563 | } |
564 | #endif | |
565 | ||
566 | #ifdef CONFIG_PM | |
567 | static const struct dev_pm_ops sdhci_pxav3_pmops = { | |
568 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume) | |
569 | SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend, | |
570 | sdhci_pxav3_runtime_resume, NULL) | |
571 | }; | |
572 | ||
573 | #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops) | |
574 | ||
575 | #else | |
576 | #define SDHCI_PXAV3_PMOPS NULL | |
577 | #endif | |
578 | ||
a702c8ab ZG |
579 | static struct platform_driver sdhci_pxav3_driver = { |
580 | .driver = { | |
581 | .name = "sdhci-pxav3", | |
59d22309 | 582 | .of_match_table = of_match_ptr(sdhci_pxav3_of_match), |
bb691ae4 | 583 | .pm = SDHCI_PXAV3_PMOPS, |
a702c8ab ZG |
584 | }, |
585 | .probe = sdhci_pxav3_probe, | |
0433c143 | 586 | .remove = sdhci_pxav3_remove, |
a702c8ab | 587 | }; |
a702c8ab | 588 | |
d1f81a64 | 589 | module_platform_driver(sdhci_pxav3_driver); |
a702c8ab ZG |
590 | |
591 | MODULE_DESCRIPTION("SDHCI driver for pxav3"); | |
592 | MODULE_AUTHOR("Marvell International Ltd."); | |
593 | MODULE_LICENSE("GPL v2"); | |
594 |