[linux-2.6-block.git] / drivers / mmc / host / sdhci-pxav3.c

/*
 * Copyright (C) 2010 Marvell International Ltd.
 *		Zhangfei Gao <zhangfei.gao@marvell.com>
 *		Kevin Wang <dwang4@marvell.com>
 *		Mingwei Wang <mwwang@marvell.com>
 *		Philip Rakity <prakity@marvell.com>
 *		Mark Brown <markb@marvell.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/platform_data/pxa_sdhci.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/mbus.h>

#include "sdhci.h"
#include "sdhci-pltfm.h"

#define PXAV3_RPM_DELAY_MS     50

#define SD_CLOCK_BURST_SIZE_SETUP		0x10A
#define SDCLK_SEL	0x100
#define SDCLK_DELAY_SHIFT	9
#define SDCLK_DELAY_MASK	0x1f

#define SD_CFG_FIFO_PARAM       0x100
#define SDCFG_GEN_PAD_CLK_ON	(1<<6)
#define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
#define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24

#define SD_SPI_MODE          0x108
#define SD_CE_ATA_1          0x10C

#define SD_CE_ATA_2          0x10E
#define SDCE_MISC_INT		(1<<2)
#define SDCE_MISC_INT_EN	(1<<1)

struct sdhci_pxa {
	struct clk *clk_core;
	struct clk *clk_io;
	u8	power_mode;
};

/*
 * These registers are relative to the second register region, for the
 * MBus bridge.
 */
#define SDHCI_WINDOW_CTRL(i)	(0x80 + ((i) << 3))
#define SDHCI_WINDOW_BASE(i)	(0x84 + ((i) << 3))
#define SDHCI_MAX_WIN_NUM	8

static int mv_conf_mbus_windows(struct platform_device *pdev,
				const struct mbus_dram_target_info *dram)
{
	int i;
	void __iomem *regs;
	struct resource *res;

	if (!dram) {
		dev_err(&pdev->dev, "no mbus dram info\n");
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		dev_err(&pdev->dev, "cannot get mbus registers\n");
		return -EINVAL;
	}

	regs = ioremap(res->start, resource_size(res));
	if (!regs) {
		dev_err(&pdev->dev, "cannot map mbus registers\n");
		return -ENOMEM;
	}

	for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
		writel(0, regs + SDHCI_WINDOW_CTRL(i));
		writel(0, regs + SDHCI_WINDOW_BASE(i));
	}

	for (i = 0; i < dram->num_cs; i++) {
		const struct mbus_dram_window *cs = dram->cs + i;

		/* Write size, attributes and target id to control register */
		writel(((cs->size - 1) & 0xffff0000) |
			(cs->mbus_attr << 8) |
			(dram->mbus_dram_target_id << 4) | 1,
			regs + SDHCI_WINDOW_CTRL(i));
		/* Write base address to base register */
		writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
	}

	iounmap(regs);

	return 0;
}

static int armada_38x_quirks(struct sdhci_host *host)
{
	host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
	/*
	 * According to erratum 'FE-2946959' both SDR50 and DDR50
	 * modes require specific clock adjustments in SDIO3
	 * Configuration register, if the adjustment is not done,
	 * remove them from the capabilities.
	 */
	host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
	host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
	return 0;
}

static void pxav3_reset(struct sdhci_host *host, u8 mask)
{
	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;

	sdhci_reset(host, mask);

	if (mask == SDHCI_RESET_ALL) {
		/*
		 * tune timing of read data/command when crc error happen
		 * no performance impact
		 */
		if (pdata && 0 != pdata->clk_delay_cycles) {
			u16 tmp;

			tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
			tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
				<< SDCLK_DELAY_SHIFT;
			tmp |= SDCLK_SEL;
			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
		}
	}
}

#define MAX_WAIT_COUNT 5
static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;
	u16 tmp;
	int count;

	if (pxa->power_mode == MMC_POWER_UP
			&& power_mode == MMC_POWER_ON) {

		dev_dbg(mmc_dev(host->mmc),
				"%s: slot->power_mode = %d,"
				"ios->power_mode = %d\n",
				__func__,
				pxa->power_mode,
				power_mode);

		/* set we want notice of when 74 clocks are sent */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT_EN;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);

		/* start sending the 74 clocks */
		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
		tmp |= SDCFG_GEN_PAD_CLK_ON;
		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);

		/* slowest speed is about 100KHz or 10usec per clock */
		udelay(740);
		count = 0;

		while (count++ < MAX_WAIT_COUNT) {
			if ((readw(host->ioaddr + SD_CE_ATA_2)
						& SDCE_MISC_INT) == 0)
				break;
			udelay(10);
		}

		if (count == MAX_WAIT_COUNT)
			dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");

		/* clear the interrupt bit if posted */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);
	}
	pxa->power_mode = power_mode;
}

static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
{
	u16 ctrl_2;

	/*
	 * Set V18_EN -- UHS modes do not work without this.
	 * does not change signaling voltage
	 */
	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);

	/* Select Bus Speed Mode for host */
	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	switch (uhs) {
	case MMC_TIMING_UHS_SDR12:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
		break;
	case MMC_TIMING_UHS_SDR25:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
		break;
	case MMC_TIMING_UHS_SDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_SDR104:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_MMC_DDR52:
	case MMC_TIMING_UHS_DDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
		break;
	}

	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	dev_dbg(mmc_dev(host->mmc),
		"%s uhs = %d, ctrl_2 = %04X\n",
		__func__, uhs, ctrl_2);
}

static const struct sdhci_ops pxav3_sdhci_ops = {
	.set_clock = sdhci_set_clock,
	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
	.set_bus_width = sdhci_set_bus_width,
	.reset = pxav3_reset,
	.set_uhs_signaling = pxav3_set_uhs_signaling,
};

static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
		| SDHCI_QUIRK_32BIT_ADMA_SIZE
		| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops = &pxav3_sdhci_ops,
};

#ifdef CONFIG_OF
static const struct of_device_id sdhci_pxav3_of_match[] = {
	{
		.compatible = "mrvl,pxav3-mmc",
	},
	{
		.compatible = "marvell,armada-380-sdhci",
	},
	{},
};
MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);

static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	struct sdhci_pxa_platdata *pdata;
	struct device_node *np = dev->of_node;
	u32 clk_delay_cycles;

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;

	if (!of_property_read_u32(np, "mrvl,clk-delay-cycles",
				  &clk_delay_cycles))
		pdata->clk_delay_cycles = clk_delay_cycles;

	return pdata;
}
#else
static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	return NULL;
}
#endif

static int sdhci_pxav3_probe(struct platform_device *pdev)
{
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	struct device *dev = &pdev->dev;
	struct device_node *np = pdev->dev.of_node;
	struct sdhci_host *host = NULL;
	struct sdhci_pxa *pxa = NULL;
	const struct of_device_id *match;
	int ret;

	pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
	if (!pxa)
		return -ENOMEM;

	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
	if (IS_ERR(host))
		return PTR_ERR(host);

	pltfm_host = sdhci_priv(host);
	pltfm_host->priv = pxa;

	pxa->clk_io = devm_clk_get(dev, "io");
	if (IS_ERR(pxa->clk_io))
		pxa->clk_io = devm_clk_get(dev, NULL);
	if (IS_ERR(pxa->clk_io)) {
		dev_err(dev, "failed to get io clock\n");
		ret = PTR_ERR(pxa->clk_io);
		goto err_clk_get;
	}
	pltfm_host->clk = pxa->clk_io;
	clk_prepare_enable(pxa->clk_io);

	pxa->clk_core = devm_clk_get(dev, "core");
	if (!IS_ERR(pxa->clk_core))
		clk_prepare_enable(pxa->clk_core);

	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
		ret = armada_38x_quirks(host);
		if (ret < 0)
			goto err_clk_get;
		ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
		if (ret < 0)
			goto err_mbus_win;
	}

	/* enable 1/8V DDR capable */
	host->mmc->caps |= MMC_CAP_1_8V_DDR;

	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
	if (match) {
		ret = mmc_of_parse(host->mmc);
		if (ret)
			goto err_of_parse;
		sdhci_get_of_property(pdev);
		pdata = pxav3_get_mmc_pdata(dev);
	} else if (pdata) {
		/* on-chip device */
		if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
			host->mmc->caps |= MMC_CAP_NONREMOVABLE;

		/* If slot design supports 8 bit data, indicate this to MMC. */
		if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
			host->mmc->caps |= MMC_CAP_8_BIT_DATA;

		if (pdata->quirks)
			host->quirks |= pdata->quirks;
		if (pdata->quirks2)
			host->quirks2 |= pdata->quirks2;
		if (pdata->host_caps)
			host->mmc->caps |= pdata->host_caps;
		if (pdata->host_caps2)
			host->mmc->caps2 |= pdata->host_caps2;
		if (pdata->pm_caps)
			host->mmc->pm_caps |= pdata->pm_caps;

		if (gpio_is_valid(pdata->ext_cd_gpio)) {
			ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
						  0);
			if (ret) {
				dev_err(mmc_dev(host->mmc),
					"failed to allocate card detect gpio\n");
				goto err_cd_req;
			}
		}
	}

	pm_runtime_get_noresume(&pdev->dev);
	pm_runtime_set_active(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_enable(&pdev->dev);
	pm_suspend_ignore_children(&pdev->dev, 1);

	ret = sdhci_add_host(host);
	if (ret) {
		dev_err(&pdev->dev, "failed to add host\n");
		goto err_add_host;
	}

	platform_set_drvdata(pdev, host);

	if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
		device_init_wakeup(&pdev->dev, 1);
		host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ;
	} else {
		device_init_wakeup(&pdev->dev, 0);
	}

	pm_runtime_put_autosuspend(&pdev->dev);

	return 0;

err_add_host:
	pm_runtime_disable(&pdev->dev);
	pm_runtime_put_noidle(&pdev->dev);
err_of_parse:
err_cd_req:
err_mbus_win:
	clk_disable_unprepare(pxa->clk_io);
	clk_disable_unprepare(pxa->clk_core);
err_clk_get:
	sdhci_pltfm_free(pdev);
	return ret;
}

static int sdhci_pxav3_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;

	pm_runtime_get_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	pm_runtime_put_noidle(&pdev->dev);

	sdhci_remove_host(host, 1);

	clk_disable_unprepare(pxa->clk_io);
	clk_disable_unprepare(pxa->clk_core);

	sdhci_pltfm_free(pdev);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int sdhci_pxav3_suspend(struct device *dev)
{
	int ret;
	struct sdhci_host *host = dev_get_drvdata(dev);

	pm_runtime_get_sync(dev);
	ret = sdhci_suspend_host(host);
	pm_runtime_mark_last_busy(dev);
	pm_runtime_put_autosuspend(dev);

	return ret;
}

static int sdhci_pxav3_resume(struct device *dev)
{
	int ret;
	struct sdhci_host *host = dev_get_drvdata(dev);

	pm_runtime_get_sync(dev);
	ret = sdhci_resume_host(host);
	pm_runtime_mark_last_busy(dev);
	pm_runtime_put_autosuspend(dev);

	return ret;
}
#endif

#ifdef CONFIG_PM
static int sdhci_pxav3_runtime_suspend(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;
	int ret;

	ret = sdhci_runtime_suspend_host(host);
	if (ret)
		return ret;

	clk_disable_unprepare(pxa->clk_io);
	if (!IS_ERR(pxa->clk_core))
		clk_disable_unprepare(pxa->clk_core);

	return 0;
}

static int sdhci_pxav3_runtime_resume(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;

	clk_prepare_enable(pxa->clk_io);
	if (!IS_ERR(pxa->clk_core))
		clk_prepare_enable(pxa->clk_core);

	return sdhci_runtime_resume_host(host);
}
#endif

#ifdef CONFIG_PM
static const struct dev_pm_ops sdhci_pxav3_pmops = {
	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
	SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
		sdhci_pxav3_runtime_resume, NULL)
};

#define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)

#else
#define SDHCI_PXAV3_PMOPS NULL
#endif

static struct platform_driver sdhci_pxav3_driver = {
	.driver		= {
		.name	= "sdhci-pxav3",
#ifdef CONFIG_OF
		.of_match_table = sdhci_pxav3_of_match,
#endif
		.pm	= SDHCI_PXAV3_PMOPS,
	},
	.probe		= sdhci_pxav3_probe,
	.remove		= sdhci_pxav3_remove,
};

module_platform_driver(sdhci_pxav3_driver);

MODULE_DESCRIPTION("SDHCI driver for pxav3");
MODULE_AUTHOR("Marvell International Ltd.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a702c8ab ZG	1	/*
	2	* Copyright (C) 2010 Marvell International Ltd.
	3	* Zhangfei Gao <zhangfei.gao@marvell.com>
	4	* Kevin Wang <dwang4@marvell.com>
	5	* Mingwei Wang <mwwang@marvell.com>
	6	* Philip Rakity <prakity@marvell.com>
	7	* Mark Brown <markb@marvell.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19	#include <linux/err.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/clk.h>
	23	#include <linux/io.h>
	24	#include <linux/gpio.h>
	25	#include <linux/mmc/card.h>
	26	#include <linux/mmc/host.h>
8f63795c	27	#include <linux/mmc/slot-gpio.h>
bfed345e	28	#include <linux/platform_data/pxa_sdhci.h>
a702c8ab ZG	29	#include <linux/slab.h>
a702c8ab ZG	30	#include <linux/delay.h>
88b47679	31	#include <linux/module.h>
b650352d CB	32	#include <linux/of.h>
b650352d CB	33	#include <linux/of_device.h>
8f63795c	34	#include <linux/of_gpio.h>
bb691ae4 KL	35	#include <linux/pm.h>
bb691ae4 KL	36	#include <linux/pm_runtime.h>
5491ce3f	37	#include <linux/mbus.h>
b650352d	38
a702c8ab ZG	39	#include "sdhci.h"
	40	#include "sdhci-pltfm.h"
	41
bb691ae4 KL	42	#define PXAV3_RPM_DELAY_MS 50
bb691ae4 KL	43
a702c8ab ZG	44	#define SD_CLOCK_BURST_SIZE_SETUP 0x10A
	45	#define SDCLK_SEL 0x100
	46	#define SDCLK_DELAY_SHIFT 9
	47	#define SDCLK_DELAY_MASK 0x1f
	48
	49	#define SD_CFG_FIFO_PARAM 0x100
	50	#define SDCFG_GEN_PAD_CLK_ON (1<<6)
	51	#define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
	52	#define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
	53
	54	#define SD_SPI_MODE 0x108
	55	#define SD_CE_ATA_1 0x10C
	56
	57	#define SD_CE_ATA_2 0x10E
	58	#define SDCE_MISC_INT (1<<2)
	59	#define SDCE_MISC_INT_EN (1<<1)
	60
cc9571e8	61	struct sdhci_pxa {
8afdc9cc	62	struct clk *clk_core;
8c96a7a3	63	struct clk *clk_io;
cc9571e8 SH	64	u8 power_mode;
	65	};
	66
5491ce3f MW	67	/*
	68	* These registers are relative to the second register region, for the
	69	* MBus bridge.
	70	*/
	71	#define SDHCI_WINDOW_CTRL(i) (0x80 + ((i) << 3))
	72	#define SDHCI_WINDOW_BASE(i) (0x84 + ((i) << 3))
	73	#define SDHCI_MAX_WIN_NUM 8
	74
	75	static int mv_conf_mbus_windows(struct platform_device *pdev,
	76	const struct mbus_dram_target_info *dram)
	77	{
	78	int i;
	79	void __iomem *regs;
	80	struct resource *res;
	81
	82	if (!dram) {
	83	dev_err(&pdev->dev, "no mbus dram info\n");
	84	return -EINVAL;
	85	}
	86
	87	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	88	if (!res) {
	89	dev_err(&pdev->dev, "cannot get mbus registers\n");
	90	return -EINVAL;
	91	}
	92
	93	regs = ioremap(res->start, resource_size(res));
	94	if (!regs) {
	95	dev_err(&pdev->dev, "cannot map mbus registers\n");
	96	return -ENOMEM;
	97	}
	98
	99	for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
	100	writel(0, regs + SDHCI_WINDOW_CTRL(i));
	101	writel(0, regs + SDHCI_WINDOW_BASE(i));
	102	}
	103
	104	for (i = 0; i < dram->num_cs; i++) {
	105	const struct mbus_dram_window *cs = dram->cs + i;
	106
	107	/* Write size, attributes and target id to control register */
	108	writel(((cs->size - 1) & 0xffff0000) \|
	109	(cs->mbus_attr << 8) \|
	110	(dram->mbus_dram_target_id << 4) \| 1,
	111	regs + SDHCI_WINDOW_CTRL(i));
	112	/* Write base address to base register */
	113	writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
	114	}
	115
	116	iounmap(regs);
	117
	118	return 0;
	119	}
	120
d4b803c5 GC	121	static int armada_38x_quirks(struct sdhci_host *host)
	122	{
	123	host->quirks \|= SDHCI_QUIRK_MISSING_CAPS;
	124	/*
	125	* According to erratum 'FE-2946959' both SDR50 and DDR50
	126	* modes require specific clock adjustments in SDIO3
	127	* Configuration register, if the adjustment is not done,
	128	* remove them from the capabilities.
	129	*/
	130	host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
	131	host->caps1 &= ~(SDHCI_SUPPORT_SDR50 \| SDHCI_SUPPORT_DDR50);
	132	return 0;
	133	}
	134
03231f9b	135	static void pxav3_reset(struct sdhci_host *host, u8 mask)
a702c8ab ZG	136	{
	137	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	138	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	139
03231f9b RK	140	sdhci_reset(host, mask);
03231f9b RK	141
a702c8ab ZG	142	if (mask == SDHCI_RESET_ALL) {
	143	/*
	144	* tune timing of read data/command when crc error happen
	145	* no performance impact
	146	*/
	147	if (pdata && 0 != pdata->clk_delay_cycles) {
	148	u16 tmp;
	149
	150	tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	151	tmp \|= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
	152	<< SDCLK_DELAY_SHIFT;
	153	tmp \|= SDCLK_SEL;
	154	writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	155	}
	156	}
	157	}
	158
	159	#define MAX_WAIT_COUNT 5
	160	static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
	161	{
	162	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	163	struct sdhci_pxa *pxa = pltfm_host->priv;
	164	u16 tmp;
	165	int count;
	166
	167	if (pxa->power_mode == MMC_POWER_UP
	168	&& power_mode == MMC_POWER_ON) {
	169
	170	dev_dbg(mmc_dev(host->mmc),
	171	"%s: slot->power_mode = %d,"
	172	"ios->power_mode = %d\n",
	173	__func__,
	174	pxa->power_mode,
	175	power_mode);
	176
	177	/* set we want notice of when 74 clocks are sent */
	178	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	179	tmp \|= SDCE_MISC_INT_EN;
	180	writew(tmp, host->ioaddr + SD_CE_ATA_2);
	181
	182	/* start sending the 74 clocks */
	183	tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
	184	tmp \|= SDCFG_GEN_PAD_CLK_ON;
	185	writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
	186
	187	/* slowest speed is about 100KHz or 10usec per clock */
	188	udelay(740);
	189	count = 0;
	190
	191	while (count++ < MAX_WAIT_COUNT) {
	192	if ((readw(host->ioaddr + SD_CE_ATA_2)
	193	& SDCE_MISC_INT) == 0)
	194	break;
	195	udelay(10);
	196	}
	197
	198	if (count == MAX_WAIT_COUNT)
	199	dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
	200
	201	/* clear the interrupt bit if posted */
	202	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	203	tmp \|= SDCE_MISC_INT;
	204	writew(tmp, host->ioaddr + SD_CE_ATA_2);
	205	}
206	pxa->power_mode = power_mode;
207	}
208
13e64501	209	static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
a702c8ab ZG	210	{
	211	u16 ctrl_2;
	212
	213	/*
	214	* Set V18_EN -- UHS modes do not work without this.
	215	* does not change signaling voltage
	216	*/
	217	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	218
	219	/* Select Bus Speed Mode for host */
	220	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	221	switch (uhs) {
	222	case MMC_TIMING_UHS_SDR12:
	223	ctrl_2 \|= SDHCI_CTRL_UHS_SDR12;
	224	break;
	225	case MMC_TIMING_UHS_SDR25:
	226	ctrl_2 \|= SDHCI_CTRL_UHS_SDR25;
	227	break;
	228	case MMC_TIMING_UHS_SDR50:
	229	ctrl_2 \|= SDHCI_CTRL_UHS_SDR50 \| SDHCI_CTRL_VDD_180;
	230	break;
	231	case MMC_TIMING_UHS_SDR104:
	232	ctrl_2 \|= SDHCI_CTRL_UHS_SDR104 \| SDHCI_CTRL_VDD_180;
	233	break;
668e84b2	234	case MMC_TIMING_MMC_DDR52:
a702c8ab ZG	235	case MMC_TIMING_UHS_DDR50:
	236	ctrl_2 \|= SDHCI_CTRL_UHS_DDR50 \| SDHCI_CTRL_VDD_180;
	237	break;
	238	}
	239
	240	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	241	dev_dbg(mmc_dev(host->mmc),
	242	"%s uhs = %d, ctrl_2 = %04X\n",
	243	__func__, uhs, ctrl_2);
a702c8ab ZG	244	}
a702c8ab ZG	245
c915568d	246	static const struct sdhci_ops pxav3_sdhci_ops = {
1771059c	247	.set_clock = sdhci_set_clock,
a702c8ab	248	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
d005d943	249	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
2317f56c	250	.set_bus_width = sdhci_set_bus_width,
03231f9b	251	.reset = pxav3_reset,
b3153765	252	.set_uhs_signaling = pxav3_set_uhs_signaling,
a702c8ab ZG	253	};
a702c8ab ZG	254
73b7afb9	255	static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
e065162a	256	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
73b7afb9 KL	257	\| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
	258	\| SDHCI_QUIRK_32BIT_ADMA_SIZE
	259	\| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	260	.ops = &pxav3_sdhci_ops,
	261	};
	262
b650352d CB	263	#ifdef CONFIG_OF
	264	static const struct of_device_id sdhci_pxav3_of_match[] = {
	265	{
	266	.compatible = "mrvl,pxav3-mmc",
	267	},
5491ce3f MW	268	{
	269	.compatible = "marvell,armada-380-sdhci",
	270	},
b650352d CB	271	{},
	272	};
	273	MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
	274
	275	static struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	276	{
	277	struct sdhci_pxa_platdata *pdata;
	278	struct device_node *np = dev->of_node;
b650352d CB	279	u32 clk_delay_cycles;
	280
	281	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	282	if (!pdata)
	283	return NULL;
	284
14460dba JZ	285	if (!of_property_read_u32(np, "mrvl,clk-delay-cycles",
14460dba JZ	286	&clk_delay_cycles))
b650352d CB	287	pdata->clk_delay_cycles = clk_delay_cycles;
	288
	289	return pdata;
	290	}
	291	#else
	292	static inline struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	293	{
	294	return NULL;
	295	}
	296	#endif
	297
c3be1efd	298	static int sdhci_pxav3_probe(struct platform_device *pdev)
a702c8ab ZG	299	{
	300	struct sdhci_pltfm_host *pltfm_host;
	301	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	302	struct device *dev = &pdev->dev;
5491ce3f	303	struct device_node *np = pdev->dev.of_node;
a702c8ab ZG	304	struct sdhci_host *host = NULL;
a702c8ab ZG	305	struct sdhci_pxa *pxa = NULL;
b650352d	306	const struct of_device_id *match;
a702c8ab	307	int ret;
a702c8ab	308
3df5b281	309	pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
a702c8ab ZG	310	if (!pxa)
	311	return -ENOMEM;
	312
0e748234	313	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
3df5b281	314	if (IS_ERR(host))
a702c8ab	315	return PTR_ERR(host);
5491ce3f	316
a702c8ab ZG	317	pltfm_host = sdhci_priv(host);
	318	pltfm_host->priv = pxa;
	319
01ae1070 SH	320	pxa->clk_io = devm_clk_get(dev, "io");
	321	if (IS_ERR(pxa->clk_io))
	322	pxa->clk_io = devm_clk_get(dev, NULL);
8c96a7a3	323	if (IS_ERR(pxa->clk_io)) {
a702c8ab	324	dev_err(dev, "failed to get io clock\n");
8c96a7a3	325	ret = PTR_ERR(pxa->clk_io);
a702c8ab ZG	326	goto err_clk_get;
a702c8ab ZG	327	}
8c96a7a3 SH	328	pltfm_host->clk = pxa->clk_io;
8c96a7a3 SH	329	clk_prepare_enable(pxa->clk_io);
a702c8ab	330
8afdc9cc SH	331	pxa->clk_core = devm_clk_get(dev, "core");
	332	if (!IS_ERR(pxa->clk_core))
	333	clk_prepare_enable(pxa->clk_core);
	334
aa8165f9	335	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
d4b803c5 GC	336	ret = armada_38x_quirks(host);
	337	if (ret < 0)
	338	goto err_clk_get;
aa8165f9 TP	339	ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
	340	if (ret < 0)
	341	goto err_mbus_win;
	342	}
	343
a702c8ab ZG	344	/* enable 1/8V DDR capable */
	345	host->mmc->caps \|= MMC_CAP_1_8V_DDR;
	346
b650352d	347	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
943647f6	348	if (match) {
d2cf6071 SB	349	ret = mmc_of_parse(host->mmc);
	350	if (ret)
	351	goto err_of_parse;
943647f6	352	sdhci_get_of_property(pdev);
b650352d	353	pdata = pxav3_get_mmc_pdata(dev);
943647f6	354	} else if (pdata) {
c844a46f KL	355	/* on-chip device */
c844a46f KL	356	if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
a702c8ab	357	host->mmc->caps \|= MMC_CAP_NONREMOVABLE;
a702c8ab ZG	358
	359	/* If slot design supports 8 bit data, indicate this to MMC. */
	360	if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
	361	host->mmc->caps \|= MMC_CAP_8_BIT_DATA;
	362
	363	if (pdata->quirks)
	364	host->quirks \|= pdata->quirks;
7c52d7bb KL	365	if (pdata->quirks2)
7c52d7bb KL	366	host->quirks2 \|= pdata->quirks2;
a702c8ab ZG	367	if (pdata->host_caps)
a702c8ab ZG	368	host->mmc->caps \|= pdata->host_caps;
8f63795c CB	369	if (pdata->host_caps2)
8f63795c CB	370	host->mmc->caps2 \|= pdata->host_caps2;
a702c8ab ZG	371	if (pdata->pm_caps)
a702c8ab ZG	372	host->mmc->pm_caps \|= pdata->pm_caps;
8f63795c CB	373
8f63795c CB	374	if (gpio_is_valid(pdata->ext_cd_gpio)) {
214fc309 LP	375	ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
214fc309 LP	376	0);
8f63795c CB	377	if (ret) {
	378	dev_err(mmc_dev(host->mmc),
	379	"failed to allocate card detect gpio\n");
	380	goto err_cd_req;
	381	}
	382	}
a702c8ab ZG	383	}
a702c8ab ZG	384
62cf983a JZ	385	pm_runtime_get_noresume(&pdev->dev);
62cf983a JZ	386	pm_runtime_set_active(&pdev->dev);
bb691ae4 KL	387	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
bb691ae4 KL	388	pm_runtime_use_autosuspend(&pdev->dev);
62cf983a	389	pm_runtime_enable(&pdev->dev);
bb691ae4	390	pm_suspend_ignore_children(&pdev->dev, 1);
bb691ae4	391
a702c8ab ZG	392	ret = sdhci_add_host(host);
	393	if (ret) {
	394	dev_err(&pdev->dev, "failed to add host\n");
	395	goto err_add_host;
	396	}
	397
	398	platform_set_drvdata(pdev, host);
	399
943647f6	400	if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
740b7a44 KL	401	device_init_wakeup(&pdev->dev, 1);
	402	host->mmc->pm_flags \|= MMC_PM_WAKE_SDIO_IRQ;
	403	} else {
	404	device_init_wakeup(&pdev->dev, 0);
	405	}
	406
bb691ae4 KL	407	pm_runtime_put_autosuspend(&pdev->dev);
bb691ae4 KL	408
a702c8ab ZG	409	return 0;
	410
	411	err_add_host:
0dcaa249	412	pm_runtime_disable(&pdev->dev);
62cf983a	413	pm_runtime_put_noidle(&pdev->dev);
87d2163d XW	414	err_of_parse:
87d2163d XW	415	err_cd_req:
aa8165f9	416	err_mbus_win:
8c96a7a3	417	clk_disable_unprepare(pxa->clk_io);
c25d9e1b	418	clk_disable_unprepare(pxa->clk_core);
a702c8ab ZG	419	err_clk_get:
a702c8ab ZG	420	sdhci_pltfm_free(pdev);
a702c8ab ZG	421	return ret;
	422	}
	423
6e0ee714	424	static int sdhci_pxav3_remove(struct platform_device *pdev)
a702c8ab ZG	425	{
	426	struct sdhci_host *host = platform_get_drvdata(pdev);
	427	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
8c96a7a3	428	struct sdhci_pxa *pxa = pltfm_host->priv;
a702c8ab	429
bb691ae4	430	pm_runtime_get_sync(&pdev->dev);
bb691ae4	431	pm_runtime_disable(&pdev->dev);
20f1f2d7 JZ	432	pm_runtime_put_noidle(&pdev->dev);
	433
	434	sdhci_remove_host(host, 1);
a702c8ab	435
8c96a7a3	436	clk_disable_unprepare(pxa->clk_io);
c25d9e1b	437	clk_disable_unprepare(pxa->clk_core);
8f63795c	438
a702c8ab	439	sdhci_pltfm_free(pdev);
a702c8ab	440
a702c8ab ZG	441	return 0;
	442	}
	443
bb691ae4 KL	444	#ifdef CONFIG_PM_SLEEP
	445	static int sdhci_pxav3_suspend(struct device *dev)
	446	{
	447	int ret;
	448	struct sdhci_host *host = dev_get_drvdata(dev);
	449
	450	pm_runtime_get_sync(dev);
	451	ret = sdhci_suspend_host(host);
	452	pm_runtime_mark_last_busy(dev);
	453	pm_runtime_put_autosuspend(dev);
	454
	455	return ret;
	456	}
	457
	458	static int sdhci_pxav3_resume(struct device *dev)
	459	{
	460	int ret;
	461	struct sdhci_host *host = dev_get_drvdata(dev);
	462
	463	pm_runtime_get_sync(dev);
	464	ret = sdhci_resume_host(host);
	465	pm_runtime_mark_last_busy(dev);
	466	pm_runtime_put_autosuspend(dev);
	467
	468	return ret;
	469	}
	470	#endif
	471
162d6f98	472	#ifdef CONFIG_PM
bb691ae4 KL	473	static int sdhci_pxav3_runtime_suspend(struct device *dev)
	474	{
	475	struct sdhci_host *host = dev_get_drvdata(dev);
	476	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
8c96a7a3	477	struct sdhci_pxa *pxa = pltfm_host->priv;
3bb10f60	478	int ret;
bb691ae4	479
3bb10f60 JZ	480	ret = sdhci_runtime_suspend_host(host);
	481	if (ret)
	482	return ret;
bb691ae4	483
8c96a7a3	484	clk_disable_unprepare(pxa->clk_io);
8afdc9cc SH	485	if (!IS_ERR(pxa->clk_core))
8afdc9cc SH	486	clk_disable_unprepare(pxa->clk_core);
bb691ae4 KL	487
	488	return 0;
	489	}
	490
	491	static int sdhci_pxav3_runtime_resume(struct device *dev)
	492	{
	493	struct sdhci_host *host = dev_get_drvdata(dev);
	494	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
8c96a7a3	495	struct sdhci_pxa *pxa = pltfm_host->priv;
bb691ae4	496
8c96a7a3	497	clk_prepare_enable(pxa->clk_io);
8afdc9cc SH	498	if (!IS_ERR(pxa->clk_core))
8afdc9cc SH	499	clk_prepare_enable(pxa->clk_core);
bb691ae4	500
3bb10f60	501	return sdhci_runtime_resume_host(host);
bb691ae4 KL	502	}
	503	#endif
	504
	505	#ifdef CONFIG_PM
	506	static const struct dev_pm_ops sdhci_pxav3_pmops = {
	507	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
	508	SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
	509	sdhci_pxav3_runtime_resume, NULL)
	510	};
	511
	512	#define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
	513
	514	#else
	515	#define SDHCI_PXAV3_PMOPS NULL
	516	#endif
	517
a702c8ab ZG	518	static struct platform_driver sdhci_pxav3_driver = {
	519	.driver = {
	520	.name = "sdhci-pxav3",
b650352d CB	521	#ifdef CONFIG_OF
	522	.of_match_table = sdhci_pxav3_of_match,
	523	#endif
bb691ae4	524	.pm = SDHCI_PXAV3_PMOPS,
a702c8ab ZG	525	},
a702c8ab ZG	526	.probe = sdhci_pxav3_probe,
0433c143	527	.remove = sdhci_pxav3_remove,
a702c8ab	528	};
a702c8ab	529
d1f81a64	530	module_platform_driver(sdhci_pxav3_driver);
a702c8ab ZG	531
	532	MODULE_DESCRIPTION("SDHCI driver for pxav3");
	533	MODULE_AUTHOR("Marvell International Ltd.");
	534	MODULE_LICENSE("GPL v2");
	535