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a702c8ab ZG |
1 | /* |
2 | * Copyright (C) 2010 Marvell International Ltd. | |
3 | * Zhangfei Gao <zhangfei.gao@marvell.com> | |
4 | * Kevin Wang <dwang4@marvell.com> | |
5 | * Mingwei Wang <mwwang@marvell.com> | |
6 | * Philip Rakity <prakity@marvell.com> | |
7 | * Mark Brown <markb@marvell.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | #include <linux/err.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/gpio.h> | |
25 | #include <linux/mmc/card.h> | |
26 | #include <linux/mmc/host.h> | |
27 | #include <plat/sdhci.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/delay.h> | |
30 | #include "sdhci.h" | |
31 | #include "sdhci-pltfm.h" | |
32 | ||
33 | #define SD_CLOCK_BURST_SIZE_SETUP 0x10A | |
34 | #define SDCLK_SEL 0x100 | |
35 | #define SDCLK_DELAY_SHIFT 9 | |
36 | #define SDCLK_DELAY_MASK 0x1f | |
37 | ||
38 | #define SD_CFG_FIFO_PARAM 0x100 | |
39 | #define SDCFG_GEN_PAD_CLK_ON (1<<6) | |
40 | #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF | |
41 | #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24 | |
42 | ||
43 | #define SD_SPI_MODE 0x108 | |
44 | #define SD_CE_ATA_1 0x10C | |
45 | ||
46 | #define SD_CE_ATA_2 0x10E | |
47 | #define SDCE_MISC_INT (1<<2) | |
48 | #define SDCE_MISC_INT_EN (1<<1) | |
49 | ||
50 | static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask) | |
51 | { | |
52 | struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); | |
53 | struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; | |
54 | ||
55 | if (mask == SDHCI_RESET_ALL) { | |
56 | /* | |
57 | * tune timing of read data/command when crc error happen | |
58 | * no performance impact | |
59 | */ | |
60 | if (pdata && 0 != pdata->clk_delay_cycles) { | |
61 | u16 tmp; | |
62 | ||
63 | tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); | |
64 | tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) | |
65 | << SDCLK_DELAY_SHIFT; | |
66 | tmp |= SDCLK_SEL; | |
67 | writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); | |
68 | } | |
69 | } | |
70 | } | |
71 | ||
72 | #define MAX_WAIT_COUNT 5 | |
73 | static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode) | |
74 | { | |
75 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
76 | struct sdhci_pxa *pxa = pltfm_host->priv; | |
77 | u16 tmp; | |
78 | int count; | |
79 | ||
80 | if (pxa->power_mode == MMC_POWER_UP | |
81 | && power_mode == MMC_POWER_ON) { | |
82 | ||
83 | dev_dbg(mmc_dev(host->mmc), | |
84 | "%s: slot->power_mode = %d," | |
85 | "ios->power_mode = %d\n", | |
86 | __func__, | |
87 | pxa->power_mode, | |
88 | power_mode); | |
89 | ||
90 | /* set we want notice of when 74 clocks are sent */ | |
91 | tmp = readw(host->ioaddr + SD_CE_ATA_2); | |
92 | tmp |= SDCE_MISC_INT_EN; | |
93 | writew(tmp, host->ioaddr + SD_CE_ATA_2); | |
94 | ||
95 | /* start sending the 74 clocks */ | |
96 | tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM); | |
97 | tmp |= SDCFG_GEN_PAD_CLK_ON; | |
98 | writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM); | |
99 | ||
100 | /* slowest speed is about 100KHz or 10usec per clock */ | |
101 | udelay(740); | |
102 | count = 0; | |
103 | ||
104 | while (count++ < MAX_WAIT_COUNT) { | |
105 | if ((readw(host->ioaddr + SD_CE_ATA_2) | |
106 | & SDCE_MISC_INT) == 0) | |
107 | break; | |
108 | udelay(10); | |
109 | } | |
110 | ||
111 | if (count == MAX_WAIT_COUNT) | |
112 | dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n"); | |
113 | ||
114 | /* clear the interrupt bit if posted */ | |
115 | tmp = readw(host->ioaddr + SD_CE_ATA_2); | |
116 | tmp |= SDCE_MISC_INT; | |
117 | writew(tmp, host->ioaddr + SD_CE_ATA_2); | |
118 | } | |
119 | pxa->power_mode = power_mode; | |
120 | } | |
121 | ||
122 | static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) | |
123 | { | |
124 | u16 ctrl_2; | |
125 | ||
126 | /* | |
127 | * Set V18_EN -- UHS modes do not work without this. | |
128 | * does not change signaling voltage | |
129 | */ | |
130 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
131 | ||
132 | /* Select Bus Speed Mode for host */ | |
133 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
134 | switch (uhs) { | |
135 | case MMC_TIMING_UHS_SDR12: | |
136 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | |
137 | break; | |
138 | case MMC_TIMING_UHS_SDR25: | |
139 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
140 | break; | |
141 | case MMC_TIMING_UHS_SDR50: | |
142 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180; | |
143 | break; | |
144 | case MMC_TIMING_UHS_SDR104: | |
145 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; | |
146 | break; | |
147 | case MMC_TIMING_UHS_DDR50: | |
148 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; | |
149 | break; | |
150 | } | |
151 | ||
152 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
153 | dev_dbg(mmc_dev(host->mmc), | |
154 | "%s uhs = %d, ctrl_2 = %04X\n", | |
155 | __func__, uhs, ctrl_2); | |
156 | ||
157 | return 0; | |
158 | } | |
159 | ||
160 | static struct sdhci_ops pxav3_sdhci_ops = { | |
161 | .platform_reset_exit = pxav3_set_private_registers, | |
162 | .set_uhs_signaling = pxav3_set_uhs_signaling, | |
163 | .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, | |
164 | }; | |
165 | ||
166 | static int __devinit sdhci_pxav3_probe(struct platform_device *pdev) | |
167 | { | |
168 | struct sdhci_pltfm_host *pltfm_host; | |
169 | struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; | |
170 | struct device *dev = &pdev->dev; | |
171 | struct sdhci_host *host = NULL; | |
172 | struct sdhci_pxa *pxa = NULL; | |
173 | int ret; | |
174 | struct clk *clk; | |
175 | ||
176 | pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL); | |
177 | if (!pxa) | |
178 | return -ENOMEM; | |
179 | ||
180 | host = sdhci_pltfm_init(pdev, NULL); | |
181 | if (IS_ERR(host)) { | |
182 | kfree(pxa); | |
183 | return PTR_ERR(host); | |
184 | } | |
185 | pltfm_host = sdhci_priv(host); | |
186 | pltfm_host->priv = pxa; | |
187 | ||
188 | clk = clk_get(dev, "PXA-SDHCLK"); | |
189 | if (IS_ERR(clk)) { | |
190 | dev_err(dev, "failed to get io clock\n"); | |
191 | ret = PTR_ERR(clk); | |
192 | goto err_clk_get; | |
193 | } | |
194 | pltfm_host->clk = clk; | |
195 | clk_enable(clk); | |
196 | ||
197 | host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
198 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; | |
199 | ||
200 | /* enable 1/8V DDR capable */ | |
201 | host->mmc->caps |= MMC_CAP_1_8V_DDR; | |
202 | ||
203 | if (pdata) { | |
204 | if (pdata->flags & PXA_FLAG_CARD_PERMANENT) { | |
205 | /* on-chip device */ | |
206 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
207 | host->mmc->caps |= MMC_CAP_NONREMOVABLE; | |
208 | } | |
209 | ||
210 | /* If slot design supports 8 bit data, indicate this to MMC. */ | |
211 | if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) | |
212 | host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
213 | ||
214 | if (pdata->quirks) | |
215 | host->quirks |= pdata->quirks; | |
216 | if (pdata->host_caps) | |
217 | host->mmc->caps |= pdata->host_caps; | |
218 | if (pdata->pm_caps) | |
219 | host->mmc->pm_caps |= pdata->pm_caps; | |
220 | } | |
221 | ||
222 | host->ops = &pxav3_sdhci_ops; | |
223 | ||
224 | ret = sdhci_add_host(host); | |
225 | if (ret) { | |
226 | dev_err(&pdev->dev, "failed to add host\n"); | |
227 | goto err_add_host; | |
228 | } | |
229 | ||
230 | platform_set_drvdata(pdev, host); | |
231 | ||
232 | return 0; | |
233 | ||
234 | err_add_host: | |
235 | clk_disable(clk); | |
236 | clk_put(clk); | |
237 | err_clk_get: | |
238 | sdhci_pltfm_free(pdev); | |
239 | kfree(pxa); | |
240 | return ret; | |
241 | } | |
242 | ||
243 | static int __devexit sdhci_pxav3_remove(struct platform_device *pdev) | |
244 | { | |
245 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
246 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
247 | struct sdhci_pxa *pxa = pltfm_host->priv; | |
248 | ||
249 | sdhci_remove_host(host, 1); | |
250 | ||
251 | clk_disable(pltfm_host->clk); | |
252 | clk_put(pltfm_host->clk); | |
253 | sdhci_pltfm_free(pdev); | |
254 | kfree(pxa); | |
255 | ||
256 | platform_set_drvdata(pdev, NULL); | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | static struct platform_driver sdhci_pxav3_driver = { | |
262 | .driver = { | |
263 | .name = "sdhci-pxav3", | |
264 | .owner = THIS_MODULE, | |
265 | }, | |
266 | .probe = sdhci_pxav3_probe, | |
267 | .remove = __devexit_p(sdhci_pxav3_remove), | |
268 | #ifdef CONFIG_PM | |
269 | .suspend = sdhci_pltfm_suspend, | |
270 | .resume = sdhci_pltfm_resume, | |
271 | #endif | |
272 | }; | |
273 | static int __init sdhci_pxav3_init(void) | |
274 | { | |
275 | return platform_driver_register(&sdhci_pxav3_driver); | |
276 | } | |
277 | ||
278 | static void __exit sdhci_pxav3_exit(void) | |
279 | { | |
280 | platform_driver_unregister(&sdhci_pxav3_driver); | |
281 | } | |
282 | ||
283 | module_init(sdhci_pxav3_init); | |
284 | module_exit(sdhci_pxav3_exit); | |
285 | ||
286 | MODULE_DESCRIPTION("SDHCI driver for pxav3"); | |
287 | MODULE_AUTHOR("Marvell International Ltd."); | |
288 | MODULE_LICENSE("GPL v2"); | |
289 |