[linux-2.6-block.git] / drivers / mmc / host / sdhci-pxav3.c

/*
 * Copyright (C) 2010 Marvell International Ltd.
 *		Zhangfei Gao <zhangfei.gao@marvell.com>
 *		Kevin Wang <dwang4@marvell.com>
 *		Mingwei Wang <mwwang@marvell.com>
 *		Philip Rakity <prakity@marvell.com>
 *		Mark Brown <markb@marvell.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/platform_data/pxa_sdhci.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/mbus.h>

#include "sdhci.h"
#include "sdhci-pltfm.h"

#define PXAV3_RPM_DELAY_MS     50

#define SD_CLOCK_BURST_SIZE_SETUP		0x10A
#define SDCLK_SEL	0x100
#define SDCLK_DELAY_SHIFT	9
#define SDCLK_DELAY_MASK	0x1f

#define SD_CFG_FIFO_PARAM       0x100
#define SDCFG_GEN_PAD_CLK_ON	(1<<6)
#define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
#define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24

#define SD_SPI_MODE          0x108
#define SD_CE_ATA_1          0x10C

#define SD_CE_ATA_2          0x10E
#define SDCE_MISC_INT		(1<<2)
#define SDCE_MISC_INT_EN	(1<<1)

/*
 * These registers are relative to the second register region, for the
 * MBus bridge.
 */
#define SDHCI_WINDOW_CTRL(i)	(0x80 + ((i) << 3))
#define SDHCI_WINDOW_BASE(i)	(0x84 + ((i) << 3))
#define SDHCI_MAX_WIN_NUM	8

static int mv_conf_mbus_windows(struct platform_device *pdev,
				const struct mbus_dram_target_info *dram)
{
	int i;
	void __iomem *regs;
	struct resource *res;

	if (!dram) {
		dev_err(&pdev->dev, "no mbus dram info\n");
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		dev_err(&pdev->dev, "cannot get mbus registers\n");
		return -EINVAL;
	}

	regs = ioremap(res->start, resource_size(res));
	if (!regs) {
		dev_err(&pdev->dev, "cannot map mbus registers\n");
		return -ENOMEM;
	}

	for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
		writel(0, regs + SDHCI_WINDOW_CTRL(i));
		writel(0, regs + SDHCI_WINDOW_BASE(i));
	}

	for (i = 0; i < dram->num_cs; i++) {
		const struct mbus_dram_window *cs = dram->cs + i;

		/* Write size, attributes and target id to control register */
		writel(((cs->size - 1) & 0xffff0000) |
			(cs->mbus_attr << 8) |
			(dram->mbus_dram_target_id << 4) | 1,
			regs + SDHCI_WINDOW_CTRL(i));
		/* Write base address to base register */
		writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
	}

	iounmap(regs);

	return 0;
}

static void pxav3_reset(struct sdhci_host *host, u8 mask)
{
	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;

	sdhci_reset(host, mask);

	if (mask == SDHCI_RESET_ALL) {
		/*
		 * tune timing of read data/command when crc error happen
		 * no performance impact
		 */
		if (pdata && 0 != pdata->clk_delay_cycles) {
			u16 tmp;

			tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
			tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
				<< SDCLK_DELAY_SHIFT;
			tmp |= SDCLK_SEL;
			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
		}
	}
}

#define MAX_WAIT_COUNT 5
static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;
	u16 tmp;
	int count;

	if (pxa->power_mode == MMC_POWER_UP
			&& power_mode == MMC_POWER_ON) {

		dev_dbg(mmc_dev(host->mmc),
				"%s: slot->power_mode = %d,"
				"ios->power_mode = %d\n",
				__func__,
				pxa->power_mode,
				power_mode);

		/* set we want notice of when 74 clocks are sent */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT_EN;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);

		/* start sending the 74 clocks */
		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
		tmp |= SDCFG_GEN_PAD_CLK_ON;
		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);

		/* slowest speed is about 100KHz or 10usec per clock */
		udelay(740);
		count = 0;

		while (count++ < MAX_WAIT_COUNT) {
			if ((readw(host->ioaddr + SD_CE_ATA_2)
						& SDCE_MISC_INT) == 0)
				break;
			udelay(10);
		}

		if (count == MAX_WAIT_COUNT)
			dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");

		/* clear the interrupt bit if posted */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);
	}
	pxa->power_mode = power_mode;
}

static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
{
	u16 ctrl_2;

	/*
	 * Set V18_EN -- UHS modes do not work without this.
	 * does not change signaling voltage
	 */
	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);

	/* Select Bus Speed Mode for host */
	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	switch (uhs) {
	case MMC_TIMING_UHS_SDR12:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
		break;
	case MMC_TIMING_UHS_SDR25:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
		break;
	case MMC_TIMING_UHS_SDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_SDR104:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_DDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
		break;
	}

	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	dev_dbg(mmc_dev(host->mmc),
		"%s uhs = %d, ctrl_2 = %04X\n",
		__func__, uhs, ctrl_2);
}

static const struct sdhci_ops pxav3_sdhci_ops = {
	.set_clock = sdhci_set_clock,
	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
	.set_bus_width = sdhci_set_bus_width,
	.reset = pxav3_reset,
	.set_uhs_signaling = pxav3_set_uhs_signaling,
};

static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
		| SDHCI_QUIRK_32BIT_ADMA_SIZE
		| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops = &pxav3_sdhci_ops,
};

#ifdef CONFIG_OF
static const struct of_device_id sdhci_pxav3_of_match[] = {
	{
		.compatible = "mrvl,pxav3-mmc",
	},
	{
		.compatible = "marvell,armada-380-sdhci",
	},
	{},
};
MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);

static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	struct sdhci_pxa_platdata *pdata;
	struct device_node *np = dev->of_node;
	u32 clk_delay_cycles;

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;

	of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
	if (clk_delay_cycles > 0)
		pdata->clk_delay_cycles = clk_delay_cycles;

	return pdata;
}
#else
static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	return NULL;
}
#endif

static int sdhci_pxav3_probe(struct platform_device *pdev)
{
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	struct device *dev = &pdev->dev;
	struct device_node *np = pdev->dev.of_node;
	struct sdhci_host *host = NULL;
	struct sdhci_pxa *pxa = NULL;
	const struct of_device_id *match;

	int ret;
	struct clk *clk;

	pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
	if (!pxa)
		return -ENOMEM;

	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
	if (IS_ERR(host))
		return PTR_ERR(host);

	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
		ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
		if (ret < 0)
			goto err_mbus_win;
	}


	pltfm_host = sdhci_priv(host);
	pltfm_host->priv = pxa;

	clk = devm_clk_get(dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(dev, "failed to get io clock\n");
		ret = PTR_ERR(clk);
		goto err_clk_get;
	}
	pltfm_host->clk = clk;
	clk_prepare_enable(clk);

	/* enable 1/8V DDR capable */
	host->mmc->caps |= MMC_CAP_1_8V_DDR;

	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
	if (match) {
		ret = mmc_of_parse(host->mmc);
		if (ret)
			goto err_of_parse;
		sdhci_get_of_property(pdev);
		pdata = pxav3_get_mmc_pdata(dev);
	} else if (pdata) {
		/* on-chip device */
		if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
			host->mmc->caps |= MMC_CAP_NONREMOVABLE;

		/* If slot design supports 8 bit data, indicate this to MMC. */
		if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
			host->mmc->caps |= MMC_CAP_8_BIT_DATA;

		if (pdata->quirks)
			host->quirks |= pdata->quirks;
		if (pdata->quirks2)
			host->quirks2 |= pdata->quirks2;
		if (pdata->host_caps)
			host->mmc->caps |= pdata->host_caps;
		if (pdata->host_caps2)
			host->mmc->caps2 |= pdata->host_caps2;
		if (pdata->pm_caps)
			host->mmc->pm_caps |= pdata->pm_caps;

		if (gpio_is_valid(pdata->ext_cd_gpio)) {
			ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
						  0);
			if (ret) {
				dev_err(mmc_dev(host->mmc),
					"failed to allocate card detect gpio\n");
				goto err_cd_req;
			}
		}
	}

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_suspend_ignore_children(&pdev->dev, 1);

	ret = sdhci_add_host(host);
	if (ret) {
		dev_err(&pdev->dev, "failed to add host\n");
		goto err_add_host;
	}

	platform_set_drvdata(pdev, host);

	if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
		device_init_wakeup(&pdev->dev, 1);
		host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ;
	} else {
		device_init_wakeup(&pdev->dev, 0);
	}

	pm_runtime_put_autosuspend(&pdev->dev);

	return 0;

err_add_host:
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
err_of_parse:
err_cd_req:
	clk_disable_unprepare(clk);
err_clk_get:
err_mbus_win:
	sdhci_pltfm_free(pdev);
	return ret;
}

static int sdhci_pxav3_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	pm_runtime_get_sync(&pdev->dev);
	sdhci_remove_host(host, 1);
	pm_runtime_disable(&pdev->dev);

	clk_disable_unprepare(pltfm_host->clk);

	sdhci_pltfm_free(pdev);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int sdhci_pxav3_suspend(struct device *dev)
{
	int ret;
	struct sdhci_host *host = dev_get_drvdata(dev);

	pm_runtime_get_sync(dev);
	ret = sdhci_suspend_host(host);
	pm_runtime_mark_last_busy(dev);
	pm_runtime_put_autosuspend(dev);

	return ret;
}

static int sdhci_pxav3_resume(struct device *dev)
{
	int ret;
	struct sdhci_host *host = dev_get_drvdata(dev);

	pm_runtime_get_sync(dev);
	ret = sdhci_resume_host(host);
	pm_runtime_mark_last_busy(dev);
	pm_runtime_put_autosuspend(dev);

	return ret;
}
#endif

#ifdef CONFIG_PM_RUNTIME
static int sdhci_pxav3_runtime_suspend(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	unsigned long flags;

	if (pltfm_host->clk) {
		spin_lock_irqsave(&host->lock, flags);
		host->runtime_suspended = true;
		spin_unlock_irqrestore(&host->lock, flags);

		clk_disable_unprepare(pltfm_host->clk);
	}

	return 0;
}

static int sdhci_pxav3_runtime_resume(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	unsigned long flags;

	if (pltfm_host->clk) {
		clk_prepare_enable(pltfm_host->clk);

		spin_lock_irqsave(&host->lock, flags);
		host->runtime_suspended = false;
		spin_unlock_irqrestore(&host->lock, flags);
	}

	return 0;
}
#endif

#ifdef CONFIG_PM
static const struct dev_pm_ops sdhci_pxav3_pmops = {
	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
	SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
		sdhci_pxav3_runtime_resume, NULL)
};

#define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)

#else
#define SDHCI_PXAV3_PMOPS NULL
#endif

static struct platform_driver sdhci_pxav3_driver = {
	.driver		= {
		.name	= "sdhci-pxav3",
#ifdef CONFIG_OF
		.of_match_table = sdhci_pxav3_of_match,
#endif
		.pm	= SDHCI_PXAV3_PMOPS,
	},
	.probe		= sdhci_pxav3_probe,
	.remove		= sdhci_pxav3_remove,
};

module_platform_driver(sdhci_pxav3_driver);

MODULE_DESCRIPTION("SDHCI driver for pxav3");
MODULE_AUTHOR("Marvell International Ltd.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a702c8ab ZG	1	/*
	2	* Copyright (C) 2010 Marvell International Ltd.
	3	* Zhangfei Gao <zhangfei.gao@marvell.com>
	4	* Kevin Wang <dwang4@marvell.com>
	5	* Mingwei Wang <mwwang@marvell.com>
	6	* Philip Rakity <prakity@marvell.com>
	7	* Mark Brown <markb@marvell.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19	#include <linux/err.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/clk.h>
	23	#include <linux/io.h>
	24	#include <linux/gpio.h>
	25	#include <linux/mmc/card.h>
	26	#include <linux/mmc/host.h>
8f63795c	27	#include <linux/mmc/slot-gpio.h>
bfed345e	28	#include <linux/platform_data/pxa_sdhci.h>
a702c8ab ZG	29	#include <linux/slab.h>
a702c8ab ZG	30	#include <linux/delay.h>
88b47679	31	#include <linux/module.h>
b650352d CB	32	#include <linux/of.h>
b650352d CB	33	#include <linux/of_device.h>
8f63795c	34	#include <linux/of_gpio.h>
bb691ae4 KL	35	#include <linux/pm.h>
bb691ae4 KL	36	#include <linux/pm_runtime.h>
5491ce3f	37	#include <linux/mbus.h>
b650352d	38
a702c8ab ZG	39	#include "sdhci.h"
	40	#include "sdhci-pltfm.h"
	41
bb691ae4 KL	42	#define PXAV3_RPM_DELAY_MS 50
bb691ae4 KL	43
a702c8ab ZG	44	#define SD_CLOCK_BURST_SIZE_SETUP 0x10A
	45	#define SDCLK_SEL 0x100
	46	#define SDCLK_DELAY_SHIFT 9
	47	#define SDCLK_DELAY_MASK 0x1f
	48
	49	#define SD_CFG_FIFO_PARAM 0x100
	50	#define SDCFG_GEN_PAD_CLK_ON (1<<6)
	51	#define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
	52	#define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
	53
	54	#define SD_SPI_MODE 0x108
	55	#define SD_CE_ATA_1 0x10C
	56
	57	#define SD_CE_ATA_2 0x10E
	58	#define SDCE_MISC_INT (1<<2)
	59	#define SDCE_MISC_INT_EN (1<<1)
	60
5491ce3f MW	61	/*
	62	* These registers are relative to the second register region, for the
	63	* MBus bridge.
	64	*/
	65	#define SDHCI_WINDOW_CTRL(i) (0x80 + ((i) << 3))
	66	#define SDHCI_WINDOW_BASE(i) (0x84 + ((i) << 3))
	67	#define SDHCI_MAX_WIN_NUM 8
	68
	69	static int mv_conf_mbus_windows(struct platform_device *pdev,
	70	const struct mbus_dram_target_info *dram)
	71	{
	72	int i;
	73	void __iomem *regs;
	74	struct resource *res;
	75
	76	if (!dram) {
	77	dev_err(&pdev->dev, "no mbus dram info\n");
	78	return -EINVAL;
	79	}
	80
	81	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	82	if (!res) {
	83	dev_err(&pdev->dev, "cannot get mbus registers\n");
	84	return -EINVAL;
	85	}
	86
	87	regs = ioremap(res->start, resource_size(res));
	88	if (!regs) {
	89	dev_err(&pdev->dev, "cannot map mbus registers\n");
	90	return -ENOMEM;
	91	}
	92
	93	for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
	94	writel(0, regs + SDHCI_WINDOW_CTRL(i));
	95	writel(0, regs + SDHCI_WINDOW_BASE(i));
	96	}
	97
	98	for (i = 0; i < dram->num_cs; i++) {
	99	const struct mbus_dram_window *cs = dram->cs + i;
	100
	101	/* Write size, attributes and target id to control register */
	102	writel(((cs->size - 1) & 0xffff0000) \|
	103	(cs->mbus_attr << 8) \|
	104	(dram->mbus_dram_target_id << 4) \| 1,
	105	regs + SDHCI_WINDOW_CTRL(i));
	106	/* Write base address to base register */
	107	writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
	108	}
	109
	110	iounmap(regs);
	111
	112	return 0;
	113	}
	114
03231f9b	115	static void pxav3_reset(struct sdhci_host *host, u8 mask)
a702c8ab ZG	116	{
	117	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	118	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	119
03231f9b RK	120	sdhci_reset(host, mask);
03231f9b RK	121
a702c8ab ZG	122	if (mask == SDHCI_RESET_ALL) {
	123	/*
	124	* tune timing of read data/command when crc error happen
	125	* no performance impact
	126	*/
	127	if (pdata && 0 != pdata->clk_delay_cycles) {
	128	u16 tmp;
	129
	130	tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	131	tmp \|= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
	132	<< SDCLK_DELAY_SHIFT;
	133	tmp \|= SDCLK_SEL;
	134	writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	135	}
	136	}
	137	}
	138
	139	#define MAX_WAIT_COUNT 5
	140	static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
	141	{
	142	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	143	struct sdhci_pxa *pxa = pltfm_host->priv;
	144	u16 tmp;
	145	int count;
	146
	147	if (pxa->power_mode == MMC_POWER_UP
	148	&& power_mode == MMC_POWER_ON) {
	149
	150	dev_dbg(mmc_dev(host->mmc),
	151	"%s: slot->power_mode = %d,"
	152	"ios->power_mode = %d\n",
	153	__func__,
	154	pxa->power_mode,
	155	power_mode);
	156
	157	/* set we want notice of when 74 clocks are sent */
	158	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	159	tmp \|= SDCE_MISC_INT_EN;
	160	writew(tmp, host->ioaddr + SD_CE_ATA_2);
	161
	162	/* start sending the 74 clocks */
	163	tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
	164	tmp \|= SDCFG_GEN_PAD_CLK_ON;
	165	writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
	166
	167	/* slowest speed is about 100KHz or 10usec per clock */
	168	udelay(740);
	169	count = 0;
	170
	171	while (count++ < MAX_WAIT_COUNT) {
	172	if ((readw(host->ioaddr + SD_CE_ATA_2)
	173	& SDCE_MISC_INT) == 0)
	174	break;
	175	udelay(10);
	176	}
	177
	178	if (count == MAX_WAIT_COUNT)
	179	dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
	180
	181	/* clear the interrupt bit if posted */
	182	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	183	tmp \|= SDCE_MISC_INT;
	184	writew(tmp, host->ioaddr + SD_CE_ATA_2);
	185	}
186	pxa->power_mode = power_mode;
187	}
188
13e64501	189	static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
a702c8ab ZG	190	{
	191	u16 ctrl_2;
	192
	193	/*
	194	* Set V18_EN -- UHS modes do not work without this.
	195	* does not change signaling voltage
	196	*/
	197	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	198
	199	/* Select Bus Speed Mode for host */
	200	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	201	switch (uhs) {
	202	case MMC_TIMING_UHS_SDR12:
	203	ctrl_2 \|= SDHCI_CTRL_UHS_SDR12;
	204	break;
	205	case MMC_TIMING_UHS_SDR25:
	206	ctrl_2 \|= SDHCI_CTRL_UHS_SDR25;
	207	break;
	208	case MMC_TIMING_UHS_SDR50:
	209	ctrl_2 \|= SDHCI_CTRL_UHS_SDR50 \| SDHCI_CTRL_VDD_180;
	210	break;
	211	case MMC_TIMING_UHS_SDR104:
	212	ctrl_2 \|= SDHCI_CTRL_UHS_SDR104 \| SDHCI_CTRL_VDD_180;
	213	break;
	214	case MMC_TIMING_UHS_DDR50:
	215	ctrl_2 \|= SDHCI_CTRL_UHS_DDR50 \| SDHCI_CTRL_VDD_180;
	216	break;
	217	}
	218
	219	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	220	dev_dbg(mmc_dev(host->mmc),
	221	"%s uhs = %d, ctrl_2 = %04X\n",
	222	__func__, uhs, ctrl_2);
a702c8ab ZG	223	}
a702c8ab ZG	224
c915568d	225	static const struct sdhci_ops pxav3_sdhci_ops = {
1771059c	226	.set_clock = sdhci_set_clock,
a702c8ab	227	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
d005d943	228	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
2317f56c	229	.set_bus_width = sdhci_set_bus_width,
03231f9b	230	.reset = pxav3_reset,
b3153765	231	.set_uhs_signaling = pxav3_set_uhs_signaling,
a702c8ab ZG	232	};
a702c8ab ZG	233
73b7afb9	234	static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
e065162a	235	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
73b7afb9 KL	236	\| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
	237	\| SDHCI_QUIRK_32BIT_ADMA_SIZE
	238	\| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	239	.ops = &pxav3_sdhci_ops,
	240	};
	241
b650352d CB	242	#ifdef CONFIG_OF
	243	static const struct of_device_id sdhci_pxav3_of_match[] = {
	244	{
	245	.compatible = "mrvl,pxav3-mmc",
	246	},
5491ce3f MW	247	{
	248	.compatible = "marvell,armada-380-sdhci",
	249	},
b650352d CB	250	{},
	251	};
	252	MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
	253
	254	static struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	255	{
	256	struct sdhci_pxa_platdata *pdata;
	257	struct device_node *np = dev->of_node;
b650352d CB	258	u32 clk_delay_cycles;
	259
	260	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	261	if (!pdata)
	262	return NULL;
	263
b650352d CB	264	of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
	265	if (clk_delay_cycles > 0)
	266	pdata->clk_delay_cycles = clk_delay_cycles;
	267
	268	return pdata;
	269	}
	270	#else
	271	static inline struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	272	{
	273	return NULL;
	274	}
	275	#endif
	276
c3be1efd	277	static int sdhci_pxav3_probe(struct platform_device *pdev)
a702c8ab ZG	278	{
	279	struct sdhci_pltfm_host *pltfm_host;
	280	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	281	struct device *dev = &pdev->dev;
5491ce3f	282	struct device_node *np = pdev->dev.of_node;
a702c8ab ZG	283	struct sdhci_host *host = NULL;
a702c8ab ZG	284	struct sdhci_pxa *pxa = NULL;
b650352d CB	285	const struct of_device_id *match;
b650352d CB	286
a702c8ab ZG	287	int ret;
	288	struct clk *clk;
	289
3df5b281	290	pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
a702c8ab ZG	291	if (!pxa)
	292	return -ENOMEM;
	293
0e748234	294	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
3df5b281	295	if (IS_ERR(host))
a702c8ab	296	return PTR_ERR(host);
5491ce3f MW	297
	298	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
	299	ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
	300	if (ret < 0)
	301	goto err_mbus_win;
	302	}
	303
	304
a702c8ab ZG	305	pltfm_host = sdhci_priv(host);
	306	pltfm_host->priv = pxa;
	307
3df5b281	308	clk = devm_clk_get(dev, NULL);
a702c8ab ZG	309	if (IS_ERR(clk)) {
	310	dev_err(dev, "failed to get io clock\n");
	311	ret = PTR_ERR(clk);
	312	goto err_clk_get;
	313	}
	314	pltfm_host->clk = clk;
164378ef	315	clk_prepare_enable(clk);
a702c8ab	316
a702c8ab ZG	317	/* enable 1/8V DDR capable */
	318	host->mmc->caps \|= MMC_CAP_1_8V_DDR;
	319
b650352d	320	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
943647f6	321	if (match) {
d2cf6071 SB	322	ret = mmc_of_parse(host->mmc);
	323	if (ret)
	324	goto err_of_parse;
943647f6	325	sdhci_get_of_property(pdev);
b650352d	326	pdata = pxav3_get_mmc_pdata(dev);
943647f6	327	} else if (pdata) {
c844a46f KL	328	/* on-chip device */
c844a46f KL	329	if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
a702c8ab	330	host->mmc->caps \|= MMC_CAP_NONREMOVABLE;
a702c8ab ZG	331
	332	/* If slot design supports 8 bit data, indicate this to MMC. */
	333	if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
	334	host->mmc->caps \|= MMC_CAP_8_BIT_DATA;
	335
	336	if (pdata->quirks)
	337	host->quirks \|= pdata->quirks;
7c52d7bb KL	338	if (pdata->quirks2)
7c52d7bb KL	339	host->quirks2 \|= pdata->quirks2;
a702c8ab ZG	340	if (pdata->host_caps)
a702c8ab ZG	341	host->mmc->caps \|= pdata->host_caps;
8f63795c CB	342	if (pdata->host_caps2)
8f63795c CB	343	host->mmc->caps2 \|= pdata->host_caps2;
a702c8ab ZG	344	if (pdata->pm_caps)
a702c8ab ZG	345	host->mmc->pm_caps \|= pdata->pm_caps;
8f63795c CB	346
8f63795c CB	347	if (gpio_is_valid(pdata->ext_cd_gpio)) {
214fc309 LP	348	ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
214fc309 LP	349	0);
8f63795c CB	350	if (ret) {
	351	dev_err(mmc_dev(host->mmc),
	352	"failed to allocate card detect gpio\n");
	353	goto err_cd_req;
	354	}
	355	}
a702c8ab ZG	356	}
a702c8ab ZG	357
bb691ae4	358	pm_runtime_enable(&pdev->dev);
0dcaa249	359	pm_runtime_get_sync(&pdev->dev);
bb691ae4 KL	360	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
	361	pm_runtime_use_autosuspend(&pdev->dev);
	362	pm_suspend_ignore_children(&pdev->dev, 1);
bb691ae4	363
a702c8ab ZG	364	ret = sdhci_add_host(host);
	365	if (ret) {
	366	dev_err(&pdev->dev, "failed to add host\n");
	367	goto err_add_host;
	368	}
	369
	370	platform_set_drvdata(pdev, host);
	371
943647f6	372	if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
740b7a44 KL	373	device_init_wakeup(&pdev->dev, 1);
	374	host->mmc->pm_flags \|= MMC_PM_WAKE_SDIO_IRQ;
	375	} else {
	376	device_init_wakeup(&pdev->dev, 0);
	377	}
	378
bb691ae4 KL	379	pm_runtime_put_autosuspend(&pdev->dev);
bb691ae4 KL	380
a702c8ab ZG	381	return 0;
	382
	383	err_add_host:
0dcaa249 DD	384	pm_runtime_put_sync(&pdev->dev);
0dcaa249 DD	385	pm_runtime_disable(&pdev->dev);
87d2163d XW	386	err_of_parse:
87d2163d XW	387	err_cd_req:
164378ef	388	clk_disable_unprepare(clk);
a702c8ab	389	err_clk_get:
5491ce3f	390	err_mbus_win:
a702c8ab	391	sdhci_pltfm_free(pdev);
a702c8ab ZG	392	return ret;
	393	}
	394
6e0ee714	395	static int sdhci_pxav3_remove(struct platform_device *pdev)
a702c8ab ZG	396	{
	397	struct sdhci_host *host = platform_get_drvdata(pdev);
	398	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
a702c8ab	399
bb691ae4	400	pm_runtime_get_sync(&pdev->dev);
a702c8ab	401	sdhci_remove_host(host, 1);
bb691ae4	402	pm_runtime_disable(&pdev->dev);
a702c8ab	403
164378ef	404	clk_disable_unprepare(pltfm_host->clk);
8f63795c	405
a702c8ab	406	sdhci_pltfm_free(pdev);
a702c8ab	407
a702c8ab ZG	408	return 0;
	409	}
	410
bb691ae4 KL	411	#ifdef CONFIG_PM_SLEEP
	412	static int sdhci_pxav3_suspend(struct device *dev)
	413	{
	414	int ret;
	415	struct sdhci_host *host = dev_get_drvdata(dev);
	416
	417	pm_runtime_get_sync(dev);
	418	ret = sdhci_suspend_host(host);
	419	pm_runtime_mark_last_busy(dev);
	420	pm_runtime_put_autosuspend(dev);
	421
	422	return ret;
	423	}
	424
	425	static int sdhci_pxav3_resume(struct device *dev)
	426	{
	427	int ret;
	428	struct sdhci_host *host = dev_get_drvdata(dev);
	429
	430	pm_runtime_get_sync(dev);
	431	ret = sdhci_resume_host(host);
	432	pm_runtime_mark_last_busy(dev);
	433	pm_runtime_put_autosuspend(dev);
	434
	435	return ret;
	436	}
	437	#endif
	438
	439	#ifdef CONFIG_PM_RUNTIME
	440	static int sdhci_pxav3_runtime_suspend(struct device *dev)
	441	{
	442	struct sdhci_host *host = dev_get_drvdata(dev);
	443	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	444	unsigned long flags;
	445
	446	if (pltfm_host->clk) {
	447	spin_lock_irqsave(&host->lock, flags);
	448	host->runtime_suspended = true;
	449	spin_unlock_irqrestore(&host->lock, flags);
	450
	451	clk_disable_unprepare(pltfm_host->clk);
	452	}
	453
	454	return 0;
	455	}
	456
	457	static int sdhci_pxav3_runtime_resume(struct device *dev)
	458	{
	459	struct sdhci_host *host = dev_get_drvdata(dev);
	460	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	461	unsigned long flags;
	462
	463	if (pltfm_host->clk) {
	464	clk_prepare_enable(pltfm_host->clk);
	465
	466	spin_lock_irqsave(&host->lock, flags);
	467	host->runtime_suspended = false;
	468	spin_unlock_irqrestore(&host->lock, flags);
	469	}
	470
	471	return 0;
	472	}
	473	#endif
	474
475	#ifdef CONFIG_PM
476	static const struct dev_pm_ops sdhci_pxav3_pmops = {
477	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
478	SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
479	sdhci_pxav3_runtime_resume, NULL)
480	};
481
482	#define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
483
484	#else
485	#define SDHCI_PXAV3_PMOPS NULL
486	#endif
487
a702c8ab ZG	488	static struct platform_driver sdhci_pxav3_driver = {
	489	.driver = {
	490	.name = "sdhci-pxav3",
b650352d CB	491	#ifdef CONFIG_OF
	492	.of_match_table = sdhci_pxav3_of_match,
	493	#endif
bb691ae4	494	.pm = SDHCI_PXAV3_PMOPS,
a702c8ab ZG	495	},
a702c8ab ZG	496	.probe = sdhci_pxav3_probe,
0433c143	497	.remove = sdhci_pxav3_remove,
a702c8ab	498	};
a702c8ab	499
d1f81a64	500	module_platform_driver(sdhci_pxav3_driver);
a702c8ab ZG	501
	502	MODULE_DESCRIPTION("SDHCI driver for pxav3");
	503	MODULE_AUTHOR("Marvell International Ltd.");
	504	MODULE_LICENSE("GPL v2");
	505