[linux-2.6-block.git] / drivers / mmc / host / sdhci-pxav3.c

/*
 * Copyright (C) 2010 Marvell International Ltd.
 *		Zhangfei Gao <zhangfei.gao@marvell.com>
 *		Kevin Wang <dwang4@marvell.com>
 *		Mingwei Wang <mwwang@marvell.com>
 *		Philip Rakity <prakity@marvell.com>
 *		Mark Brown <markb@marvell.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/platform_data/pxa_sdhci.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/module.h>
#include "sdhci.h"
#include "sdhci-pltfm.h"

#define SD_CLOCK_BURST_SIZE_SETUP		0x10A
#define SDCLK_SEL	0x100
#define SDCLK_DELAY_SHIFT	9
#define SDCLK_DELAY_MASK	0x1f

#define SD_CFG_FIFO_PARAM       0x100
#define SDCFG_GEN_PAD_CLK_ON	(1<<6)
#define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
#define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24

#define SD_SPI_MODE          0x108
#define SD_CE_ATA_1          0x10C

#define SD_CE_ATA_2          0x10E
#define SDCE_MISC_INT		(1<<2)
#define SDCE_MISC_INT_EN	(1<<1)

static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
{
	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;

	if (mask == SDHCI_RESET_ALL) {
		/*
		 * tune timing of read data/command when crc error happen
		 * no performance impact
		 */
		if (pdata && 0 != pdata->clk_delay_cycles) {
			u16 tmp;

			tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
			tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
				<< SDCLK_DELAY_SHIFT;
			tmp |= SDCLK_SEL;
			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
		}
	}
}

#define MAX_WAIT_COUNT 5
static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;
	u16 tmp;
	int count;

	if (pxa->power_mode == MMC_POWER_UP
			&& power_mode == MMC_POWER_ON) {

		dev_dbg(mmc_dev(host->mmc),
				"%s: slot->power_mode = %d,"
				"ios->power_mode = %d\n",
				__func__,
				pxa->power_mode,
				power_mode);

		/* set we want notice of when 74 clocks are sent */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT_EN;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);

		/* start sending the 74 clocks */
		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
		tmp |= SDCFG_GEN_PAD_CLK_ON;
		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);

		/* slowest speed is about 100KHz or 10usec per clock */
		udelay(740);
		count = 0;

		while (count++ < MAX_WAIT_COUNT) {
			if ((readw(host->ioaddr + SD_CE_ATA_2)
						& SDCE_MISC_INT) == 0)
				break;
			udelay(10);
		}

		if (count == MAX_WAIT_COUNT)
			dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");

		/* clear the interrupt bit if posted */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);
	}
	pxa->power_mode = power_mode;
}

static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
{
	u16 ctrl_2;

	/*
	 * Set V18_EN -- UHS modes do not work without this.
	 * does not change signaling voltage
	 */
	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);

	/* Select Bus Speed Mode for host */
	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	switch (uhs) {
	case MMC_TIMING_UHS_SDR12:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
		break;
	case MMC_TIMING_UHS_SDR25:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
		break;
	case MMC_TIMING_UHS_SDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_SDR104:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_DDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
		break;
	}

	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	dev_dbg(mmc_dev(host->mmc),
		"%s uhs = %d, ctrl_2 = %04X\n",
		__func__, uhs, ctrl_2);

	return 0;
}

static struct sdhci_ops pxav3_sdhci_ops = {
	.platform_reset_exit = pxav3_set_private_registers,
	.set_uhs_signaling = pxav3_set_uhs_signaling,
	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
};

static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
{
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	struct device *dev = &pdev->dev;
	struct sdhci_host *host = NULL;
	struct sdhci_pxa *pxa = NULL;
	int ret;
	struct clk *clk;

	pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
	if (!pxa)
		return -ENOMEM;

	host = sdhci_pltfm_init(pdev, NULL);
	if (IS_ERR(host)) {
		kfree(pxa);
		return PTR_ERR(host);
	}
	pltfm_host = sdhci_priv(host);
	pltfm_host->priv = pxa;

	clk = clk_get(dev, "PXA-SDHCLK");
	if (IS_ERR(clk)) {
		dev_err(dev, "failed to get io clock\n");
		ret = PTR_ERR(clk);
		goto err_clk_get;
	}
	pltfm_host->clk = clk;
	clk_enable(clk);

	host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
		| SDHCI_QUIRK_32BIT_ADMA_SIZE;

	/* enable 1/8V DDR capable */
	host->mmc->caps |= MMC_CAP_1_8V_DDR;

	if (pdata) {
		if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
			/* on-chip device */
			host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
			host->mmc->caps |= MMC_CAP_NONREMOVABLE;
		}

		/* If slot design supports 8 bit data, indicate this to MMC. */
		if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
			host->mmc->caps |= MMC_CAP_8_BIT_DATA;

		if (pdata->quirks)
			host->quirks |= pdata->quirks;
		if (pdata->host_caps)
			host->mmc->caps |= pdata->host_caps;
		if (pdata->pm_caps)
			host->mmc->pm_caps |= pdata->pm_caps;
	}

	host->ops = &pxav3_sdhci_ops;

	ret = sdhci_add_host(host);
	if (ret) {
		dev_err(&pdev->dev, "failed to add host\n");
		goto err_add_host;
	}

	platform_set_drvdata(pdev, host);

	return 0;

err_add_host:
	clk_disable(clk);
	clk_put(clk);
err_clk_get:
	sdhci_pltfm_free(pdev);
	kfree(pxa);
	return ret;
}

static int __devexit sdhci_pxav3_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;

	sdhci_remove_host(host, 1);

	clk_disable(pltfm_host->clk);
	clk_put(pltfm_host->clk);
	sdhci_pltfm_free(pdev);
	kfree(pxa);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static struct platform_driver sdhci_pxav3_driver = {
	.driver		= {
		.name	= "sdhci-pxav3",
		.owner	= THIS_MODULE,
		.pm	= SDHCI_PLTFM_PMOPS,
	},
	.probe		= sdhci_pxav3_probe,
	.remove		= __devexit_p(sdhci_pxav3_remove),
};
static int __init sdhci_pxav3_init(void)
{
	return platform_driver_register(&sdhci_pxav3_driver);
}

static void __exit sdhci_pxav3_exit(void)
{
	platform_driver_unregister(&sdhci_pxav3_driver);
}

module_init(sdhci_pxav3_init);
module_exit(sdhci_pxav3_exit);

MODULE_DESCRIPTION("SDHCI driver for pxav3");
MODULE_AUTHOR("Marvell International Ltd.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a702c8ab ZG	1	/*
	2	* Copyright (C) 2010 Marvell International Ltd.
	3	* Zhangfei Gao <zhangfei.gao@marvell.com>
	4	* Kevin Wang <dwang4@marvell.com>
	5	* Mingwei Wang <mwwang@marvell.com>
	6	* Philip Rakity <prakity@marvell.com>
	7	* Mark Brown <markb@marvell.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19	#include <linux/err.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/clk.h>
	23	#include <linux/io.h>
	24	#include <linux/gpio.h>
	25	#include <linux/mmc/card.h>
	26	#include <linux/mmc/host.h>
bfed345e	27	#include <linux/platform_data/pxa_sdhci.h>
a702c8ab ZG	28	#include <linux/slab.h>
a702c8ab ZG	29	#include <linux/delay.h>
88b47679	30	#include <linux/module.h>
a702c8ab ZG	31	#include "sdhci.h"
	32	#include "sdhci-pltfm.h"
	33
	34	#define SD_CLOCK_BURST_SIZE_SETUP 0x10A
	35	#define SDCLK_SEL 0x100
	36	#define SDCLK_DELAY_SHIFT 9
	37	#define SDCLK_DELAY_MASK 0x1f
	38
	39	#define SD_CFG_FIFO_PARAM 0x100
	40	#define SDCFG_GEN_PAD_CLK_ON (1<<6)
	41	#define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
	42	#define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
	43
	44	#define SD_SPI_MODE 0x108
	45	#define SD_CE_ATA_1 0x10C
	46
	47	#define SD_CE_ATA_2 0x10E
	48	#define SDCE_MISC_INT (1<<2)
	49	#define SDCE_MISC_INT_EN (1<<1)
	50
	51	static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
	52	{
	53	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	54	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	55
	56	if (mask == SDHCI_RESET_ALL) {
	57	/*
	58	* tune timing of read data/command when crc error happen
	59	* no performance impact
	60	*/
	61	if (pdata && 0 != pdata->clk_delay_cycles) {
	62	u16 tmp;
	63
	64	tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	65	tmp \|= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
	66	<< SDCLK_DELAY_SHIFT;
	67	tmp \|= SDCLK_SEL;
	68	writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	69	}
	70	}
	71	}
	72
	73	#define MAX_WAIT_COUNT 5
	74	static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
	75	{
	76	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	77	struct sdhci_pxa *pxa = pltfm_host->priv;
	78	u16 tmp;
	79	int count;
	80
	81	if (pxa->power_mode == MMC_POWER_UP
	82	&& power_mode == MMC_POWER_ON) {
	83
	84	dev_dbg(mmc_dev(host->mmc),
	85	"%s: slot->power_mode = %d,"
	86	"ios->power_mode = %d\n",
	87	__func__,
	88	pxa->power_mode,
	89	power_mode);
	90
	91	/* set we want notice of when 74 clocks are sent */
	92	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	93	tmp \|= SDCE_MISC_INT_EN;
	94	writew(tmp, host->ioaddr + SD_CE_ATA_2);
95
96	/* start sending the 74 clocks */
97	tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
98	tmp \|= SDCFG_GEN_PAD_CLK_ON;
99	writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
100
101	/* slowest speed is about 100KHz or 10usec per clock */
102	udelay(740);
103	count = 0;
104
105	while (count++ < MAX_WAIT_COUNT) {
106	if ((readw(host->ioaddr + SD_CE_ATA_2)
107	& SDCE_MISC_INT) == 0)
108	break;
109	udelay(10);
110	}
111
112	if (count == MAX_WAIT_COUNT)
113	dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
114
115	/* clear the interrupt bit if posted */
116	tmp = readw(host->ioaddr + SD_CE_ATA_2);
117	tmp \|= SDCE_MISC_INT;
118	writew(tmp, host->ioaddr + SD_CE_ATA_2);
119	}
120	pxa->power_mode = power_mode;
121	}
122
123	static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
124	{
125	u16 ctrl_2;
126
127	/*
128	* Set V18_EN -- UHS modes do not work without this.
129	* does not change signaling voltage
130	*/
131	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
132
133	/* Select Bus Speed Mode for host */
134	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
135	switch (uhs) {
136	case MMC_TIMING_UHS_SDR12:
137	ctrl_2 \|= SDHCI_CTRL_UHS_SDR12;
138	break;
139	case MMC_TIMING_UHS_SDR25:
140	ctrl_2 \|= SDHCI_CTRL_UHS_SDR25;
141	break;
142	case MMC_TIMING_UHS_SDR50:
143	ctrl_2 \|= SDHCI_CTRL_UHS_SDR50 \| SDHCI_CTRL_VDD_180;
144	break;
145	case MMC_TIMING_UHS_SDR104:
146	ctrl_2 \|= SDHCI_CTRL_UHS_SDR104 \| SDHCI_CTRL_VDD_180;
147	break;
148	case MMC_TIMING_UHS_DDR50:
149	ctrl_2 \|= SDHCI_CTRL_UHS_DDR50 \| SDHCI_CTRL_VDD_180;
150	break;
151	}
152
153	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
154	dev_dbg(mmc_dev(host->mmc),
155	"%s uhs = %d, ctrl_2 = %04X\n",
156	__func__, uhs, ctrl_2);
157
158	return 0;
159	}
160
161	static struct sdhci_ops pxav3_sdhci_ops = {
162	.platform_reset_exit = pxav3_set_private_registers,
163	.set_uhs_signaling = pxav3_set_uhs_signaling,
164	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
165	};
166
167	static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
168	{
169	struct sdhci_pltfm_host *pltfm_host;
170	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
171	struct device *dev = &pdev->dev;
172	struct sdhci_host *host = NULL;
173	struct sdhci_pxa *pxa = NULL;
174	int ret;
175	struct clk *clk;
176
177	pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
178	if (!pxa)
179	return -ENOMEM;
180
181	host = sdhci_pltfm_init(pdev, NULL);
182	if (IS_ERR(host)) {
183	kfree(pxa);
184	return PTR_ERR(host);
185	}
186	pltfm_host = sdhci_priv(host);
187	pltfm_host->priv = pxa;
188
189	clk = clk_get(dev, "PXA-SDHCLK");
190	if (IS_ERR(clk)) {
191	dev_err(dev, "failed to get io clock\n");
192	ret = PTR_ERR(clk);
193	goto err_clk_get;
194	}
195	pltfm_host->clk = clk;
196	clk_enable(clk);
197
198	host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
606a15e4 PR	199	\| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
606a15e4 PR	200	\| SDHCI_QUIRK_32BIT_ADMA_SIZE;
a702c8ab ZG	201
	202	/* enable 1/8V DDR capable */
	203	host->mmc->caps \|= MMC_CAP_1_8V_DDR;
	204
	205	if (pdata) {
	206	if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
	207	/* on-chip device */
	208	host->quirks \|= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
	209	host->mmc->caps \|= MMC_CAP_NONREMOVABLE;
	210	}
	211
	212	/* If slot design supports 8 bit data, indicate this to MMC. */
	213	if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
	214	host->mmc->caps \|= MMC_CAP_8_BIT_DATA;
	215
	216	if (pdata->quirks)
	217	host->quirks \|= pdata->quirks;
	218	if (pdata->host_caps)
	219	host->mmc->caps \|= pdata->host_caps;
	220	if (pdata->pm_caps)
	221	host->mmc->pm_caps \|= pdata->pm_caps;
	222	}
	223
	224	host->ops = &pxav3_sdhci_ops;
	225
	226	ret = sdhci_add_host(host);
	227	if (ret) {
	228	dev_err(&pdev->dev, "failed to add host\n");
	229	goto err_add_host;
	230	}
	231
	232	platform_set_drvdata(pdev, host);
	233
	234	return 0;
	235
	236	err_add_host:
	237	clk_disable(clk);
	238	clk_put(clk);
	239	err_clk_get:
	240	sdhci_pltfm_free(pdev);
	241	kfree(pxa);
	242	return ret;
	243	}
	244
	245	static int __devexit sdhci_pxav3_remove(struct platform_device *pdev)
	246	{
	247	struct sdhci_host *host = platform_get_drvdata(pdev);
	248	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	249	struct sdhci_pxa *pxa = pltfm_host->priv;
	250
	251	sdhci_remove_host(host, 1);
	252
	253	clk_disable(pltfm_host->clk);
	254	clk_put(pltfm_host->clk);
	255	sdhci_pltfm_free(pdev);
	256	kfree(pxa);
	257
	258	platform_set_drvdata(pdev, NULL);
	259
	260	return 0;
	261	}
	262
	263	static struct platform_driver sdhci_pxav3_driver = {
	264	.driver = {
265	.name = "sdhci-pxav3",
266	.owner = THIS_MODULE,
29495aa0	267	.pm = SDHCI_PLTFM_PMOPS,
a702c8ab ZG	268	},
	269	.probe = sdhci_pxav3_probe,
	270	.remove = __devexit_p(sdhci_pxav3_remove),
a702c8ab ZG	271	};
	272	static int __init sdhci_pxav3_init(void)
	273	{
	274	return platform_driver_register(&sdhci_pxav3_driver);
	275	}
	276
	277	static void __exit sdhci_pxav3_exit(void)
	278	{
	279	platform_driver_unregister(&sdhci_pxav3_driver);
	280	}
	281
	282	module_init(sdhci_pxav3_init);
	283	module_exit(sdhci_pxav3_exit);
	284
	285	MODULE_DESCRIPTION("SDHCI driver for pxav3");
	286	MODULE_AUTHOR("Marvell International Ltd.");
	287	MODULE_LICENSE("GPL v2");
	288