[linux-2.6-block.git] / drivers / mmc / host / sdhci-pxav3.c

/*
 * Copyright (C) 2010 Marvell International Ltd.
 *		Zhangfei Gao <zhangfei.gao@marvell.com>
 *		Kevin Wang <dwang4@marvell.com>
 *		Mingwei Wang <mwwang@marvell.com>
 *		Philip Rakity <prakity@marvell.com>
 *		Mark Brown <markb@marvell.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/platform_data/pxa_sdhci.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>

#include "sdhci.h"
#include "sdhci-pltfm.h"

#define PXAV3_RPM_DELAY_MS     50

#define SD_CLOCK_BURST_SIZE_SETUP		0x10A
#define SDCLK_SEL	0x100
#define SDCLK_DELAY_SHIFT	9
#define SDCLK_DELAY_MASK	0x1f

#define SD_CFG_FIFO_PARAM       0x100
#define SDCFG_GEN_PAD_CLK_ON	(1<<6)
#define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
#define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24

#define SD_SPI_MODE          0x108
#define SD_CE_ATA_1          0x10C

#define SD_CE_ATA_2          0x10E
#define SDCE_MISC_INT		(1<<2)
#define SDCE_MISC_INT_EN	(1<<1)

static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
{
	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;

	if (mask == SDHCI_RESET_ALL) {
		/*
		 * tune timing of read data/command when crc error happen
		 * no performance impact
		 */
		if (pdata && 0 != pdata->clk_delay_cycles) {
			u16 tmp;

			tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
			tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
				<< SDCLK_DELAY_SHIFT;
			tmp |= SDCLK_SEL;
			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
		}
	}
}

#define MAX_WAIT_COUNT 5
static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;
	u16 tmp;
	int count;

	if (pxa->power_mode == MMC_POWER_UP
			&& power_mode == MMC_POWER_ON) {

		dev_dbg(mmc_dev(host->mmc),
				"%s: slot->power_mode = %d,"
				"ios->power_mode = %d\n",
				__func__,
				pxa->power_mode,
				power_mode);

		/* set we want notice of when 74 clocks are sent */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT_EN;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);

		/* start sending the 74 clocks */
		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
		tmp |= SDCFG_GEN_PAD_CLK_ON;
		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);

		/* slowest speed is about 100KHz or 10usec per clock */
		udelay(740);
		count = 0;

		while (count++ < MAX_WAIT_COUNT) {
			if ((readw(host->ioaddr + SD_CE_ATA_2)
						& SDCE_MISC_INT) == 0)
				break;
			udelay(10);
		}

		if (count == MAX_WAIT_COUNT)
			dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");

		/* clear the interrupt bit if posted */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);
	}
	pxa->power_mode = power_mode;
}

static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
{
	u16 ctrl_2;

	/*
	 * Set V18_EN -- UHS modes do not work without this.
	 * does not change signaling voltage
	 */
	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);

	/* Select Bus Speed Mode for host */
	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	switch (uhs) {
	case MMC_TIMING_UHS_SDR12:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
		break;
	case MMC_TIMING_UHS_SDR25:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
		break;
	case MMC_TIMING_UHS_SDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_SDR104:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_DDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
		break;
	}

	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	dev_dbg(mmc_dev(host->mmc),
		"%s uhs = %d, ctrl_2 = %04X\n",
		__func__, uhs, ctrl_2);

	return 0;
}

static const struct sdhci_ops pxav3_sdhci_ops = {
	.platform_reset_exit = pxav3_set_private_registers,
	.set_uhs_signaling = pxav3_set_uhs_signaling,
	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
};

static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
		| SDHCI_QUIRK_32BIT_ADMA_SIZE
		| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops = &pxav3_sdhci_ops,
};

#ifdef CONFIG_OF
static const struct of_device_id sdhci_pxav3_of_match[] = {
	{
		.compatible = "mrvl,pxav3-mmc",
	},
	{},
};
MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);

static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	struct sdhci_pxa_platdata *pdata;
	struct device_node *np = dev->of_node;
	u32 clk_delay_cycles;

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;

	of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
	if (clk_delay_cycles > 0)
		pdata->clk_delay_cycles = clk_delay_cycles;

	return pdata;
}
#else
static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	return NULL;
}
#endif

static int sdhci_pxav3_probe(struct platform_device *pdev)
{
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	struct device *dev = &pdev->dev;
	struct sdhci_host *host = NULL;
	struct sdhci_pxa *pxa = NULL;
	const struct of_device_id *match;

	int ret;
	struct clk *clk;

	pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
	if (!pxa)
		return -ENOMEM;

	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
	if (IS_ERR(host)) {
		kfree(pxa);
		return PTR_ERR(host);
	}
	pltfm_host = sdhci_priv(host);
	pltfm_host->priv = pxa;

	clk = clk_get(dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(dev, "failed to get io clock\n");
		ret = PTR_ERR(clk);
		goto err_clk_get;
	}
	pltfm_host->clk = clk;
	clk_prepare_enable(clk);

	/* enable 1/8V DDR capable */
	host->mmc->caps |= MMC_CAP_1_8V_DDR;

	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
	if (match) {
		ret = mmc_of_parse(host->mmc);
		if (ret)
			goto err_of_parse;
		sdhci_get_of_property(pdev);
		pdata = pxav3_get_mmc_pdata(dev);
	} else if (pdata) {
		/* on-chip device */
		if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
			host->mmc->caps |= MMC_CAP_NONREMOVABLE;

		/* If slot design supports 8 bit data, indicate this to MMC. */
		if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
			host->mmc->caps |= MMC_CAP_8_BIT_DATA;

		if (pdata->quirks)
			host->quirks |= pdata->quirks;
		if (pdata->quirks2)
			host->quirks2 |= pdata->quirks2;
		if (pdata->host_caps)
			host->mmc->caps |= pdata->host_caps;
		if (pdata->host_caps2)
			host->mmc->caps2 |= pdata->host_caps2;
		if (pdata->pm_caps)
			host->mmc->pm_caps |= pdata->pm_caps;

		if (gpio_is_valid(pdata->ext_cd_gpio)) {
			ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio);
			if (ret) {
				dev_err(mmc_dev(host->mmc),
					"failed to allocate card detect gpio\n");
				goto err_cd_req;
			}
		}
	}

	pm_runtime_set_active(&pdev->dev);
	pm_runtime_enable(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_suspend_ignore_children(&pdev->dev, 1);
	pm_runtime_get_noresume(&pdev->dev);

	ret = sdhci_add_host(host);
	if (ret) {
		dev_err(&pdev->dev, "failed to add host\n");
		pm_runtime_forbid(&pdev->dev);
		pm_runtime_disable(&pdev->dev);
		goto err_add_host;
	}

	platform_set_drvdata(pdev, host);

	if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
		device_init_wakeup(&pdev->dev, 1);
		host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ;
	} else {
		device_init_wakeup(&pdev->dev, 0);
	}

	pm_runtime_put_autosuspend(&pdev->dev);

	return 0;

err_of_parse:
err_cd_req:
err_add_host:
	clk_disable_unprepare(clk);
	clk_put(clk);
err_clk_get:
	sdhci_pltfm_free(pdev);
	kfree(pxa);
	return ret;
}

static int sdhci_pxav3_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;

	pm_runtime_get_sync(&pdev->dev);
	sdhci_remove_host(host, 1);
	pm_runtime_disable(&pdev->dev);

	clk_disable_unprepare(pltfm_host->clk);
	clk_put(pltfm_host->clk);

	sdhci_pltfm_free(pdev);
	kfree(pxa);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int sdhci_pxav3_suspend(struct device *dev)
{
	int ret;
	struct sdhci_host *host = dev_get_drvdata(dev);

	pm_runtime_get_sync(dev);
	ret = sdhci_suspend_host(host);
	pm_runtime_mark_last_busy(dev);
	pm_runtime_put_autosuspend(dev);

	return ret;
}

static int sdhci_pxav3_resume(struct device *dev)
{
	int ret;
	struct sdhci_host *host = dev_get_drvdata(dev);

	pm_runtime_get_sync(dev);
	ret = sdhci_resume_host(host);
	pm_runtime_mark_last_busy(dev);
	pm_runtime_put_autosuspend(dev);

	return ret;
}
#endif

#ifdef CONFIG_PM_RUNTIME
static int sdhci_pxav3_runtime_suspend(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	unsigned long flags;

	if (pltfm_host->clk) {
		spin_lock_irqsave(&host->lock, flags);
		host->runtime_suspended = true;
		spin_unlock_irqrestore(&host->lock, flags);

		clk_disable_unprepare(pltfm_host->clk);
	}

	return 0;
}

static int sdhci_pxav3_runtime_resume(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	unsigned long flags;

	if (pltfm_host->clk) {
		clk_prepare_enable(pltfm_host->clk);

		spin_lock_irqsave(&host->lock, flags);
		host->runtime_suspended = false;
		spin_unlock_irqrestore(&host->lock, flags);
	}

	return 0;
}
#endif

#ifdef CONFIG_PM
static const struct dev_pm_ops sdhci_pxav3_pmops = {
	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
	SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
		sdhci_pxav3_runtime_resume, NULL)
};

#define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)

#else
#define SDHCI_PXAV3_PMOPS NULL
#endif

static struct platform_driver sdhci_pxav3_driver = {
	.driver		= {
		.name	= "sdhci-pxav3",
#ifdef CONFIG_OF
		.of_match_table = sdhci_pxav3_of_match,
#endif
		.owner	= THIS_MODULE,
		.pm	= SDHCI_PXAV3_PMOPS,
	},
	.probe		= sdhci_pxav3_probe,
	.remove		= sdhci_pxav3_remove,
};

module_platform_driver(sdhci_pxav3_driver);

MODULE_DESCRIPTION("SDHCI driver for pxav3");
MODULE_AUTHOR("Marvell International Ltd.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a702c8ab ZG	1	/*
	2	* Copyright (C) 2010 Marvell International Ltd.
	3	* Zhangfei Gao <zhangfei.gao@marvell.com>
	4	* Kevin Wang <dwang4@marvell.com>
	5	* Mingwei Wang <mwwang@marvell.com>
	6	* Philip Rakity <prakity@marvell.com>
	7	* Mark Brown <markb@marvell.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19	#include <linux/err.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/clk.h>
	23	#include <linux/io.h>
	24	#include <linux/gpio.h>
	25	#include <linux/mmc/card.h>
	26	#include <linux/mmc/host.h>
8f63795c	27	#include <linux/mmc/slot-gpio.h>
bfed345e	28	#include <linux/platform_data/pxa_sdhci.h>
a702c8ab ZG	29	#include <linux/slab.h>
a702c8ab ZG	30	#include <linux/delay.h>
88b47679	31	#include <linux/module.h>
b650352d CB	32	#include <linux/of.h>
b650352d CB	33	#include <linux/of_device.h>
8f63795c	34	#include <linux/of_gpio.h>
bb691ae4 KL	35	#include <linux/pm.h>
bb691ae4 KL	36	#include <linux/pm_runtime.h>
b650352d	37
a702c8ab ZG	38	#include "sdhci.h"
	39	#include "sdhci-pltfm.h"
	40
bb691ae4 KL	41	#define PXAV3_RPM_DELAY_MS 50
bb691ae4 KL	42
a702c8ab ZG	43	#define SD_CLOCK_BURST_SIZE_SETUP 0x10A
	44	#define SDCLK_SEL 0x100
	45	#define SDCLK_DELAY_SHIFT 9
	46	#define SDCLK_DELAY_MASK 0x1f
	47
	48	#define SD_CFG_FIFO_PARAM 0x100
	49	#define SDCFG_GEN_PAD_CLK_ON (1<<6)
	50	#define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
	51	#define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
	52
	53	#define SD_SPI_MODE 0x108
	54	#define SD_CE_ATA_1 0x10C
	55
	56	#define SD_CE_ATA_2 0x10E
	57	#define SDCE_MISC_INT (1<<2)
	58	#define SDCE_MISC_INT_EN (1<<1)
	59
	60	static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
	61	{
	62	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	63	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	64
	65	if (mask == SDHCI_RESET_ALL) {
	66	/*
	67	* tune timing of read data/command when crc error happen
	68	* no performance impact
	69	*/
	70	if (pdata && 0 != pdata->clk_delay_cycles) {
	71	u16 tmp;
	72
	73	tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	74	tmp \|= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
	75	<< SDCLK_DELAY_SHIFT;
	76	tmp \|= SDCLK_SEL;
	77	writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	78	}
	79	}
	80	}
	81
	82	#define MAX_WAIT_COUNT 5
	83	static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
	84	{
	85	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	86	struct sdhci_pxa *pxa = pltfm_host->priv;
	87	u16 tmp;
	88	int count;
	89
	90	if (pxa->power_mode == MMC_POWER_UP
	91	&& power_mode == MMC_POWER_ON) {
	92
	93	dev_dbg(mmc_dev(host->mmc),
	94	"%s: slot->power_mode = %d,"
	95	"ios->power_mode = %d\n",
	96	__func__,
	97	pxa->power_mode,
	98	power_mode);
	99
	100	/* set we want notice of when 74 clocks are sent */
	101	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	102	tmp \|= SDCE_MISC_INT_EN;
	103	writew(tmp, host->ioaddr + SD_CE_ATA_2);
	104
	105	/* start sending the 74 clocks */
	106	tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
107	tmp \|= SDCFG_GEN_PAD_CLK_ON;
108	writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
109
110	/* slowest speed is about 100KHz or 10usec per clock */
111	udelay(740);
112	count = 0;
113
114	while (count++ < MAX_WAIT_COUNT) {
115	if ((readw(host->ioaddr + SD_CE_ATA_2)
116	& SDCE_MISC_INT) == 0)
117	break;
118	udelay(10);
119	}
120
121	if (count == MAX_WAIT_COUNT)
122	dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
123
124	/* clear the interrupt bit if posted */
125	tmp = readw(host->ioaddr + SD_CE_ATA_2);
126	tmp \|= SDCE_MISC_INT;
127	writew(tmp, host->ioaddr + SD_CE_ATA_2);
128	}
129	pxa->power_mode = power_mode;
130	}
131
132	static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
133	{
134	u16 ctrl_2;
135
136	/*
137	* Set V18_EN -- UHS modes do not work without this.
138	* does not change signaling voltage
139	*/
140	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
141
142	/* Select Bus Speed Mode for host */
143	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
144	switch (uhs) {
145	case MMC_TIMING_UHS_SDR12:
146	ctrl_2 \|= SDHCI_CTRL_UHS_SDR12;
147	break;
148	case MMC_TIMING_UHS_SDR25:
149	ctrl_2 \|= SDHCI_CTRL_UHS_SDR25;
150	break;
151	case MMC_TIMING_UHS_SDR50:
152	ctrl_2 \|= SDHCI_CTRL_UHS_SDR50 \| SDHCI_CTRL_VDD_180;
153	break;
154	case MMC_TIMING_UHS_SDR104:
155	ctrl_2 \|= SDHCI_CTRL_UHS_SDR104 \| SDHCI_CTRL_VDD_180;
156	break;
157	case MMC_TIMING_UHS_DDR50:
158	ctrl_2 \|= SDHCI_CTRL_UHS_DDR50 \| SDHCI_CTRL_VDD_180;
159	break;
160	}
161
162	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
163	dev_dbg(mmc_dev(host->mmc),
164	"%s uhs = %d, ctrl_2 = %04X\n",
165	__func__, uhs, ctrl_2);
166
167	return 0;
168	}
169
c915568d	170	static const struct sdhci_ops pxav3_sdhci_ops = {
a702c8ab ZG	171	.platform_reset_exit = pxav3_set_private_registers,
	172	.set_uhs_signaling = pxav3_set_uhs_signaling,
	173	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
d005d943	174	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
a702c8ab ZG	175	};
a702c8ab ZG	176
73b7afb9	177	static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
e065162a	178	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
73b7afb9 KL	179	\| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
	180	\| SDHCI_QUIRK_32BIT_ADMA_SIZE
	181	\| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	182	.ops = &pxav3_sdhci_ops,
	183	};
	184
b650352d CB	185	#ifdef CONFIG_OF
	186	static const struct of_device_id sdhci_pxav3_of_match[] = {
	187	{
	188	.compatible = "mrvl,pxav3-mmc",
	189	},
	190	{},
	191	};
	192	MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
	193
	194	static struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	195	{
	196	struct sdhci_pxa_platdata *pdata;
	197	struct device_node *np = dev->of_node;
b650352d CB	198	u32 clk_delay_cycles;
	199
	200	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	201	if (!pdata)
	202	return NULL;
	203
b650352d CB	204	of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
	205	if (clk_delay_cycles > 0)
	206	pdata->clk_delay_cycles = clk_delay_cycles;
	207
	208	return pdata;
	209	}
	210	#else
	211	static inline struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	212	{
	213	return NULL;
	214	}
	215	#endif
	216
c3be1efd	217	static int sdhci_pxav3_probe(struct platform_device *pdev)
a702c8ab ZG	218	{
	219	struct sdhci_pltfm_host *pltfm_host;
	220	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	221	struct device *dev = &pdev->dev;
	222	struct sdhci_host *host = NULL;
	223	struct sdhci_pxa *pxa = NULL;
b650352d CB	224	const struct of_device_id *match;
b650352d CB	225
a702c8ab ZG	226	int ret;
	227	struct clk *clk;
	228
	229	pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
	230	if (!pxa)
	231	return -ENOMEM;
	232
0e748234	233	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
a702c8ab ZG	234	if (IS_ERR(host)) {
	235	kfree(pxa);
	236	return PTR_ERR(host);
	237	}
	238	pltfm_host = sdhci_priv(host);
	239	pltfm_host->priv = pxa;
	240
164378ef	241	clk = clk_get(dev, NULL);
a702c8ab ZG	242	if (IS_ERR(clk)) {
	243	dev_err(dev, "failed to get io clock\n");
	244	ret = PTR_ERR(clk);
	245	goto err_clk_get;
	246	}
	247	pltfm_host->clk = clk;
164378ef	248	clk_prepare_enable(clk);
a702c8ab	249
a702c8ab ZG	250	/* enable 1/8V DDR capable */
	251	host->mmc->caps \|= MMC_CAP_1_8V_DDR;
	252
b650352d	253	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
943647f6	254	if (match) {
d2cf6071 SB	255	ret = mmc_of_parse(host->mmc);
	256	if (ret)
	257	goto err_of_parse;
943647f6	258	sdhci_get_of_property(pdev);
b650352d	259	pdata = pxav3_get_mmc_pdata(dev);
943647f6	260	} else if (pdata) {
c844a46f KL	261	/* on-chip device */
c844a46f KL	262	if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
a702c8ab	263	host->mmc->caps \|= MMC_CAP_NONREMOVABLE;
a702c8ab ZG	264
	265	/* If slot design supports 8 bit data, indicate this to MMC. */
	266	if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
	267	host->mmc->caps \|= MMC_CAP_8_BIT_DATA;
	268
	269	if (pdata->quirks)
	270	host->quirks \|= pdata->quirks;
7c52d7bb KL	271	if (pdata->quirks2)
7c52d7bb KL	272	host->quirks2 \|= pdata->quirks2;
a702c8ab ZG	273	if (pdata->host_caps)
a702c8ab ZG	274	host->mmc->caps \|= pdata->host_caps;
8f63795c CB	275	if (pdata->host_caps2)
8f63795c CB	276	host->mmc->caps2 \|= pdata->host_caps2;
a702c8ab ZG	277	if (pdata->pm_caps)
a702c8ab ZG	278	host->mmc->pm_caps \|= pdata->pm_caps;
8f63795c CB	279
	280	if (gpio_is_valid(pdata->ext_cd_gpio)) {
	281	ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio);
	282	if (ret) {
	283	dev_err(mmc_dev(host->mmc),
	284	"failed to allocate card detect gpio\n");
	285	goto err_cd_req;
	286	}
	287	}
a702c8ab ZG	288	}
a702c8ab ZG	289
bb691ae4 KL	290	pm_runtime_set_active(&pdev->dev);
	291	pm_runtime_enable(&pdev->dev);
	292	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
	293	pm_runtime_use_autosuspend(&pdev->dev);
	294	pm_suspend_ignore_children(&pdev->dev, 1);
	295	pm_runtime_get_noresume(&pdev->dev);
	296
a702c8ab ZG	297	ret = sdhci_add_host(host);
	298	if (ret) {
	299	dev_err(&pdev->dev, "failed to add host\n");
bb691ae4 KL	300	pm_runtime_forbid(&pdev->dev);
bb691ae4 KL	301	pm_runtime_disable(&pdev->dev);
a702c8ab ZG	302	goto err_add_host;
	303	}
	304
	305	platform_set_drvdata(pdev, host);
	306
943647f6	307	if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
740b7a44 KL	308	device_init_wakeup(&pdev->dev, 1);
	309	host->mmc->pm_flags \|= MMC_PM_WAKE_SDIO_IRQ;
	310	} else {
	311	device_init_wakeup(&pdev->dev, 0);
	312	}
	313
bb691ae4 KL	314	pm_runtime_put_autosuspend(&pdev->dev);
bb691ae4 KL	315
a702c8ab ZG	316	return 0;
a702c8ab ZG	317
d2cf6071 SB	318	err_of_parse:
d2cf6071 SB	319	err_cd_req:
a702c8ab	320	err_add_host:
164378ef	321	clk_disable_unprepare(clk);
a702c8ab ZG	322	clk_put(clk);
	323	err_clk_get:
	324	sdhci_pltfm_free(pdev);
	325	kfree(pxa);
	326	return ret;
	327	}
	328
6e0ee714	329	static int sdhci_pxav3_remove(struct platform_device *pdev)
a702c8ab ZG	330	{
	331	struct sdhci_host *host = platform_get_drvdata(pdev);
	332	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	333	struct sdhci_pxa *pxa = pltfm_host->priv;
	334
bb691ae4	335	pm_runtime_get_sync(&pdev->dev);
a702c8ab	336	sdhci_remove_host(host, 1);
bb691ae4	337	pm_runtime_disable(&pdev->dev);
a702c8ab	338
164378ef	339	clk_disable_unprepare(pltfm_host->clk);
a702c8ab	340	clk_put(pltfm_host->clk);
8f63795c	341
a702c8ab ZG	342	sdhci_pltfm_free(pdev);
	343	kfree(pxa);
	344
a702c8ab ZG	345	return 0;
	346	}
	347
bb691ae4 KL	348	#ifdef CONFIG_PM_SLEEP
	349	static int sdhci_pxav3_suspend(struct device *dev)
	350	{
	351	int ret;
	352	struct sdhci_host *host = dev_get_drvdata(dev);
	353
	354	pm_runtime_get_sync(dev);
	355	ret = sdhci_suspend_host(host);
	356	pm_runtime_mark_last_busy(dev);
	357	pm_runtime_put_autosuspend(dev);
	358
	359	return ret;
	360	}
	361
	362	static int sdhci_pxav3_resume(struct device *dev)
	363	{
	364	int ret;
	365	struct sdhci_host *host = dev_get_drvdata(dev);
	366
	367	pm_runtime_get_sync(dev);
	368	ret = sdhci_resume_host(host);
	369	pm_runtime_mark_last_busy(dev);
	370	pm_runtime_put_autosuspend(dev);
	371
	372	return ret;
	373	}
	374	#endif
	375
	376	#ifdef CONFIG_PM_RUNTIME
	377	static int sdhci_pxav3_runtime_suspend(struct device *dev)
	378	{
	379	struct sdhci_host *host = dev_get_drvdata(dev);
	380	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	381	unsigned long flags;
	382
	383	if (pltfm_host->clk) {
	384	spin_lock_irqsave(&host->lock, flags);
	385	host->runtime_suspended = true;
	386	spin_unlock_irqrestore(&host->lock, flags);
	387
	388	clk_disable_unprepare(pltfm_host->clk);
	389	}
	390
	391	return 0;
	392	}
	393
	394	static int sdhci_pxav3_runtime_resume(struct device *dev)
	395	{
	396	struct sdhci_host *host = dev_get_drvdata(dev);
	397	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	398	unsigned long flags;
	399
	400	if (pltfm_host->clk) {
	401	clk_prepare_enable(pltfm_host->clk);
	402
	403	spin_lock_irqsave(&host->lock, flags);
	404	host->runtime_suspended = false;
	405	spin_unlock_irqrestore(&host->lock, flags);
	406	}
	407
	408	return 0;
	409	}
	410	#endif
	411
412	#ifdef CONFIG_PM
413	static const struct dev_pm_ops sdhci_pxav3_pmops = {
414	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
415	SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
416	sdhci_pxav3_runtime_resume, NULL)
417	};
418
419	#define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
420
421	#else
422	#define SDHCI_PXAV3_PMOPS NULL
423	#endif
424
a702c8ab ZG	425	static struct platform_driver sdhci_pxav3_driver = {
	426	.driver = {
	427	.name = "sdhci-pxav3",
b650352d CB	428	#ifdef CONFIG_OF
	429	.of_match_table = sdhci_pxav3_of_match,
	430	#endif
a702c8ab	431	.owner = THIS_MODULE,
bb691ae4	432	.pm = SDHCI_PXAV3_PMOPS,
a702c8ab ZG	433	},
a702c8ab ZG	434	.probe = sdhci_pxav3_probe,
0433c143	435	.remove = sdhci_pxav3_remove,
a702c8ab	436	};
a702c8ab	437
d1f81a64	438	module_platform_driver(sdhci_pxav3_driver);
a702c8ab ZG	439
	440	MODULE_DESCRIPTION("SDHCI driver for pxav3");
	441	MODULE_AUTHOR("Marvell International Ltd.");
	442	MODULE_LICENSE("GPL v2");
	443