[linux-2.6-block.git] / drivers / mmc / host / sdhci-pxav3.c

/*
 * Copyright (C) 2010 Marvell International Ltd.
 *		Zhangfei Gao <zhangfei.gao@marvell.com>
 *		Kevin Wang <dwang4@marvell.com>
 *		Mingwei Wang <mwwang@marvell.com>
 *		Philip Rakity <prakity@marvell.com>
 *		Mark Brown <markb@marvell.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/platform_data/pxa_sdhci.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/mbus.h>

#include "sdhci.h"
#include "sdhci-pltfm.h"

#define PXAV3_RPM_DELAY_MS     50

#define SD_CLOCK_BURST_SIZE_SETUP		0x10A
#define SDCLK_SEL	0x100
#define SDCLK_DELAY_SHIFT	9
#define SDCLK_DELAY_MASK	0x1f

#define SD_CFG_FIFO_PARAM       0x100
#define SDCFG_GEN_PAD_CLK_ON	(1<<6)
#define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
#define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24

#define SD_SPI_MODE          0x108
#define SD_CE_ATA_1          0x10C

#define SD_CE_ATA_2          0x10E
#define SDCE_MISC_INT		(1<<2)
#define SDCE_MISC_INT_EN	(1<<1)

struct sdhci_pxa {
	struct clk *clk_core;
	struct clk *clk_io;
	u8	power_mode;
	void __iomem *sdio3_conf_reg;
};

/*
 * These registers are relative to the second register region, for the
 * MBus bridge.
 */
#define SDHCI_WINDOW_CTRL(i)	(0x80 + ((i) << 3))
#define SDHCI_WINDOW_BASE(i)	(0x84 + ((i) << 3))
#define SDHCI_MAX_WIN_NUM	8

/*
 * Fields below belong to SDIO3 Configuration Register (third register
 * region for the Armada 38x flavor)
 */

#define SDIO3_CONF_CLK_INV	BIT(0)
#define SDIO3_CONF_SD_FB_CLK	BIT(2)

static int mv_conf_mbus_windows(struct platform_device *pdev,
				const struct mbus_dram_target_info *dram)
{
	int i;
	void __iomem *regs;
	struct resource *res;

	if (!dram) {
		dev_err(&pdev->dev, "no mbus dram info\n");
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		dev_err(&pdev->dev, "cannot get mbus registers\n");
		return -EINVAL;
	}

	regs = ioremap(res->start, resource_size(res));
	if (!regs) {
		dev_err(&pdev->dev, "cannot map mbus registers\n");
		return -ENOMEM;
	}

	for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
		writel(0, regs + SDHCI_WINDOW_CTRL(i));
		writel(0, regs + SDHCI_WINDOW_BASE(i));
	}

	for (i = 0; i < dram->num_cs; i++) {
		const struct mbus_dram_window *cs = dram->cs + i;

		/* Write size, attributes and target id to control register */
		writel(((cs->size - 1) & 0xffff0000) |
			(cs->mbus_attr << 8) |
			(dram->mbus_dram_target_id << 4) | 1,
			regs + SDHCI_WINDOW_CTRL(i));
		/* Write base address to base register */
		writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
	}

	iounmap(regs);

	return 0;
}

static int armada_38x_quirks(struct platform_device *pdev,
			     struct sdhci_host *host)
{
	struct device_node *np = pdev->dev.of_node;
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;
	struct resource *res;

	host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
					   "conf-sdio3");
	if (res) {
		pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(pxa->sdio3_conf_reg))
			return PTR_ERR(pxa->sdio3_conf_reg);
	} else {
		/*
		 * According to erratum 'FE-2946959' both SDR50 and DDR50
		 * modes require specific clock adjustments in SDIO3
		 * Configuration register, if the adjustment is not done,
		 * remove them from the capabilities.
		 */
		host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
		host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);

		dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n");
	}

	/*
	 * According to erratum 'ERR-7878951' Armada 38x SDHCI
	 * controller has different capabilities than the ones shown
	 * in its registers
	 */
	host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
	if (of_property_read_bool(np, "no-1-8-v")) {
		host->caps &= ~SDHCI_CAN_VDD_180;
		host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
	} else {
		host->caps &= ~SDHCI_CAN_VDD_330;
	}
	host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);

	return 0;
}

static void pxav3_reset(struct sdhci_host *host, u8 mask)
{
	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;

	sdhci_reset(host, mask);

	if (mask == SDHCI_RESET_ALL) {
		/*
		 * tune timing of read data/command when crc error happen
		 * no performance impact
		 */
		if (pdata && 0 != pdata->clk_delay_cycles) {
			u16 tmp;

			tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
			tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
				<< SDCLK_DELAY_SHIFT;
			tmp |= SDCLK_SEL;
			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
		}
	}
}

#define MAX_WAIT_COUNT 5
static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;
	u16 tmp;
	int count;

	if (pxa->power_mode == MMC_POWER_UP
			&& power_mode == MMC_POWER_ON) {

		dev_dbg(mmc_dev(host->mmc),
				"%s: slot->power_mode = %d,"
				"ios->power_mode = %d\n",
				__func__,
				pxa->power_mode,
				power_mode);

		/* set we want notice of when 74 clocks are sent */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT_EN;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);

		/* start sending the 74 clocks */
		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
		tmp |= SDCFG_GEN_PAD_CLK_ON;
		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);

		/* slowest speed is about 100KHz or 10usec per clock */
		udelay(740);
		count = 0;

		while (count++ < MAX_WAIT_COUNT) {
			if ((readw(host->ioaddr + SD_CE_ATA_2)
						& SDCE_MISC_INT) == 0)
				break;
			udelay(10);
		}

		if (count == MAX_WAIT_COUNT)
			dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");

		/* clear the interrupt bit if posted */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);
	}
	pxa->power_mode = power_mode;
}

static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;
	u16 ctrl_2;

	/*
	 * Set V18_EN -- UHS modes do not work without this.
	 * does not change signaling voltage
	 */
	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);

	/* Select Bus Speed Mode for host */
	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	switch (uhs) {
	case MMC_TIMING_UHS_SDR12:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
		break;
	case MMC_TIMING_UHS_SDR25:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
		break;
	case MMC_TIMING_UHS_SDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_SDR104:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_MMC_DDR52:
	case MMC_TIMING_UHS_DDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
		break;
	}

	/*
	 * Update SDIO3 Configuration register according to erratum
	 * FE-2946959
	 */
	if (pxa->sdio3_conf_reg) {
		u8 reg_val  = readb(pxa->sdio3_conf_reg);

		if (uhs == MMC_TIMING_UHS_SDR50 ||
		    uhs == MMC_TIMING_UHS_DDR50) {
			reg_val &= ~SDIO3_CONF_CLK_INV;
			reg_val |= SDIO3_CONF_SD_FB_CLK;
		} else {
			reg_val |= SDIO3_CONF_CLK_INV;
			reg_val &= ~SDIO3_CONF_SD_FB_CLK;
		}
		writeb(reg_val, pxa->sdio3_conf_reg);
	}

	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	dev_dbg(mmc_dev(host->mmc),
		"%s uhs = %d, ctrl_2 = %04X\n",
		__func__, uhs, ctrl_2);
}

static const struct sdhci_ops pxav3_sdhci_ops = {
	.set_clock = sdhci_set_clock,
	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
	.set_bus_width = sdhci_set_bus_width,
	.reset = pxav3_reset,
	.set_uhs_signaling = pxav3_set_uhs_signaling,
};

static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
		| SDHCI_QUIRK_32BIT_ADMA_SIZE
		| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops = &pxav3_sdhci_ops,
};

#ifdef CONFIG_OF
static const struct of_device_id sdhci_pxav3_of_match[] = {
	{
		.compatible = "mrvl,pxav3-mmc",
	},
	{
		.compatible = "marvell,armada-380-sdhci",
	},
	{},
};
MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);

static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	struct sdhci_pxa_platdata *pdata;
	struct device_node *np = dev->of_node;
	u32 clk_delay_cycles;

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;

	if (!of_property_read_u32(np, "mrvl,clk-delay-cycles",
				  &clk_delay_cycles))
		pdata->clk_delay_cycles = clk_delay_cycles;

	return pdata;
}
#else
static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	return NULL;
}
#endif

static int sdhci_pxav3_probe(struct platform_device *pdev)
{
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	struct device *dev = &pdev->dev;
	struct device_node *np = pdev->dev.of_node;
	struct sdhci_host *host = NULL;
	struct sdhci_pxa *pxa = NULL;
	const struct of_device_id *match;
	int ret;

	pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
	if (!pxa)
		return -ENOMEM;

	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
	if (IS_ERR(host))
		return PTR_ERR(host);

	pltfm_host = sdhci_priv(host);
	pltfm_host->priv = pxa;

	pxa->clk_io = devm_clk_get(dev, "io");
	if (IS_ERR(pxa->clk_io))
		pxa->clk_io = devm_clk_get(dev, NULL);
	if (IS_ERR(pxa->clk_io)) {
		dev_err(dev, "failed to get io clock\n");
		ret = PTR_ERR(pxa->clk_io);
		goto err_clk_get;
	}
	pltfm_host->clk = pxa->clk_io;
	clk_prepare_enable(pxa->clk_io);

	pxa->clk_core = devm_clk_get(dev, "core");
	if (!IS_ERR(pxa->clk_core))
		clk_prepare_enable(pxa->clk_core);

	/* enable 1/8V DDR capable */
	host->mmc->caps |= MMC_CAP_1_8V_DDR;

	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
		ret = armada_38x_quirks(pdev, host);
		if (ret < 0)
			goto err_clk_get;
		ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
		if (ret < 0)
			goto err_mbus_win;
	}

	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
	if (match) {
		ret = mmc_of_parse(host->mmc);
		if (ret)
			goto err_of_parse;
		sdhci_get_of_property(pdev);
		pdata = pxav3_get_mmc_pdata(dev);
		pdev->dev.platform_data = pdata;
	} else if (pdata) {
		/* on-chip device */
		if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
			host->mmc->caps |= MMC_CAP_NONREMOVABLE;

		/* If slot design supports 8 bit data, indicate this to MMC. */
		if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
			host->mmc->caps |= MMC_CAP_8_BIT_DATA;

		if (pdata->quirks)
			host->quirks |= pdata->quirks;
		if (pdata->quirks2)
			host->quirks2 |= pdata->quirks2;
		if (pdata->host_caps)
			host->mmc->caps |= pdata->host_caps;
		if (pdata->host_caps2)
			host->mmc->caps2 |= pdata->host_caps2;
		if (pdata->pm_caps)
			host->mmc->pm_caps |= pdata->pm_caps;

		if (gpio_is_valid(pdata->ext_cd_gpio)) {
			ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
						  0);
			if (ret) {
				dev_err(mmc_dev(host->mmc),
					"failed to allocate card detect gpio\n");
				goto err_cd_req;
			}
		}
	}

	pm_runtime_get_noresume(&pdev->dev);
	pm_runtime_set_active(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_enable(&pdev->dev);
	pm_suspend_ignore_children(&pdev->dev, 1);

	ret = sdhci_add_host(host);
	if (ret) {
		dev_err(&pdev->dev, "failed to add host\n");
		goto err_add_host;
	}

	platform_set_drvdata(pdev, host);

	if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)
		device_init_wakeup(&pdev->dev, 1);

	pm_runtime_put_autosuspend(&pdev->dev);

	return 0;

err_add_host:
	pm_runtime_disable(&pdev->dev);
	pm_runtime_put_noidle(&pdev->dev);
err_of_parse:
err_cd_req:
err_mbus_win:
	clk_disable_unprepare(pxa->clk_io);
	clk_disable_unprepare(pxa->clk_core);
err_clk_get:
	sdhci_pltfm_free(pdev);
	return ret;
}

static int sdhci_pxav3_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;

	pm_runtime_get_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	pm_runtime_put_noidle(&pdev->dev);

	sdhci_remove_host(host, 1);

	clk_disable_unprepare(pxa->clk_io);
	clk_disable_unprepare(pxa->clk_core);

	sdhci_pltfm_free(pdev);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int sdhci_pxav3_suspend(struct device *dev)
{
	int ret;
	struct sdhci_host *host = dev_get_drvdata(dev);

	pm_runtime_get_sync(dev);
	ret = sdhci_suspend_host(host);
	pm_runtime_mark_last_busy(dev);
	pm_runtime_put_autosuspend(dev);

	return ret;
}

static int sdhci_pxav3_resume(struct device *dev)
{
	int ret;
	struct sdhci_host *host = dev_get_drvdata(dev);

	pm_runtime_get_sync(dev);
	ret = sdhci_resume_host(host);
	pm_runtime_mark_last_busy(dev);
	pm_runtime_put_autosuspend(dev);

	return ret;
}
#endif

#ifdef CONFIG_PM
static int sdhci_pxav3_runtime_suspend(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;
	int ret;

	ret = sdhci_runtime_suspend_host(host);
	if (ret)
		return ret;

	clk_disable_unprepare(pxa->clk_io);
	if (!IS_ERR(pxa->clk_core))
		clk_disable_unprepare(pxa->clk_core);

	return 0;
}

static int sdhci_pxav3_runtime_resume(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;

	clk_prepare_enable(pxa->clk_io);
	if (!IS_ERR(pxa->clk_core))
		clk_prepare_enable(pxa->clk_core);

	return sdhci_runtime_resume_host(host);
}
#endif

#ifdef CONFIG_PM
static const struct dev_pm_ops sdhci_pxav3_pmops = {
	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
	SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
		sdhci_pxav3_runtime_resume, NULL)
};

#define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)

#else
#define SDHCI_PXAV3_PMOPS NULL
#endif

static struct platform_driver sdhci_pxav3_driver = {
	.driver		= {
		.name	= "sdhci-pxav3",
		.of_match_table = of_match_ptr(sdhci_pxav3_of_match),
		.pm	= SDHCI_PXAV3_PMOPS,
	},
	.probe		= sdhci_pxav3_probe,
	.remove		= sdhci_pxav3_remove,
};

module_platform_driver(sdhci_pxav3_driver);

MODULE_DESCRIPTION("SDHCI driver for pxav3");
MODULE_AUTHOR("Marvell International Ltd.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a702c8ab ZG	1	/*
	2	* Copyright (C) 2010 Marvell International Ltd.
	3	* Zhangfei Gao <zhangfei.gao@marvell.com>
	4	* Kevin Wang <dwang4@marvell.com>
	5	* Mingwei Wang <mwwang@marvell.com>
	6	* Philip Rakity <prakity@marvell.com>
	7	* Mark Brown <markb@marvell.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19	#include <linux/err.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/clk.h>
	23	#include <linux/io.h>
	24	#include <linux/gpio.h>
	25	#include <linux/mmc/card.h>
	26	#include <linux/mmc/host.h>
8f63795c	27	#include <linux/mmc/slot-gpio.h>
bfed345e	28	#include <linux/platform_data/pxa_sdhci.h>
a702c8ab ZG	29	#include <linux/slab.h>
a702c8ab ZG	30	#include <linux/delay.h>
88b47679	31	#include <linux/module.h>
b650352d CB	32	#include <linux/of.h>
b650352d CB	33	#include <linux/of_device.h>
8f63795c	34	#include <linux/of_gpio.h>
bb691ae4 KL	35	#include <linux/pm.h>
bb691ae4 KL	36	#include <linux/pm_runtime.h>
5491ce3f	37	#include <linux/mbus.h>
b650352d	38
a702c8ab ZG	39	#include "sdhci.h"
	40	#include "sdhci-pltfm.h"
	41
bb691ae4 KL	42	#define PXAV3_RPM_DELAY_MS 50
bb691ae4 KL	43
a702c8ab ZG	44	#define SD_CLOCK_BURST_SIZE_SETUP 0x10A
	45	#define SDCLK_SEL 0x100
	46	#define SDCLK_DELAY_SHIFT 9
	47	#define SDCLK_DELAY_MASK 0x1f
	48
	49	#define SD_CFG_FIFO_PARAM 0x100
	50	#define SDCFG_GEN_PAD_CLK_ON (1<<6)
	51	#define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
	52	#define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
	53
	54	#define SD_SPI_MODE 0x108
	55	#define SD_CE_ATA_1 0x10C
	56
	57	#define SD_CE_ATA_2 0x10E
	58	#define SDCE_MISC_INT (1<<2)
	59	#define SDCE_MISC_INT_EN (1<<1)
	60
cc9571e8	61	struct sdhci_pxa {
8afdc9cc	62	struct clk *clk_core;
8c96a7a3	63	struct clk *clk_io;
cc9571e8	64	u8 power_mode;
1140011e	65	void __iomem *sdio3_conf_reg;
cc9571e8 SH	66	};
cc9571e8 SH	67
5491ce3f MW	68	/*
	69	* These registers are relative to the second register region, for the
	70	* MBus bridge.
	71	*/
	72	#define SDHCI_WINDOW_CTRL(i) (0x80 + ((i) << 3))
	73	#define SDHCI_WINDOW_BASE(i) (0x84 + ((i) << 3))
	74	#define SDHCI_MAX_WIN_NUM 8
	75
1140011e MW	76	/*
	77	* Fields below belong to SDIO3 Configuration Register (third register
	78	* region for the Armada 38x flavor)
	79	*/
	80
	81	#define SDIO3_CONF_CLK_INV BIT(0)
	82	#define SDIO3_CONF_SD_FB_CLK BIT(2)
	83
5491ce3f MW	84	static int mv_conf_mbus_windows(struct platform_device *pdev,
	85	const struct mbus_dram_target_info *dram)
	86	{
	87	int i;
	88	void __iomem *regs;
	89	struct resource *res;
	90
	91	if (!dram) {
	92	dev_err(&pdev->dev, "no mbus dram info\n");
	93	return -EINVAL;
	94	}
	95
	96	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	97	if (!res) {
	98	dev_err(&pdev->dev, "cannot get mbus registers\n");
	99	return -EINVAL;
	100	}
	101
	102	regs = ioremap(res->start, resource_size(res));
	103	if (!regs) {
	104	dev_err(&pdev->dev, "cannot map mbus registers\n");
	105	return -ENOMEM;
	106	}
	107
	108	for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
	109	writel(0, regs + SDHCI_WINDOW_CTRL(i));
	110	writel(0, regs + SDHCI_WINDOW_BASE(i));
	111	}
	112
	113	for (i = 0; i < dram->num_cs; i++) {
	114	const struct mbus_dram_window *cs = dram->cs + i;
	115
	116	/* Write size, attributes and target id to control register */
	117	writel(((cs->size - 1) & 0xffff0000) \|
	118	(cs->mbus_attr << 8) \|
	119	(dram->mbus_dram_target_id << 4) \| 1,
	120	regs + SDHCI_WINDOW_CTRL(i));
	121	/* Write base address to base register */
	122	writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
	123	}
	124
	125	iounmap(regs);
	126
	127	return 0;
	128	}
	129
a39128bc MW	130	static int armada_38x_quirks(struct platform_device *pdev,
a39128bc MW	131	struct sdhci_host *host)
d4b803c5	132	{
a39128bc	133	struct device_node *np = pdev->dev.of_node;
1140011e MW	134	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	135	struct sdhci_pxa *pxa = pltfm_host->priv;
	136	struct resource *res;
a39128bc	137
d4b803c5	138	host->quirks \|= SDHCI_QUIRK_MISSING_CAPS;
1140011e MW	139	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
	140	"conf-sdio3");
	141	if (res) {
	142	pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res);
	143	if (IS_ERR(pxa->sdio3_conf_reg))
	144	return PTR_ERR(pxa->sdio3_conf_reg);
	145	} else {
	146	/*
	147	* According to erratum 'FE-2946959' both SDR50 and DDR50
	148	* modes require specific clock adjustments in SDIO3
	149	* Configuration register, if the adjustment is not done,
	150	* remove them from the capabilities.
	151	*/
	152	host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
	153	host->caps1 &= ~(SDHCI_SUPPORT_SDR50 \| SDHCI_SUPPORT_DDR50);
	154
	155	dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n");
	156	}
a39128bc MW	157
	158	/*
	159	* According to erratum 'ERR-7878951' Armada 38x SDHCI
	160	* controller has different capabilities than the ones shown
	161	* in its registers
	162	*/
	163	host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
	164	if (of_property_read_bool(np, "no-1-8-v")) {
	165	host->caps &= ~SDHCI_CAN_VDD_180;
	166	host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
	167	} else {
	168	host->caps &= ~SDHCI_CAN_VDD_330;
	169	}
	170	host->caps1 &= ~(SDHCI_SUPPORT_SDR104 \| SDHCI_USE_SDR50_TUNING);
	171
d4b803c5 GC	172	return 0;
	173	}
	174
03231f9b	175	static void pxav3_reset(struct sdhci_host *host, u8 mask)
a702c8ab ZG	176	{
	177	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	178	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	179
03231f9b RK	180	sdhci_reset(host, mask);
03231f9b RK	181
a702c8ab ZG	182	if (mask == SDHCI_RESET_ALL) {
	183	/*
	184	* tune timing of read data/command when crc error happen
	185	* no performance impact
	186	*/
	187	if (pdata && 0 != pdata->clk_delay_cycles) {
	188	u16 tmp;
	189
	190	tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	191	tmp \|= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
	192	<< SDCLK_DELAY_SHIFT;
	193	tmp \|= SDCLK_SEL;
	194	writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	195	}
	196	}
	197	}
	198
	199	#define MAX_WAIT_COUNT 5
	200	static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
	201	{
	202	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	203	struct sdhci_pxa *pxa = pltfm_host->priv;
	204	u16 tmp;
	205	int count;
	206
	207	if (pxa->power_mode == MMC_POWER_UP
	208	&& power_mode == MMC_POWER_ON) {
	209
	210	dev_dbg(mmc_dev(host->mmc),
	211	"%s: slot->power_mode = %d,"
	212	"ios->power_mode = %d\n",
	213	__func__,
	214	pxa->power_mode,
	215	power_mode);
	216
	217	/* set we want notice of when 74 clocks are sent */
	218	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	219	tmp \|= SDCE_MISC_INT_EN;
	220	writew(tmp, host->ioaddr + SD_CE_ATA_2);
	221
	222	/* start sending the 74 clocks */
	223	tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
	224	tmp \|= SDCFG_GEN_PAD_CLK_ON;
	225	writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
	226
	227	/* slowest speed is about 100KHz or 10usec per clock */
	228	udelay(740);
	229	count = 0;
	230
	231	while (count++ < MAX_WAIT_COUNT) {
	232	if ((readw(host->ioaddr + SD_CE_ATA_2)
	233	& SDCE_MISC_INT) == 0)
	234	break;
	235	udelay(10);
	236	}
	237
	238	if (count == MAX_WAIT_COUNT)
	239	dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
	240
	241	/* clear the interrupt bit if posted */
	242	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	243	tmp \|= SDCE_MISC_INT;
	244	writew(tmp, host->ioaddr + SD_CE_ATA_2);
	245	}
246	pxa->power_mode = power_mode;
247	}
248
13e64501	249	static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
a702c8ab	250	{
1140011e MW	251	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1140011e MW	252	struct sdhci_pxa *pxa = pltfm_host->priv;
a702c8ab ZG	253	u16 ctrl_2;
	254
	255	/*
	256	* Set V18_EN -- UHS modes do not work without this.
	257	* does not change signaling voltage
	258	*/
	259	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	260
	261	/* Select Bus Speed Mode for host */
	262	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	263	switch (uhs) {
	264	case MMC_TIMING_UHS_SDR12:
	265	ctrl_2 \|= SDHCI_CTRL_UHS_SDR12;
	266	break;
	267	case MMC_TIMING_UHS_SDR25:
	268	ctrl_2 \|= SDHCI_CTRL_UHS_SDR25;
	269	break;
	270	case MMC_TIMING_UHS_SDR50:
	271	ctrl_2 \|= SDHCI_CTRL_UHS_SDR50 \| SDHCI_CTRL_VDD_180;
	272	break;
	273	case MMC_TIMING_UHS_SDR104:
	274	ctrl_2 \|= SDHCI_CTRL_UHS_SDR104 \| SDHCI_CTRL_VDD_180;
	275	break;
668e84b2	276	case MMC_TIMING_MMC_DDR52:
a702c8ab ZG	277	case MMC_TIMING_UHS_DDR50:
	278	ctrl_2 \|= SDHCI_CTRL_UHS_DDR50 \| SDHCI_CTRL_VDD_180;
	279	break;
	280	}
	281
1140011e MW	282	/*
	283	* Update SDIO3 Configuration register according to erratum
	284	* FE-2946959
	285	*/
	286	if (pxa->sdio3_conf_reg) {
	287	u8 reg_val = readb(pxa->sdio3_conf_reg);
	288
	289	if (uhs == MMC_TIMING_UHS_SDR50 \|\|
	290	uhs == MMC_TIMING_UHS_DDR50) {
	291	reg_val &= ~SDIO3_CONF_CLK_INV;
	292	reg_val \|= SDIO3_CONF_SD_FB_CLK;
	293	} else {
	294	reg_val \|= SDIO3_CONF_CLK_INV;
	295	reg_val &= ~SDIO3_CONF_SD_FB_CLK;
	296	}
	297	writeb(reg_val, pxa->sdio3_conf_reg);
	298	}
	299
a702c8ab ZG	300	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	301	dev_dbg(mmc_dev(host->mmc),
	302	"%s uhs = %d, ctrl_2 = %04X\n",
	303	__func__, uhs, ctrl_2);
a702c8ab ZG	304	}
a702c8ab ZG	305
c915568d	306	static const struct sdhci_ops pxav3_sdhci_ops = {
1771059c	307	.set_clock = sdhci_set_clock,
a702c8ab	308	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
d005d943	309	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
2317f56c	310	.set_bus_width = sdhci_set_bus_width,
03231f9b	311	.reset = pxav3_reset,
b3153765	312	.set_uhs_signaling = pxav3_set_uhs_signaling,
a702c8ab ZG	313	};
a702c8ab ZG	314
73b7afb9	315	static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
e065162a	316	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
73b7afb9 KL	317	\| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
	318	\| SDHCI_QUIRK_32BIT_ADMA_SIZE
	319	\| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	320	.ops = &pxav3_sdhci_ops,
	321	};
	322
b650352d CB	323	#ifdef CONFIG_OF
	324	static const struct of_device_id sdhci_pxav3_of_match[] = {
	325	{
	326	.compatible = "mrvl,pxav3-mmc",
	327	},
5491ce3f MW	328	{
	329	.compatible = "marvell,armada-380-sdhci",
	330	},
b650352d CB	331	{},
	332	};
	333	MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
	334
	335	static struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	336	{
	337	struct sdhci_pxa_platdata *pdata;
	338	struct device_node *np = dev->of_node;
b650352d CB	339	u32 clk_delay_cycles;
	340
	341	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	342	if (!pdata)
	343	return NULL;
	344
14460dba JZ	345	if (!of_property_read_u32(np, "mrvl,clk-delay-cycles",
14460dba JZ	346	&clk_delay_cycles))
b650352d CB	347	pdata->clk_delay_cycles = clk_delay_cycles;
	348
	349	return pdata;
	350	}
	351	#else
	352	static inline struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	353	{
	354	return NULL;
	355	}
	356	#endif
	357
c3be1efd	358	static int sdhci_pxav3_probe(struct platform_device *pdev)
a702c8ab ZG	359	{
	360	struct sdhci_pltfm_host *pltfm_host;
	361	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	362	struct device *dev = &pdev->dev;
5491ce3f	363	struct device_node *np = pdev->dev.of_node;
a702c8ab ZG	364	struct sdhci_host *host = NULL;
a702c8ab ZG	365	struct sdhci_pxa *pxa = NULL;
b650352d	366	const struct of_device_id *match;
a702c8ab	367	int ret;
a702c8ab	368
3df5b281	369	pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
a702c8ab ZG	370	if (!pxa)
	371	return -ENOMEM;
	372
0e748234	373	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
3df5b281	374	if (IS_ERR(host))
a702c8ab	375	return PTR_ERR(host);
5491ce3f	376
a702c8ab ZG	377	pltfm_host = sdhci_priv(host);
	378	pltfm_host->priv = pxa;
	379
01ae1070 SH	380	pxa->clk_io = devm_clk_get(dev, "io");
	381	if (IS_ERR(pxa->clk_io))
	382	pxa->clk_io = devm_clk_get(dev, NULL);
8c96a7a3	383	if (IS_ERR(pxa->clk_io)) {
a702c8ab	384	dev_err(dev, "failed to get io clock\n");
8c96a7a3	385	ret = PTR_ERR(pxa->clk_io);
a702c8ab ZG	386	goto err_clk_get;
a702c8ab ZG	387	}
8c96a7a3 SH	388	pltfm_host->clk = pxa->clk_io;
8c96a7a3 SH	389	clk_prepare_enable(pxa->clk_io);
a702c8ab	390
8afdc9cc SH	391	pxa->clk_core = devm_clk_get(dev, "core");
	392	if (!IS_ERR(pxa->clk_core))
	393	clk_prepare_enable(pxa->clk_core);
	394
a39128bc MW	395	/* enable 1/8V DDR capable */
	396	host->mmc->caps \|= MMC_CAP_1_8V_DDR;
	397
aa8165f9	398	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
a39128bc	399	ret = armada_38x_quirks(pdev, host);
d4b803c5 GC	400	if (ret < 0)
d4b803c5 GC	401	goto err_clk_get;
aa8165f9 TP	402	ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
	403	if (ret < 0)
	404	goto err_mbus_win;
	405	}
	406
b650352d	407	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
943647f6	408	if (match) {
d2cf6071 SB	409	ret = mmc_of_parse(host->mmc);
	410	if (ret)
	411	goto err_of_parse;
943647f6	412	sdhci_get_of_property(pdev);
b650352d	413	pdata = pxav3_get_mmc_pdata(dev);
9cd76049	414	pdev->dev.platform_data = pdata;
943647f6	415	} else if (pdata) {
c844a46f KL	416	/* on-chip device */
c844a46f KL	417	if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
a702c8ab	418	host->mmc->caps \|= MMC_CAP_NONREMOVABLE;
a702c8ab ZG	419
	420	/* If slot design supports 8 bit data, indicate this to MMC. */
	421	if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
	422	host->mmc->caps \|= MMC_CAP_8_BIT_DATA;
	423
	424	if (pdata->quirks)
	425	host->quirks \|= pdata->quirks;
7c52d7bb KL	426	if (pdata->quirks2)
7c52d7bb KL	427	host->quirks2 \|= pdata->quirks2;
a702c8ab ZG	428	if (pdata->host_caps)
a702c8ab ZG	429	host->mmc->caps \|= pdata->host_caps;
8f63795c CB	430	if (pdata->host_caps2)
8f63795c CB	431	host->mmc->caps2 \|= pdata->host_caps2;
a702c8ab ZG	432	if (pdata->pm_caps)
a702c8ab ZG	433	host->mmc->pm_caps \|= pdata->pm_caps;
8f63795c CB	434
8f63795c CB	435	if (gpio_is_valid(pdata->ext_cd_gpio)) {
214fc309 LP	436	ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
214fc309 LP	437	0);
8f63795c CB	438	if (ret) {
	439	dev_err(mmc_dev(host->mmc),
	440	"failed to allocate card detect gpio\n");
	441	goto err_cd_req;
	442	}
	443	}
a702c8ab ZG	444	}
a702c8ab ZG	445
62cf983a JZ	446	pm_runtime_get_noresume(&pdev->dev);
62cf983a JZ	447	pm_runtime_set_active(&pdev->dev);
bb691ae4 KL	448	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
bb691ae4 KL	449	pm_runtime_use_autosuspend(&pdev->dev);
62cf983a	450	pm_runtime_enable(&pdev->dev);
bb691ae4	451	pm_suspend_ignore_children(&pdev->dev, 1);
bb691ae4	452
a702c8ab ZG	453	ret = sdhci_add_host(host);
	454	if (ret) {
	455	dev_err(&pdev->dev, "failed to add host\n");
	456	goto err_add_host;
	457	}
	458
	459	platform_set_drvdata(pdev, host);
	460
83dc9fec	461	if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)
740b7a44	462	device_init_wakeup(&pdev->dev, 1);
740b7a44	463
bb691ae4 KL	464	pm_runtime_put_autosuspend(&pdev->dev);
bb691ae4 KL	465
a702c8ab ZG	466	return 0;
	467
	468	err_add_host:
0dcaa249	469	pm_runtime_disable(&pdev->dev);
62cf983a	470	pm_runtime_put_noidle(&pdev->dev);
87d2163d XW	471	err_of_parse:
87d2163d XW	472	err_cd_req:
aa8165f9	473	err_mbus_win:
8c96a7a3	474	clk_disable_unprepare(pxa->clk_io);
c25d9e1b	475	clk_disable_unprepare(pxa->clk_core);
a702c8ab ZG	476	err_clk_get:
a702c8ab ZG	477	sdhci_pltfm_free(pdev);
a702c8ab ZG	478	return ret;
	479	}
	480
6e0ee714	481	static int sdhci_pxav3_remove(struct platform_device *pdev)
a702c8ab ZG	482	{
	483	struct sdhci_host *host = platform_get_drvdata(pdev);
	484	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
8c96a7a3	485	struct sdhci_pxa *pxa = pltfm_host->priv;
a702c8ab	486
bb691ae4	487	pm_runtime_get_sync(&pdev->dev);
bb691ae4	488	pm_runtime_disable(&pdev->dev);
20f1f2d7 JZ	489	pm_runtime_put_noidle(&pdev->dev);
	490
	491	sdhci_remove_host(host, 1);
a702c8ab	492
8c96a7a3	493	clk_disable_unprepare(pxa->clk_io);
c25d9e1b	494	clk_disable_unprepare(pxa->clk_core);
8f63795c	495
a702c8ab	496	sdhci_pltfm_free(pdev);
a702c8ab	497
a702c8ab ZG	498	return 0;
	499	}
	500
bb691ae4 KL	501	#ifdef CONFIG_PM_SLEEP
	502	static int sdhci_pxav3_suspend(struct device *dev)
	503	{
	504	int ret;
	505	struct sdhci_host *host = dev_get_drvdata(dev);
	506
	507	pm_runtime_get_sync(dev);
	508	ret = sdhci_suspend_host(host);
	509	pm_runtime_mark_last_busy(dev);
	510	pm_runtime_put_autosuspend(dev);
	511
	512	return ret;
	513	}
	514
	515	static int sdhci_pxav3_resume(struct device *dev)
	516	{
	517	int ret;
	518	struct sdhci_host *host = dev_get_drvdata(dev);
	519
	520	pm_runtime_get_sync(dev);
	521	ret = sdhci_resume_host(host);
	522	pm_runtime_mark_last_busy(dev);
	523	pm_runtime_put_autosuspend(dev);
	524
	525	return ret;
	526	}
	527	#endif
	528
162d6f98	529	#ifdef CONFIG_PM
bb691ae4 KL	530	static int sdhci_pxav3_runtime_suspend(struct device *dev)
	531	{
	532	struct sdhci_host *host = dev_get_drvdata(dev);
	533	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
8c96a7a3	534	struct sdhci_pxa *pxa = pltfm_host->priv;
3bb10f60	535	int ret;
bb691ae4	536
3bb10f60 JZ	537	ret = sdhci_runtime_suspend_host(host);
	538	if (ret)
	539	return ret;
bb691ae4	540
8c96a7a3	541	clk_disable_unprepare(pxa->clk_io);
8afdc9cc SH	542	if (!IS_ERR(pxa->clk_core))
8afdc9cc SH	543	clk_disable_unprepare(pxa->clk_core);
bb691ae4 KL	544
	545	return 0;
	546	}
	547
	548	static int sdhci_pxav3_runtime_resume(struct device *dev)
	549	{
	550	struct sdhci_host *host = dev_get_drvdata(dev);
	551	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
8c96a7a3	552	struct sdhci_pxa *pxa = pltfm_host->priv;
bb691ae4	553
8c96a7a3	554	clk_prepare_enable(pxa->clk_io);
8afdc9cc SH	555	if (!IS_ERR(pxa->clk_core))
8afdc9cc SH	556	clk_prepare_enable(pxa->clk_core);
bb691ae4	557
3bb10f60	558	return sdhci_runtime_resume_host(host);
bb691ae4 KL	559	}
	560	#endif
	561
	562	#ifdef CONFIG_PM
	563	static const struct dev_pm_ops sdhci_pxav3_pmops = {
	564	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
	565	SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
	566	sdhci_pxav3_runtime_resume, NULL)
	567	};
	568
	569	#define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
	570
	571	#else
	572	#define SDHCI_PXAV3_PMOPS NULL
	573	#endif
	574
a702c8ab ZG	575	static struct platform_driver sdhci_pxav3_driver = {
	576	.driver = {
	577	.name = "sdhci-pxav3",
59d22309	578	.of_match_table = of_match_ptr(sdhci_pxav3_of_match),
bb691ae4	579	.pm = SDHCI_PXAV3_PMOPS,
a702c8ab ZG	580	},
a702c8ab ZG	581	.probe = sdhci_pxav3_probe,
0433c143	582	.remove = sdhci_pxav3_remove,
a702c8ab	583	};
a702c8ab	584
d1f81a64	585	module_platform_driver(sdhci_pxav3_driver);
a702c8ab ZG	586
	587	MODULE_DESCRIPTION("SDHCI driver for pxav3");
	588	MODULE_AUTHOR("Marvell International Ltd.");
	589	MODULE_LICENSE("GPL v2");
	590