[linux-2.6-block.git] / drivers / mmc / host / sdhci-pxav3.c

/*
 * Copyright (C) 2010 Marvell International Ltd.
 *		Zhangfei Gao <zhangfei.gao@marvell.com>
 *		Kevin Wang <dwang4@marvell.com>
 *		Mingwei Wang <mwwang@marvell.com>
 *		Philip Rakity <prakity@marvell.com>
 *		Mark Brown <markb@marvell.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/platform_data/pxa_sdhci.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>

#include "sdhci.h"
#include "sdhci-pltfm.h"

#define SD_CLOCK_BURST_SIZE_SETUP		0x10A
#define SDCLK_SEL	0x100
#define SDCLK_DELAY_SHIFT	9
#define SDCLK_DELAY_MASK	0x1f

#define SD_CFG_FIFO_PARAM       0x100
#define SDCFG_GEN_PAD_CLK_ON	(1<<6)
#define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
#define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24

#define SD_SPI_MODE          0x108
#define SD_CE_ATA_1          0x10C

#define SD_CE_ATA_2          0x10E
#define SDCE_MISC_INT		(1<<2)
#define SDCE_MISC_INT_EN	(1<<1)

static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
{
	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;

	if (mask == SDHCI_RESET_ALL) {
		/*
		 * tune timing of read data/command when crc error happen
		 * no performance impact
		 */
		if (pdata && 0 != pdata->clk_delay_cycles) {
			u16 tmp;

			tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
			tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
				<< SDCLK_DELAY_SHIFT;
			tmp |= SDCLK_SEL;
			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
		}
	}
}

#define MAX_WAIT_COUNT 5
static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;
	u16 tmp;
	int count;

	if (pxa->power_mode == MMC_POWER_UP
			&& power_mode == MMC_POWER_ON) {

		dev_dbg(mmc_dev(host->mmc),
				"%s: slot->power_mode = %d,"
				"ios->power_mode = %d\n",
				__func__,
				pxa->power_mode,
				power_mode);

		/* set we want notice of when 74 clocks are sent */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT_EN;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);

		/* start sending the 74 clocks */
		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
		tmp |= SDCFG_GEN_PAD_CLK_ON;
		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);

		/* slowest speed is about 100KHz or 10usec per clock */
		udelay(740);
		count = 0;

		while (count++ < MAX_WAIT_COUNT) {
			if ((readw(host->ioaddr + SD_CE_ATA_2)
						& SDCE_MISC_INT) == 0)
				break;
			udelay(10);
		}

		if (count == MAX_WAIT_COUNT)
			dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");

		/* clear the interrupt bit if posted */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);
	}
	pxa->power_mode = power_mode;
}

static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
{
	u16 ctrl_2;

	/*
	 * Set V18_EN -- UHS modes do not work without this.
	 * does not change signaling voltage
	 */
	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);

	/* Select Bus Speed Mode for host */
	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	switch (uhs) {
	case MMC_TIMING_UHS_SDR12:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
		break;
	case MMC_TIMING_UHS_SDR25:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
		break;
	case MMC_TIMING_UHS_SDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_SDR104:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_DDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
		break;
	}

	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	dev_dbg(mmc_dev(host->mmc),
		"%s uhs = %d, ctrl_2 = %04X\n",
		__func__, uhs, ctrl_2);

	return 0;
}

static struct sdhci_ops pxav3_sdhci_ops = {
	.platform_reset_exit = pxav3_set_private_registers,
	.set_uhs_signaling = pxav3_set_uhs_signaling,
	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
};

#ifdef CONFIG_OF
static const struct of_device_id sdhci_pxav3_of_match[] = {
	{
		.compatible = "mrvl,pxav3-mmc",
	},
	{},
};
MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);

static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	struct sdhci_pxa_platdata *pdata;
	struct device_node *np = dev->of_node;
	u32 bus_width;
	u32 clk_delay_cycles;
	enum of_gpio_flags gpio_flags;

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;

	if (of_find_property(np, "non-removable", NULL))
		pdata->flags |= PXA_FLAG_CARD_PERMANENT;

	of_property_read_u32(np, "bus-width", &bus_width);
	if (bus_width == 8)
		pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;

	of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
	if (clk_delay_cycles > 0)
		pdata->clk_delay_cycles = clk_delay_cycles;

	pdata->ext_cd_gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &gpio_flags);
	if (gpio_flags != OF_GPIO_ACTIVE_LOW)
		pdata->host_caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;

	return pdata;
}
#else
static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	return NULL;
}
#endif

static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
{
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	struct device *dev = &pdev->dev;
	struct sdhci_host *host = NULL;
	struct sdhci_pxa *pxa = NULL;
	const struct of_device_id *match;

	int ret;
	struct clk *clk;

	pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
	if (!pxa)
		return -ENOMEM;

	host = sdhci_pltfm_init(pdev, NULL);
	if (IS_ERR(host)) {
		kfree(pxa);
		return PTR_ERR(host);
	}
	pltfm_host = sdhci_priv(host);
	pltfm_host->priv = pxa;

	clk = clk_get(dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(dev, "failed to get io clock\n");
		ret = PTR_ERR(clk);
		goto err_clk_get;
	}
	pltfm_host->clk = clk;
	clk_prepare_enable(clk);

	host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
		| SDHCI_QUIRK_32BIT_ADMA_SIZE;

	/* enable 1/8V DDR capable */
	host->mmc->caps |= MMC_CAP_1_8V_DDR;

	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
	if (match)
		pdata = pxav3_get_mmc_pdata(dev);

	if (pdata) {
		if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
			/* on-chip device */
			host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
			host->mmc->caps |= MMC_CAP_NONREMOVABLE;
		}

		/* If slot design supports 8 bit data, indicate this to MMC. */
		if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
			host->mmc->caps |= MMC_CAP_8_BIT_DATA;

		if (pdata->quirks)
			host->quirks |= pdata->quirks;
		if (pdata->host_caps)
			host->mmc->caps |= pdata->host_caps;
		if (pdata->host_caps2)
			host->mmc->caps2 |= pdata->host_caps2;
		if (pdata->pm_caps)
			host->mmc->pm_caps |= pdata->pm_caps;

		if (gpio_is_valid(pdata->ext_cd_gpio)) {
			ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio);
			if (ret) {
				dev_err(mmc_dev(host->mmc),
					"failed to allocate card detect gpio\n");
				goto err_cd_req;
			}
		}
	}

	host->ops = &pxav3_sdhci_ops;

	sdhci_get_of_property(pdev);

	ret = sdhci_add_host(host);
	if (ret) {
		dev_err(&pdev->dev, "failed to add host\n");
		goto err_add_host;
	}

	platform_set_drvdata(pdev, host);

	return 0;

err_add_host:
	clk_disable_unprepare(clk);
	clk_put(clk);
	mmc_gpio_free_cd(host->mmc);
err_cd_req:
err_clk_get:
	sdhci_pltfm_free(pdev);
	kfree(pxa);
	return ret;
}

static int __devexit sdhci_pxav3_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;

	sdhci_remove_host(host, 1);

	clk_disable_unprepare(pltfm_host->clk);
	clk_put(pltfm_host->clk);

	if (gpio_is_valid(pdata->ext_cd_gpio))
		mmc_gpio_free_cd(host->mmc);

	sdhci_pltfm_free(pdev);
	kfree(pxa);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static struct platform_driver sdhci_pxav3_driver = {
	.driver		= {
		.name	= "sdhci-pxav3",
#ifdef CONFIG_OF
		.of_match_table = sdhci_pxav3_of_match,
#endif
		.owner	= THIS_MODULE,
		.pm	= SDHCI_PLTFM_PMOPS,
	},
	.probe		= sdhci_pxav3_probe,
	.remove		= sdhci_pxav3_remove,
};

module_platform_driver(sdhci_pxav3_driver);

MODULE_DESCRIPTION("SDHCI driver for pxav3");
MODULE_AUTHOR("Marvell International Ltd.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a702c8ab ZG	1	/*
	2	* Copyright (C) 2010 Marvell International Ltd.
	3	* Zhangfei Gao <zhangfei.gao@marvell.com>
	4	* Kevin Wang <dwang4@marvell.com>
	5	* Mingwei Wang <mwwang@marvell.com>
	6	* Philip Rakity <prakity@marvell.com>
	7	* Mark Brown <markb@marvell.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19	#include <linux/err.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/clk.h>
	23	#include <linux/io.h>
	24	#include <linux/gpio.h>
	25	#include <linux/mmc/card.h>
	26	#include <linux/mmc/host.h>
8f63795c	27	#include <linux/mmc/slot-gpio.h>
bfed345e	28	#include <linux/platform_data/pxa_sdhci.h>
a702c8ab ZG	29	#include <linux/slab.h>
a702c8ab ZG	30	#include <linux/delay.h>
88b47679	31	#include <linux/module.h>
b650352d CB	32	#include <linux/of.h>
b650352d CB	33	#include <linux/of_device.h>
8f63795c	34	#include <linux/of_gpio.h>
b650352d	35
a702c8ab ZG	36	#include "sdhci.h"
	37	#include "sdhci-pltfm.h"
	38
	39	#define SD_CLOCK_BURST_SIZE_SETUP 0x10A
	40	#define SDCLK_SEL 0x100
	41	#define SDCLK_DELAY_SHIFT 9
	42	#define SDCLK_DELAY_MASK 0x1f
	43
	44	#define SD_CFG_FIFO_PARAM 0x100
	45	#define SDCFG_GEN_PAD_CLK_ON (1<<6)
	46	#define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
	47	#define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
	48
	49	#define SD_SPI_MODE 0x108
	50	#define SD_CE_ATA_1 0x10C
	51
	52	#define SD_CE_ATA_2 0x10E
	53	#define SDCE_MISC_INT (1<<2)
	54	#define SDCE_MISC_INT_EN (1<<1)
	55
	56	static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
	57	{
	58	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	59	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	60
	61	if (mask == SDHCI_RESET_ALL) {
	62	/*
	63	* tune timing of read data/command when crc error happen
	64	* no performance impact
	65	*/
	66	if (pdata && 0 != pdata->clk_delay_cycles) {
	67	u16 tmp;
	68
	69	tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	70	tmp \|= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
	71	<< SDCLK_DELAY_SHIFT;
	72	tmp \|= SDCLK_SEL;
	73	writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	74	}
	75	}
	76	}
	77
	78	#define MAX_WAIT_COUNT 5
	79	static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
	80	{
	81	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	82	struct sdhci_pxa *pxa = pltfm_host->priv;
	83	u16 tmp;
	84	int count;
	85
	86	if (pxa->power_mode == MMC_POWER_UP
	87	&& power_mode == MMC_POWER_ON) {
	88
	89	dev_dbg(mmc_dev(host->mmc),
	90	"%s: slot->power_mode = %d,"
	91	"ios->power_mode = %d\n",
	92	__func__,
	93	pxa->power_mode,
	94	power_mode);
	95
	96	/* set we want notice of when 74 clocks are sent */
	97	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	98	tmp \|= SDCE_MISC_INT_EN;
	99	writew(tmp, host->ioaddr + SD_CE_ATA_2);
100
101	/* start sending the 74 clocks */
102	tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
103	tmp \|= SDCFG_GEN_PAD_CLK_ON;
104	writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
105
106	/* slowest speed is about 100KHz or 10usec per clock */
107	udelay(740);
108	count = 0;
109
110	while (count++ < MAX_WAIT_COUNT) {
111	if ((readw(host->ioaddr + SD_CE_ATA_2)
112	& SDCE_MISC_INT) == 0)
113	break;
114	udelay(10);
115	}
116
117	if (count == MAX_WAIT_COUNT)
118	dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
119
120	/* clear the interrupt bit if posted */
121	tmp = readw(host->ioaddr + SD_CE_ATA_2);
122	tmp \|= SDCE_MISC_INT;
123	writew(tmp, host->ioaddr + SD_CE_ATA_2);
124	}
125	pxa->power_mode = power_mode;
126	}
127
128	static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
129	{
130	u16 ctrl_2;
131
132	/*
133	* Set V18_EN -- UHS modes do not work without this.
134	* does not change signaling voltage
135	*/
136	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
137
138	/* Select Bus Speed Mode for host */
139	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
140	switch (uhs) {
141	case MMC_TIMING_UHS_SDR12:
142	ctrl_2 \|= SDHCI_CTRL_UHS_SDR12;
143	break;
144	case MMC_TIMING_UHS_SDR25:
145	ctrl_2 \|= SDHCI_CTRL_UHS_SDR25;
146	break;
147	case MMC_TIMING_UHS_SDR50:
148	ctrl_2 \|= SDHCI_CTRL_UHS_SDR50 \| SDHCI_CTRL_VDD_180;
149	break;
150	case MMC_TIMING_UHS_SDR104:
151	ctrl_2 \|= SDHCI_CTRL_UHS_SDR104 \| SDHCI_CTRL_VDD_180;
152	break;
153	case MMC_TIMING_UHS_DDR50:
154	ctrl_2 \|= SDHCI_CTRL_UHS_DDR50 \| SDHCI_CTRL_VDD_180;
155	break;
156	}
157
158	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
159	dev_dbg(mmc_dev(host->mmc),
160	"%s uhs = %d, ctrl_2 = %04X\n",
161	__func__, uhs, ctrl_2);
162
163	return 0;
164	}
165
166	static struct sdhci_ops pxav3_sdhci_ops = {
167	.platform_reset_exit = pxav3_set_private_registers,
168	.set_uhs_signaling = pxav3_set_uhs_signaling,
169	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
170	};
171
b650352d CB	172	#ifdef CONFIG_OF
	173	static const struct of_device_id sdhci_pxav3_of_match[] = {
	174	{
	175	.compatible = "mrvl,pxav3-mmc",
	176	},
	177	{},
	178	};
	179	MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
	180
	181	static struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	182	{
	183	struct sdhci_pxa_platdata *pdata;
	184	struct device_node *np = dev->of_node;
	185	u32 bus_width;
	186	u32 clk_delay_cycles;
8f63795c	187	enum of_gpio_flags gpio_flags;
b650352d CB	188
	189	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	190	if (!pdata)
	191	return NULL;
	192
	193	if (of_find_property(np, "non-removable", NULL))
	194	pdata->flags \|= PXA_FLAG_CARD_PERMANENT;
	195
	196	of_property_read_u32(np, "bus-width", &bus_width);
	197	if (bus_width == 8)
	198	pdata->flags \|= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
	199
	200	of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
	201	if (clk_delay_cycles > 0)
	202	pdata->clk_delay_cycles = clk_delay_cycles;
	203
8f63795c CB	204	pdata->ext_cd_gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &gpio_flags);
	205	if (gpio_flags != OF_GPIO_ACTIVE_LOW)
	206	pdata->host_caps2 \|= MMC_CAP2_CD_ACTIVE_HIGH;
	207
b650352d CB	208	return pdata;
	209	}
	210	#else
	211	static inline struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	212	{
	213	return NULL;
	214	}
	215	#endif
	216
a702c8ab ZG	217	static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
	218	{
	219	struct sdhci_pltfm_host *pltfm_host;
	220	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	221	struct device *dev = &pdev->dev;
	222	struct sdhci_host *host = NULL;
	223	struct sdhci_pxa *pxa = NULL;
b650352d CB	224	const struct of_device_id *match;
b650352d CB	225
a702c8ab ZG	226	int ret;
	227	struct clk *clk;
	228
	229	pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
	230	if (!pxa)
	231	return -ENOMEM;
	232
	233	host = sdhci_pltfm_init(pdev, NULL);
	234	if (IS_ERR(host)) {
	235	kfree(pxa);
	236	return PTR_ERR(host);
	237	}
	238	pltfm_host = sdhci_priv(host);
	239	pltfm_host->priv = pxa;
	240
164378ef	241	clk = clk_get(dev, NULL);
a702c8ab ZG	242	if (IS_ERR(clk)) {
	243	dev_err(dev, "failed to get io clock\n");
	244	ret = PTR_ERR(clk);
	245	goto err_clk_get;
	246	}
	247	pltfm_host->clk = clk;
164378ef	248	clk_prepare_enable(clk);
a702c8ab ZG	249
a702c8ab ZG	250	host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
606a15e4 PR	251	\| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
606a15e4 PR	252	\| SDHCI_QUIRK_32BIT_ADMA_SIZE;
a702c8ab ZG	253
	254	/* enable 1/8V DDR capable */
	255	host->mmc->caps \|= MMC_CAP_1_8V_DDR;
	256
b650352d CB	257	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
	258	if (match)
	259	pdata = pxav3_get_mmc_pdata(dev);
	260
a702c8ab ZG	261	if (pdata) {
	262	if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
	263	/* on-chip device */
	264	host->quirks \|= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
	265	host->mmc->caps \|= MMC_CAP_NONREMOVABLE;
	266	}
	267
	268	/* If slot design supports 8 bit data, indicate this to MMC. */
	269	if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
	270	host->mmc->caps \|= MMC_CAP_8_BIT_DATA;
	271
	272	if (pdata->quirks)
	273	host->quirks \|= pdata->quirks;
	274	if (pdata->host_caps)
	275	host->mmc->caps \|= pdata->host_caps;
8f63795c CB	276	if (pdata->host_caps2)
8f63795c CB	277	host->mmc->caps2 \|= pdata->host_caps2;
a702c8ab ZG	278	if (pdata->pm_caps)
a702c8ab ZG	279	host->mmc->pm_caps \|= pdata->pm_caps;
8f63795c CB	280
	281	if (gpio_is_valid(pdata->ext_cd_gpio)) {
	282	ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio);
	283	if (ret) {
	284	dev_err(mmc_dev(host->mmc),
	285	"failed to allocate card detect gpio\n");
	286	goto err_cd_req;
	287	}
	288	}
a702c8ab ZG	289	}
	290
	291	host->ops = &pxav3_sdhci_ops;
	292
f4f24ade CB	293	sdhci_get_of_property(pdev);
f4f24ade CB	294
a702c8ab ZG	295	ret = sdhci_add_host(host);
	296	if (ret) {
	297	dev_err(&pdev->dev, "failed to add host\n");
	298	goto err_add_host;
	299	}
	300
	301	platform_set_drvdata(pdev, host);
	302
	303	return 0;
	304
	305	err_add_host:
164378ef	306	clk_disable_unprepare(clk);
a702c8ab	307	clk_put(clk);
8f63795c CB	308	mmc_gpio_free_cd(host->mmc);
8f63795c CB	309	err_cd_req:
a702c8ab ZG	310	err_clk_get:
	311	sdhci_pltfm_free(pdev);
	312	kfree(pxa);
	313	return ret;
	314	}
	315
	316	static int __devexit sdhci_pxav3_remove(struct platform_device *pdev)
	317	{
	318	struct sdhci_host *host = platform_get_drvdata(pdev);
	319	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	320	struct sdhci_pxa *pxa = pltfm_host->priv;
8f63795c	321	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
a702c8ab ZG	322
	323	sdhci_remove_host(host, 1);
	324
164378ef	325	clk_disable_unprepare(pltfm_host->clk);
a702c8ab	326	clk_put(pltfm_host->clk);
8f63795c CB	327
	328	if (gpio_is_valid(pdata->ext_cd_gpio))
	329	mmc_gpio_free_cd(host->mmc);
	330
a702c8ab ZG	331	sdhci_pltfm_free(pdev);
	332	kfree(pxa);
	333
	334	platform_set_drvdata(pdev, NULL);
	335
	336	return 0;
	337	}
	338
	339	static struct platform_driver sdhci_pxav3_driver = {
	340	.driver = {
	341	.name = "sdhci-pxav3",
b650352d CB	342	#ifdef CONFIG_OF
	343	.of_match_table = sdhci_pxav3_of_match,
	344	#endif
a702c8ab	345	.owner = THIS_MODULE,
29495aa0	346	.pm = SDHCI_PLTFM_PMOPS,
a702c8ab ZG	347	},
a702c8ab ZG	348	.probe = sdhci_pxav3_probe,
0433c143	349	.remove = sdhci_pxav3_remove,
a702c8ab	350	};
a702c8ab	351
d1f81a64	352	module_platform_driver(sdhci_pxav3_driver);
a702c8ab ZG	353
	354	MODULE_DESCRIPTION("SDHCI driver for pxav3");
	355	MODULE_AUTHOR("Marvell International Ltd.");
	356	MODULE_LICENSE("GPL v2");
	357