[linux-2.6-block.git] / drivers / mmc / host / sdhci-pxav2.c

/*
 * Copyright (C) 2010 Marvell International Ltd.
 *		Zhangfei Gao <zhangfei.gao@marvell.com>
 *		Kevin Wang <dwang4@marvell.com>
 *		Jun Nie <njun@marvell.com>
 *		Qiming Wu <wuqm@marvell.com>
 *		Philip Rakity <prakity@marvell.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/platform_data/pxa_sdhci.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>

#include "sdhci.h"
#include "sdhci-pltfm.h"

#define SD_FIFO_PARAM		0xe0
#define DIS_PAD_SD_CLK_GATE	0x0400 /* Turn on/off Dynamic SD Clock Gating */
#define CLK_GATE_ON		0x0200 /* Disable/enable Clock Gate */
#define CLK_GATE_CTL		0x0100 /* Clock Gate Control */
#define CLK_GATE_SETTING_BITS	(DIS_PAD_SD_CLK_GATE | \
		CLK_GATE_ON | CLK_GATE_CTL)

#define SD_CLOCK_BURST_SIZE_SETUP	0xe6
#define SDCLK_SEL_SHIFT		8
#define SDCLK_SEL_MASK		0x3
#define SDCLK_DELAY_SHIFT	10
#define SDCLK_DELAY_MASK	0x3c

#define SD_CE_ATA_2		0xea
#define MMC_CARD		0x1000
#define MMC_WIDTH		0x0100

static void pxav2_reset(struct sdhci_host *host, u8 mask)
{
	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;

	sdhci_reset(host, mask);

	if (mask == SDHCI_RESET_ALL) {
		u16 tmp = 0;

		/*
		 * tune timing of read data/command when crc error happen
		 * no performance impact
		 */
		if (pdata && pdata->clk_delay_sel == 1) {
			tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);

			tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
			tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
				<< SDCLK_DELAY_SHIFT;
			tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
			tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;

			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
		}

		if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) {
			tmp = readw(host->ioaddr + SD_FIFO_PARAM);
			tmp &= ~CLK_GATE_SETTING_BITS;
			writew(tmp, host->ioaddr + SD_FIFO_PARAM);
		} else {
			tmp = readw(host->ioaddr + SD_FIFO_PARAM);
			tmp &= ~CLK_GATE_SETTING_BITS;
			tmp |= CLK_GATE_SETTING_BITS;
			writew(tmp, host->ioaddr + SD_FIFO_PARAM);
		}
	}
}

static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width)
{
	u8 ctrl;
	u16 tmp;

	ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	if (width == MMC_BUS_WIDTH_8) {
		ctrl &= ~SDHCI_CTRL_4BITBUS;
		tmp |= MMC_CARD | MMC_WIDTH;
	} else {
		tmp &= ~(MMC_CARD | MMC_WIDTH);
		if (width == MMC_BUS_WIDTH_4)
			ctrl |= SDHCI_CTRL_4BITBUS;
		else
			ctrl &= ~SDHCI_CTRL_4BITBUS;
	}
	writew(tmp, host->ioaddr + SD_CE_ATA_2);
	writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
}

static const struct sdhci_ops pxav2_sdhci_ops = {
	.set_clock     = sdhci_set_clock,
	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
	.set_bus_width = pxav2_mmc_set_bus_width,
	.reset         = pxav2_reset,
	.set_uhs_signaling = sdhci_set_uhs_signaling,
};

#ifdef CONFIG_OF
static const struct of_device_id sdhci_pxav2_of_match[] = {
	{
		.compatible = "mrvl,pxav2-mmc",
	},
	{},
};
MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match);

static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
{
	struct sdhci_pxa_platdata *pdata;
	struct device_node *np = dev->of_node;
	u32 bus_width;
	u32 clk_delay_cycles;

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;

	if (of_find_property(np, "non-removable", NULL))
		pdata->flags |= PXA_FLAG_CARD_PERMANENT;

	of_property_read_u32(np, "bus-width", &bus_width);
	if (bus_width == 8)
		pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;

	of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
	if (clk_delay_cycles > 0) {
		pdata->clk_delay_sel = 1;
		pdata->clk_delay_cycles = clk_delay_cycles;
	}

	return pdata;
}
#else
static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
{
	return NULL;
}
#endif

static int sdhci_pxav2_probe(struct platform_device *pdev)
{
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	struct device *dev = &pdev->dev;
	struct sdhci_host *host = NULL;
	const struct of_device_id *match;

	int ret;
	struct clk *clk;

	host = sdhci_pltfm_init(pdev, NULL, 0);
	if (IS_ERR(host))
		return PTR_ERR(host);

	pltfm_host = sdhci_priv(host);

	clk = clk_get(dev, "PXA-SDHCLK");
	if (IS_ERR(clk)) {
		dev_err(dev, "failed to get io clock\n");
		ret = PTR_ERR(clk);
		goto err_clk_get;
	}
	pltfm_host->clk = clk;
	clk_prepare_enable(clk);

	host->quirks = SDHCI_QUIRK_BROKEN_ADMA
		| SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
		| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;

	match = of_match_device(of_match_ptr(sdhci_pxav2_of_match), &pdev->dev);
	if (match) {
		pdata = pxav2_get_mmc_pdata(dev);
	}
	if (pdata) {
		if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
			/* on-chip device */
			host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
			host->mmc->caps |= MMC_CAP_NONREMOVABLE;
		}

		/* If slot design supports 8 bit data, indicate this to MMC. */
		if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
			host->mmc->caps |= MMC_CAP_8_BIT_DATA;

		if (pdata->quirks)
			host->quirks |= pdata->quirks;
		if (pdata->host_caps)
			host->mmc->caps |= pdata->host_caps;
		if (pdata->pm_caps)
			host->mmc->pm_caps |= pdata->pm_caps;
	}

	host->ops = &pxav2_sdhci_ops;

	ret = sdhci_add_host(host);
	if (ret) {
		dev_err(&pdev->dev, "failed to add host\n");
		goto err_add_host;
	}

	platform_set_drvdata(pdev, host);

	return 0;

err_add_host:
	clk_disable_unprepare(clk);
	clk_put(clk);
err_clk_get:
	sdhci_pltfm_free(pdev);
	return ret;
}

static int sdhci_pxav2_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	sdhci_remove_host(host, 1);

	clk_disable_unprepare(pltfm_host->clk);
	clk_put(pltfm_host->clk);
	sdhci_pltfm_free(pdev);

	return 0;
}

static struct platform_driver sdhci_pxav2_driver = {
	.driver		= {
		.name	= "sdhci-pxav2",
		.of_match_table = of_match_ptr(sdhci_pxav2_of_match),
		.pm	= &sdhci_pltfm_pmops,
	},
	.probe		= sdhci_pxav2_probe,
	.remove		= sdhci_pxav2_remove,
};

module_platform_driver(sdhci_pxav2_driver);

MODULE_DESCRIPTION("SDHCI driver for pxav2");
MODULE_AUTHOR("Marvell International Ltd.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9f5d71e4 ZG	1	/*
	2	* Copyright (C) 2010 Marvell International Ltd.
	3	* Zhangfei Gao <zhangfei.gao@marvell.com>
	4	* Kevin Wang <dwang4@marvell.com>
	5	* Jun Nie <njun@marvell.com>
	6	* Qiming Wu <wuqm@marvell.com>
	7	* Philip Rakity <prakity@marvell.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/err.h>
	21	#include <linux/init.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/clk.h>
88b47679	24	#include <linux/module.h>
9f5d71e4 ZG	25	#include <linux/io.h>
	26	#include <linux/gpio.h>
	27	#include <linux/mmc/card.h>
	28	#include <linux/mmc/host.h>
bfed345e	29	#include <linux/platform_data/pxa_sdhci.h>
9f5d71e4	30	#include <linux/slab.h>
b650352d CB	31	#include <linux/of.h>
	32	#include <linux/of_device.h>
	33
9f5d71e4 ZG	34	#include "sdhci.h"
	35	#include "sdhci-pltfm.h"
	36
	37	#define SD_FIFO_PARAM 0xe0
	38	#define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */
	39	#define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */
	40	#define CLK_GATE_CTL 0x0100 /* Clock Gate Control */
	41	#define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE \| \
	42	CLK_GATE_ON \| CLK_GATE_CTL)
	43
	44	#define SD_CLOCK_BURST_SIZE_SETUP 0xe6
	45	#define SDCLK_SEL_SHIFT 8
	46	#define SDCLK_SEL_MASK 0x3
	47	#define SDCLK_DELAY_SHIFT 10
	48	#define SDCLK_DELAY_MASK 0x3c
	49
	50	#define SD_CE_ATA_2 0xea
	51	#define MMC_CARD 0x1000
	52	#define MMC_WIDTH 0x0100
	53
03231f9b	54	static void pxav2_reset(struct sdhci_host *host, u8 mask)
9f5d71e4 ZG	55	{
	56	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	57	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	58
03231f9b RK	59	sdhci_reset(host, mask);
03231f9b RK	60
9f5d71e4 ZG	61	if (mask == SDHCI_RESET_ALL) {
	62	u16 tmp = 0;
	63
	64	/*
	65	* tune timing of read data/command when crc error happen
	66	* no performance impact
	67	*/
329f2237	68	if (pdata && pdata->clk_delay_sel == 1) {
9f5d71e4 ZG	69	tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	70
	71	tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
	72	tmp \|= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
	73	<< SDCLK_DELAY_SHIFT;
	74	tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
	75	tmp \|= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
	76
	77	writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	78	}
	79
329f2237	80	if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) {
9f5d71e4 ZG	81	tmp = readw(host->ioaddr + SD_FIFO_PARAM);
	82	tmp &= ~CLK_GATE_SETTING_BITS;
	83	writew(tmp, host->ioaddr + SD_FIFO_PARAM);
	84	} else {
	85	tmp = readw(host->ioaddr + SD_FIFO_PARAM);
	86	tmp &= ~CLK_GATE_SETTING_BITS;
	87	tmp \|= CLK_GATE_SETTING_BITS;
	88	writew(tmp, host->ioaddr + SD_FIFO_PARAM);
	89	}
	90	}
	91	}
	92
2317f56c	93	static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width)
9f5d71e4 ZG	94	{
	95	u8 ctrl;
	96	u16 tmp;
	97
	98	ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
	99	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	100	if (width == MMC_BUS_WIDTH_8) {
	101	ctrl &= ~SDHCI_CTRL_4BITBUS;
	102	tmp \|= MMC_CARD \| MMC_WIDTH;
	103	} else {
	104	tmp &= ~(MMC_CARD \| MMC_WIDTH);
	105	if (width == MMC_BUS_WIDTH_4)
	106	ctrl \|= SDHCI_CTRL_4BITBUS;
	107	else
	108	ctrl &= ~SDHCI_CTRL_4BITBUS;
	109	}
	110	writew(tmp, host->ioaddr + SD_CE_ATA_2);
	111	writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
9f5d71e4 ZG	112	}
9f5d71e4 ZG	113
c915568d	114	static const struct sdhci_ops pxav2_sdhci_ops = {
1771059c	115	.set_clock = sdhci_set_clock,
d005d943	116	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
2317f56c	117	.set_bus_width = pxav2_mmc_set_bus_width,
03231f9b	118	.reset = pxav2_reset,
96d7b78c	119	.set_uhs_signaling = sdhci_set_uhs_signaling,
9f5d71e4 ZG	120	};
9f5d71e4 ZG	121
b650352d CB	122	#ifdef CONFIG_OF
	123	static const struct of_device_id sdhci_pxav2_of_match[] = {
	124	{
	125	.compatible = "mrvl,pxav2-mmc",
	126	},
	127	{},
	128	};
	129	MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match);
	130
	131	static struct sdhci_pxa_platdata pxav2_get_mmc_pdata(struct device dev)
	132	{
	133	struct sdhci_pxa_platdata *pdata;
	134	struct device_node *np = dev->of_node;
	135	u32 bus_width;
	136	u32 clk_delay_cycles;
	137
	138	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	139	if (!pdata)
	140	return NULL;
	141
	142	if (of_find_property(np, "non-removable", NULL))
	143	pdata->flags \|= PXA_FLAG_CARD_PERMANENT;
	144
	145	of_property_read_u32(np, "bus-width", &bus_width);
	146	if (bus_width == 8)
	147	pdata->flags \|= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
	148
	149	of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
	150	if (clk_delay_cycles > 0) {
	151	pdata->clk_delay_sel = 1;
	152	pdata->clk_delay_cycles = clk_delay_cycles;
	153	}
	154
	155	return pdata;
	156	}
	157	#else
	158	static inline struct sdhci_pxa_platdata pxav2_get_mmc_pdata(struct device dev)
	159	{
	160	return NULL;
	161	}
	162	#endif
	163
c3be1efd	164	static int sdhci_pxav2_probe(struct platform_device *pdev)
9f5d71e4 ZG	165	{
	166	struct sdhci_pltfm_host *pltfm_host;
	167	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	168	struct device *dev = &pdev->dev;
	169	struct sdhci_host *host = NULL;
b650352d CB	170	const struct of_device_id *match;
b650352d CB	171
9f5d71e4 ZG	172	int ret;
	173	struct clk *clk;
	174
0e748234	175	host = sdhci_pltfm_init(pdev, NULL, 0);
6a686c31	176	if (IS_ERR(host))
9f5d71e4	177	return PTR_ERR(host);
6a686c31	178
9f5d71e4	179	pltfm_host = sdhci_priv(host);
9f5d71e4 ZG	180
	181	clk = clk_get(dev, "PXA-SDHCLK");
	182	if (IS_ERR(clk)) {
	183	dev_err(dev, "failed to get io clock\n");
	184	ret = PTR_ERR(clk);
	185	goto err_clk_get;
	186	}
	187	pltfm_host->clk = clk;
164378ef	188	clk_prepare_enable(clk);
9f5d71e4 ZG	189
	190	host->quirks = SDHCI_QUIRK_BROKEN_ADMA
	191	\| SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
	192	\| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
	193
b650352d CB	194	match = of_match_device(of_match_ptr(sdhci_pxav2_of_match), &pdev->dev);
	195	if (match) {
	196	pdata = pxav2_get_mmc_pdata(dev);
	197	}
9f5d71e4 ZG	198	if (pdata) {
	199	if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
	200	/* on-chip device */
	201	host->quirks \|= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
	202	host->mmc->caps \|= MMC_CAP_NONREMOVABLE;
	203	}
	204
	205	/* If slot design supports 8 bit data, indicate this to MMC. */
	206	if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
	207	host->mmc->caps \|= MMC_CAP_8_BIT_DATA;
	208
	209	if (pdata->quirks)
	210	host->quirks \|= pdata->quirks;
	211	if (pdata->host_caps)
	212	host->mmc->caps \|= pdata->host_caps;
	213	if (pdata->pm_caps)
	214	host->mmc->pm_caps \|= pdata->pm_caps;
	215	}
	216
	217	host->ops = &pxav2_sdhci_ops;
	218
	219	ret = sdhci_add_host(host);
	220	if (ret) {
	221	dev_err(&pdev->dev, "failed to add host\n");
	222	goto err_add_host;
	223	}
	224
	225	platform_set_drvdata(pdev, host);
	226
	227	return 0;
	228
	229	err_add_host:
164378ef	230	clk_disable_unprepare(clk);
9f5d71e4 ZG	231	clk_put(clk);
	232	err_clk_get:
	233	sdhci_pltfm_free(pdev);
9f5d71e4 ZG	234	return ret;
	235	}
	236
6e0ee714	237	static int sdhci_pxav2_remove(struct platform_device *pdev)
9f5d71e4 ZG	238	{
	239	struct sdhci_host *host = platform_get_drvdata(pdev);
	240	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
9f5d71e4 ZG	241
	242	sdhci_remove_host(host, 1);
	243
164378ef	244	clk_disable_unprepare(pltfm_host->clk);
9f5d71e4 ZG	245	clk_put(pltfm_host->clk);
9f5d71e4 ZG	246	sdhci_pltfm_free(pdev);
9f5d71e4	247
9f5d71e4 ZG	248	return 0;
	249	}
	250
	251	static struct platform_driver sdhci_pxav2_driver = {
	252	.driver = {
	253	.name = "sdhci-pxav2",
59d22309	254	.of_match_table = of_match_ptr(sdhci_pxav2_of_match),
fa243f64	255	.pm = &sdhci_pltfm_pmops,
9f5d71e4 ZG	256	},
9f5d71e4 ZG	257	.probe = sdhci_pxav2_probe,
0433c143	258	.remove = sdhci_pxav2_remove,
9f5d71e4	259	};
9f5d71e4	260
d1f81a64	261	module_platform_driver(sdhci_pxav2_driver);
9f5d71e4 ZG	262
	263	MODULE_DESCRIPTION("SDHCI driver for pxav2");
	264	MODULE_AUTHOR("Marvell International Ltd.");
	265	MODULE_LICENSE("GPL v2");
	266