Commit | Line | Data |
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95f25efe WS |
1 | /* |
2 | * Freescale eSDHC i.MX controller driver for the platform bus. | |
3 | * | |
4 | * derived from the OF-version. | |
5 | * | |
6 | * Copyright (c) 2010 Pengutronix e.K. | |
7 | * Author: Wolfram Sang <w.sang@pengutronix.de> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/io.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/clk.h> | |
0c6d49ce | 18 | #include <linux/gpio.h> |
66506f76 | 19 | #include <linux/module.h> |
e149860d | 20 | #include <linux/slab.h> |
95f25efe | 21 | #include <linux/mmc/host.h> |
58ac8177 RZ |
22 | #include <linux/mmc/mmc.h> |
23 | #include <linux/mmc/sdio.h> | |
fbe5fdd1 | 24 | #include <linux/mmc/slot-gpio.h> |
abfafc2d SG |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
27 | #include <linux/of_gpio.h> | |
e62d8b8f | 28 | #include <linux/pinctrl/consumer.h> |
82906b13 | 29 | #include <linux/platform_data/mmc-esdhc-imx.h> |
95f25efe WS |
30 | #include "sdhci-pltfm.h" |
31 | #include "sdhci-esdhc.h" | |
32 | ||
60bf6396 | 33 | #define ESDHC_CTRL_D3CD 0x08 |
58ac8177 | 34 | /* VENDOR SPEC register */ |
60bf6396 SG |
35 | #define ESDHC_VENDOR_SPEC 0xc0 |
36 | #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) | |
37 | #define ESDHC_WTMK_LVL 0x44 | |
38 | #define ESDHC_MIX_CTRL 0x48 | |
2a15f981 SG |
39 | #define ESDHC_MIX_CTRL_AC23EN (1 << 7) |
40 | /* Bits 3 and 6 are not SDHCI standard definitions */ | |
41 | #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 | |
58ac8177 | 42 | |
af51079e SH |
43 | /* |
44 | * Our interpretation of the SDHCI_HOST_CONTROL register | |
45 | */ | |
46 | #define ESDHC_CTRL_4BITBUS (0x1 << 1) | |
47 | #define ESDHC_CTRL_8BITBUS (0x2 << 1) | |
48 | #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) | |
49 | ||
97e4ba6a RZ |
50 | /* |
51 | * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: | |
52 | * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, | |
53 | * but bit28 is used as the INT DMA ERR in fsl eSDHC design. | |
54 | * Define this macro DMA error INT for fsl eSDHC | |
55 | */ | |
60bf6396 | 56 | #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) |
97e4ba6a | 57 | |
58ac8177 RZ |
58 | /* |
59 | * The CMDTYPE of the CMD register (offset 0xE) should be set to | |
60 | * "11" when the STOP CMD12 is issued on imx53 to abort one | |
61 | * open ended multi-blk IO. Otherwise the TC INT wouldn't | |
62 | * be generated. | |
63 | * In exact block transfer, the controller doesn't complete the | |
64 | * operations automatically as required at the end of the | |
65 | * transfer and remains on hold if the abort command is not sent. | |
66 | * As a result, the TC flag is not asserted and SW received timeout | |
67 | * exeception. Bit1 of Vendor Spec registor is used to fix it. | |
68 | */ | |
69 | #define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1) | |
e149860d | 70 | |
57ed3314 SG |
71 | enum imx_esdhc_type { |
72 | IMX25_ESDHC, | |
73 | IMX35_ESDHC, | |
74 | IMX51_ESDHC, | |
75 | IMX53_ESDHC, | |
95a2482a | 76 | IMX6Q_USDHC, |
57ed3314 SG |
77 | }; |
78 | ||
e149860d RZ |
79 | struct pltfm_imx_data { |
80 | int flags; | |
81 | u32 scratchpad; | |
57ed3314 | 82 | enum imx_esdhc_type devtype; |
e62d8b8f | 83 | struct pinctrl *pinctrl; |
842afc02 | 84 | struct esdhc_platform_data boarddata; |
52dac615 SH |
85 | struct clk *clk_ipg; |
86 | struct clk *clk_ahb; | |
87 | struct clk *clk_per; | |
e149860d RZ |
88 | }; |
89 | ||
57ed3314 SG |
90 | static struct platform_device_id imx_esdhc_devtype[] = { |
91 | { | |
92 | .name = "sdhci-esdhc-imx25", | |
93 | .driver_data = IMX25_ESDHC, | |
94 | }, { | |
95 | .name = "sdhci-esdhc-imx35", | |
96 | .driver_data = IMX35_ESDHC, | |
97 | }, { | |
98 | .name = "sdhci-esdhc-imx51", | |
99 | .driver_data = IMX51_ESDHC, | |
100 | }, { | |
101 | .name = "sdhci-esdhc-imx53", | |
102 | .driver_data = IMX53_ESDHC, | |
95a2482a SG |
103 | }, { |
104 | .name = "sdhci-usdhc-imx6q", | |
105 | .driver_data = IMX6Q_USDHC, | |
57ed3314 SG |
106 | }, { |
107 | /* sentinel */ | |
108 | } | |
109 | }; | |
110 | MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); | |
111 | ||
abfafc2d SG |
112 | static const struct of_device_id imx_esdhc_dt_ids[] = { |
113 | { .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], }, | |
114 | { .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], }, | |
115 | { .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], }, | |
116 | { .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], }, | |
95a2482a | 117 | { .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], }, |
abfafc2d SG |
118 | { /* sentinel */ } |
119 | }; | |
120 | MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); | |
121 | ||
57ed3314 SG |
122 | static inline int is_imx25_esdhc(struct pltfm_imx_data *data) |
123 | { | |
124 | return data->devtype == IMX25_ESDHC; | |
125 | } | |
126 | ||
127 | static inline int is_imx35_esdhc(struct pltfm_imx_data *data) | |
128 | { | |
129 | return data->devtype == IMX35_ESDHC; | |
130 | } | |
131 | ||
132 | static inline int is_imx51_esdhc(struct pltfm_imx_data *data) | |
133 | { | |
134 | return data->devtype == IMX51_ESDHC; | |
135 | } | |
136 | ||
137 | static inline int is_imx53_esdhc(struct pltfm_imx_data *data) | |
138 | { | |
139 | return data->devtype == IMX53_ESDHC; | |
140 | } | |
141 | ||
95a2482a SG |
142 | static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) |
143 | { | |
144 | return data->devtype == IMX6Q_USDHC; | |
145 | } | |
146 | ||
95f25efe WS |
147 | static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) |
148 | { | |
149 | void __iomem *base = host->ioaddr + (reg & ~0x3); | |
150 | u32 shift = (reg & 0x3) * 8; | |
151 | ||
152 | writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); | |
153 | } | |
154 | ||
7e29c306 WS |
155 | static u32 esdhc_readl_le(struct sdhci_host *host, int reg) |
156 | { | |
7e29c306 WS |
157 | u32 val = readl(host->ioaddr + reg); |
158 | ||
97e4ba6a RZ |
159 | if (unlikely(reg == SDHCI_CAPABILITIES)) { |
160 | /* In FSL esdhc IC module, only bit20 is used to indicate the | |
161 | * ADMA2 capability of esdhc, but this bit is messed up on | |
162 | * some SOCs (e.g. on MX25, MX35 this bit is set, but they | |
163 | * don't actually support ADMA2). So set the BROKEN_ADMA | |
164 | * uirk on MX25/35 platforms. | |
165 | */ | |
166 | ||
167 | if (val & SDHCI_CAN_DO_ADMA1) { | |
168 | val &= ~SDHCI_CAN_DO_ADMA1; | |
169 | val |= SDHCI_CAN_DO_ADMA2; | |
170 | } | |
171 | } | |
172 | ||
173 | if (unlikely(reg == SDHCI_INT_STATUS)) { | |
60bf6396 SG |
174 | if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { |
175 | val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; | |
97e4ba6a RZ |
176 | val |= SDHCI_INT_ADMA_ERROR; |
177 | } | |
178 | } | |
179 | ||
7e29c306 WS |
180 | return val; |
181 | } | |
182 | ||
183 | static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) | |
184 | { | |
e149860d RZ |
185 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
186 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
0d58864b TL |
187 | u32 data; |
188 | ||
189 | if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { | |
0d58864b TL |
190 | if (val & SDHCI_INT_CARD_INT) { |
191 | /* | |
192 | * Clear and then set D3CD bit to avoid missing the | |
193 | * card interrupt. This is a eSDHC controller problem | |
194 | * so we need to apply the following workaround: clear | |
195 | * and set D3CD bit will make eSDHC re-sample the card | |
196 | * interrupt. In case a card interrupt was lost, | |
197 | * re-sample it by the following steps. | |
198 | */ | |
199 | data = readl(host->ioaddr + SDHCI_HOST_CONTROL); | |
60bf6396 | 200 | data &= ~ESDHC_CTRL_D3CD; |
0d58864b | 201 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
60bf6396 | 202 | data |= ESDHC_CTRL_D3CD; |
0d58864b TL |
203 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
204 | } | |
205 | } | |
7e29c306 | 206 | |
58ac8177 RZ |
207 | if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
208 | && (reg == SDHCI_INT_STATUS) | |
209 | && (val & SDHCI_INT_DATA_END))) { | |
210 | u32 v; | |
60bf6396 SG |
211 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
212 | v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; | |
213 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | |
58ac8177 RZ |
214 | } |
215 | ||
97e4ba6a RZ |
216 | if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { |
217 | if (val & SDHCI_INT_ADMA_ERROR) { | |
218 | val &= ~SDHCI_INT_ADMA_ERROR; | |
60bf6396 | 219 | val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; |
97e4ba6a RZ |
220 | } |
221 | } | |
222 | ||
7e29c306 WS |
223 | writel(val, host->ioaddr + reg); |
224 | } | |
225 | ||
95f25efe WS |
226 | static u16 esdhc_readw_le(struct sdhci_host *host, int reg) |
227 | { | |
ef4d0888 SG |
228 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
229 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
230 | ||
95a2482a | 231 | if (unlikely(reg == SDHCI_HOST_VERSION)) { |
ef4d0888 SG |
232 | reg ^= 2; |
233 | if (is_imx6q_usdhc(imx_data)) { | |
234 | /* | |
235 | * The usdhc register returns a wrong host version. | |
236 | * Correct it here. | |
237 | */ | |
238 | return SDHCI_SPEC_300; | |
239 | } | |
95a2482a | 240 | } |
95f25efe WS |
241 | |
242 | return readw(host->ioaddr + reg); | |
243 | } | |
244 | ||
245 | static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) | |
246 | { | |
247 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
e149860d | 248 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
95f25efe WS |
249 | |
250 | switch (reg) { | |
251 | case SDHCI_TRANSFER_MODE: | |
58ac8177 RZ |
252 | if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
253 | && (host->cmd->opcode == SD_IO_RW_EXTENDED) | |
254 | && (host->cmd->data->blocks > 1) | |
255 | && (host->cmd->data->flags & MMC_DATA_READ)) { | |
256 | u32 v; | |
60bf6396 SG |
257 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
258 | v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; | |
259 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | |
58ac8177 | 260 | } |
69f54698 SG |
261 | |
262 | if (is_imx6q_usdhc(imx_data)) { | |
263 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
2a15f981 SG |
264 | /* Swap AC23 bit */ |
265 | if (val & SDHCI_TRNS_AUTO_CMD23) { | |
266 | val &= ~SDHCI_TRNS_AUTO_CMD23; | |
267 | val |= ESDHC_MIX_CTRL_AC23EN; | |
268 | } | |
269 | m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); | |
69f54698 SG |
270 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); |
271 | } else { | |
272 | /* | |
273 | * Postpone this write, we must do it together with a | |
274 | * command write that is down below. | |
275 | */ | |
276 | imx_data->scratchpad = val; | |
277 | } | |
95f25efe WS |
278 | return; |
279 | case SDHCI_COMMAND: | |
5b6b0ad6 SH |
280 | if ((host->cmd->opcode == MMC_STOP_TRANSMISSION || |
281 | host->cmd->opcode == MMC_SET_BLOCK_COUNT) && | |
282 | (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) | |
58ac8177 | 283 | val |= SDHCI_CMD_ABORTCMD; |
95a2482a | 284 | |
69f54698 | 285 | if (is_imx6q_usdhc(imx_data)) |
95a2482a SG |
286 | writel(val << 16, |
287 | host->ioaddr + SDHCI_TRANSFER_MODE); | |
69f54698 | 288 | else |
95a2482a SG |
289 | writel(val << 16 | imx_data->scratchpad, |
290 | host->ioaddr + SDHCI_TRANSFER_MODE); | |
95f25efe WS |
291 | return; |
292 | case SDHCI_BLOCK_SIZE: | |
293 | val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); | |
294 | break; | |
295 | } | |
296 | esdhc_clrset_le(host, 0xffff, val, reg); | |
297 | } | |
298 | ||
299 | static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) | |
300 | { | |
9a0985b7 WC |
301 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
302 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
95f25efe | 303 | u32 new_val; |
af51079e | 304 | u32 mask; |
95f25efe WS |
305 | |
306 | switch (reg) { | |
307 | case SDHCI_POWER_CONTROL: | |
308 | /* | |
309 | * FSL put some DMA bits here | |
310 | * If your board has a regulator, code should be here | |
311 | */ | |
312 | return; | |
313 | case SDHCI_HOST_CONTROL: | |
6b40d182 | 314 | /* FSL messed up here, so we need to manually compose it. */ |
af51079e | 315 | new_val = val & SDHCI_CTRL_LED; |
7122bbb0 | 316 | /* ensure the endianness */ |
95f25efe | 317 | new_val |= ESDHC_HOST_CONTROL_LE; |
9a0985b7 WC |
318 | /* bits 8&9 are reserved on mx25 */ |
319 | if (!is_imx25_esdhc(imx_data)) { | |
320 | /* DMA mode bits are shifted */ | |
321 | new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; | |
322 | } | |
95f25efe | 323 | |
af51079e SH |
324 | /* |
325 | * Do not touch buswidth bits here. This is done in | |
326 | * esdhc_pltfm_bus_width. | |
f6825748 MF |
327 | * Do not touch the D3CD bit either which is used for the |
328 | * SDIO interrupt errata workaround. | |
af51079e | 329 | */ |
f6825748 | 330 | mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); |
af51079e SH |
331 | |
332 | esdhc_clrset_le(host, mask, new_val, reg); | |
95f25efe WS |
333 | return; |
334 | } | |
335 | esdhc_clrset_le(host, 0xff, val, reg); | |
913413c3 SG |
336 | |
337 | /* | |
338 | * The esdhc has a design violation to SDHC spec which tells | |
339 | * that software reset should not affect card detection circuit. | |
340 | * But esdhc clears its SYSCTL register bits [0..2] during the | |
341 | * software reset. This will stop those clocks that card detection | |
342 | * circuit relies on. To work around it, we turn the clocks on back | |
343 | * to keep card detection circuit functional. | |
344 | */ | |
58c8c4fb | 345 | if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { |
913413c3 | 346 | esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); |
58c8c4fb SG |
347 | /* |
348 | * The reset on usdhc fails to clear MIX_CTRL register. | |
349 | * Do it manually here. | |
350 | */ | |
351 | if (is_imx6q_usdhc(imx_data)) | |
352 | writel(0, host->ioaddr + ESDHC_MIX_CTRL); | |
353 | } | |
95f25efe WS |
354 | } |
355 | ||
95f25efe WS |
356 | static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) |
357 | { | |
358 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
359 | ||
360 | return clk_get_rate(pltfm_host->clk) / 256 / 16; | |
361 | } | |
362 | ||
913413c3 SG |
363 | static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) |
364 | { | |
842afc02 SG |
365 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
366 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
367 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; | |
913413c3 SG |
368 | |
369 | switch (boarddata->wp_type) { | |
370 | case ESDHC_WP_GPIO: | |
fbe5fdd1 | 371 | return mmc_gpio_get_ro(host->mmc); |
913413c3 SG |
372 | case ESDHC_WP_CONTROLLER: |
373 | return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & | |
374 | SDHCI_WRITE_PROTECT); | |
375 | case ESDHC_WP_NONE: | |
376 | break; | |
377 | } | |
378 | ||
379 | return -ENOSYS; | |
380 | } | |
381 | ||
af51079e SH |
382 | static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) |
383 | { | |
384 | u32 ctrl; | |
385 | ||
386 | switch (width) { | |
387 | case MMC_BUS_WIDTH_8: | |
388 | ctrl = ESDHC_CTRL_8BITBUS; | |
389 | break; | |
390 | case MMC_BUS_WIDTH_4: | |
391 | ctrl = ESDHC_CTRL_4BITBUS; | |
392 | break; | |
393 | default: | |
394 | ctrl = 0; | |
395 | break; | |
396 | } | |
397 | ||
398 | esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, | |
399 | SDHCI_HOST_CONTROL); | |
400 | ||
401 | return 0; | |
402 | } | |
403 | ||
c915568d | 404 | static const struct sdhci_ops sdhci_esdhc_ops = { |
e149860d | 405 | .read_l = esdhc_readl_le, |
0c6d49ce | 406 | .read_w = esdhc_readw_le, |
e149860d | 407 | .write_l = esdhc_writel_le, |
0c6d49ce WS |
408 | .write_w = esdhc_writew_le, |
409 | .write_b = esdhc_writeb_le, | |
410 | .set_clock = esdhc_set_clock, | |
d005d943 | 411 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
0c6d49ce | 412 | .get_min_clock = esdhc_pltfm_get_min_clock, |
913413c3 | 413 | .get_ro = esdhc_pltfm_get_ro, |
af51079e | 414 | .platform_bus_width = esdhc_pltfm_bus_width, |
0c6d49ce WS |
415 | }; |
416 | ||
1db5eebf | 417 | static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { |
97e4ba6a RZ |
418 | .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT |
419 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | |
420 | | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
85d6509d | 421 | | SDHCI_QUIRK_BROKEN_CARD_DETECTION, |
85d6509d SG |
422 | .ops = &sdhci_esdhc_ops, |
423 | }; | |
424 | ||
abfafc2d | 425 | #ifdef CONFIG_OF |
c3be1efd | 426 | static int |
abfafc2d SG |
427 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, |
428 | struct esdhc_platform_data *boarddata) | |
429 | { | |
430 | struct device_node *np = pdev->dev.of_node; | |
431 | ||
432 | if (!np) | |
433 | return -ENODEV; | |
434 | ||
7f217794 | 435 | if (of_get_property(np, "non-removable", NULL)) |
abfafc2d SG |
436 | boarddata->cd_type = ESDHC_CD_PERMANENT; |
437 | ||
438 | if (of_get_property(np, "fsl,cd-controller", NULL)) | |
439 | boarddata->cd_type = ESDHC_CD_CONTROLLER; | |
440 | ||
441 | if (of_get_property(np, "fsl,wp-controller", NULL)) | |
442 | boarddata->wp_type = ESDHC_WP_CONTROLLER; | |
443 | ||
444 | boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); | |
445 | if (gpio_is_valid(boarddata->cd_gpio)) | |
446 | boarddata->cd_type = ESDHC_CD_GPIO; | |
447 | ||
448 | boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); | |
449 | if (gpio_is_valid(boarddata->wp_gpio)) | |
450 | boarddata->wp_type = ESDHC_WP_GPIO; | |
451 | ||
af51079e SH |
452 | of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); |
453 | ||
abfafc2d SG |
454 | return 0; |
455 | } | |
456 | #else | |
457 | static inline int | |
458 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, | |
459 | struct esdhc_platform_data *boarddata) | |
460 | { | |
461 | return -ENODEV; | |
462 | } | |
463 | #endif | |
464 | ||
c3be1efd | 465 | static int sdhci_esdhc_imx_probe(struct platform_device *pdev) |
95f25efe | 466 | { |
abfafc2d SG |
467 | const struct of_device_id *of_id = |
468 | of_match_device(imx_esdhc_dt_ids, &pdev->dev); | |
85d6509d SG |
469 | struct sdhci_pltfm_host *pltfm_host; |
470 | struct sdhci_host *host; | |
471 | struct esdhc_platform_data *boarddata; | |
0c6d49ce | 472 | int err; |
e149860d | 473 | struct pltfm_imx_data *imx_data; |
95f25efe | 474 | |
85d6509d SG |
475 | host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata); |
476 | if (IS_ERR(host)) | |
477 | return PTR_ERR(host); | |
478 | ||
479 | pltfm_host = sdhci_priv(host); | |
480 | ||
e3af31c6 | 481 | imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); |
abfafc2d SG |
482 | if (!imx_data) { |
483 | err = -ENOMEM; | |
e3af31c6 | 484 | goto free_sdhci; |
abfafc2d | 485 | } |
57ed3314 | 486 | |
abfafc2d SG |
487 | if (of_id) |
488 | pdev->id_entry = of_id->data; | |
57ed3314 | 489 | imx_data->devtype = pdev->id_entry->driver_data; |
85d6509d SG |
490 | pltfm_host->priv = imx_data; |
491 | ||
52dac615 SH |
492 | imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
493 | if (IS_ERR(imx_data->clk_ipg)) { | |
494 | err = PTR_ERR(imx_data->clk_ipg); | |
e3af31c6 | 495 | goto free_sdhci; |
95f25efe | 496 | } |
52dac615 SH |
497 | |
498 | imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
499 | if (IS_ERR(imx_data->clk_ahb)) { | |
500 | err = PTR_ERR(imx_data->clk_ahb); | |
e3af31c6 | 501 | goto free_sdhci; |
52dac615 SH |
502 | } |
503 | ||
504 | imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); | |
505 | if (IS_ERR(imx_data->clk_per)) { | |
506 | err = PTR_ERR(imx_data->clk_per); | |
e3af31c6 | 507 | goto free_sdhci; |
52dac615 SH |
508 | } |
509 | ||
510 | pltfm_host->clk = imx_data->clk_per; | |
511 | ||
512 | clk_prepare_enable(imx_data->clk_per); | |
513 | clk_prepare_enable(imx_data->clk_ipg); | |
514 | clk_prepare_enable(imx_data->clk_ahb); | |
95f25efe | 515 | |
e62d8b8f DA |
516 | imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
517 | if (IS_ERR(imx_data->pinctrl)) { | |
518 | err = PTR_ERR(imx_data->pinctrl); | |
e3af31c6 | 519 | goto disable_clk; |
e62d8b8f DA |
520 | } |
521 | ||
b8915282 | 522 | host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; |
37865fe9 | 523 | |
57ed3314 | 524 | if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) |
0c6d49ce | 525 | /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ |
97e4ba6a RZ |
526 | host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK |
527 | | SDHCI_QUIRK_BROKEN_ADMA; | |
0c6d49ce | 528 | |
57ed3314 | 529 | if (is_imx53_esdhc(imx_data)) |
58ac8177 RZ |
530 | imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT; |
531 | ||
f750ba9b SG |
532 | /* |
533 | * The imx6q ROM code will change the default watermark level setting | |
534 | * to something insane. Change it back here. | |
535 | */ | |
536 | if (is_imx6q_usdhc(imx_data)) | |
60bf6396 | 537 | writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); |
f750ba9b | 538 | |
842afc02 | 539 | boarddata = &imx_data->boarddata; |
abfafc2d SG |
540 | if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { |
541 | if (!host->mmc->parent->platform_data) { | |
542 | dev_err(mmc_dev(host->mmc), "no board data!\n"); | |
543 | err = -EINVAL; | |
e3af31c6 | 544 | goto disable_clk; |
abfafc2d SG |
545 | } |
546 | imx_data->boarddata = *((struct esdhc_platform_data *) | |
547 | host->mmc->parent->platform_data); | |
548 | } | |
913413c3 SG |
549 | |
550 | /* write_protect */ | |
551 | if (boarddata->wp_type == ESDHC_WP_GPIO) { | |
fbe5fdd1 | 552 | err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); |
0c6d49ce | 553 | if (err) { |
fbe5fdd1 SG |
554 | dev_err(mmc_dev(host->mmc), |
555 | "failed to request write-protect gpio!\n"); | |
556 | goto disable_clk; | |
0c6d49ce | 557 | } |
fbe5fdd1 | 558 | host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; |
913413c3 SG |
559 | } |
560 | ||
561 | /* card_detect */ | |
913413c3 SG |
562 | switch (boarddata->cd_type) { |
563 | case ESDHC_CD_GPIO: | |
fbe5fdd1 | 564 | err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio); |
7e29c306 | 565 | if (err) { |
913413c3 | 566 | dev_err(mmc_dev(host->mmc), |
fbe5fdd1 | 567 | "failed to request card-detect gpio!\n"); |
e3af31c6 | 568 | goto disable_clk; |
7e29c306 | 569 | } |
913413c3 | 570 | /* fall through */ |
7e29c306 | 571 | |
913413c3 SG |
572 | case ESDHC_CD_CONTROLLER: |
573 | /* we have a working card_detect back */ | |
7e29c306 | 574 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; |
913413c3 SG |
575 | break; |
576 | ||
577 | case ESDHC_CD_PERMANENT: | |
578 | host->mmc->caps = MMC_CAP_NONREMOVABLE; | |
579 | break; | |
580 | ||
581 | case ESDHC_CD_NONE: | |
582 | break; | |
0c6d49ce | 583 | } |
16a790bc | 584 | |
af51079e SH |
585 | switch (boarddata->max_bus_width) { |
586 | case 8: | |
587 | host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; | |
588 | break; | |
589 | case 4: | |
590 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; | |
591 | break; | |
592 | case 1: | |
593 | default: | |
594 | host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; | |
595 | break; | |
596 | } | |
597 | ||
85d6509d SG |
598 | err = sdhci_add_host(host); |
599 | if (err) | |
e3af31c6 | 600 | goto disable_clk; |
85d6509d | 601 | |
95f25efe | 602 | return 0; |
7e29c306 | 603 | |
e3af31c6 | 604 | disable_clk: |
52dac615 SH |
605 | clk_disable_unprepare(imx_data->clk_per); |
606 | clk_disable_unprepare(imx_data->clk_ipg); | |
607 | clk_disable_unprepare(imx_data->clk_ahb); | |
e3af31c6 | 608 | free_sdhci: |
85d6509d SG |
609 | sdhci_pltfm_free(pdev); |
610 | return err; | |
95f25efe WS |
611 | } |
612 | ||
6e0ee714 | 613 | static int sdhci_esdhc_imx_remove(struct platform_device *pdev) |
95f25efe | 614 | { |
85d6509d | 615 | struct sdhci_host *host = platform_get_drvdata(pdev); |
95f25efe | 616 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
e149860d | 617 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
85d6509d SG |
618 | int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); |
619 | ||
620 | sdhci_remove_host(host, dead); | |
0c6d49ce | 621 | |
52dac615 SH |
622 | clk_disable_unprepare(imx_data->clk_per); |
623 | clk_disable_unprepare(imx_data->clk_ipg); | |
624 | clk_disable_unprepare(imx_data->clk_ahb); | |
625 | ||
85d6509d SG |
626 | sdhci_pltfm_free(pdev); |
627 | ||
628 | return 0; | |
95f25efe WS |
629 | } |
630 | ||
85d6509d SG |
631 | static struct platform_driver sdhci_esdhc_imx_driver = { |
632 | .driver = { | |
633 | .name = "sdhci-esdhc-imx", | |
634 | .owner = THIS_MODULE, | |
abfafc2d | 635 | .of_match_table = imx_esdhc_dt_ids, |
29495aa0 | 636 | .pm = SDHCI_PLTFM_PMOPS, |
85d6509d | 637 | }, |
57ed3314 | 638 | .id_table = imx_esdhc_devtype, |
85d6509d | 639 | .probe = sdhci_esdhc_imx_probe, |
0433c143 | 640 | .remove = sdhci_esdhc_imx_remove, |
95f25efe | 641 | }; |
85d6509d | 642 | |
d1f81a64 | 643 | module_platform_driver(sdhci_esdhc_imx_driver); |
85d6509d SG |
644 | |
645 | MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); | |
646 | MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); | |
647 | MODULE_LICENSE("GPL v2"); |