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mmc: sdhci-esdhc-imx: change pinctrl state according to uhs mode
[linux-2.6-block.git] / drivers / mmc / host / sdhci-esdhc-imx.c
CommitLineData
95f25efe
WS		 1/*
2 * Freescale eSDHC i.MX controller driver for the platform bus.
3 *
4 * derived from the OF-version.
5 *
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <w.sang@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14#include <linux/io.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/clk.h>
0c6d49ce 18#include <linux/gpio.h>
66506f76 19#include <linux/module.h>
e149860d 20#include <linux/slab.h>
95f25efe 21#include <linux/mmc/host.h>
58ac8177
RZ		 22#include <linux/mmc/mmc.h>
23#include <linux/mmc/sdio.h>
fbe5fdd1 24#include <linux/mmc/slot-gpio.h>
abfafc2d
SG		 25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/of_gpio.h>
e62d8b8f 28#include <linux/pinctrl/consumer.h>
82906b13 29#include <linux/platform_data/mmc-esdhc-imx.h>
95f25efe
WS		 30#include "sdhci-pltfm.h"
31#include "sdhci-esdhc.h"
32
60bf6396 33#define ESDHC_CTRL_D3CD 0x08
58ac8177 34/* VENDOR SPEC register */
60bf6396
SG		 35#define ESDHC_VENDOR_SPEC 0xc0
36#define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
0322191e 37#define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
fed2f6e2 38#define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
60bf6396
SG		 39#define ESDHC_WTMK_LVL 0x44
40#define ESDHC_MIX_CTRL 0x48
2a15f981 41#define ESDHC_MIX_CTRL_AC23EN (1 << 7)
0322191e
DA		 42#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
43#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
44#define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
2a15f981
SG		 45/* Bits 3 and 6 are not SDHCI standard definitions */
46#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
58ac8177 47
0322191e
DA		 48/* tune control register */
49#define ESDHC_TUNE_CTRL_STATUS 0x68
50#define ESDHC_TUNE_CTRL_STEP 1
51#define ESDHC_TUNE_CTRL_MIN 0
52#define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
53
54#define ESDHC_TUNING_BLOCK_PATTERN_LEN 64
55
ad93220d
DA		 56/* pinctrl state */
57#define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
58#define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
59
af51079e
SH		 60/*
61 * Our interpretation of the SDHCI_HOST_CONTROL register
62 */
63#define ESDHC_CTRL_4BITBUS (0x1 << 1)
64#define ESDHC_CTRL_8BITBUS (0x2 << 1)
65#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
66
97e4ba6a
RZ		 67/*
68 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
69 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
70 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
71 * Define this macro DMA error INT for fsl eSDHC
72 */
60bf6396 73#define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
97e4ba6a 74
58ac8177
RZ		 75/*
76 * The CMDTYPE of the CMD register (offset 0xE) should be set to
77 * "11" when the STOP CMD12 is issued on imx53 to abort one
78 * open ended multi-blk IO. Otherwise the TC INT wouldn't
79 * be generated.
80 * In exact block transfer, the controller doesn't complete the
81 * operations automatically as required at the end of the
82 * transfer and remains on hold if the abort command is not sent.
83 * As a result, the TC flag is not asserted and SW received timeout
84 * exeception. Bit1 of Vendor Spec registor is used to fix it.
85 */
86#define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1)
e149860d 87
57ed3314
SG		 88enum imx_esdhc_type {
89 IMX25_ESDHC,
90 IMX35_ESDHC,
91 IMX51_ESDHC,
92 IMX53_ESDHC,
95a2482a 93 IMX6Q_USDHC,
57ed3314
SG		 94};
95
e149860d
RZ		 96struct pltfm_imx_data {
97 int flags;
98 u32 scratchpad;
57ed3314 99 enum imx_esdhc_type devtype;
e62d8b8f 100 struct pinctrl *pinctrl;
ad93220d
DA		 101 struct pinctrl_state *pins_default;
102 struct pinctrl_state *pins_100mhz;
103 struct pinctrl_state *pins_200mhz;
842afc02 104 struct esdhc_platform_data boarddata;
52dac615
SH		 105 struct clk *clk_ipg;
106 struct clk *clk_ahb;
107 struct clk *clk_per;
361b8482
LS		 108 enum {
109 NO_CMD_PENDING, /* no multiblock command pending*/
110 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
111 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
112 } multiblock_status;
0322191e 113 u32 uhs_mode;
e149860d
RZ		 114};
115
57ed3314
SG		 116static struct platform_device_id imx_esdhc_devtype[] = {
117 {
118 .name = "sdhci-esdhc-imx25",
119 .driver_data = IMX25_ESDHC,
120 }, {
121 .name = "sdhci-esdhc-imx35",
122 .driver_data = IMX35_ESDHC,
123 }, {
124 .name = "sdhci-esdhc-imx51",
125 .driver_data = IMX51_ESDHC,
126 }, {
127 .name = "sdhci-esdhc-imx53",
128 .driver_data = IMX53_ESDHC,
95a2482a
SG		 129 }, {
130 .name = "sdhci-usdhc-imx6q",
131 .driver_data = IMX6Q_USDHC,
57ed3314
SG		 132 }, {
133 /* sentinel */
134 }
135};
136MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
137
abfafc2d
SG		 138static const struct of_device_id imx_esdhc_dt_ids[] = {
139 { .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], },
140 { .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], },
141 { .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], },
142 { .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], },
95a2482a 143 { .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], },
abfafc2d
SG		 144 { /* sentinel */ }
145};
146MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
147
57ed3314
SG		 148static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
149{
150 return data->devtype == IMX25_ESDHC;
151}
152
153static inline int is_imx35_esdhc(struct pltfm_imx_data *data)
154{
155 return data->devtype == IMX35_ESDHC;
156}
157
158static inline int is_imx51_esdhc(struct pltfm_imx_data *data)
159{
160 return data->devtype == IMX51_ESDHC;
161}
162
163static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
164{
165 return data->devtype == IMX53_ESDHC;
166}
167
95a2482a
SG		 168static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
169{
170 return data->devtype == IMX6Q_USDHC;
171}
172
95f25efe
WS		 173static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
174{
175 void __iomem *base = host->ioaddr + (reg & ~0x3);
176 u32 shift = (reg & 0x3) * 8;
177
178 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
179}
180
7e29c306
WS		 181static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
182{
361b8482
LS		 183 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
184 struct pltfm_imx_data *imx_data = pltfm_host->priv;
7e29c306
WS		 185 u32 val = readl(host->ioaddr + reg);
186
0322191e
DA		 187 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
188 u32 fsl_prss = val;
189 /* save the least 20 bits */
190 val = fsl_prss & 0x000FFFFF;
191 /* move dat[0-3] bits */
192 val |= (fsl_prss & 0x0F000000) >> 4;
193 /* move cmd line bit */
194 val |= (fsl_prss & 0x00800000) << 1;
195 }
196
97e4ba6a
RZ		 197 if (unlikely(reg == SDHCI_CAPABILITIES)) {
198 /* In FSL esdhc IC module, only bit20 is used to indicate the
199 * ADMA2 capability of esdhc, but this bit is messed up on
200 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
201 * don't actually support ADMA2). So set the BROKEN_ADMA
202 * uirk on MX25/35 platforms.
203 */
204
205 if (val & SDHCI_CAN_DO_ADMA1) {
206 val &= ~SDHCI_CAN_DO_ADMA1;
207 val |= SDHCI_CAN_DO_ADMA2;
208 }
209 }
210
0322191e
DA		 211 if (unlikely(reg == SDHCI_CAPABILITIES_1) && is_imx6q_usdhc(imx_data))
212 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
213 | SDHCI_SUPPORT_SDR50;
214
215 if (unlikely(reg == SDHCI_MAX_CURRENT) && is_imx6q_usdhc(imx_data)) {
216 val = 0;
217 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
218 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
219 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
220 }
221
97e4ba6a 222 if (unlikely(reg == SDHCI_INT_STATUS)) {
60bf6396
SG		 223 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
224 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
97e4ba6a
RZ		 225 val |= SDHCI_INT_ADMA_ERROR;
226 }
361b8482
LS		 227
228 /*
229 * mask off the interrupt we get in response to the manually
230 * sent CMD12
231 */
232 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
233 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
234 val &= ~SDHCI_INT_RESPONSE;
235 writel(SDHCI_INT_RESPONSE, host->ioaddr +
236 SDHCI_INT_STATUS);
237 imx_data->multiblock_status = NO_CMD_PENDING;
238 }
97e4ba6a
RZ		 239 }
240
7e29c306
WS		 241 return val;
242}
243
244static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
245{
e149860d
RZ		 246 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
247 struct pltfm_imx_data *imx_data = pltfm_host->priv;
0d58864b
TL		 248 u32 data;
249
250 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
0d58864b
TL		 251 if (val & SDHCI_INT_CARD_INT) {
252 /*
253 * Clear and then set D3CD bit to avoid missing the
254 * card interrupt. This is a eSDHC controller problem
255 * so we need to apply the following workaround: clear
256 * and set D3CD bit will make eSDHC re-sample the card
257 * interrupt. In case a card interrupt was lost,
258 * re-sample it by the following steps.
259 */
260 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
60bf6396 261 data &= ~ESDHC_CTRL_D3CD;
0d58864b 262 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
60bf6396 263 data |= ESDHC_CTRL_D3CD;
0d58864b
TL		 264 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
265 }
266 }
7e29c306 267
58ac8177
RZ		 268 if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
269 && (reg == SDHCI_INT_STATUS)
270 && (val & SDHCI_INT_DATA_END))) {
271 u32 v;
60bf6396
SG		 272 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
273 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
274 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
361b8482
LS		 275
276 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
277 {
278 /* send a manual CMD12 with RESPTYP=none */
279 data = MMC_STOP_TRANSMISSION << 24 |
280 SDHCI_CMD_ABORTCMD << 16;
281 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
282 imx_data->multiblock_status = WAIT_FOR_INT;
283 }
58ac8177
RZ		 284 }
285
97e4ba6a
RZ		 286 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
287 if (val & SDHCI_INT_ADMA_ERROR) {
288 val &= ~SDHCI_INT_ADMA_ERROR;
60bf6396 289 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
97e4ba6a
RZ		 290 }
291 }
292
7e29c306
WS		 293 writel(val, host->ioaddr + reg);
294}
295
95f25efe
WS		 296static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
297{
ef4d0888
SG		 298 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
299 struct pltfm_imx_data *imx_data = pltfm_host->priv;
0322191e
DA		 300 u16 ret = 0;
301 u32 val;
ef4d0888 302
95a2482a 303 if (unlikely(reg == SDHCI_HOST_VERSION)) {
ef4d0888
SG		 304 reg ^= 2;
305 if (is_imx6q_usdhc(imx_data)) {
306 /*
307 * The usdhc register returns a wrong host version.
308 * Correct it here.
309 */
310 return SDHCI_SPEC_300;
311 }
95a2482a 312 }
95f25efe 313
0322191e
DA		 314 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
315 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
316 if (val & ESDHC_VENDOR_SPEC_VSELECT)
317 ret |= SDHCI_CTRL_VDD_180;
318
319 if (is_imx6q_usdhc(imx_data)) {
320 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
321 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
322 ret |= SDHCI_CTRL_EXEC_TUNING;
323 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
324 ret |= SDHCI_CTRL_TUNED_CLK;
325 }
326
327 ret |= (imx_data->uhs_mode & SDHCI_CTRL_UHS_MASK);
328 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
329
330 return ret;
331 }
332
95f25efe
WS		 333 return readw(host->ioaddr + reg);
334}
335
336static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
337{
338 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
e149860d 339 struct pltfm_imx_data *imx_data = pltfm_host->priv;
0322191e 340 u32 new_val = 0;
95f25efe
WS		 341
342 switch (reg) {
0322191e
DA		 343 case SDHCI_CLOCK_CONTROL:
344 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
345 if (val & SDHCI_CLOCK_CARD_EN)
346 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
347 else
348 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
349 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
350 return;
351 case SDHCI_HOST_CONTROL2:
352 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
353 if (val & SDHCI_CTRL_VDD_180)
354 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
355 else
356 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
357 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
358 imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK;
359 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
360 if (val & SDHCI_CTRL_TUNED_CLK)
361 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
362 else
363 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
364 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
365 return;
95f25efe 366 case SDHCI_TRANSFER_MODE:
58ac8177
RZ		 367 if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
368 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
369 && (host->cmd->data->blocks > 1)
370 && (host->cmd->data->flags & MMC_DATA_READ)) {
371 u32 v;
60bf6396
SG		 372 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
373 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
374 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
58ac8177 375 }
69f54698
SG		 376
377 if (is_imx6q_usdhc(imx_data)) {
378 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
2a15f981
SG		 379 /* Swap AC23 bit */
380 if (val & SDHCI_TRNS_AUTO_CMD23) {
381 val &= ~SDHCI_TRNS_AUTO_CMD23;
382 val |= ESDHC_MIX_CTRL_AC23EN;
383 }
384 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
69f54698
SG		 385 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
386 } else {
387 /*
388 * Postpone this write, we must do it together with a
389 * command write that is down below.
390 */
391 imx_data->scratchpad = val;
392 }
95f25efe
WS		 393 return;
394 case SDHCI_COMMAND:
361b8482 395 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
58ac8177 396 val |= SDHCI_CMD_ABORTCMD;
95a2482a 397
361b8482
LS		 398 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
399 (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
400 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
401
69f54698 402 if (is_imx6q_usdhc(imx_data))
95a2482a
SG		 403 writel(val << 16,
404 host->ioaddr + SDHCI_TRANSFER_MODE);
69f54698 405 else
95a2482a
SG		 406 writel(val << 16 | imx_data->scratchpad,
407 host->ioaddr + SDHCI_TRANSFER_MODE);
95f25efe
WS		 408 return;
409 case SDHCI_BLOCK_SIZE:
410 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
411 break;
412 }
413 esdhc_clrset_le(host, 0xffff, val, reg);
414}
415
416static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
417{
9a0985b7
WC		 418 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
419 struct pltfm_imx_data *imx_data = pltfm_host->priv;
95f25efe 420 u32 new_val;
af51079e 421 u32 mask;
95f25efe
WS		 422
423 switch (reg) {
424 case SDHCI_POWER_CONTROL:
425 /*
426 * FSL put some DMA bits here
427 * If your board has a regulator, code should be here
428 */
429 return;
430 case SDHCI_HOST_CONTROL:
6b40d182 431 /* FSL messed up here, so we need to manually compose it. */
af51079e 432 new_val = val & SDHCI_CTRL_LED;
7122bbb0 433 /* ensure the endianness */
95f25efe 434 new_val |= ESDHC_HOST_CONTROL_LE;
9a0985b7
WC		 435 /* bits 8&9 are reserved on mx25 */
436 if (!is_imx25_esdhc(imx_data)) {
437 /* DMA mode bits are shifted */
438 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
439 }
95f25efe 440
af51079e
SH		 441 /*
442 * Do not touch buswidth bits here. This is done in
443 * esdhc_pltfm_bus_width.
f6825748
MF		 444 * Do not touch the D3CD bit either which is used for the
445 * SDIO interrupt errata workaround.
af51079e 446 */
f6825748 447 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
af51079e
SH		 448
449 esdhc_clrset_le(host, mask, new_val, reg);
95f25efe
WS		 450 return;
451 }
452 esdhc_clrset_le(host, 0xff, val, reg);
913413c3
SG		 453
454 /*
455 * The esdhc has a design violation to SDHC spec which tells
456 * that software reset should not affect card detection circuit.
457 * But esdhc clears its SYSCTL register bits [0..2] during the
458 * software reset. This will stop those clocks that card detection
459 * circuit relies on. To work around it, we turn the clocks on back
460 * to keep card detection circuit functional.
461 */
58c8c4fb 462 if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
913413c3 463 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
58c8c4fb
SG		 464 /*
465 * The reset on usdhc fails to clear MIX_CTRL register.
466 * Do it manually here.
467 */
468 if (is_imx6q_usdhc(imx_data))
469 writel(0, host->ioaddr + ESDHC_MIX_CTRL);
470 }
95f25efe
WS		 471}
472
0ddf03c9
LS		 473static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
474{
475 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
476 struct pltfm_imx_data *imx_data = pltfm_host->priv;
477 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
478
479 u32 f_host = clk_get_rate(pltfm_host->clk);
480
481 if (boarddata->f_max && (boarddata->f_max < f_host))
482 return boarddata->f_max;
483 else
484 return f_host;
485}
486
95f25efe
WS		 487static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
488{
489 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
490
491 return clk_get_rate(pltfm_host->clk) / 256 / 16;
492}
493
8ba9580a
LS		 494static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
495 unsigned int clock)
496{
497 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
fed2f6e2 498 struct pltfm_imx_data *imx_data = pltfm_host->priv;
d31fc00a
DA		 499 unsigned int host_clock = clk_get_rate(pltfm_host->clk);
500 int pre_div = 2;
501 int div = 1;
fed2f6e2 502 u32 temp, val;
d31fc00a 503
fed2f6e2
DA		 504 if (clock == 0) {
505 if (is_imx6q_usdhc(imx_data)) {
506 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
507 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
508 host->ioaddr + ESDHC_VENDOR_SPEC);
509 }
d31fc00a 510 goto out;
fed2f6e2 511 }
d31fc00a
DA		 512
513 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
514 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
515 | ESDHC_CLOCK_MASK);
516 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
517
518 while (host_clock / pre_div / 16 > clock && pre_div < 256)
519 pre_div *= 2;
520
521 while (host_clock / pre_div / div > clock && div < 16)
522 div++;
523
524 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
525 clock, host_clock / pre_div / div);
526
527 pre_div >>= 1;
528 div--;
529
530 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
531 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
532 | (div << ESDHC_DIVIDER_SHIFT)
533 | (pre_div << ESDHC_PREDIV_SHIFT));
534 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
fed2f6e2
DA		 535
536 if (is_imx6q_usdhc(imx_data)) {
537 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
538 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
539 host->ioaddr + ESDHC_VENDOR_SPEC);
540 }
541
d31fc00a
DA		 542 mdelay(1);
543out:
544 host->clock = clock;
8ba9580a
LS		 545}
546
913413c3
SG		 547static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
548{
842afc02
SG		 549 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
550 struct pltfm_imx_data *imx_data = pltfm_host->priv;
551 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
913413c3
SG		 552
553 switch (boarddata->wp_type) {
554 case ESDHC_WP_GPIO:
fbe5fdd1 555 return mmc_gpio_get_ro(host->mmc);
913413c3
SG		 556 case ESDHC_WP_CONTROLLER:
557 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
558 SDHCI_WRITE_PROTECT);
559 case ESDHC_WP_NONE:
560 break;
561 }
562
563 return -ENOSYS;
564}
565
af51079e
SH		 566static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width)
567{
568 u32 ctrl;
569
570 switch (width) {
571 case MMC_BUS_WIDTH_8:
572 ctrl = ESDHC_CTRL_8BITBUS;
573 break;
574 case MMC_BUS_WIDTH_4:
575 ctrl = ESDHC_CTRL_4BITBUS;
576 break;
577 default:
578 ctrl = 0;
579 break;
580 }
581
582 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
583 SDHCI_HOST_CONTROL);
584
585 return 0;
586}
587
0322191e
DA		 588static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
589{
590 u32 reg;
591
592 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
593 mdelay(1);
594
595 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
596 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
597 ESDHC_MIX_CTRL_FBCLK_SEL;
598 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
599 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
600 dev_dbg(mmc_dev(host->mmc),
601 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
602 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
603}
604
605static void esdhc_request_done(struct mmc_request *mrq)
606{
607 complete(&mrq->completion);
608}
609
610static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode)
611{
612 struct mmc_command cmd = {0};
613 struct mmc_request mrq = {0};
614 struct mmc_data data = {0};
615 struct scatterlist sg;
616 char tuning_pattern[ESDHC_TUNING_BLOCK_PATTERN_LEN];
617
618 cmd.opcode = opcode;
619 cmd.arg = 0;
620 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
621
622 data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN;
623 data.blocks = 1;
624 data.flags = MMC_DATA_READ;
625 data.sg = &sg;
626 data.sg_len = 1;
627
628 sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern));
629
630 mrq.cmd = &cmd;
631 mrq.cmd->mrq = &mrq;
632 mrq.data = &data;
633 mrq.data->mrq = &mrq;
634 mrq.cmd->data = mrq.data;
635
636 mrq.done = esdhc_request_done;
637 init_completion(&(mrq.completion));
638
639 disable_irq(host->irq);
640 spin_lock(&host->lock);
641 host->mrq = &mrq;
642
643 sdhci_send_command(host, mrq.cmd);
644
645 spin_unlock(&host->lock);
646 enable_irq(host->irq);
647
648 wait_for_completion(&mrq.completion);
649
650 if (cmd.error)
651 return cmd.error;
652 if (data.error)
653 return data.error;
654
655 return 0;
656}
657
658static void esdhc_post_tuning(struct sdhci_host *host)
659{
660 u32 reg;
661
662 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
663 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
664 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
665}
666
667static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
668{
669 int min, max, avg, ret;
670
671 /* find the mininum delay first which can pass tuning */
672 min = ESDHC_TUNE_CTRL_MIN;
673 while (min < ESDHC_TUNE_CTRL_MAX) {
674 esdhc_prepare_tuning(host, min);
675 if (!esdhc_send_tuning_cmd(host, opcode))
676 break;
677 min += ESDHC_TUNE_CTRL_STEP;
678 }
679
680 /* find the maxinum delay which can not pass tuning */
681 max = min + ESDHC_TUNE_CTRL_STEP;
682 while (max < ESDHC_TUNE_CTRL_MAX) {
683 esdhc_prepare_tuning(host, max);
684 if (esdhc_send_tuning_cmd(host, opcode)) {
685 max -= ESDHC_TUNE_CTRL_STEP;
686 break;
687 }
688 max += ESDHC_TUNE_CTRL_STEP;
689 }
690
691 /* use average delay to get the best timing */
692 avg = (min + max) / 2;
693 esdhc_prepare_tuning(host, avg);
694 ret = esdhc_send_tuning_cmd(host, opcode);
695 esdhc_post_tuning(host);
696
697 dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
698 ret ? "failed" : "passed", avg, ret);
699
700 return ret;
701}
702
ad93220d
DA		 703static int esdhc_change_pinstate(struct sdhci_host *host,
704 unsigned int uhs)
705{
706 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
707 struct pltfm_imx_data *imx_data = pltfm_host->priv;
708 struct pinctrl_state *pinctrl;
709
710 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
711
712 if (IS_ERR(imx_data->pinctrl) ||
713 IS_ERR(imx_data->pins_default) ||
714 IS_ERR(imx_data->pins_100mhz) ||
715 IS_ERR(imx_data->pins_200mhz))
716 return -EINVAL;
717
718 switch (uhs) {
719 case MMC_TIMING_UHS_SDR50:
720 pinctrl = imx_data->pins_100mhz;
721 break;
722 case MMC_TIMING_UHS_SDR104:
723 pinctrl = imx_data->pins_200mhz;
724 break;
725 default:
726 /* back to default state for other legacy timing */
727 pinctrl = imx_data->pins_default;
728 }
729
730 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
731}
732
733static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
734{
735 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
736 struct pltfm_imx_data *imx_data = pltfm_host->priv;
737
738 switch (uhs) {
739 case MMC_TIMING_UHS_SDR12:
740 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR12;
741 break;
742 case MMC_TIMING_UHS_SDR25:
743 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR25;
744 break;
745 case MMC_TIMING_UHS_SDR50:
746 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR50;
747 break;
748 case MMC_TIMING_UHS_SDR104:
749 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR104;
750 break;
751 case MMC_TIMING_UHS_DDR50:
752 imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50;
753 break;
754 }
755
756 return esdhc_change_pinstate(host, uhs);
757}
758
c915568d 759static const struct sdhci_ops sdhci_esdhc_ops = {
e149860d 760 .read_l = esdhc_readl_le,
0c6d49ce 761 .read_w = esdhc_readw_le,
e149860d 762 .write_l = esdhc_writel_le,
0c6d49ce
WS		 763 .write_w = esdhc_writew_le,
764 .write_b = esdhc_writeb_le,
8ba9580a 765 .set_clock = esdhc_pltfm_set_clock,
0ddf03c9 766 .get_max_clock = esdhc_pltfm_get_max_clock,
0c6d49ce 767 .get_min_clock = esdhc_pltfm_get_min_clock,
913413c3 768 .get_ro = esdhc_pltfm_get_ro,
af51079e 769 .platform_bus_width = esdhc_pltfm_bus_width,
ad93220d 770 .set_uhs_signaling = esdhc_set_uhs_signaling,
0322191e 771 .platform_execute_tuning = esdhc_executing_tuning,
0c6d49ce
WS		 772};
773
1db5eebf 774static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
97e4ba6a
RZ		 775 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
776 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
777 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
85d6509d 778 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
85d6509d
SG		 779 .ops = &sdhci_esdhc_ops,
780};
781
abfafc2d 782#ifdef CONFIG_OF
c3be1efd 783static int
abfafc2d
SG		 784sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
785 struct esdhc_platform_data *boarddata)
786{
787 struct device_node *np = pdev->dev.of_node;
788
789 if (!np)
790 return -ENODEV;
791
7f217794 792 if (of_get_property(np, "non-removable", NULL))
abfafc2d
SG		 793 boarddata->cd_type = ESDHC_CD_PERMANENT;
794
795 if (of_get_property(np, "fsl,cd-controller", NULL))
796 boarddata->cd_type = ESDHC_CD_CONTROLLER;
797
798 if (of_get_property(np, "fsl,wp-controller", NULL))
799 boarddata->wp_type = ESDHC_WP_CONTROLLER;
800
801 boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
802 if (gpio_is_valid(boarddata->cd_gpio))
803 boarddata->cd_type = ESDHC_CD_GPIO;
804
805 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
806 if (gpio_is_valid(boarddata->wp_gpio))
807 boarddata->wp_type = ESDHC_WP_GPIO;
808
af51079e
SH		 809 of_property_read_u32(np, "bus-width", &boarddata->max_bus_width);
810
0ddf03c9
LS		 811 of_property_read_u32(np, "max-frequency", &boarddata->f_max);
812
ad93220d
DA		 813 if (of_find_property(np, "no-1-8-v", NULL))
814 boarddata->support_vsel = false;
815 else
816 boarddata->support_vsel = true;
817
abfafc2d
SG		 818 return 0;
819}
820#else
821static inline int
822sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
823 struct esdhc_platform_data *boarddata)
824{
825 return -ENODEV;
826}
827#endif
828
c3be1efd 829static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
95f25efe 830{
abfafc2d
SG		 831 const struct of_device_id *of_id =
832 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
85d6509d
SG		 833 struct sdhci_pltfm_host *pltfm_host;
834 struct sdhci_host *host;
835 struct esdhc_platform_data *boarddata;
0c6d49ce 836 int err;
e149860d 837 struct pltfm_imx_data *imx_data;
95f25efe 838
0e748234 839 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
85d6509d
SG		 840 if (IS_ERR(host))
841 return PTR_ERR(host);
842
843 pltfm_host = sdhci_priv(host);
844
e3af31c6 845 imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
abfafc2d
SG		 846 if (!imx_data) {
847 err = -ENOMEM;
e3af31c6 848 goto free_sdhci;
abfafc2d 849 }
57ed3314 850
abfafc2d
SG		 851 if (of_id)
852 pdev->id_entry = of_id->data;
57ed3314 853 imx_data->devtype = pdev->id_entry->driver_data;
85d6509d
SG		 854 pltfm_host->priv = imx_data;
855
52dac615
SH		 856 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
857 if (IS_ERR(imx_data->clk_ipg)) {
858 err = PTR_ERR(imx_data->clk_ipg);
e3af31c6 859 goto free_sdhci;
95f25efe 860 }
52dac615
SH		 861
862 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
863 if (IS_ERR(imx_data->clk_ahb)) {
864 err = PTR_ERR(imx_data->clk_ahb);
e3af31c6 865 goto free_sdhci;
52dac615
SH		 866 }
867
868 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
869 if (IS_ERR(imx_data->clk_per)) {
870 err = PTR_ERR(imx_data->clk_per);
e3af31c6 871 goto free_sdhci;
52dac615
SH		 872 }
873
874 pltfm_host->clk = imx_data->clk_per;
875
876 clk_prepare_enable(imx_data->clk_per);
877 clk_prepare_enable(imx_data->clk_ipg);
878 clk_prepare_enable(imx_data->clk_ahb);
95f25efe 879
ad93220d 880 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
e62d8b8f
DA		 881 if (IS_ERR(imx_data->pinctrl)) {
882 err = PTR_ERR(imx_data->pinctrl);
e3af31c6 883 goto disable_clk;
e62d8b8f
DA		 884 }
885
ad93220d
DA		 886 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
887 PINCTRL_STATE_DEFAULT);
888 if (IS_ERR(imx_data->pins_default)) {
889 err = PTR_ERR(imx_data->pins_default);
890 dev_err(mmc_dev(host->mmc), "could not get default state\n");
891 goto disable_clk;
892 }
893
b8915282 894 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
37865fe9 895
57ed3314 896 if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
0c6d49ce 897 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
97e4ba6a
RZ		 898 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
899 | SDHCI_QUIRK_BROKEN_ADMA;
0c6d49ce 900
57ed3314 901 if (is_imx53_esdhc(imx_data))
58ac8177
RZ		 902 imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;
903
f750ba9b
SG		 904 /*
905 * The imx6q ROM code will change the default watermark level setting
906 * to something insane. Change it back here.
907 */
908 if (is_imx6q_usdhc(imx_data))
60bf6396 909 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
f750ba9b 910
842afc02 911 boarddata = &imx_data->boarddata;
abfafc2d
SG		 912 if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
913 if (!host->mmc->parent->platform_data) {
914 dev_err(mmc_dev(host->mmc), "no board data!\n");
915 err = -EINVAL;
e3af31c6 916 goto disable_clk;
abfafc2d
SG		 917 }
918 imx_data->boarddata = *((struct esdhc_platform_data *)
919 host->mmc->parent->platform_data);
920 }
913413c3
SG		 921
922 /* write_protect */
923 if (boarddata->wp_type == ESDHC_WP_GPIO) {
fbe5fdd1 924 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
0c6d49ce 925 if (err) {
fbe5fdd1
SG		 926 dev_err(mmc_dev(host->mmc),
927 "failed to request write-protect gpio!\n");
928 goto disable_clk;
0c6d49ce 929 }
fbe5fdd1 930 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
913413c3
SG		 931 }
932
933 /* card_detect */
913413c3
SG		 934 switch (boarddata->cd_type) {
935 case ESDHC_CD_GPIO:
214fc309 936 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
7e29c306 937 if (err) {
913413c3 938 dev_err(mmc_dev(host->mmc),
fbe5fdd1 939 "failed to request card-detect gpio!\n");
e3af31c6 940 goto disable_clk;
7e29c306 941 }
913413c3 942 /* fall through */
7e29c306 943
913413c3
SG		 944 case ESDHC_CD_CONTROLLER:
945 /* we have a working card_detect back */
7e29c306 946 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
913413c3
SG		 947 break;
948
949 case ESDHC_CD_PERMANENT:
950 host->mmc->caps = MMC_CAP_NONREMOVABLE;
951 break;
952
953 case ESDHC_CD_NONE:
954 break;
0c6d49ce 955 }
16a790bc 956
af51079e
SH		 957 switch (boarddata->max_bus_width) {
958 case 8:
959 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
960 break;
961 case 4:
962 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
963 break;
964 case 1:
965 default:
966 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
967 break;
968 }
969
ad93220d
DA		 970 /* sdr50 and sdr104 needs work on 1.8v signal voltage */
971 if ((boarddata->support_vsel) && is_imx6q_usdhc(imx_data)) {
972 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
973 ESDHC_PINCTRL_STATE_100MHZ);
974 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
975 ESDHC_PINCTRL_STATE_200MHZ);
976 if (IS_ERR(imx_data->pins_100mhz) ||
977 IS_ERR(imx_data->pins_200mhz)) {
978 dev_warn(mmc_dev(host->mmc),
979 "could not get ultra high speed state, work on normal mode\n");
980 /* fall back to not support uhs by specify no 1.8v quirk */
981 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
982 }
983 } else {
984 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
985 }
986
85d6509d
SG		 987 err = sdhci_add_host(host);
988 if (err)
e3af31c6 989 goto disable_clk;
85d6509d 990
95f25efe 991 return 0;
7e29c306 992
e3af31c6 993disable_clk:
52dac615
SH		 994 clk_disable_unprepare(imx_data->clk_per);
995 clk_disable_unprepare(imx_data->clk_ipg);
996 clk_disable_unprepare(imx_data->clk_ahb);
e3af31c6 997free_sdhci:
85d6509d
SG		 998 sdhci_pltfm_free(pdev);
999 return err;
95f25efe
WS		 1000}
1001
6e0ee714 1002static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
95f25efe 1003{
85d6509d 1004 struct sdhci_host *host = platform_get_drvdata(pdev);
95f25efe 1005 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
e149860d 1006 struct pltfm_imx_data *imx_data = pltfm_host->priv;
85d6509d
SG		 1007 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1008
1009 sdhci_remove_host(host, dead);
0c6d49ce 1010
52dac615
SH		 1011 clk_disable_unprepare(imx_data->clk_per);
1012 clk_disable_unprepare(imx_data->clk_ipg);
1013 clk_disable_unprepare(imx_data->clk_ahb);
1014
85d6509d
SG		 1015 sdhci_pltfm_free(pdev);
1016
1017 return 0;
95f25efe
WS		 1018}
1019
85d6509d
SG		 1020static struct platform_driver sdhci_esdhc_imx_driver = {
1021 .driver = {
1022 .name = "sdhci-esdhc-imx",
1023 .owner = THIS_MODULE,
abfafc2d 1024 .of_match_table = imx_esdhc_dt_ids,
29495aa0 1025 .pm = SDHCI_PLTFM_PMOPS,
85d6509d 1026 },
57ed3314 1027 .id_table = imx_esdhc_devtype,
85d6509d 1028 .probe = sdhci_esdhc_imx_probe,
0433c143 1029 .remove = sdhci_esdhc_imx_remove,
95f25efe 1030};
85d6509d 1031
d1f81a64 1032module_platform_driver(sdhci_esdhc_imx_driver);
85d6509d
SG		 1033
1034MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1035MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
1036MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)