[linux-2.6-block.git] / drivers / mmc / host / sdhci-esdhc-imx.c

/*
 * Freescale eSDHC i.MX controller driver for the platform bus.
 *
 * derived from the OF-version.
 *
 * Copyright (c) 2010 Pengutronix e.K.
 *   Author: Wolfram Sang <w.sang@pengutronix.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */

#include <linux/io.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sdhci-pltfm.h>
#include "sdhci.h"
#include "sdhci-pltfm.h"
#include "sdhci-esdhc.h"

static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
{
	void __iomem *base = host->ioaddr + (reg & ~0x3);
	u32 shift = (reg & 0x3) * 8;

	writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
}

static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
{
	if (unlikely(reg == SDHCI_HOST_VERSION))
		reg ^= 2;

	return readw(host->ioaddr + reg);
}

static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	switch (reg) {
	case SDHCI_TRANSFER_MODE:
		/*
		 * Postpone this write, we must do it together with a
		 * command write that is down below.
		 */
		pltfm_host->scratchpad = val;
		return;
	case SDHCI_COMMAND:
		writel(val << 16 | pltfm_host->scratchpad,
			host->ioaddr + SDHCI_TRANSFER_MODE);
		return;
	case SDHCI_BLOCK_SIZE:
		val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
		break;
	}
	esdhc_clrset_le(host, 0xffff, val, reg);
}

static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
{
	u32 new_val;

	switch (reg) {
	case SDHCI_POWER_CONTROL:
		/*
		 * FSL put some DMA bits here
		 * If your board has a regulator, code should be here
		 */
		return;
	case SDHCI_HOST_CONTROL:
		/* FSL messed up here, so we can just keep those two */
		new_val = val & (SDHCI_CTRL_LED | SDHCI_CTRL_4BITBUS);
		/* ensure the endianess */
		new_val |= ESDHC_HOST_CONTROL_LE;
		/* DMA mode bits are shifted */
		new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;

		esdhc_clrset_le(host, 0xffff, new_val, reg);
		return;
	}
	esdhc_clrset_le(host, 0xff, val, reg);
}

static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	return clk_get_rate(pltfm_host->clk);
}

static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	return clk_get_rate(pltfm_host->clk) / 256 / 16;
}

static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pdata)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct clk *clk;

	clk = clk_get(mmc_dev(host->mmc), NULL);
	if (IS_ERR(clk)) {
		dev_err(mmc_dev(host->mmc), "clk err\n");
		return PTR_ERR(clk);
	}
	clk_enable(clk);
	pltfm_host->clk = clk;

	return 0;
}

static void esdhc_pltfm_exit(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	clk_disable(pltfm_host->clk);
	clk_put(pltfm_host->clk);
}

static struct sdhci_ops sdhci_esdhc_ops = {
	.read_w = esdhc_readw_le,
	.write_w = esdhc_writew_le,
	.write_b = esdhc_writeb_le,
	.set_clock = esdhc_set_clock,
	.get_max_clock = esdhc_pltfm_get_max_clock,
	.get_min_clock = esdhc_pltfm_get_min_clock,
};

struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
	.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_MULTIBLOCK
			| SDHCI_QUIRK_BROKEN_ADMA,
	/* ADMA has issues. Might be fixable */
	/* NO_MULTIBLOCK might be MX35 only (Errata: ENGcm07207) */
	.ops = &sdhci_esdhc_ops,
	.init = esdhc_pltfm_init,
	.exit = esdhc_pltfm_exit,
};
Commit	Line	Data
95f25efe WS	1	/*
	2	* Freescale eSDHC i.MX controller driver for the platform bus.
	3	*
	4	* derived from the OF-version.
	5	*
	6	* Copyright (c) 2010 Pengutronix e.K.
	7	* Author: Wolfram Sang <w.sang@pengutronix.de>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License.
	12	*/
	13
	14	#include <linux/io.h>
	15	#include <linux/delay.h>
	16	#include <linux/err.h>
	17	#include <linux/clk.h>
	18	#include <linux/mmc/host.h>
	19	#include <linux/mmc/sdhci-pltfm.h>
	20	#include "sdhci.h"
	21	#include "sdhci-pltfm.h"
	22	#include "sdhci-esdhc.h"
	23
	24	static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
	25	{
	26	void __iomem *base = host->ioaddr + (reg & ~0x3);
	27	u32 shift = (reg & 0x3) * 8;
	28
	29	writel(((readl(base) & ~(mask << shift)) \| (val << shift)), base);
	30	}
	31
	32	static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
	33	{
	34	if (unlikely(reg == SDHCI_HOST_VERSION))
	35	reg ^= 2;
	36
	37	return readw(host->ioaddr + reg);
	38	}
	39
	40	static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
	41	{
	42	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	43
	44	switch (reg) {
	45	case SDHCI_TRANSFER_MODE:
	46	/*
	47	* Postpone this write, we must do it together with a
	48	* command write that is down below.
	49	*/
	50	pltfm_host->scratchpad = val;
	51	return;
	52	case SDHCI_COMMAND:
	53	writel(val << 16 \| pltfm_host->scratchpad,
	54	host->ioaddr + SDHCI_TRANSFER_MODE);
	55	return;
	56	case SDHCI_BLOCK_SIZE:
	57	val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
	58	break;
	59	}
	60	esdhc_clrset_le(host, 0xffff, val, reg);
	61	}
	62
	63	static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
	64	{
65	u32 new_val;
66
67	switch (reg) {
68	case SDHCI_POWER_CONTROL:
69	/*
70	* FSL put some DMA bits here
71	* If your board has a regulator, code should be here
72	*/
73	return;
74	case SDHCI_HOST_CONTROL:
75	/* FSL messed up here, so we can just keep those two */
76	new_val = val & (SDHCI_CTRL_LED \| SDHCI_CTRL_4BITBUS);
77	/* ensure the endianess */
78	new_val \|= ESDHC_HOST_CONTROL_LE;
79	/* DMA mode bits are shifted */
80	new_val \|= (val & SDHCI_CTRL_DMA_MASK) << 5;
81
82	esdhc_clrset_le(host, 0xffff, new_val, reg);
83	return;
84	}
85	esdhc_clrset_le(host, 0xff, val, reg);
86	}
87
88	static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
89	{
90	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
91
92	return clk_get_rate(pltfm_host->clk);
93	}
94
95	static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
96	{
97	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
98
99	return clk_get_rate(pltfm_host->clk) / 256 / 16;
100	}
101
102	static int esdhc_pltfm_init(struct sdhci_host host, struct sdhci_pltfm_data pdata)
103	{
104	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
105	struct clk *clk;
106
107	clk = clk_get(mmc_dev(host->mmc), NULL);
108	if (IS_ERR(clk)) {
109	dev_err(mmc_dev(host->mmc), "clk err\n");
110	return PTR_ERR(clk);
111	}
112	clk_enable(clk);
113	pltfm_host->clk = clk;
114
115	return 0;
116	}
117
118	static void esdhc_pltfm_exit(struct sdhci_host *host)
119	{
120	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
121
122	clk_disable(pltfm_host->clk);
123	clk_put(pltfm_host->clk);
124	}
125
126	static struct sdhci_ops sdhci_esdhc_ops = {
127	.read_w = esdhc_readw_le,
128	.write_w = esdhc_writew_le,
129	.write_b = esdhc_writeb_le,
130	.set_clock = esdhc_set_clock,
131	.get_max_clock = esdhc_pltfm_get_max_clock,
132	.get_min_clock = esdhc_pltfm_get_min_clock,
133	};
134
135	struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
136	.quirks = ESDHC_DEFAULT_QUIRKS \| SDHCI_QUIRK_NO_MULTIBLOCK
137	\| SDHCI_QUIRK_BROKEN_ADMA,
138	/* ADMA has issues. Might be fixable */
139	/* NO_MULTIBLOCK might be MX35 only (Errata: ENGcm07207) */
140	.ops = &sdhci_esdhc_ops,
141	.init = esdhc_pltfm_init,
142	.exit = esdhc_pltfm_exit,
143	};