[linux-2.6-block.git] / drivers / mmc / host / sdhci-esdhc-imx.c

/*
 * Freescale eSDHC i.MX controller driver for the platform bus.
 *
 * derived from the OF-version.
 *
 * Copyright (c) 2010 Pengutronix e.K.
 *   Author: Wolfram Sang <w.sang@pengutronix.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */

#include <linux/io.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h>
#include <linux/mmc/sdio.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_data/mmc-esdhc-imx.h>
#include "sdhci-pltfm.h"
#include "sdhci-esdhc.h"

#define	ESDHC_CTRL_D3CD			0x08
/* VENDOR SPEC register */
#define ESDHC_VENDOR_SPEC		0xc0
#define  ESDHC_VENDOR_SPEC_SDIO_QUIRK	(1 << 1)
#define ESDHC_WTMK_LVL			0x44
#define ESDHC_MIX_CTRL			0x48

/*
 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
 * Define this macro DMA error INT for fsl eSDHC
 */
#define ESDHC_INT_VENDOR_SPEC_DMA_ERR	(1 << 28)

/*
 * The CMDTYPE of the CMD register (offset 0xE) should be set to
 * "11" when the STOP CMD12 is issued on imx53 to abort one
 * open ended multi-blk IO. Otherwise the TC INT wouldn't
 * be generated.
 * In exact block transfer, the controller doesn't complete the
 * operations automatically as required at the end of the
 * transfer and remains on hold if the abort command is not sent.
 * As a result, the TC flag is not asserted and SW  received timeout
 * exeception. Bit1 of Vendor Spec registor is used to fix it.
 */
#define ESDHC_FLAG_MULTIBLK_NO_INT	(1 << 1)

enum imx_esdhc_type {
	IMX25_ESDHC,
	IMX35_ESDHC,
	IMX51_ESDHC,
	IMX53_ESDHC,
	IMX6Q_USDHC,
};

struct pltfm_imx_data {
	int flags;
	u32 scratchpad;
	enum imx_esdhc_type devtype;
	struct pinctrl *pinctrl;
	struct esdhc_platform_data boarddata;
	struct clk *clk_ipg;
	struct clk *clk_ahb;
	struct clk *clk_per;
};

static struct platform_device_id imx_esdhc_devtype[] = {
	{
		.name = "sdhci-esdhc-imx25",
		.driver_data = IMX25_ESDHC,
	}, {
		.name = "sdhci-esdhc-imx35",
		.driver_data = IMX35_ESDHC,
	}, {
		.name = "sdhci-esdhc-imx51",
		.driver_data = IMX51_ESDHC,
	}, {
		.name = "sdhci-esdhc-imx53",
		.driver_data = IMX53_ESDHC,
	}, {
		.name = "sdhci-usdhc-imx6q",
		.driver_data = IMX6Q_USDHC,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);

static const struct of_device_id imx_esdhc_dt_ids[] = {
	{ .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], },
	{ .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], },
	{ .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], },
	{ .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], },
	{ .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);

static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
{
	return data->devtype == IMX25_ESDHC;
}

static inline int is_imx35_esdhc(struct pltfm_imx_data *data)
{
	return data->devtype == IMX35_ESDHC;
}

static inline int is_imx51_esdhc(struct pltfm_imx_data *data)
{
	return data->devtype == IMX51_ESDHC;
}

static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
{
	return data->devtype == IMX53_ESDHC;
}

static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
{
	return data->devtype == IMX6Q_USDHC;
}

static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
{
	void __iomem *base = host->ioaddr + (reg & ~0x3);
	u32 shift = (reg & 0x3) * 8;

	writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
}

static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
{
	u32 val = readl(host->ioaddr + reg);

	if (unlikely(reg == SDHCI_CAPABILITIES)) {
		/* In FSL esdhc IC module, only bit20 is used to indicate the
		 * ADMA2 capability of esdhc, but this bit is messed up on
		 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
		 * don't actually support ADMA2). So set the BROKEN_ADMA
		 * uirk on MX25/35 platforms.
		 */

		if (val & SDHCI_CAN_DO_ADMA1) {
			val &= ~SDHCI_CAN_DO_ADMA1;
			val |= SDHCI_CAN_DO_ADMA2;
		}
	}

	if (unlikely(reg == SDHCI_INT_STATUS)) {
		if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
			val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
			val |= SDHCI_INT_ADMA_ERROR;
		}
	}

	return val;
}

static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct pltfm_imx_data *imx_data = pltfm_host->priv;
	u32 data;

	if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
		if (val & SDHCI_INT_CARD_INT) {
			/*
			 * Clear and then set D3CD bit to avoid missing the
			 * card interrupt.  This is a eSDHC controller problem
			 * so we need to apply the following workaround: clear
			 * and set D3CD bit will make eSDHC re-sample the card
			 * interrupt. In case a card interrupt was lost,
			 * re-sample it by the following steps.
			 */
			data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
			data &= ~ESDHC_CTRL_D3CD;
			writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
			data |= ESDHC_CTRL_D3CD;
			writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
		}
	}

	if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
				&& (reg == SDHCI_INT_STATUS)
				&& (val & SDHCI_INT_DATA_END))) {
			u32 v;
			v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
			v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
			writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
	}

	if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
		if (val & SDHCI_INT_ADMA_ERROR) {
			val &= ~SDHCI_INT_ADMA_ERROR;
			val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
		}
	}

	writel(val, host->ioaddr + reg);
}

static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct pltfm_imx_data *imx_data = pltfm_host->priv;

	if (unlikely(reg == SDHCI_HOST_VERSION)) {
		reg ^= 2;
		if (is_imx6q_usdhc(imx_data)) {
			/*
			 * The usdhc register returns a wrong host version.
			 * Correct it here.
			 */
			return SDHCI_SPEC_300;
		}
	}

	return readw(host->ioaddr + reg);
}

static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct pltfm_imx_data *imx_data = pltfm_host->priv;

	switch (reg) {
	case SDHCI_TRANSFER_MODE:
		if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
				&& (host->cmd->opcode == SD_IO_RW_EXTENDED)
				&& (host->cmd->data->blocks > 1)
				&& (host->cmd->data->flags & MMC_DATA_READ)) {
			u32 v;
			v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
			v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
			writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
		}

		if (is_imx6q_usdhc(imx_data)) {
			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
			m = val | (m & 0xffff0000);
			writel(m, host->ioaddr + ESDHC_MIX_CTRL);
		} else {
			/*
			 * Postpone this write, we must do it together with a
			 * command write that is down below.
			 */
			imx_data->scratchpad = val;
		}
		return;
	case SDHCI_COMMAND:
		if ((host->cmd->opcode == MMC_STOP_TRANSMISSION ||
		     host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
	            (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
			val |= SDHCI_CMD_ABORTCMD;

		if (is_imx6q_usdhc(imx_data))
			writel(val << 16,
			       host->ioaddr + SDHCI_TRANSFER_MODE);
		else
			writel(val << 16 | imx_data->scratchpad,
			       host->ioaddr + SDHCI_TRANSFER_MODE);
		return;
	case SDHCI_BLOCK_SIZE:
		val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
		break;
	}
	esdhc_clrset_le(host, 0xffff, val, reg);
}

static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct pltfm_imx_data *imx_data = pltfm_host->priv;
	u32 new_val;

	switch (reg) {
	case SDHCI_POWER_CONTROL:
		/*
		 * FSL put some DMA bits here
		 * If your board has a regulator, code should be here
		 */
		return;
	case SDHCI_HOST_CONTROL:
		/* FSL messed up here, so we need to manually compose it. */
		new_val = val & (SDHCI_CTRL_LED | SDHCI_CTRL_4BITBUS);
		/* ensure the endianness */
		new_val |= ESDHC_HOST_CONTROL_LE;
		/* bits 8&9 are reserved on mx25 */
		if (!is_imx25_esdhc(imx_data)) {
			/* DMA mode bits are shifted */
			new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
		}

		esdhc_clrset_le(host, 0xffff, new_val, reg);
		return;
	}
	esdhc_clrset_le(host, 0xff, val, reg);

	/*
	 * The esdhc has a design violation to SDHC spec which tells
	 * that software reset should not affect card detection circuit.
	 * But esdhc clears its SYSCTL register bits [0..2] during the
	 * software reset.  This will stop those clocks that card detection
	 * circuit relies on.  To work around it, we turn the clocks on back
	 * to keep card detection circuit functional.
	 */
	if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
		esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
		/*
		 * The reset on usdhc fails to clear MIX_CTRL register.
		 * Do it manually here.
		 */
		if (is_imx6q_usdhc(imx_data))
			writel(0, host->ioaddr + ESDHC_MIX_CTRL);
	}
}

static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	return clk_get_rate(pltfm_host->clk);
}

static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	return clk_get_rate(pltfm_host->clk) / 256 / 16;
}

static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct pltfm_imx_data *imx_data = pltfm_host->priv;
	struct esdhc_platform_data *boarddata = &imx_data->boarddata;

	switch (boarddata->wp_type) {
	case ESDHC_WP_GPIO:
		return mmc_gpio_get_ro(host->mmc);
	case ESDHC_WP_CONTROLLER:
		return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
			       SDHCI_WRITE_PROTECT);
	case ESDHC_WP_NONE:
		break;
	}

	return -ENOSYS;
}

static struct sdhci_ops sdhci_esdhc_ops = {
	.read_l = esdhc_readl_le,
	.read_w = esdhc_readw_le,
	.write_l = esdhc_writel_le,
	.write_w = esdhc_writew_le,
	.write_b = esdhc_writeb_le,
	.set_clock = esdhc_set_clock,
	.get_max_clock = esdhc_pltfm_get_max_clock,
	.get_min_clock = esdhc_pltfm_get_min_clock,
	.get_ro = esdhc_pltfm_get_ro,
};

static struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
	.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
			| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
			| SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
			| SDHCI_QUIRK_BROKEN_CARD_DETECTION,
	.ops = &sdhci_esdhc_ops,
};

#ifdef CONFIG_OF
static int
sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
			 struct esdhc_platform_data *boarddata)
{
	struct device_node *np = pdev->dev.of_node;

	if (!np)
		return -ENODEV;

	if (of_get_property(np, "non-removable", NULL))
		boarddata->cd_type = ESDHC_CD_PERMANENT;

	if (of_get_property(np, "fsl,cd-controller", NULL))
		boarddata->cd_type = ESDHC_CD_CONTROLLER;

	if (of_get_property(np, "fsl,wp-controller", NULL))
		boarddata->wp_type = ESDHC_WP_CONTROLLER;

	boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
	if (gpio_is_valid(boarddata->cd_gpio))
		boarddata->cd_type = ESDHC_CD_GPIO;

	boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
	if (gpio_is_valid(boarddata->wp_gpio))
		boarddata->wp_type = ESDHC_WP_GPIO;

	return 0;
}
#else
static inline int
sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
			 struct esdhc_platform_data *boarddata)
{
	return -ENODEV;
}
#endif

static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(imx_esdhc_dt_ids, &pdev->dev);
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_host *host;
	struct esdhc_platform_data *boarddata;
	int err;
	struct pltfm_imx_data *imx_data;

	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata);
	if (IS_ERR(host))
		return PTR_ERR(host);

	pltfm_host = sdhci_priv(host);

	imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
	if (!imx_data) {
		err = -ENOMEM;
		goto free_sdhci;
	}

	if (of_id)
		pdev->id_entry = of_id->data;
	imx_data->devtype = pdev->id_entry->driver_data;
	pltfm_host->priv = imx_data;

	imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(imx_data->clk_ipg)) {
		err = PTR_ERR(imx_data->clk_ipg);
		goto free_sdhci;
	}

	imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
	if (IS_ERR(imx_data->clk_ahb)) {
		err = PTR_ERR(imx_data->clk_ahb);
		goto free_sdhci;
	}

	imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
	if (IS_ERR(imx_data->clk_per)) {
		err = PTR_ERR(imx_data->clk_per);
		goto free_sdhci;
	}

	pltfm_host->clk = imx_data->clk_per;

	clk_prepare_enable(imx_data->clk_per);
	clk_prepare_enable(imx_data->clk_ipg);
	clk_prepare_enable(imx_data->clk_ahb);

	imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
	if (IS_ERR(imx_data->pinctrl)) {
		err = PTR_ERR(imx_data->pinctrl);
		goto disable_clk;
	}

	host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;

	if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
		/* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
		host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
			| SDHCI_QUIRK_BROKEN_ADMA;

	if (is_imx53_esdhc(imx_data))
		imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;

	/*
	 * The imx6q ROM code will change the default watermark level setting
	 * to something insane.  Change it back here.
	 */
	if (is_imx6q_usdhc(imx_data))
		writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);

	boarddata = &imx_data->boarddata;
	if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
		if (!host->mmc->parent->platform_data) {
			dev_err(mmc_dev(host->mmc), "no board data!\n");
			err = -EINVAL;
			goto disable_clk;
		}
		imx_data->boarddata = *((struct esdhc_platform_data *)
					host->mmc->parent->platform_data);
	}

	/* write_protect */
	if (boarddata->wp_type == ESDHC_WP_GPIO) {
		err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
		if (err) {
			dev_err(mmc_dev(host->mmc),
				"failed to request write-protect gpio!\n");
			goto disable_clk;
		}
		host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
	}

	/* card_detect */
	switch (boarddata->cd_type) {
	case ESDHC_CD_GPIO:
		err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio);
		if (err) {
			dev_err(mmc_dev(host->mmc),
				"failed to request card-detect gpio!\n");
			goto disable_clk;
		}
		/* fall through */

	case ESDHC_CD_CONTROLLER:
		/* we have a working card_detect back */
		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
		break;

	case ESDHC_CD_PERMANENT:
		host->mmc->caps = MMC_CAP_NONREMOVABLE;
		break;

	case ESDHC_CD_NONE:
		break;
	}

	err = sdhci_add_host(host);
	if (err)
		goto disable_clk;

	return 0;

disable_clk:
	clk_disable_unprepare(imx_data->clk_per);
	clk_disable_unprepare(imx_data->clk_ipg);
	clk_disable_unprepare(imx_data->clk_ahb);
free_sdhci:
	sdhci_pltfm_free(pdev);
	return err;
}

static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct pltfm_imx_data *imx_data = pltfm_host->priv;
	int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);

	sdhci_remove_host(host, dead);

	clk_disable_unprepare(imx_data->clk_per);
	clk_disable_unprepare(imx_data->clk_ipg);
	clk_disable_unprepare(imx_data->clk_ahb);

	sdhci_pltfm_free(pdev);

	return 0;
}

static struct platform_driver sdhci_esdhc_imx_driver = {
	.driver		= {
		.name	= "sdhci-esdhc-imx",
		.owner	= THIS_MODULE,
		.of_match_table = imx_esdhc_dt_ids,
		.pm	= SDHCI_PLTFM_PMOPS,
	},
	.id_table	= imx_esdhc_devtype,
	.probe		= sdhci_esdhc_imx_probe,
	.remove		= sdhci_esdhc_imx_remove,
};

module_platform_driver(sdhci_esdhc_imx_driver);

MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
95f25efe WS	1	/*
	2	* Freescale eSDHC i.MX controller driver for the platform bus.
	3	*
	4	* derived from the OF-version.
	5	*
	6	* Copyright (c) 2010 Pengutronix e.K.
	7	* Author: Wolfram Sang <w.sang@pengutronix.de>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License.
	12	*/
	13
	14	#include <linux/io.h>
	15	#include <linux/delay.h>
	16	#include <linux/err.h>
	17	#include <linux/clk.h>
0c6d49ce	18	#include <linux/gpio.h>
66506f76	19	#include <linux/module.h>
e149860d	20	#include <linux/slab.h>
95f25efe	21	#include <linux/mmc/host.h>
58ac8177 RZ	22	#include <linux/mmc/mmc.h>
58ac8177 RZ	23	#include <linux/mmc/sdio.h>
fbe5fdd1	24	#include <linux/mmc/slot-gpio.h>
abfafc2d SG	25	#include <linux/of.h>
	26	#include <linux/of_device.h>
	27	#include <linux/of_gpio.h>
e62d8b8f	28	#include <linux/pinctrl/consumer.h>
82906b13	29	#include <linux/platform_data/mmc-esdhc-imx.h>
95f25efe WS	30	#include "sdhci-pltfm.h"
	31	#include "sdhci-esdhc.h"
	32
60bf6396	33	#define ESDHC_CTRL_D3CD 0x08
58ac8177	34	/* VENDOR SPEC register */
60bf6396 SG	35	#define ESDHC_VENDOR_SPEC 0xc0
	36	#define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
	37	#define ESDHC_WTMK_LVL 0x44
	38	#define ESDHC_MIX_CTRL 0x48
58ac8177	39
97e4ba6a RZ	40	/*
	41	* There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
	42	* Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
	43	* but bit28 is used as the INT DMA ERR in fsl eSDHC design.
	44	* Define this macro DMA error INT for fsl eSDHC
	45	*/
60bf6396	46	#define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
97e4ba6a	47
58ac8177 RZ	48	/*
	49	* The CMDTYPE of the CMD register (offset 0xE) should be set to
	50	* "11" when the STOP CMD12 is issued on imx53 to abort one
	51	* open ended multi-blk IO. Otherwise the TC INT wouldn't
	52	* be generated.
	53	* In exact block transfer, the controller doesn't complete the
	54	* operations automatically as required at the end of the
	55	* transfer and remains on hold if the abort command is not sent.
	56	* As a result, the TC flag is not asserted and SW received timeout
	57	* exeception. Bit1 of Vendor Spec registor is used to fix it.
	58	*/
	59	#define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1)
e149860d	60
57ed3314 SG	61	enum imx_esdhc_type {
	62	IMX25_ESDHC,
	63	IMX35_ESDHC,
	64	IMX51_ESDHC,
	65	IMX53_ESDHC,
95a2482a	66	IMX6Q_USDHC,
57ed3314 SG	67	};
57ed3314 SG	68
e149860d RZ	69	struct pltfm_imx_data {
	70	int flags;
	71	u32 scratchpad;
57ed3314	72	enum imx_esdhc_type devtype;
e62d8b8f	73	struct pinctrl *pinctrl;
842afc02	74	struct esdhc_platform_data boarddata;
52dac615 SH	75	struct clk *clk_ipg;
	76	struct clk *clk_ahb;
	77	struct clk *clk_per;
e149860d RZ	78	};
e149860d RZ	79
57ed3314 SG	80	static struct platform_device_id imx_esdhc_devtype[] = {
	81	{
	82	.name = "sdhci-esdhc-imx25",
	83	.driver_data = IMX25_ESDHC,
	84	}, {
	85	.name = "sdhci-esdhc-imx35",
	86	.driver_data = IMX35_ESDHC,
	87	}, {
	88	.name = "sdhci-esdhc-imx51",
	89	.driver_data = IMX51_ESDHC,
	90	}, {
	91	.name = "sdhci-esdhc-imx53",
	92	.driver_data = IMX53_ESDHC,
95a2482a SG	93	}, {
	94	.name = "sdhci-usdhc-imx6q",
	95	.driver_data = IMX6Q_USDHC,
57ed3314 SG	96	}, {
	97	/* sentinel */
	98	}
	99	};
	100	MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
	101
abfafc2d SG	102	static const struct of_device_id imx_esdhc_dt_ids[] = {
	103	{ .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], },
	104	{ .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], },
	105	{ .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], },
	106	{ .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], },
95a2482a	107	{ .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], },
abfafc2d SG	108	{ /* sentinel */ }
	109	};
	110	MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
	111
57ed3314 SG	112	static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
	113	{
	114	return data->devtype == IMX25_ESDHC;
	115	}
	116
	117	static inline int is_imx35_esdhc(struct pltfm_imx_data *data)
	118	{
	119	return data->devtype == IMX35_ESDHC;
	120	}
	121
	122	static inline int is_imx51_esdhc(struct pltfm_imx_data *data)
	123	{
	124	return data->devtype == IMX51_ESDHC;
	125	}
	126
	127	static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
	128	{
	129	return data->devtype == IMX53_ESDHC;
	130	}
	131
95a2482a SG	132	static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
	133	{
	134	return data->devtype == IMX6Q_USDHC;
	135	}
	136
95f25efe WS	137	static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
	138	{
	139	void __iomem *base = host->ioaddr + (reg & ~0x3);
	140	u32 shift = (reg & 0x3) * 8;
	141
	142	writel(((readl(base) & ~(mask << shift)) \| (val << shift)), base);
	143	}
	144
7e29c306 WS	145	static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
7e29c306 WS	146	{
7e29c306 WS	147	u32 val = readl(host->ioaddr + reg);
7e29c306 WS	148
97e4ba6a RZ	149	if (unlikely(reg == SDHCI_CAPABILITIES)) {
	150	/* In FSL esdhc IC module, only bit20 is used to indicate the
	151	* ADMA2 capability of esdhc, but this bit is messed up on
	152	* some SOCs (e.g. on MX25, MX35 this bit is set, but they
	153	* don't actually support ADMA2). So set the BROKEN_ADMA
	154	* uirk on MX25/35 platforms.
	155	*/
	156
	157	if (val & SDHCI_CAN_DO_ADMA1) {
	158	val &= ~SDHCI_CAN_DO_ADMA1;
	159	val \|= SDHCI_CAN_DO_ADMA2;
	160	}
	161	}
	162
	163	if (unlikely(reg == SDHCI_INT_STATUS)) {
60bf6396 SG	164	if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
60bf6396 SG	165	val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
97e4ba6a RZ	166	val \|= SDHCI_INT_ADMA_ERROR;
	167	}
	168	}
	169
7e29c306 WS	170	return val;
	171	}
	172
	173	static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
	174	{
e149860d RZ	175	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
e149860d RZ	176	struct pltfm_imx_data *imx_data = pltfm_host->priv;
0d58864b TL	177	u32 data;
	178
	179	if (unlikely(reg == SDHCI_INT_ENABLE \|\| reg == SDHCI_SIGNAL_ENABLE)) {
0d58864b TL	180	if (val & SDHCI_INT_CARD_INT) {
	181	/*
	182	* Clear and then set D3CD bit to avoid missing the
	183	* card interrupt. This is a eSDHC controller problem
	184	* so we need to apply the following workaround: clear
	185	* and set D3CD bit will make eSDHC re-sample the card
	186	* interrupt. In case a card interrupt was lost,
	187	* re-sample it by the following steps.
	188	*/
	189	data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
60bf6396	190	data &= ~ESDHC_CTRL_D3CD;
0d58864b	191	writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
60bf6396	192	data \|= ESDHC_CTRL_D3CD;
0d58864b TL	193	writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
	194	}
	195	}
7e29c306	196
58ac8177 RZ	197	if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
	198	&& (reg == SDHCI_INT_STATUS)
	199	&& (val & SDHCI_INT_DATA_END))) {
	200	u32 v;
60bf6396 SG	201	v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
	202	v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
	203	writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
58ac8177 RZ	204	}
58ac8177 RZ	205
97e4ba6a RZ	206	if (unlikely(reg == SDHCI_INT_ENABLE \|\| reg == SDHCI_SIGNAL_ENABLE)) {
	207	if (val & SDHCI_INT_ADMA_ERROR) {
	208	val &= ~SDHCI_INT_ADMA_ERROR;
60bf6396	209	val \|= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
97e4ba6a RZ	210	}
	211	}
	212
7e29c306 WS	213	writel(val, host->ioaddr + reg);
	214	}
	215
95f25efe WS	216	static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
95f25efe WS	217	{
ef4d0888 SG	218	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	219	struct pltfm_imx_data *imx_data = pltfm_host->priv;
	220
95a2482a	221	if (unlikely(reg == SDHCI_HOST_VERSION)) {
ef4d0888 SG	222	reg ^= 2;
	223	if (is_imx6q_usdhc(imx_data)) {
	224	/*
	225	* The usdhc register returns a wrong host version.
	226	* Correct it here.
	227	*/
	228	return SDHCI_SPEC_300;
	229	}
95a2482a	230	}
95f25efe WS	231
	232	return readw(host->ioaddr + reg);
	233	}
	234
	235	static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
	236	{
	237	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
e149860d	238	struct pltfm_imx_data *imx_data = pltfm_host->priv;
95f25efe WS	239
	240	switch (reg) {
	241	case SDHCI_TRANSFER_MODE:
58ac8177 RZ	242	if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
	243	&& (host->cmd->opcode == SD_IO_RW_EXTENDED)
	244	&& (host->cmd->data->blocks > 1)
	245	&& (host->cmd->data->flags & MMC_DATA_READ)) {
	246	u32 v;
60bf6396 SG	247	v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
	248	v \|= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
	249	writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
58ac8177	250	}
69f54698 SG	251
	252	if (is_imx6q_usdhc(imx_data)) {
	253	u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
	254	m = val \| (m & 0xffff0000);
	255	writel(m, host->ioaddr + ESDHC_MIX_CTRL);
	256	} else {
	257	/*
	258	* Postpone this write, we must do it together with a
	259	* command write that is down below.
	260	*/
	261	imx_data->scratchpad = val;
	262	}
95f25efe WS	263	return;
95f25efe WS	264	case SDHCI_COMMAND:
5b6b0ad6 SH	265	if ((host->cmd->opcode == MMC_STOP_TRANSMISSION \|\|
	266	host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
	267	(imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
58ac8177	268	val \|= SDHCI_CMD_ABORTCMD;
95a2482a	269
69f54698	270	if (is_imx6q_usdhc(imx_data))
95a2482a SG	271	writel(val << 16,
95a2482a SG	272	host->ioaddr + SDHCI_TRANSFER_MODE);
69f54698	273	else
95a2482a SG	274	writel(val << 16 \| imx_data->scratchpad,
95a2482a SG	275	host->ioaddr + SDHCI_TRANSFER_MODE);
95f25efe WS	276	return;
	277	case SDHCI_BLOCK_SIZE:
	278	val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
	279	break;
	280	}
	281	esdhc_clrset_le(host, 0xffff, val, reg);
	282	}
	283
	284	static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
	285	{
9a0985b7 WC	286	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
9a0985b7 WC	287	struct pltfm_imx_data *imx_data = pltfm_host->priv;
95f25efe WS	288	u32 new_val;
	289
	290	switch (reg) {
	291	case SDHCI_POWER_CONTROL:
	292	/*
	293	* FSL put some DMA bits here
	294	* If your board has a regulator, code should be here
	295	*/
	296	return;
	297	case SDHCI_HOST_CONTROL:
6b40d182 SG	298	/* FSL messed up here, so we need to manually compose it. */
6b40d182 SG	299	new_val = val & (SDHCI_CTRL_LED \| SDHCI_CTRL_4BITBUS);
7122bbb0	300	/* ensure the endianness */
95f25efe	301	new_val \|= ESDHC_HOST_CONTROL_LE;
9a0985b7 WC	302	/* bits 8&9 are reserved on mx25 */
	303	if (!is_imx25_esdhc(imx_data)) {
	304	/* DMA mode bits are shifted */
	305	new_val \|= (val & SDHCI_CTRL_DMA_MASK) << 5;
	306	}
95f25efe WS	307
	308	esdhc_clrset_le(host, 0xffff, new_val, reg);
	309	return;
	310	}
	311	esdhc_clrset_le(host, 0xff, val, reg);
913413c3 SG	312
	313	/*
	314	* The esdhc has a design violation to SDHC spec which tells
	315	* that software reset should not affect card detection circuit.
	316	* But esdhc clears its SYSCTL register bits [0..2] during the
	317	* software reset. This will stop those clocks that card detection
	318	* circuit relies on. To work around it, we turn the clocks on back
	319	* to keep card detection circuit functional.
	320	*/
58c8c4fb	321	if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
913413c3	322	esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
58c8c4fb SG	323	/*
	324	* The reset on usdhc fails to clear MIX_CTRL register.
	325	* Do it manually here.
	326	*/
	327	if (is_imx6q_usdhc(imx_data))
	328	writel(0, host->ioaddr + ESDHC_MIX_CTRL);
	329	}
95f25efe WS	330	}
	331
	332	static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
	333	{
	334	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	335
	336	return clk_get_rate(pltfm_host->clk);
	337	}
	338
	339	static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
	340	{
	341	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	342
	343	return clk_get_rate(pltfm_host->clk) / 256 / 16;
	344	}
	345
913413c3 SG	346	static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
913413c3 SG	347	{
842afc02 SG	348	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	349	struct pltfm_imx_data *imx_data = pltfm_host->priv;
	350	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
913413c3 SG	351
	352	switch (boarddata->wp_type) {
	353	case ESDHC_WP_GPIO:
fbe5fdd1	354	return mmc_gpio_get_ro(host->mmc);
913413c3 SG	355	case ESDHC_WP_CONTROLLER:
	356	return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
	357	SDHCI_WRITE_PROTECT);
	358	case ESDHC_WP_NONE:
	359	break;
	360	}
	361
	362	return -ENOSYS;
	363	}
	364
0c6d49ce	365	static struct sdhci_ops sdhci_esdhc_ops = {
e149860d	366	.read_l = esdhc_readl_le,
0c6d49ce	367	.read_w = esdhc_readw_le,
e149860d	368	.write_l = esdhc_writel_le,
0c6d49ce WS	369	.write_w = esdhc_writew_le,
	370	.write_b = esdhc_writeb_le,
	371	.set_clock = esdhc_set_clock,
	372	.get_max_clock = esdhc_pltfm_get_max_clock,
	373	.get_min_clock = esdhc_pltfm_get_min_clock,
913413c3	374	.get_ro = esdhc_pltfm_get_ro,
0c6d49ce WS	375	};
0c6d49ce WS	376
85d6509d	377	static struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
97e4ba6a RZ	378	.quirks = ESDHC_DEFAULT_QUIRKS \| SDHCI_QUIRK_NO_HISPD_BIT
	379	\| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
	380	\| SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
85d6509d	381	\| SDHCI_QUIRK_BROKEN_CARD_DETECTION,
85d6509d SG	382	.ops = &sdhci_esdhc_ops,
	383	};
	384
abfafc2d	385	#ifdef CONFIG_OF
c3be1efd	386	static int
abfafc2d SG	387	sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
	388	struct esdhc_platform_data *boarddata)
	389	{
	390	struct device_node *np = pdev->dev.of_node;
	391
	392	if (!np)
	393	return -ENODEV;
	394
7f217794	395	if (of_get_property(np, "non-removable", NULL))
abfafc2d SG	396	boarddata->cd_type = ESDHC_CD_PERMANENT;
	397
	398	if (of_get_property(np, "fsl,cd-controller", NULL))
	399	boarddata->cd_type = ESDHC_CD_CONTROLLER;
	400
	401	if (of_get_property(np, "fsl,wp-controller", NULL))
	402	boarddata->wp_type = ESDHC_WP_CONTROLLER;
	403
	404	boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
	405	if (gpio_is_valid(boarddata->cd_gpio))
	406	boarddata->cd_type = ESDHC_CD_GPIO;
	407
	408	boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
	409	if (gpio_is_valid(boarddata->wp_gpio))
	410	boarddata->wp_type = ESDHC_WP_GPIO;
	411
	412	return 0;
	413	}
	414	#else
	415	static inline int
	416	sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
	417	struct esdhc_platform_data *boarddata)
	418	{
	419	return -ENODEV;
	420	}
	421	#endif
	422
c3be1efd	423	static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
95f25efe	424	{
abfafc2d SG	425	const struct of_device_id *of_id =
abfafc2d SG	426	of_match_device(imx_esdhc_dt_ids, &pdev->dev);
85d6509d SG	427	struct sdhci_pltfm_host *pltfm_host;
	428	struct sdhci_host *host;
	429	struct esdhc_platform_data *boarddata;
0c6d49ce	430	int err;
e149860d	431	struct pltfm_imx_data *imx_data;
95f25efe	432
85d6509d SG	433	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata);
	434	if (IS_ERR(host))
	435	return PTR_ERR(host);
	436
	437	pltfm_host = sdhci_priv(host);
	438
e3af31c6	439	imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
abfafc2d SG	440	if (!imx_data) {
abfafc2d SG	441	err = -ENOMEM;
e3af31c6	442	goto free_sdhci;
abfafc2d	443	}
57ed3314	444
abfafc2d SG	445	if (of_id)
abfafc2d SG	446	pdev->id_entry = of_id->data;
57ed3314	447	imx_data->devtype = pdev->id_entry->driver_data;
85d6509d SG	448	pltfm_host->priv = imx_data;
85d6509d SG	449
52dac615 SH	450	imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	451	if (IS_ERR(imx_data->clk_ipg)) {
	452	err = PTR_ERR(imx_data->clk_ipg);
e3af31c6	453	goto free_sdhci;
95f25efe	454	}
52dac615 SH	455
	456	imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
	457	if (IS_ERR(imx_data->clk_ahb)) {
	458	err = PTR_ERR(imx_data->clk_ahb);
e3af31c6	459	goto free_sdhci;
52dac615 SH	460	}
	461
	462	imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
	463	if (IS_ERR(imx_data->clk_per)) {
	464	err = PTR_ERR(imx_data->clk_per);
e3af31c6	465	goto free_sdhci;
52dac615 SH	466	}
	467
	468	pltfm_host->clk = imx_data->clk_per;
	469
	470	clk_prepare_enable(imx_data->clk_per);
	471	clk_prepare_enable(imx_data->clk_ipg);
	472	clk_prepare_enable(imx_data->clk_ahb);
95f25efe	473
e62d8b8f DA	474	imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
	475	if (IS_ERR(imx_data->pinctrl)) {
	476	err = PTR_ERR(imx_data->pinctrl);
e3af31c6	477	goto disable_clk;
e62d8b8f DA	478	}
e62d8b8f DA	479
b8915282	480	host->quirks \|= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
37865fe9	481
57ed3314	482	if (is_imx25_esdhc(imx_data) \|\| is_imx35_esdhc(imx_data))
0c6d49ce	483	/* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
97e4ba6a RZ	484	host->quirks \|= SDHCI_QUIRK_NO_MULTIBLOCK
97e4ba6a RZ	485	\| SDHCI_QUIRK_BROKEN_ADMA;
0c6d49ce	486
57ed3314	487	if (is_imx53_esdhc(imx_data))
58ac8177 RZ	488	imx_data->flags \|= ESDHC_FLAG_MULTIBLK_NO_INT;
58ac8177 RZ	489
f750ba9b SG	490	/*
	491	* The imx6q ROM code will change the default watermark level setting
	492	* to something insane. Change it back here.
	493	*/
	494	if (is_imx6q_usdhc(imx_data))
60bf6396	495	writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
f750ba9b	496
842afc02	497	boarddata = &imx_data->boarddata;
abfafc2d SG	498	if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
	499	if (!host->mmc->parent->platform_data) {
	500	dev_err(mmc_dev(host->mmc), "no board data!\n");
	501	err = -EINVAL;
e3af31c6	502	goto disable_clk;
abfafc2d SG	503	}
	504	imx_data->boarddata = ((struct esdhc_platform_data )
	505	host->mmc->parent->platform_data);
	506	}
913413c3 SG	507
	508	/* write_protect */
	509	if (boarddata->wp_type == ESDHC_WP_GPIO) {
fbe5fdd1	510	err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
0c6d49ce	511	if (err) {
fbe5fdd1 SG	512	dev_err(mmc_dev(host->mmc),
	513	"failed to request write-protect gpio!\n");
	514	goto disable_clk;
0c6d49ce	515	}
fbe5fdd1	516	host->mmc->caps2 \|= MMC_CAP2_RO_ACTIVE_HIGH;
913413c3 SG	517	}
	518
	519	/* card_detect */
913413c3 SG	520	switch (boarddata->cd_type) {
913413c3 SG	521	case ESDHC_CD_GPIO:
fbe5fdd1	522	err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio);
7e29c306	523	if (err) {
913413c3	524	dev_err(mmc_dev(host->mmc),
fbe5fdd1	525	"failed to request card-detect gpio!\n");
e3af31c6	526	goto disable_clk;
7e29c306	527	}
913413c3	528	/* fall through */
7e29c306	529
913413c3 SG	530	case ESDHC_CD_CONTROLLER:
913413c3 SG	531	/* we have a working card_detect back */
7e29c306	532	host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
913413c3 SG	533	break;
	534
	535	case ESDHC_CD_PERMANENT:
	536	host->mmc->caps = MMC_CAP_NONREMOVABLE;
	537	break;
	538
	539	case ESDHC_CD_NONE:
	540	break;
0c6d49ce	541	}
16a790bc	542
85d6509d SG	543	err = sdhci_add_host(host);
85d6509d SG	544	if (err)
e3af31c6	545	goto disable_clk;
85d6509d	546
95f25efe	547	return 0;
7e29c306	548
e3af31c6	549	disable_clk:
52dac615 SH	550	clk_disable_unprepare(imx_data->clk_per);
	551	clk_disable_unprepare(imx_data->clk_ipg);
	552	clk_disable_unprepare(imx_data->clk_ahb);
e3af31c6	553	free_sdhci:
85d6509d SG	554	sdhci_pltfm_free(pdev);
85d6509d SG	555	return err;
95f25efe WS	556	}
95f25efe WS	557
6e0ee714	558	static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
95f25efe	559	{
85d6509d	560	struct sdhci_host *host = platform_get_drvdata(pdev);
95f25efe	561	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
e149860d	562	struct pltfm_imx_data *imx_data = pltfm_host->priv;
85d6509d SG	563	int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
	564
	565	sdhci_remove_host(host, dead);
0c6d49ce	566
52dac615 SH	567	clk_disable_unprepare(imx_data->clk_per);
	568	clk_disable_unprepare(imx_data->clk_ipg);
	569	clk_disable_unprepare(imx_data->clk_ahb);
	570
85d6509d SG	571	sdhci_pltfm_free(pdev);
	572
	573	return 0;
95f25efe WS	574	}
95f25efe WS	575
85d6509d SG	576	static struct platform_driver sdhci_esdhc_imx_driver = {
	577	.driver = {
	578	.name = "sdhci-esdhc-imx",
	579	.owner = THIS_MODULE,
abfafc2d	580	.of_match_table = imx_esdhc_dt_ids,
29495aa0	581	.pm = SDHCI_PLTFM_PMOPS,
85d6509d	582	},
57ed3314	583	.id_table = imx_esdhc_devtype,
85d6509d	584	.probe = sdhci_esdhc_imx_probe,
0433c143	585	.remove = sdhci_esdhc_imx_remove,
95f25efe	586	};
85d6509d	587
d1f81a64	588	module_platform_driver(sdhci_esdhc_imx_driver);
85d6509d SG	589
	590	MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
	591	MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
	592	MODULE_LICENSE("GPL v2");