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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc
[linux-2.6-block.git] / drivers / mmc / host / mxcmmc.c
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d96be879
SH		 1/*
2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
3 *
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
3ad2f3fb 7 * not need all the quirks found in imxmmc.c, hence the separate driver.
d96be879
SH		 8 *
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
11 *
12 * derived from pxamci.c by Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/blkdev.h>
27#include <linux/dma-mapping.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/card.h>
30#include <linux/delay.h>
31#include <linux/clk.h>
32#include <linux/io.h>
33#include <linux/gpio.h>
74b66954 34#include <linux/regulator/consumer.h>
f53fbde4 35#include <linux/dmaengine.h>
258aea76 36#include <linux/types.h>
7ff747c4
MP		 37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_dma.h>
40#include <linux/of_gpio.h>
bcf53524 41#include <linux/mmc/slot-gpio.h>
d96be879
SH		 42
43#include <asm/dma.h>
44#include <asm/irq.h>
82906b13 45#include <linux/platform_data/mmc-mxcmmc.h>
d96be879 46
82906b13 47#include <linux/platform_data/dma-imx.h>
d96be879 48
9563b1db 49#define DRIVER_NAME "mxc-mmc"
f6ad0a48 50#define MXCMCI_TIMEOUT_MS 10000
d96be879
SH		 51
52#define MMC_REG_STR_STP_CLK 0x00
53#define MMC_REG_STATUS 0x04
54#define MMC_REG_CLK_RATE 0x08
55#define MMC_REG_CMD_DAT_CONT 0x0C
56#define MMC_REG_RES_TO 0x10
57#define MMC_REG_READ_TO 0x14
58#define MMC_REG_BLK_LEN 0x18
59#define MMC_REG_NOB 0x1C
60#define MMC_REG_REV_NO 0x20
61#define MMC_REG_INT_CNTR 0x24
62#define MMC_REG_CMD 0x28
63#define MMC_REG_ARG 0x2C
64#define MMC_REG_RES_FIFO 0x34
65#define MMC_REG_BUFFER_ACCESS 0x38
66
67#define STR_STP_CLK_RESET (1 << 3)
68#define STR_STP_CLK_START_CLK (1 << 1)
69#define STR_STP_CLK_STOP_CLK (1 << 0)
70
71#define STATUS_CARD_INSERTION (1 << 31)
72#define STATUS_CARD_REMOVAL (1 << 30)
73#define STATUS_YBUF_EMPTY (1 << 29)
74#define STATUS_XBUF_EMPTY (1 << 28)
75#define STATUS_YBUF_FULL (1 << 27)
76#define STATUS_XBUF_FULL (1 << 26)
77#define STATUS_BUF_UND_RUN (1 << 25)
78#define STATUS_BUF_OVFL (1 << 24)
79#define STATUS_SDIO_INT_ACTIVE (1 << 14)
80#define STATUS_END_CMD_RESP (1 << 13)
81#define STATUS_WRITE_OP_DONE (1 << 12)
82#define STATUS_DATA_TRANS_DONE (1 << 11)
83#define STATUS_READ_OP_DONE (1 << 11)
84#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
85#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
86#define STATUS_BUF_READ_RDY (1 << 7)
87#define STATUS_BUF_WRITE_RDY (1 << 6)
88#define STATUS_RESP_CRC_ERR (1 << 5)
89#define STATUS_CRC_READ_ERR (1 << 3)
90#define STATUS_CRC_WRITE_ERR (1 << 2)
91#define STATUS_TIME_OUT_RESP (1 << 1)
92#define STATUS_TIME_OUT_READ (1 << 0)
93#define STATUS_ERR_MASK 0x2f
94
95#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
96#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
97#define CMD_DAT_CONT_START_READWAIT (1 << 10)
98#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
99#define CMD_DAT_CONT_INIT (1 << 7)
100#define CMD_DAT_CONT_WRITE (1 << 4)
101#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
102#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
103#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
104#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
105
106#define INT_SDIO_INT_WKP_EN (1 << 18)
107#define INT_CARD_INSERTION_WKP_EN (1 << 17)
108#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
109#define INT_CARD_INSERTION_EN (1 << 15)
110#define INT_CARD_REMOVAL_EN (1 << 14)
111#define INT_SDIO_IRQ_EN (1 << 13)
112#define INT_DAT0_EN (1 << 12)
113#define INT_BUF_READ_EN (1 << 4)
114#define INT_BUF_WRITE_EN (1 << 3)
115#define INT_END_CMD_RES_EN (1 << 2)
116#define INT_WRITE_OP_DONE_EN (1 << 1)
117#define INT_READ_OP_EN (1 << 0)
118
7f917a8d
SG		 119enum mxcmci_type {
120 IMX21_MMC,
121 IMX31_MMC,
c7ceab02 122 MPC512X_MMC,
7f917a8d
SG		 123};
124
d96be879
SH		 125struct mxcmci_host {
126 struct mmc_host *mmc;
d96be879 127 void __iomem *base;
01e4f958 128 dma_addr_t phys_base;
d96be879 129 int detect_irq;
f53fbde4
SH		 130 struct dma_chan *dma;
131 struct dma_async_tx_descriptor *desc;
d96be879 132 int do_dma;
16b3bf8c 133 int default_irq_mask;
f441b993 134 int use_sdio;
d96be879
SH		 135 unsigned int power_mode;
136 struct imxmmc_platform_data *pdata;
137
138 struct mmc_request *req;
139 struct mmc_command *cmd;
140 struct mmc_data *data;
141
d96be879
SH		 142 unsigned int datasize;
143 unsigned int dma_dir;
144
145 u16 rev_no;
146 unsigned int cmdat;
147
529aa29e
SH		 148 struct clk *clk_ipg;
149 struct clk *clk_per;
d96be879
SH		 150
151 int clock;
152
153 struct work_struct datawork;
f441b993 154 spinlock_t lock;
74b66954 155
f53fbde4
SH		 156 int burstlen;
157 int dmareq;
158 struct dma_slave_config dma_slave_config;
159 struct imx_dma_data dma_data;
f6ad0a48
JM		 160
161 struct timer_list watchdog;
7f917a8d
SG		 162 enum mxcmci_type devtype;
163};
164
42477053 165static const struct platform_device_id mxcmci_devtype[] = {
7f917a8d
SG		 166 {
167 .name = "imx21-mmc",
168 .driver_data = IMX21_MMC,
169 }, {
170 .name = "imx31-mmc",
171 .driver_data = IMX31_MMC,
c7ceab02
AG		 172 }, {
173 .name = "mpc512x-sdhc",
174 .driver_data = MPC512X_MMC,
7f917a8d
SG		 175 }, {
176 /* sentinel */
177 }
d96be879 178};
7f917a8d
SG		 179MODULE_DEVICE_TABLE(platform, mxcmci_devtype);
180
7ff747c4
MP		 181static const struct of_device_id mxcmci_of_match[] = {
182 {
183 .compatible = "fsl,imx21-mmc",
184 .data = &mxcmci_devtype[IMX21_MMC],
185 }, {
186 .compatible = "fsl,imx31-mmc",
187 .data = &mxcmci_devtype[IMX31_MMC],
c7ceab02
AG		 188 }, {
189 .compatible = "fsl,mpc5121-sdhc",
190 .data = &mxcmci_devtype[MPC512X_MMC],
7ff747c4
MP		 191 }, {
192 /* sentinel */
193 }
194};
195MODULE_DEVICE_TABLE(of, mxcmci_of_match);
196
7f917a8d
SG		 197static inline int is_imx31_mmc(struct mxcmci_host *host)
198{
199 return host->devtype == IMX31_MMC;
200}
d96be879 201
c7ceab02
AG		 202static inline int is_mpc512x_mmc(struct mxcmci_host *host)
203{
204 return host->devtype == MPC512X_MMC;
205}
206
207static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
208{
209 if (IS_ENABLED(CONFIG_PPC_MPC512x))
210 return ioread32be(host->base + reg);
211 else
212 return readl(host->base + reg);
213}
214
215static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
216{
217 if (IS_ENABLED(CONFIG_PPC_MPC512x))
218 iowrite32be(val, host->base + reg);
219 else
220 writel(val, host->base + reg);
221}
222
223static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
224{
225 if (IS_ENABLED(CONFIG_PPC_MPC512x))
226 return ioread32be(host->base + reg);
227 else
228 return readw(host->base + reg);
229}
230
231static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
232{
233 if (IS_ENABLED(CONFIG_PPC_MPC512x))
234 iowrite32be(val, host->base + reg);
235 else
236 writew(val, host->base + reg);
237}
238
18489fa2
MF		 239static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
240
bc3c1771 241static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
74b66954 242{
bc3c1771
AS		 243 if (!IS_ERR(host->mmc->supply.vmmc)) {
244 if (host->power_mode == MMC_POWER_UP)
245 mmc_regulator_set_ocr(host->mmc,
246 host->mmc->supply.vmmc, vdd);
247 else if (host->power_mode == MMC_POWER_OFF)
248 mmc_regulator_set_ocr(host->mmc,
249 host->mmc->supply.vmmc, 0);
d078d242
AP		 250 }
251
74b66954
AP		 252 if (host->pdata && host->pdata->setpower)
253 host->pdata->setpower(mmc_dev(host->mmc), vdd);
254}
255
d96be879
SH		 256static inline int mxcmci_use_dma(struct mxcmci_host *host)
257{
258 return host->do_dma;
259}
260
261static void mxcmci_softreset(struct mxcmci_host *host)
262{
263 int i;
264
4725f6f1
DM		 265 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
266
d96be879 267 /* reset sequence */
c7ceab02
AG		 268 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
269 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
270 MMC_REG_STR_STP_CLK);
d96be879
SH		 271
272 for (i = 0; i < 8; i++)
c7ceab02 273 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
d96be879 274
c7ceab02 275 mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
d96be879
SH		 276}
277
e48fc15a
AG		 278#if IS_ENABLED(CONFIG_PPC_MPC512x)
279static inline void buffer_swap32(u32 *buf, int len)
280{
281 int i;
282
283 for (i = 0; i < ((len + 3) / 4); i++) {
7a8bf874 284 *buf = swab32(*buf);
e48fc15a
AG		 285 buf++;
286 }
287}
288
289static void mxcmci_swap_buffers(struct mmc_data *data)
290{
291 struct scatterlist *sg;
292 int i;
293
294 for_each_sg(data->sg, sg, data->sg_len, i)
295 buffer_swap32(sg_virt(sg), sg->length);
296}
297#else
298static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
299#endif
300
656217d2 301static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
d96be879
SH		 302{
303 unsigned int nob = data->blocks;
304 unsigned int blksz = data->blksz;
305 unsigned int datasize = nob * blksz;
d96be879 306 struct scatterlist *sg;
05f5799c 307 enum dma_transfer_direction slave_dirn;
f53fbde4
SH		 308 int i, nents;
309
d96be879
SH		 310 host->data = data;
311 data->bytes_xfered = 0;
312
c7ceab02
AG		 313 mxcmci_writew(host, nob, MMC_REG_NOB);
314 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
d96be879
SH		 315 host->datasize = datasize;
316
f53fbde4
SH		 317 if (!mxcmci_use_dma(host))
318 return 0;
319
d96be879 320 for_each_sg(data->sg, sg, data->sg_len, i) {
2cb53552 321 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
d96be879 322 host->do_dma = 0;
656217d2 323 return 0;
d96be879
SH		 324 }
325 }
326
05f5799c 327 if (data->flags & MMC_DATA_READ) {
d96be879 328 host->dma_dir = DMA_FROM_DEVICE;
05f5799c
VK		 329 slave_dirn = DMA_DEV_TO_MEM;
330 } else {
d96be879 331 host->dma_dir = DMA_TO_DEVICE;
05f5799c 332 slave_dirn = DMA_MEM_TO_DEV;
e48fc15a
AG		 333
334 mxcmci_swap_buffers(data);
05f5799c 335 }
d96be879 336
f53fbde4
SH		 337 nents = dma_map_sg(host->dma->device->dev, data->sg,
338 data->sg_len, host->dma_dir);
339 if (nents != data->sg_len)
340 return -EINVAL;
341
16052827 342 host->desc = dmaengine_prep_slave_sg(host->dma,
05f5799c 343 data->sg, data->sg_len, slave_dirn,
f53fbde4 344 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
d96be879 345
f53fbde4
SH		 346 if (!host->desc) {
347 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
348 host->dma_dir);
349 host->do_dma = 0;
350 return 0; /* Fall back to PIO */
656217d2 351 }
d96be879
SH		 352 wmb();
353
f53fbde4 354 dmaengine_submit(host->desc);
439aa0ef 355 dma_async_issue_pending(host->dma);
f53fbde4 356
f6ad0a48
JM		 357 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
358
656217d2 359 return 0;
d96be879
SH		 360}
361
f6ad0a48
JM		 362static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
363static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
364
365static void mxcmci_dma_callback(void *data)
366{
367 struct mxcmci_host *host = data;
368 u32 stat;
369
370 del_timer(&host->watchdog);
371
c7ceab02 372 stat = mxcmci_readl(host, MMC_REG_STATUS);
f6ad0a48
JM		 373
374 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
375
f6ad0a48
JM		 376 mxcmci_data_done(host, stat);
377}
378
d96be879
SH		 379static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
380 unsigned int cmdat)
381{
16b3bf8c 382 u32 int_cntr = host->default_irq_mask;
f441b993
DM		 383 unsigned long flags;
384
d96be879
SH		 385 WARN_ON(host->cmd != NULL);
386 host->cmd = cmd;
387
388 switch (mmc_resp_type(cmd)) {
389 case MMC_RSP_R1: /* short CRC, OPCODE */
390 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
391 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
392 break;
393 case MMC_RSP_R2: /* long 136 bit + CRC */
394 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
395 break;
396 case MMC_RSP_R3: /* short */
397 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
398 break;
399 case MMC_RSP_NONE:
400 break;
401 default:
402 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
403 mmc_resp_type(cmd));
404 cmd->error = -EINVAL;
405 return -EINVAL;
406 }
407
f441b993
DM		 408 int_cntr = INT_END_CMD_RES_EN;
409
f6ad0a48
JM		 410 if (mxcmci_use_dma(host)) {
411 if (host->dma_dir == DMA_FROM_DEVICE) {
412 host->desc->callback = mxcmci_dma_callback;
413 host->desc->callback_param = host;
414 } else {
415 int_cntr |= INT_WRITE_OP_DONE_EN;
416 }
417 }
f441b993
DM		 418
419 spin_lock_irqsave(&host->lock, flags);
420 if (host->use_sdio)
421 int_cntr |= INT_SDIO_IRQ_EN;
c7ceab02 422 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
f441b993 423 spin_unlock_irqrestore(&host->lock, flags);
d96be879 424
c7ceab02
AG		 425 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
426 mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
427 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
d96be879
SH		 428
429 return 0;
430}
431
432static void mxcmci_finish_request(struct mxcmci_host *host,
433 struct mmc_request *req)
434{
16b3bf8c 435 u32 int_cntr = host->default_irq_mask;
f441b993
DM		 436 unsigned long flags;
437
438 spin_lock_irqsave(&host->lock, flags);
439 if (host->use_sdio)
440 int_cntr |= INT_SDIO_IRQ_EN;
c7ceab02 441 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
f441b993 442 spin_unlock_irqrestore(&host->lock, flags);
d96be879
SH		 443
444 host->req = NULL;
445 host->cmd = NULL;
446 host->data = NULL;
447
448 mmc_request_done(host->mmc, req);
449}
450
451static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
452{
453 struct mmc_data *data = host->data;
454 int data_error;
455
e48fc15a 456 if (mxcmci_use_dma(host)) {
f53fbde4 457 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
d96be879 458 host->dma_dir);
e48fc15a
AG		 459 mxcmci_swap_buffers(data);
460 }
d96be879
SH		 461
462 if (stat & STATUS_ERR_MASK) {
463 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
464 stat);
465 if (stat & STATUS_CRC_READ_ERR) {
4725f6f1 466 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
d96be879
SH		 467 data->error = -EILSEQ;
468 } else if (stat & STATUS_CRC_WRITE_ERR) {
469 u32 err_code = (stat >> 9) & 0x3;
4725f6f1
DM		 470 if (err_code == 2) { /* No CRC response */
471 dev_err(mmc_dev(host->mmc),
472 "%s: No CRC -ETIMEDOUT\n", __func__);
d96be879 473 data->error = -ETIMEDOUT;
4725f6f1
DM		 474 } else {
475 dev_err(mmc_dev(host->mmc),
476 "%s: -EILSEQ\n", __func__);
d96be879 477 data->error = -EILSEQ;
4725f6f1 478 }
d96be879 479 } else if (stat & STATUS_TIME_OUT_READ) {
4725f6f1
DM		 480 dev_err(mmc_dev(host->mmc),
481 "%s: read -ETIMEDOUT\n", __func__);
d96be879
SH		 482 data->error = -ETIMEDOUT;
483 } else {
4725f6f1 484 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
d96be879
SH		 485 data->error = -EIO;
486 }
487 } else {
488 data->bytes_xfered = host->datasize;
489 }
490
491 data_error = data->error;
492
493 host->data = NULL;
494
495 return data_error;
496}
497
498static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
499{
500 struct mmc_command *cmd = host->cmd;
501 int i;
502 u32 a, b, c;
503
504 if (!cmd)
505 return;
506
507 if (stat & STATUS_TIME_OUT_RESP) {
508 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
509 cmd->error = -ETIMEDOUT;
510 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
511 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
512 cmd->error = -EILSEQ;
513 }
514
515 if (cmd->flags & MMC_RSP_PRESENT) {
516 if (cmd->flags & MMC_RSP_136) {
517 for (i = 0; i < 4; i++) {
c7ceab02
AG		 518 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
519 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
d96be879
SH		 520 cmd->resp[i] = a << 16 | b;
521 }
522 } else {
c7ceab02
AG		 523 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
524 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
525 c = mxcmci_readw(host, MMC_REG_RES_FIFO);
d96be879
SH		 526 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
527 }
528 }
529}
530
531static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
532{
533 u32 stat;
534 unsigned long timeout = jiffies + HZ;
535
536 do {
c7ceab02 537 stat = mxcmci_readl(host, MMC_REG_STATUS);
d96be879
SH		 538 if (stat & STATUS_ERR_MASK)
539 return stat;
18489fa2
MF		 540 if (time_after(jiffies, timeout)) {
541 mxcmci_softreset(host);
542 mxcmci_set_clk_rate(host, host->clock);
d96be879 543 return STATUS_TIME_OUT_READ;
18489fa2 544 }
d96be879
SH		 545 if (stat & mask)
546 return 0;
547 cpu_relax();
548 } while (1);
549}
550
551static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
552{
553 unsigned int stat;
554 u32 *buf = _buf;
555
556 while (bytes > 3) {
557 stat = mxcmci_poll_status(host,
558 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
559 if (stat)
560 return stat;
c7ceab02 561 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
d96be879
SH		 562 bytes -= 4;
563 }
564
565 if (bytes) {
566 u8 *b = (u8 *)buf;
567 u32 tmp;
568
569 stat = mxcmci_poll_status(host,
570 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
571 if (stat)
572 return stat;
c7ceab02 573 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
d96be879
SH		 574 memcpy(b, &tmp, bytes);
575 }
576
577 return 0;
578}
579
580static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
581{
582 unsigned int stat;
583 u32 *buf = _buf;
584
585 while (bytes > 3) {
586 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
587 if (stat)
588 return stat;
c7ceab02 589 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
d96be879
SH		 590 bytes -= 4;
591 }
592
593 if (bytes) {
594 u8 *b = (u8 *)buf;
595 u32 tmp;
596
597 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
598 if (stat)
599 return stat;
600
601 memcpy(&tmp, b, bytes);
c7ceab02 602 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
d96be879
SH		 603 }
604
6d916416 605 return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
d96be879
SH		 606}
607
608static int mxcmci_transfer_data(struct mxcmci_host *host)
609{
610 struct mmc_data *data = host->req->data;
611 struct scatterlist *sg;
612 int stat, i;
613
d96be879
SH		 614 host->data = data;
615 host->datasize = 0;
616
617 if (data->flags & MMC_DATA_READ) {
618 for_each_sg(data->sg, sg, data->sg_len, i) {
619 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
620 if (stat)
621 return stat;
622 host->datasize += sg->length;
623 }
624 } else {
625 for_each_sg(data->sg, sg, data->sg_len, i) {
626 stat = mxcmci_push(host, sg_virt(sg), sg->length);
627 if (stat)
628 return stat;
629 host->datasize += sg->length;
630 }
631 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
632 if (stat)
633 return stat;
634 }
635 return 0;
636}
637
638static void mxcmci_datawork(struct work_struct *work)
639{
640 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
641 datawork);
642 int datastat = mxcmci_transfer_data(host);
4a31f2ef 643
c7ceab02
AG		 644 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
645 MMC_REG_STATUS);
d96be879
SH		 646 mxcmci_finish_data(host, datastat);
647
648 if (host->req->stop) {
649 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
650 mxcmci_finish_request(host, host->req);
651 return;
652 }
653 } else {
654 mxcmci_finish_request(host, host->req);
655 }
656}
657
d96be879
SH		 658static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
659{
70aa6109 660 struct mmc_request *req;
d96be879 661 int data_error;
70aa6109
AG		 662 unsigned long flags;
663
664 spin_lock_irqsave(&host->lock, flags);
d96be879 665
70aa6109
AG		 666 if (!host->data) {
667 spin_unlock_irqrestore(&host->lock, flags);
d96be879 668 return;
70aa6109
AG		 669 }
670
671 if (!host->req) {
672 spin_unlock_irqrestore(&host->lock, flags);
673 return;
674 }
675
676 req = host->req;
677 if (!req->stop)
678 host->req = NULL; /* we will handle finish req below */
d96be879
SH		 679
680 data_error = mxcmci_finish_data(host, stat);
681
70aa6109
AG		 682 spin_unlock_irqrestore(&host->lock, flags);
683
d96be879
SH		 684 mxcmci_read_response(host, stat);
685 host->cmd = NULL;
686
70aa6109
AG		 687 if (req->stop) {
688 if (mxcmci_start_cmd(host, req->stop, 0)) {
689 mxcmci_finish_request(host, req);
d96be879
SH		 690 return;
691 }
692 } else {
70aa6109 693 mxcmci_finish_request(host, req);
d96be879
SH		 694 }
695}
d96be879
SH		 696
697static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
698{
699 mxcmci_read_response(host, stat);
700 host->cmd = NULL;
701
702 if (!host->data && host->req) {
703 mxcmci_finish_request(host, host->req);
704 return;
705 }
706
707 /* For the DMA case the DMA engine handles the data transfer
fd589a8f 708 * automatically. For non DMA we have to do it ourselves.
d96be879
SH		 709 * Don't do it in interrupt context though.
710 */
711 if (!mxcmci_use_dma(host) && host->data)
712 schedule_work(&host->datawork);
713
714}
715
716static irqreturn_t mxcmci_irq(int irq, void *devid)
717{
718 struct mxcmci_host *host = devid;
f441b993
DM		 719 unsigned long flags;
720 bool sdio_irq;
d96be879
SH		 721 u32 stat;
722
c7ceab02
AG		 723 stat = mxcmci_readl(host, MMC_REG_STATUS);
724 mxcmci_writel(host,
725 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
726 STATUS_WRITE_OP_DONE),
727 MMC_REG_STATUS);
d96be879
SH		 728
729 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
730
f441b993
DM		 731 spin_lock_irqsave(&host->lock, flags);
732 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
733 spin_unlock_irqrestore(&host->lock, flags);
734
adfa5703
MF		 735 if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
736 mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
4a31f2ef 737
f441b993 738 if (sdio_irq) {
c7ceab02 739 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
f441b993
DM		 740 mmc_signal_sdio_irq(host->mmc);
741 }
742
d96be879
SH		 743 if (stat & STATUS_END_CMD_RESP)
744 mxcmci_cmd_done(host, stat);
f441b993 745
adfa5703 746 if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
f6ad0a48 747 del_timer(&host->watchdog);
d96be879 748 mxcmci_data_done(host, stat);
f6ad0a48 749 }
f53fbde4 750
16b3bf8c
EB		 751 if (host->default_irq_mask &&
752 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
753 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
f53fbde4 754
d96be879
SH		 755 return IRQ_HANDLED;
756}
757
758static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
759{
760 struct mxcmci_host *host = mmc_priv(mmc);
761 unsigned int cmdat = host->cmdat;
656217d2 762 int error;
d96be879
SH		 763
764 WARN_ON(host->req != NULL);
765
766 host->req = req;
767 host->cmdat &= ~CMD_DAT_CONT_INIT;
f53fbde4
SH		 768
769 if (host->dma)
770 host->do_dma = 1;
771
d96be879 772 if (req->data) {
656217d2
MF		 773 error = mxcmci_setup_data(host, req->data);
774 if (error) {
775 req->cmd->error = error;
776 goto out;
777 }
778
d96be879
SH		 779
780 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
781
782 if (req->data->flags & MMC_DATA_WRITE)
783 cmdat |= CMD_DAT_CONT_WRITE;
784 }
785
656217d2 786 error = mxcmci_start_cmd(host, req->cmd, cmdat);
f53fbde4 787
656217d2
MF		 788out:
789 if (error)
d96be879
SH		 790 mxcmci_finish_request(host, req);
791}
792
793static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
794{
795 unsigned int divider;
796 int prescaler = 0;
529aa29e 797 unsigned int clk_in = clk_get_rate(host->clk_per);
d96be879
SH		 798
799 while (prescaler <= 0x800) {
800 for (divider = 1; divider <= 0xF; divider++) {
801 int x;
802
803 x = (clk_in / (divider + 1));
804
805 if (prescaler)
806 x /= (prescaler * 2);
807
808 if (x <= clk_ios)
809 break;
810 }
811 if (divider < 0x10)
812 break;
813
814 if (prescaler == 0)
815 prescaler = 1;
816 else
817 prescaler <<= 1;
818 }
819
c7ceab02 820 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
d96be879
SH		 821
822 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
823 prescaler, divider, clk_in, clk_ios);
824}
825
f53fbde4
SH		 826static int mxcmci_setup_dma(struct mmc_host *mmc)
827{
828 struct mxcmci_host *host = mmc_priv(mmc);
829 struct dma_slave_config *config = &host->dma_slave_config;
830
01e4f958
AS		 831 config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
832 config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
f53fbde4
SH		 833 config->dst_addr_width = 4;
834 config->src_addr_width = 4;
835 config->dst_maxburst = host->burstlen;
836 config->src_maxburst = host->burstlen;
258aea76 837 config->device_fc = false;
f53fbde4
SH		 838
839 return dmaengine_slave_config(host->dma, config);
840}
841
d96be879
SH		 842static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
843{
844 struct mxcmci_host *host = mmc_priv(mmc);
f53fbde4
SH		 845 int burstlen, ret;
846
d96be879 847 /*
6584cb88
SH		 848 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
849 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
d96be879
SH		 850 */
851 if (ios->bus_width == MMC_BUS_WIDTH_4)
f53fbde4 852 burstlen = 16;
6584cb88
SH		 853 else
854 burstlen = 4;
f53fbde4
SH		 855
856 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
857 host->burstlen = burstlen;
858 ret = mxcmci_setup_dma(mmc);
859 if (ret) {
860 dev_err(mmc_dev(host->mmc),
861 "failed to config DMA channel. Falling back to PIO\n");
862 dma_release_channel(host->dma);
863 host->do_dma = 0;
e58f516f 864 host->dma = NULL;
f53fbde4
SH		 865 }
866 }
d96be879 867
d96be879
SH		 868 if (ios->bus_width == MMC_BUS_WIDTH_4)
869 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
870 else
871 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
872
873 if (host->power_mode != ios->power_mode) {
d96be879 874 host->power_mode = ios->power_mode;
bc3c1771 875 mxcmci_set_power(host, ios->vdd);
74b66954 876
d96be879
SH		 877 if (ios->power_mode == MMC_POWER_ON)
878 host->cmdat |= CMD_DAT_CONT_INIT;
879 }
880
881 if (ios->clock) {
882 mxcmci_set_clk_rate(host, ios->clock);
c7ceab02 883 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
d96be879 884 } else {
c7ceab02 885 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
d96be879
SH		 886 }
887
888 host->clock = ios->clock;
889}
890
891static irqreturn_t mxcmci_detect_irq(int irq, void *data)
892{
893 struct mmc_host *mmc = data;
894
895 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
896
897 mmc_detect_change(mmc, msecs_to_jiffies(250));
898 return IRQ_HANDLED;
899}
900
901static int mxcmci_get_ro(struct mmc_host *mmc)
902{
903 struct mxcmci_host *host = mmc_priv(mmc);
904
905 if (host->pdata && host->pdata->get_ro)
906 return !!host->pdata->get_ro(mmc_dev(mmc));
907 /*
bcf53524
AG		 908 * If board doesn't support read only detection (no mmc_gpio
909 * context or gpio is invalid), then let the mmc core decide
910 * what to do.
d96be879 911 */
bcf53524 912 return mmc_gpio_get_ro(mmc);
d96be879
SH		 913}
914
f441b993
DM		 915static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
916{
917 struct mxcmci_host *host = mmc_priv(mmc);
918 unsigned long flags;
919 u32 int_cntr;
920
921 spin_lock_irqsave(&host->lock, flags);
922 host->use_sdio = enable;
c7ceab02 923 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
f441b993
DM		 924
925 if (enable)
926 int_cntr |= INT_SDIO_IRQ_EN;
927 else
928 int_cntr &= ~INT_SDIO_IRQ_EN;
929
c7ceab02 930 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
f441b993
DM		 931 spin_unlock_irqrestore(&host->lock, flags);
932}
d96be879 933
3fcb027d
DM		 934static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
935{
7f917a8d
SG		 936 struct mxcmci_host *mxcmci = mmc_priv(host);
937
3fcb027d
DM		 938 /*
939 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
940 * multi-block transfers when connected SDIO peripheral doesn't
941 * drive the BUSY line as required by the specs.
942 * One way to prevent this is to only allow 1-bit transfers.
943 */
944
7f917a8d 945 if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO)
3fcb027d
DM		 946 host->caps &= ~MMC_CAP_4_BIT_DATA;
947 else
948 host->caps |= MMC_CAP_4_BIT_DATA;
949}
950
f53fbde4
SH		 951static bool filter(struct dma_chan *chan, void *param)
952{
953 struct mxcmci_host *host = param;
954
955 if (!imx_dma_is_general_purpose(chan))
956 return false;
957
958 chan->private = &host->dma_data;
959
960 return true;
961}
962
f6ad0a48
JM		 963static void mxcmci_watchdog(unsigned long data)
964{
965 struct mmc_host *mmc = (struct mmc_host *)data;
966 struct mxcmci_host *host = mmc_priv(mmc);
967 struct mmc_request *req = host->req;
c7ceab02 968 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
f6ad0a48
JM		 969
970 if (host->dma_dir == DMA_FROM_DEVICE) {
971 dmaengine_terminate_all(host->dma);
972 dev_err(mmc_dev(host->mmc),
973 "%s: read time out (status = 0x%08x)\n",
974 __func__, stat);
975 } else {
976 dev_err(mmc_dev(host->mmc),
977 "%s: write time out (status = 0x%08x)\n",
978 __func__, stat);
979 mxcmci_softreset(host);
980 }
981
982 /* Mark transfer as erroneus and inform the upper layers */
983
70aa6109
AG		 984 if (host->data)
985 host->data->error = -ETIMEDOUT;
f6ad0a48
JM		 986 host->req = NULL;
987 host->cmd = NULL;
988 host->data = NULL;
989 mmc_request_done(host->mmc, req);
990}
991
d96be879 992static const struct mmc_host_ops mxcmci_ops = {
f441b993
DM		 993 .request = mxcmci_request,
994 .set_ios = mxcmci_set_ios,
995 .get_ro = mxcmci_get_ro,
996 .enable_sdio_irq = mxcmci_enable_sdio_irq,
3fcb027d 997 .init_card = mxcmci_init_card,
d96be879
SH		 998};
999
1000static int mxcmci_probe(struct platform_device *pdev)
1001{
1002 struct mmc_host *mmc;
01e4f958
AS		 1003 struct mxcmci_host *host;
1004 struct resource *res;
d96be879 1005 int ret = 0, irq;
7ff747c4 1006 bool dat3_card_detect = false;
f53fbde4 1007 dma_cap_mask_t mask;
7ff747c4
MP		 1008 const struct of_device_id *of_id;
1009 struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
d96be879 1010
c7ceab02 1011 pr_info("i.MX/MPC512x SDHC driver\n");
d96be879 1012
7ff747c4
MP		 1013 of_id = of_match_device(mxcmci_of_match, &pdev->dev);
1014
01e4f958 1015 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d96be879 1016 irq = platform_get_irq(pdev, 0);
01e4f958 1017 if (irq < 0)
d96be879
SH		 1018 return -EINVAL;
1019
01e4f958
AS		 1020 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1021 if (!mmc)
1022 return -ENOMEM;
d96be879 1023
01e4f958
AS		 1024 host = mmc_priv(mmc);
1025
1026 host->base = devm_ioremap_resource(&pdev->dev, res);
1027 if (IS_ERR(host->base)) {
1028 ret = PTR_ERR(host->base);
1029 goto out_free;
d96be879
SH		 1030 }
1031
01e4f958
AS		 1032 host->phys_base = res->start;
1033
b8857696
SB		 1034 ret = mmc_of_parse(mmc);
1035 if (ret)
1036 goto out_free;
d96be879 1037 mmc->ops = &mxcmci_ops;
7ff747c4
MP		 1038
1039 /* For devicetree parsing, the bus width is read from devicetree */
1040 if (pdata)
1041 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1042 else
1043 mmc->caps |= MMC_CAP_SDIO_IRQ;
d96be879
SH		 1044
1045 /* MMC core transfer sizes tunable parameters */
d96be879
SH		 1046 mmc->max_blk_size = 2048;
1047 mmc->max_blk_count = 65535;
1048 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
d759c374 1049 mmc->max_seg_size = mmc->max_req_size;
d96be879 1050
7ff747c4
MP		 1051 if (of_id) {
1052 const struct platform_device_id *id_entry = of_id->data;
1053 host->devtype = id_entry->driver_data;
1054 } else {
1055 host->devtype = pdev->id_entry->driver_data;
1056 }
e48fc15a
AG		 1057
1058 /* adjust max_segs after devtype detection */
1059 if (!is_mpc512x_mmc(host))
1060 mmc->max_segs = 64;
1061
d96be879 1062 host->mmc = mmc;
7ff747c4 1063 host->pdata = pdata;
f441b993 1064 spin_lock_init(&host->lock);
d96be879 1065
7ff747c4
MP		 1066 if (pdata)
1067 dat3_card_detect = pdata->dat3_card_detect;
1068 else if (!(mmc->caps & MMC_CAP_NONREMOVABLE)
1069 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1070 dat3_card_detect = true;
1071
bc3c1771 1072 ret = mmc_regulator_get_supply(mmc);
18a09806
MF		 1073 if (ret == -EPROBE_DEFER)
1074 goto out_free;
1075
1076 if (!mmc->ocr_avail) {
1077 if (pdata && pdata->ocr_avail)
1078 mmc->ocr_avail = pdata->ocr_avail;
bc3c1771 1079 else
18a09806 1080 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
bc3c1771 1081 }
d96be879 1082
7ff747c4 1083 if (dat3_card_detect)
16b3bf8c
EB		 1084 host->default_irq_mask =
1085 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1086 else
1087 host->default_irq_mask = 0;
1088
529aa29e
SH		 1089 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1090 if (IS_ERR(host->clk_ipg)) {
1091 ret = PTR_ERR(host->clk_ipg);
01e4f958 1092 goto out_free;
d96be879 1093 }
529aa29e
SH		 1094
1095 host->clk_per = devm_clk_get(&pdev->dev, "per");
1096 if (IS_ERR(host->clk_per)) {
1097 ret = PTR_ERR(host->clk_per);
01e4f958 1098 goto out_free;
529aa29e
SH		 1099 }
1100
1101 clk_prepare_enable(host->clk_per);
1102 clk_prepare_enable(host->clk_ipg);
d96be879
SH		 1103
1104 mxcmci_softreset(host);
1105
c7ceab02 1106 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
d96be879
SH		 1107 if (host->rev_no != 0x400) {
1108 ret = -ENODEV;
1109 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1110 host->rev_no);
1111 goto out_clk_put;
1112 }
1113
529aa29e
SH		 1114 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1115 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
d96be879
SH		 1116
1117 /* recommended in data sheet */
c7ceab02 1118 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
d96be879 1119
c7ceab02 1120 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
d96be879 1121
7ff747c4
MP		 1122 if (!host->pdata) {
1123 host->dma = dma_request_slave_channel(&pdev->dev, "rx-tx");
1124 } else {
01e4f958
AS		 1125 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1126 if (res) {
1127 host->dmareq = res->start;
7ff747c4
MP		 1128 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1129 host->dma_data.priority = DMA_PRIO_LOW;
1130 host->dma_data.dma_request = host->dmareq;
1131 dma_cap_zero(mask);
1132 dma_cap_set(DMA_SLAVE, mask);
1133 host->dma = dma_request_channel(mask, filter, host);
1134 }
f53fbde4 1135 }
7ff747c4
MP		 1136 if (host->dma)
1137 mmc->max_seg_size = dma_get_max_seg_size(
1138 host->dma->device->dev);
1139 else
f53fbde4 1140 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
d96be879 1141
d96be879
SH		 1142 INIT_WORK(&host->datawork, mxcmci_datawork);
1143
01e4f958
AS		 1144 ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
1145 dev_name(&pdev->dev), host);
d96be879
SH		 1146 if (ret)
1147 goto out_free_dma;
1148
1149 platform_set_drvdata(pdev, mmc);
1150
1151 if (host->pdata && host->pdata->init) {
1152 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1153 host->mmc);
1154 if (ret)
01e4f958 1155 goto out_free_dma;
d96be879
SH		 1156 }
1157
f6ad0a48
JM		 1158 init_timer(&host->watchdog);
1159 host->watchdog.function = &mxcmci_watchdog;
1160 host->watchdog.data = (unsigned long)mmc;
1161
abd4190f
AS		 1162 mmc_add_host(mmc);
1163
d96be879
SH		 1164 return 0;
1165
d96be879 1166out_free_dma:
f53fbde4
SH		 1167 if (host->dma)
1168 dma_release_channel(host->dma);
01e4f958 1169
d96be879 1170out_clk_put:
529aa29e
SH		 1171 clk_disable_unprepare(host->clk_per);
1172 clk_disable_unprepare(host->clk_ipg);
01e4f958 1173
d96be879
SH		 1174out_free:
1175 mmc_free_host(mmc);
01e4f958 1176
d96be879
SH		 1177 return ret;
1178}
1179
1180static int mxcmci_remove(struct platform_device *pdev)
1181{
1182 struct mmc_host *mmc = platform_get_drvdata(pdev);
1183 struct mxcmci_host *host = mmc_priv(mmc);
1184
d96be879
SH		 1185 mmc_remove_host(mmc);
1186
1187 if (host->pdata && host->pdata->exit)
1188 host->pdata->exit(&pdev->dev, mmc);
1189
f53fbde4
SH		 1190 if (host->dma)
1191 dma_release_channel(host->dma);
1192
529aa29e
SH		 1193 clk_disable_unprepare(host->clk_per);
1194 clk_disable_unprepare(host->clk_ipg);
d96be879 1195
d96be879
SH		 1196 mmc_free_host(mmc);
1197
1198 return 0;
1199}
1200
384a81d5 1201static int __maybe_unused mxcmci_suspend(struct device *dev)
d96be879 1202{
a7d403cf
EB		 1203 struct mmc_host *mmc = dev_get_drvdata(dev);
1204 struct mxcmci_host *host = mmc_priv(mmc);
d96be879 1205
529aa29e
SH		 1206 clk_disable_unprepare(host->clk_per);
1207 clk_disable_unprepare(host->clk_ipg);
bd190f90 1208 return 0;
d96be879
SH		 1209}
1210
384a81d5 1211static int __maybe_unused mxcmci_resume(struct device *dev)
d96be879 1212{
a7d403cf
EB		 1213 struct mmc_host *mmc = dev_get_drvdata(dev);
1214 struct mxcmci_host *host = mmc_priv(mmc);
d96be879 1215
529aa29e
SH		 1216 clk_prepare_enable(host->clk_per);
1217 clk_prepare_enable(host->clk_ipg);
bd190f90 1218 return 0;
d96be879 1219}
a7d403cf 1220
384a81d5 1221static SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
d96be879
SH		 1222
1223static struct platform_driver mxcmci_driver = {
1224 .probe = mxcmci_probe,
1225 .remove = mxcmci_remove,
7f917a8d 1226 .id_table = mxcmci_devtype,
d96be879
SH		 1227 .driver = {
1228 .name = DRIVER_NAME,
a7d403cf 1229 .pm = &mxcmci_pm_ops,
7ff747c4 1230 .of_match_table = mxcmci_of_match,
d96be879
SH		 1231 }
1232};
1233
d1f81a64 1234module_platform_driver(mxcmci_driver);
d96be879
SH		 1235
1236MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1237MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1238MODULE_LICENSE("GPL");
6eb30adf 1239MODULE_ALIAS("platform:mxc-mmc");
Linux 6.x block layer and io_uring tree(s)