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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-2.6-block.git] / drivers / mmc / host / msm_sdcc.c
CommitLineData
9d2bd738
SM		 1/*
2 * linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
3 *
4 * Copyright (C) 2007 Google Inc,
5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Based on mmci.c
12 *
13 * Author: San Mehat (san@android.com)
14 *
15 */
16
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/init.h>
20#include <linux/ioport.h>
21#include <linux/device.h>
22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/highmem.h>
26#include <linux/log2.h>
27#include <linux/mmc/host.h>
28#include <linux/mmc/card.h>
29#include <linux/clk.h>
30#include <linux/scatterlist.h>
31#include <linux/platform_device.h>
32#include <linux/dma-mapping.h>
33#include <linux/debugfs.h>
34#include <linux/io.h>
35#include <linux/memory.h>
5a0e3ad6 36#include <linux/gfp.h>
9d2bd738
SM		 37
38#include <asm/cacheflush.h>
39#include <asm/div64.h>
40#include <asm/sizes.h>
41
3989d178 42#include <mach/mmc.h>
9d2bd738
SM		 43#include <mach/msm_iomap.h>
44#include <mach/dma.h>
9d2bd738 45
9d2bd738
SM		 46#include "msm_sdcc.h"
47
48#define DRIVER_NAME "msm-sdcc"
49
50static unsigned int msmsdcc_fmin = 144000;
51static unsigned int msmsdcc_fmax = 50000000;
52static unsigned int msmsdcc_4bit = 1;
53static unsigned int msmsdcc_pwrsave = 1;
54static unsigned int msmsdcc_piopoll = 1;
55static unsigned int msmsdcc_sdioirq;
56
57#define PIO_SPINMAX 30
58#define CMD_SPINMAX 20
59
9d2bd738
SM		 60static void
61msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
62 u32 c);
63
64static void
65msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
66{
67 writel(0, host->base + MMCICOMMAND);
68
69 BUG_ON(host->curr.data);
70
71 host->curr.mrq = NULL;
72 host->curr.cmd = NULL;
73
74 if (mrq->data)
75 mrq->data->bytes_xfered = host->curr.data_xfered;
76 if (mrq->cmd->error == -ETIMEDOUT)
77 mdelay(5);
78
79 /*
80 * Need to drop the host lock here; mmc_request_done may call
81 * back into the driver...
82 */
83 spin_unlock(&host->lock);
84 mmc_request_done(host->mmc, mrq);
85 spin_lock(&host->lock);
86}
87
88static void
89msmsdcc_stop_data(struct msmsdcc_host *host)
90{
91 writel(0, host->base + MMCIDATACTRL);
92 host->curr.data = NULL;
93 host->curr.got_dataend = host->curr.got_datablkend = 0;
94}
95
96uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
97{
75d14528
JP		 98 switch (host->pdev_id) {
99 case 1:
9d2bd738 100 return MSM_SDC1_PHYS + MMCIFIFO;
75d14528 101 case 2:
9d2bd738 102 return MSM_SDC2_PHYS + MMCIFIFO;
75d14528 103 case 3:
9d2bd738 104 return MSM_SDC3_PHYS + MMCIFIFO;
75d14528 105 case 4:
9d2bd738 106 return MSM_SDC4_PHYS + MMCIFIFO;
75d14528
JP		 107 }
108 BUG();
9d2bd738
SM		 109 return 0;
110}
111
112static void
113msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
114 unsigned int result,
115 struct msm_dmov_errdata *err)
116{
117 struct msmsdcc_dma_data *dma_data =
118 container_of(cmd, struct msmsdcc_dma_data, hdr);
119 struct msmsdcc_host *host = dma_data->host;
120 unsigned long flags;
121 struct mmc_request *mrq;
122
123 spin_lock_irqsave(&host->lock, flags);
124 mrq = host->curr.mrq;
125 BUG_ON(!mrq);
126
127 if (!(result & DMOV_RSLT_VALID)) {
0a7ff7c7 128 pr_err("msmsdcc: Invalid DataMover result\n");
9d2bd738
SM		 129 goto out;
130 }
131
132 if (result & DMOV_RSLT_DONE) {
133 host->curr.data_xfered = host->curr.xfer_size;
134 } else {
135 /* Error or flush */
136 if (result & DMOV_RSLT_ERROR)
0a7ff7c7 137 pr_err("%s: DMA error (0x%.8x)\n",
9d2bd738
SM		 138 mmc_hostname(host->mmc), result);
139 if (result & DMOV_RSLT_FLUSH)
0a7ff7c7 140 pr_err("%s: DMA channel flushed (0x%.8x)\n",
9d2bd738
SM		 141 mmc_hostname(host->mmc), result);
142 if (err)
0a7ff7c7 143 pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
9d2bd738
SM		 144 err->flush[0], err->flush[1], err->flush[2],
145 err->flush[3], err->flush[4], err->flush[5]);
146 if (!mrq->data->error)
147 mrq->data->error = -EIO;
148 }
149 host->dma.busy = 0;
150 dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
151 host->dma.dir);
152
153 if (host->curr.user_pages) {
154 struct scatterlist *sg = host->dma.sg;
155 int i;
156
75d14528
JP		 157 for (i = 0; i < host->dma.num_ents; i++)
158 flush_dcache_page(sg_page(sg++));
9d2bd738
SM		 159 }
160
161 host->dma.sg = NULL;
162
163 if ((host->curr.got_dataend && host->curr.got_datablkend)
164 || mrq->data->error) {
165
166 /*
167 * If we've already gotten our DATAEND / DATABLKEND
168 * for this request, then complete it through here.
169 */
170 msmsdcc_stop_data(host);
171
172 if (!mrq->data->error)
173 host->curr.data_xfered = host->curr.xfer_size;
174 if (!mrq->data->stop || mrq->cmd->error) {
175 writel(0, host->base + MMCICOMMAND);
176 host->curr.mrq = NULL;
177 host->curr.cmd = NULL;
178 mrq->data->bytes_xfered = host->curr.data_xfered;
179
180 spin_unlock_irqrestore(&host->lock, flags);
181 mmc_request_done(host->mmc, mrq);
182 return;
183 } else
184 msmsdcc_start_command(host, mrq->data->stop, 0);
185 }
186
187out:
188 spin_unlock_irqrestore(&host->lock, flags);
189 return;
190}
191
192static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
193{
194 if (host->dma.channel == -1)
195 return -ENOENT;
196
197 if ((data->blksz * data->blocks) < MCI_FIFOSIZE)
198 return -EINVAL;
199 if ((data->blksz * data->blocks) % MCI_FIFOSIZE)
200 return -EINVAL;
201 return 0;
202}
203
204static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
205{
206 struct msmsdcc_nc_dmadata *nc;
207 dmov_box *box;
208 uint32_t rows;
209 uint32_t crci;
210 unsigned int n;
211 int i, rc;
212 struct scatterlist *sg = data->sg;
213
214 rc = validate_dma(host, data);
215 if (rc)
216 return rc;
217
218 host->dma.sg = data->sg;
219 host->dma.num_ents = data->sg_len;
220
221 nc = host->dma.nc;
222
75d14528
JP		 223 switch (host->pdev_id) {
224 case 1:
9d2bd738 225 crci = MSMSDCC_CRCI_SDC1;
75d14528
JP		 226 break;
227 case 2:
9d2bd738 228 crci = MSMSDCC_CRCI_SDC2;
75d14528
JP		 229 break;
230 case 3:
9d2bd738 231 crci = MSMSDCC_CRCI_SDC3;
75d14528
JP		 232 break;
233 case 4:
9d2bd738 234 crci = MSMSDCC_CRCI_SDC4;
75d14528
JP		 235 break;
236 default:
9d2bd738
SM		 237 host->dma.sg = NULL;
238 host->dma.num_ents = 0;
239 return -ENOENT;
240 }
241
242 if (data->flags & MMC_DATA_READ)
243 host->dma.dir = DMA_FROM_DEVICE;
244 else
245 host->dma.dir = DMA_TO_DEVICE;
246
247 host->curr.user_pages = 0;
248
249 n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
75d14528 250 host->dma.num_ents, host->dma.dir);
9d2bd738
SM		 251
252 if (n != host->dma.num_ents) {
0a7ff7c7 253 pr_err("%s: Unable to map in all sg elements\n",
9d2bd738
SM		 254 mmc_hostname(host->mmc));
255 host->dma.sg = NULL;
256 host->dma.num_ents = 0;
257 return -ENOMEM;
258 }
259
260 box = &nc->cmd[0];
261 for (i = 0; i < host->dma.num_ents; i++) {
262 box->cmd = CMD_MODE_BOX;
263
264 if (i == (host->dma.num_ents - 1))
265 box->cmd |= CMD_LC;
266 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ?
267 (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 :
268 (sg_dma_len(sg) / MCI_FIFOSIZE) ;
269
270 if (data->flags & MMC_DATA_READ) {
271 box->src_row_addr = msmsdcc_fifo_addr(host);
272 box->dst_row_addr = sg_dma_address(sg);
273
274 box->src_dst_len = (MCI_FIFOSIZE << 16) |
275 (MCI_FIFOSIZE);
276 box->row_offset = MCI_FIFOSIZE;
277
278 box->num_rows = rows * ((1 << 16) + 1);
279 box->cmd |= CMD_SRC_CRCI(crci);
280 } else {
281 box->src_row_addr = sg_dma_address(sg);
282 box->dst_row_addr = msmsdcc_fifo_addr(host);
283
284 box->src_dst_len = (MCI_FIFOSIZE << 16) |
285 (MCI_FIFOSIZE);
286 box->row_offset = (MCI_FIFOSIZE << 16);
287
288 box->num_rows = rows * ((1 << 16) + 1);
289 box->cmd |= CMD_DST_CRCI(crci);
290 }
291 box++;
292 sg++;
293 }
294
295 /* location of command block must be 64 bit aligned */
296 BUG_ON(host->dma.cmd_busaddr & 0x07);
297
298 nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
299 host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
300 DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
301 host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
302
303 return 0;
304}
305
306static void
307msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data)
308{
309 unsigned int datactrl, timeout;
310 unsigned long long clks;
311 void __iomem *base = host->base;
312 unsigned int pio_irqmask = 0;
313
314 host->curr.data = data;
315 host->curr.xfer_size = data->blksz * data->blocks;
316 host->curr.xfer_remain = host->curr.xfer_size;
317 host->curr.data_xfered = 0;
318 host->curr.got_dataend = 0;
319 host->curr.got_datablkend = 0;
320
321 memset(&host->pio, 0, sizeof(host->pio));
322
323 clks = (unsigned long long)data->timeout_ns * host->clk_rate;
75d14528 324 do_div(clks, NSEC_PER_SEC);
9d2bd738
SM		 325 timeout = data->timeout_clks + (unsigned int)clks;
326 writel(timeout, base + MMCIDATATIMER);
327
328 writel(host->curr.xfer_size, base + MMCIDATALENGTH);
329
330 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
331
332 if (!msmsdcc_config_dma(host, data))
333 datactrl |= MCI_DPSM_DMAENABLE;
334 else {
335 host->pio.sg = data->sg;
336 host->pio.sg_len = data->sg_len;
337 host->pio.sg_off = 0;
338
339 if (data->flags & MMC_DATA_READ) {
340 pio_irqmask = MCI_RXFIFOHALFFULLMASK;
341 if (host->curr.xfer_remain < MCI_FIFOSIZE)
342 pio_irqmask |= MCI_RXDATAAVLBLMASK;
343 } else
344 pio_irqmask = MCI_TXFIFOHALFEMPTYMASK;
345 }
346
347 if (data->flags & MMC_DATA_READ)
348 datactrl |= MCI_DPSM_DIRECTION;
349
350 writel(pio_irqmask, base + MMCIMASK1);
351 writel(datactrl, base + MMCIDATACTRL);
352
353 if (datactrl & MCI_DPSM_DMAENABLE) {
354 host->dma.busy = 1;
355 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
356 }
357}
358
359static void
360msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
361{
362 void __iomem *base = host->base;
363
364 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
365 writel(0, base + MMCICOMMAND);
366 udelay(2 + ((5 * 1000000) / host->clk_rate));
367 }
368
369 c |= cmd->opcode | MCI_CPSM_ENABLE;
370
371 if (cmd->flags & MMC_RSP_PRESENT) {
372 if (cmd->flags & MMC_RSP_136)
373 c |= MCI_CPSM_LONGRSP;
374 c |= MCI_CPSM_RESPONSE;
375 }
376
75d14528
JP		 377 if (cmd->opcode == 17 || cmd->opcode == 18 ||
378 cmd->opcode == 24 || cmd->opcode == 25 ||
379 cmd->opcode == 53)
9d2bd738
SM		 380 c |= MCI_CSPM_DATCMD;
381
382 if (cmd == cmd->mrq->stop)
383 c |= MCI_CSPM_MCIABORT;
384
385 host->curr.cmd = cmd;
386
387 host->stats.cmds++;
388
389 writel(cmd->arg, base + MMCIARGUMENT);
390 writel(c, base + MMCICOMMAND);
391}
392
393static void
394msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
395 unsigned int status)
396{
397 if (status & MCI_DATACRCFAIL) {
0a7ff7c7
JP		 398 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc));
399 pr_err("%s: opcode 0x%.8x\n", __func__,
9d2bd738 400 data->mrq->cmd->opcode);
0a7ff7c7 401 pr_err("%s: blksz %d, blocks %d\n", __func__,
9d2bd738
SM		 402 data->blksz, data->blocks);
403 data->error = -EILSEQ;
404 } else if (status & MCI_DATATIMEOUT) {
0a7ff7c7 405 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc));
9d2bd738
SM		 406 data->error = -ETIMEDOUT;
407 } else if (status & MCI_RXOVERRUN) {
0a7ff7c7 408 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
9d2bd738
SM		 409 data->error = -EIO;
410 } else if (status & MCI_TXUNDERRUN) {
0a7ff7c7 411 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc));
9d2bd738
SM		 412 data->error = -EIO;
413 } else {
0a7ff7c7
JP		 414 pr_err("%s: Unknown error (0x%.8x)\n",
415 mmc_hostname(host->mmc), status);
9d2bd738
SM		 416 data->error = -EIO;
417 }
418}
419
420
421static int
422msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
423{
424 void __iomem *base = host->base;
425 uint32_t *ptr = (uint32_t *) buffer;
426 int count = 0;
427
428 while (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL) {
429
430 *ptr = readl(base + MMCIFIFO + (count % MCI_FIFOSIZE));
431 ptr++;
432 count += sizeof(uint32_t);
433
434 remain -= sizeof(uint32_t);
435 if (remain == 0)
436 break;
437 }
438 return count;
439}
440
441static int
442msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
443 unsigned int remain, u32 status)
444{
445 void __iomem *base = host->base;
446 char *ptr = buffer;
447
448 do {
449 unsigned int count, maxcnt;
450
451 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
452 MCI_FIFOHALFSIZE;
453 count = min(remain, maxcnt);
454
455 writesl(base + MMCIFIFO, ptr, count >> 2);
456 ptr += count;
457 remain -= count;
458
459 if (remain == 0)
460 break;
461
462 status = readl(base + MMCISTATUS);
463 } while (status & MCI_TXFIFOHALFEMPTY);
464
465 return ptr - buffer;
466}
467
468static int
469msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
470{
471 while (maxspin) {
472 if ((readl(host->base + MMCISTATUS) & mask))
473 return 0;
474 udelay(1);
475 --maxspin;
476 }
477 return -ETIMEDOUT;
478}
479
480static int
481msmsdcc_pio_irq(int irq, void *dev_id)
482{
483 struct msmsdcc_host *host = dev_id;
484 void __iomem *base = host->base;
485 uint32_t status;
486
487 status = readl(base + MMCISTATUS);
488
489 do {
490 unsigned long flags;
491 unsigned int remain, len;
492 char *buffer;
493
494 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) {
495 if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
496 break;
497
498 if (msmsdcc_spin_on_status(host,
499 (MCI_TXFIFOHALFEMPTY |
500 MCI_RXDATAAVLBL),
501 PIO_SPINMAX)) {
502 break;
503 }
504 }
505
506 /* Map the current scatter buffer */
507 local_irq_save(flags);
508 buffer = kmap_atomic(sg_page(host->pio.sg),
509 KM_BIO_SRC_IRQ) + host->pio.sg->offset;
510 buffer += host->pio.sg_off;
511 remain = host->pio.sg->length - host->pio.sg_off;
512 len = 0;
513 if (status & MCI_RXACTIVE)
514 len = msmsdcc_pio_read(host, buffer, remain);
515 if (status & MCI_TXACTIVE)
516 len = msmsdcc_pio_write(host, buffer, remain, status);
517
518 /* Unmap the buffer */
519 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
520 local_irq_restore(flags);
521
522 host->pio.sg_off += len;
523 host->curr.xfer_remain -= len;
524 host->curr.data_xfered += len;
525 remain -= len;
526
527 if (remain == 0) {
528 /* This sg page is full - do some housekeeping */
529 if (status & MCI_RXACTIVE && host->curr.user_pages)
530 flush_dcache_page(sg_page(host->pio.sg));
531
532 if (!--host->pio.sg_len) {
533 memset(&host->pio, 0, sizeof(host->pio));
534 break;
535 }
536
537 /* Advance to next sg */
538 host->pio.sg++;
539 host->pio.sg_off = 0;
540 }
541
542 status = readl(base + MMCISTATUS);
543 } while (1);
544
545 if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
546 writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
547
548 if (!host->curr.xfer_remain)
549 writel(0, base + MMCIMASK1);
550
551 return IRQ_HANDLED;
552}
553
554static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
555{
556 struct mmc_command *cmd = host->curr.cmd;
557 void __iomem *base = host->base;
558
559 host->curr.cmd = NULL;
560 cmd->resp[0] = readl(base + MMCIRESPONSE0);
561 cmd->resp[1] = readl(base + MMCIRESPONSE1);
562 cmd->resp[2] = readl(base + MMCIRESPONSE2);
563 cmd->resp[3] = readl(base + MMCIRESPONSE3);
564
565 del_timer(&host->command_timer);
566 if (status & MCI_CMDTIMEOUT) {
567 cmd->error = -ETIMEDOUT;
568 } else if (status & MCI_CMDCRCFAIL &&
569 cmd->flags & MMC_RSP_CRC) {
0a7ff7c7 570 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
9d2bd738
SM		 571 cmd->error = -EILSEQ;
572 }
573
574 if (!cmd->data || cmd->error) {
575 if (host->curr.data && host->dma.sg)
576 msm_dmov_stop_cmd(host->dma.channel,
577 &host->dma.hdr, 0);
578 else if (host->curr.data) { /* Non DMA */
579 msmsdcc_stop_data(host);
580 msmsdcc_request_end(host, cmd->mrq);
581 } else /* host->data == NULL */
582 msmsdcc_request_end(host, cmd->mrq);
583 } else if (!(cmd->data->flags & MMC_DATA_READ))
584 msmsdcc_start_data(host, cmd->data);
585}
586
b5a74d60
JP		 587static void
588msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
589 void __iomem *base)
590{
591 struct mmc_data *data = host->curr.data;
592
593 if (!data)
594 return;
595
596 /* Check for data errors */
597 if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
598 MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
599 msmsdcc_data_err(host, data, status);
600 host->curr.data_xfered = 0;
601 if (host->dma.sg)
602 msm_dmov_stop_cmd(host->dma.channel,
603 &host->dma.hdr, 0);
604 else {
605 msmsdcc_stop_data(host);
606 if (!data->stop)
607 msmsdcc_request_end(host, data->mrq);
608 else
609 msmsdcc_start_command(host, data->stop, 0);
610 }
611 }
612
613 /* Check for data done */
614 if (!host->curr.got_dataend && (status & MCI_DATAEND))
615 host->curr.got_dataend = 1;
616
617 if (!host->curr.got_datablkend && (status & MCI_DATABLOCKEND))
618 host->curr.got_datablkend = 1;
619
620 /*
621 * If DMA is still in progress, we complete via the completion handler
622 */
623 if (host->curr.got_dataend && host->curr.got_datablkend &&
624 !host->dma.busy) {
625 /*
626 * There appears to be an issue in the controller where
627 * if you request a small block transfer (< fifo size),
628 * you may get your DATAEND/DATABLKEND irq without the
629 * PIO data irq.
630 *
631 * Check to see if there is still data to be read,
632 * and simulate a PIO irq.
633 */
634 if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL)
635 msmsdcc_pio_irq(1, host);
636
637 msmsdcc_stop_data(host);
638 if (!data->error)
639 host->curr.data_xfered = host->curr.xfer_size;
640
641 if (!data->stop)
642 msmsdcc_request_end(host, data->mrq);
643 else
644 msmsdcc_start_command(host, data->stop, 0);
645 }
646}
647
9d2bd738
SM		 648static irqreturn_t
649msmsdcc_irq(int irq, void *dev_id)
650{
651 struct msmsdcc_host *host = dev_id;
652 void __iomem *base = host->base;
653 u32 status;
654 int ret = 0;
655 int cardint = 0;
656
657 spin_lock(&host->lock);
658
659 do {
9d2bd738
SM		 660 status = readl(base + MMCISTATUS);
661
b5a74d60 662 status &= (readl(base + MMCIMASK0) | MCI_DATABLOCKENDMASK);
9d2bd738
SM		 663 writel(status, base + MMCICLEAR);
664
b5a74d60 665 msmsdcc_handle_irq_data(host, status, base);
9d2bd738
SM		 666
667 if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
668 MCI_CMDTIMEOUT) && host->curr.cmd) {
669 msmsdcc_do_cmdirq(host, status);
670 }
671
672 if (status & MCI_SDIOINTOPER) {
673 cardint = 1;
674 status &= ~MCI_SDIOINTOPER;
675 }
676 ret = 1;
677 } while (status);
678
679 spin_unlock(&host->lock);
680
681 /*
682 * We have to delay handling the card interrupt as it calls
683 * back into the driver.
684 */
685 if (cardint)
686 mmc_signal_sdio_irq(host->mmc);
687
688 return IRQ_RETVAL(ret);
689}
690
691static void
692msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
693{
694 struct msmsdcc_host *host = mmc_priv(mmc);
695 unsigned long flags;
696
697 WARN_ON(host->curr.mrq != NULL);
698 WARN_ON(host->pwr == 0);
699
700 spin_lock_irqsave(&host->lock, flags);
701
702 host->stats.reqs++;
703
704 if (host->eject) {
705 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
706 mrq->cmd->error = 0;
707 mrq->data->bytes_xfered = mrq->data->blksz *
708 mrq->data->blocks;
709 } else
710 mrq->cmd->error = -ENOMEDIUM;
711
712 spin_unlock_irqrestore(&host->lock, flags);
713 mmc_request_done(mmc, mrq);
714 return;
715 }
716
717 host->curr.mrq = mrq;
718
719 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
720 msmsdcc_start_data(host, mrq->data);
721
722 msmsdcc_start_command(host, mrq->cmd, 0);
723
724 if (host->cmdpoll && !msmsdcc_spin_on_status(host,
725 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
726 CMD_SPINMAX)) {
727 uint32_t status = readl(host->base + MMCISTATUS);
728 msmsdcc_do_cmdirq(host, status);
729 writel(MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
730 host->base + MMCICLEAR);
731 host->stats.cmdpoll_hits++;
732 } else {
733 host->stats.cmdpoll_misses++;
734 mod_timer(&host->command_timer, jiffies + HZ);
735 }
736 spin_unlock_irqrestore(&host->lock, flags);
737}
738
739static void
740msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
741{
742 struct msmsdcc_host *host = mmc_priv(mmc);
743 u32 clk = 0, pwr = 0;
744 int rc;
745
746 if (ios->clock) {
747
748 if (!host->clks_on) {
749 clk_enable(host->pclk);
750 clk_enable(host->clk);
751 host->clks_on = 1;
752 }
753 if (ios->clock != host->clk_rate) {
754 rc = clk_set_rate(host->clk, ios->clock);
755 if (rc < 0)
0a7ff7c7
JP		 756 pr_err("%s: Error setting clock rate (%d)\n",
757 mmc_hostname(host->mmc), rc);
9d2bd738
SM		 758 else
759 host->clk_rate = ios->clock;
760 }
761 clk |= MCI_CLK_ENABLE;
762 }
763
764 if (ios->bus_width == MMC_BUS_WIDTH_4)
765 clk |= (2 << 10); /* Set WIDEBUS */
766
767 if (ios->clock > 400000 && msmsdcc_pwrsave)
768 clk |= (1 << 9); /* PWRSAVE */
769
770 clk |= (1 << 12); /* FLOW_ENA */
771 clk |= (1 << 15); /* feedback clock */
772
773 if (host->plat->translate_vdd)
774 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
775
776 switch (ios->power_mode) {
777 case MMC_POWER_OFF:
9d2bd738
SM		 778 break;
779 case MMC_POWER_UP:
780 pwr |= MCI_PWR_UP;
781 break;
782 case MMC_POWER_ON:
9d2bd738
SM		 783 pwr |= MCI_PWR_ON;
784 break;
785 }
786
787 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
788 pwr |= MCI_OD;
789
790 writel(clk, host->base + MMCICLOCK);
791
792 if (host->pwr != pwr) {
793 host->pwr = pwr;
794 writel(pwr, host->base + MMCIPOWER);
795 }
796
797 if (!(clk & MCI_CLK_ENABLE) && host->clks_on) {
798 clk_disable(host->clk);
799 clk_disable(host->pclk);
800 host->clks_on = 0;
801 }
802}
803
804static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
805{
806 struct msmsdcc_host *host = mmc_priv(mmc);
807 unsigned long flags;
808 u32 status;
809
810 spin_lock_irqsave(&host->lock, flags);
811 if (msmsdcc_sdioirq == 1) {
812 status = readl(host->base + MMCIMASK0);
813 if (enable)
814 status |= MCI_SDIOINTOPERMASK;
815 else
816 status &= ~MCI_SDIOINTOPERMASK;
817 host->saved_irq0mask = status;
818 writel(status, host->base + MMCIMASK0);
819 }
820 spin_unlock_irqrestore(&host->lock, flags);
821}
822
823static const struct mmc_host_ops msmsdcc_ops = {
824 .request = msmsdcc_request,
825 .set_ios = msmsdcc_set_ios,
826 .enable_sdio_irq = msmsdcc_enable_sdio_irq,
827};
828
829static void
830msmsdcc_check_status(unsigned long data)
831{
832 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
833 unsigned int status;
834
835 if (!host->plat->status) {
836 mmc_detect_change(host->mmc, 0);
837 goto out;
838 }
839
840 status = host->plat->status(mmc_dev(host->mmc));
841 host->eject = !status;
842 if (status ^ host->oldstat) {
0a7ff7c7
JP		 843 pr_info("%s: Slot status change detected (%d -> %d)\n",
844 mmc_hostname(host->mmc), host->oldstat, status);
9d2bd738
SM		 845 if (status)
846 mmc_detect_change(host->mmc, (5 * HZ) / 2);
847 else
848 mmc_detect_change(host->mmc, 0);
849 }
850
851 host->oldstat = status;
852
853out:
854 if (host->timer.function)
855 mod_timer(&host->timer, jiffies + HZ);
856}
857
858static irqreturn_t
859msmsdcc_platform_status_irq(int irq, void *dev_id)
860{
861 struct msmsdcc_host *host = dev_id;
862
863 printk(KERN_DEBUG "%s: %d\n", __func__, irq);
864 msmsdcc_check_status((unsigned long) host);
865 return IRQ_HANDLED;
866}
867
868static void
869msmsdcc_status_notify_cb(int card_present, void *dev_id)
870{
871 struct msmsdcc_host *host = dev_id;
872
873 printk(KERN_DEBUG "%s: card_present %d\n", mmc_hostname(host->mmc),
874 card_present);
875 msmsdcc_check_status((unsigned long) host);
876}
877
878/*
879 * called when a command expires.
880 * Dump some debugging, and then error
881 * out the transaction.
882 */
883static void
884msmsdcc_command_expired(unsigned long _data)
885{
886 struct msmsdcc_host *host = (struct msmsdcc_host *) _data;
887 struct mmc_request *mrq;
888 unsigned long flags;
889
890 spin_lock_irqsave(&host->lock, flags);
891 mrq = host->curr.mrq;
892
893 if (!mrq) {
0a7ff7c7
JP		 894 pr_info("%s: Command expiry misfire\n",
895 mmc_hostname(host->mmc));
9d2bd738
SM		 896 spin_unlock_irqrestore(&host->lock, flags);
897 return;
898 }
899
0a7ff7c7 900 pr_err("%s: Command timeout (%p %p %p %p)\n",
9d2bd738
SM		 901 mmc_hostname(host->mmc), mrq, mrq->cmd,
902 mrq->data, host->dma.sg);
903
904 mrq->cmd->error = -ETIMEDOUT;
905 msmsdcc_stop_data(host);
906
907 writel(0, host->base + MMCICOMMAND);
908
909 host->curr.mrq = NULL;
910 host->curr.cmd = NULL;
911
912 spin_unlock_irqrestore(&host->lock, flags);
913 mmc_request_done(host->mmc, mrq);
914}
915
916static int
917msmsdcc_init_dma(struct msmsdcc_host *host)
918{
919 memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
920 host->dma.host = host;
921 host->dma.channel = -1;
922
923 if (!host->dmares)
924 return -ENODEV;
925
926 host->dma.nc = dma_alloc_coherent(NULL,
927 sizeof(struct msmsdcc_nc_dmadata),
928 &host->dma.nc_busaddr,
929 GFP_KERNEL);
930 if (host->dma.nc == NULL) {
0a7ff7c7 931 pr_err("Unable to allocate DMA buffer\n");
9d2bd738
SM		 932 return -ENOMEM;
933 }
934 memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
935 host->dma.cmd_busaddr = host->dma.nc_busaddr;
936 host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
937 offsetof(struct msmsdcc_nc_dmadata, cmdptr);
938 host->dma.channel = host->dmares->start;
939
940 return 0;
941}
942
943#ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ
944static void
945do_resume_work(struct work_struct *work)
946{
947 struct msmsdcc_host *host =
948 container_of(work, struct msmsdcc_host, resume_task);
949 struct mmc_host *mmc = host->mmc;
950
951 if (mmc) {
952 mmc_resume_host(mmc);
953 if (host->stat_irq)
954 enable_irq(host->stat_irq);
955 }
956}
957#endif
958
959static int
960msmsdcc_probe(struct platform_device *pdev)
961{
962 struct mmc_platform_data *plat = pdev->dev.platform_data;
963 struct msmsdcc_host *host;
964 struct mmc_host *mmc;
965 struct resource *cmd_irqres = NULL;
966 struct resource *pio_irqres = NULL;
967 struct resource *stat_irqres = NULL;
968 struct resource *memres = NULL;
969 struct resource *dmares = NULL;
970 int ret;
971
972 /* must have platform data */
973 if (!plat) {
0a7ff7c7 974 pr_err("%s: Platform data not available\n", __func__);
9d2bd738
SM		 975 ret = -EINVAL;
976 goto out;
977 }
978
979 if (pdev->id < 1 || pdev->id > 4)
980 return -EINVAL;
981
982 if (pdev->resource == NULL || pdev->num_resources < 2) {
0a7ff7c7 983 pr_err("%s: Invalid resource\n", __func__);
9d2bd738
SM		 984 return -ENXIO;
985 }
986
987 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
988 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
989 cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
990 "cmd_irq");
991 pio_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
992 "pio_irq");
993 stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
994 "status_irq");
995
996 if (!cmd_irqres || !pio_irqres || !memres) {
0a7ff7c7 997 pr_err("%s: Invalid resource\n", __func__);
9d2bd738
SM		 998 return -ENXIO;
999 }
1000
1001 /*
1002 * Setup our host structure
1003 */
1004
1005 mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev);
1006 if (!mmc) {
1007 ret = -ENOMEM;
1008 goto out;
1009 }
1010
1011 host = mmc_priv(mmc);
1012 host->pdev_id = pdev->id;
1013 host->plat = plat;
1014 host->mmc = mmc;
1015
1016 host->cmdpoll = 1;
1017
1018 host->base = ioremap(memres->start, PAGE_SIZE);
1019 if (!host->base) {
1020 ret = -ENOMEM;
1021 goto out;
1022 }
1023
1024 host->cmd_irqres = cmd_irqres;
1025 host->pio_irqres = pio_irqres;
1026 host->memres = memres;
1027 host->dmares = dmares;
1028 spin_lock_init(&host->lock);
1029
1030 /*
1031 * Setup DMA
1032 */
1033 msmsdcc_init_dma(host);
1034
1035 /*
1036 * Setup main peripheral bus clock
1037 */
1038 host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1039 if (IS_ERR(host->pclk)) {
1040 ret = PTR_ERR(host->pclk);
1041 goto host_free;
1042 }
1043
1044 ret = clk_enable(host->pclk);
1045 if (ret)
1046 goto pclk_put;
1047
1048 host->pclk_rate = clk_get_rate(host->pclk);
1049
1050 /*
1051 * Setup SDC MMC clock
1052 */
1053 host->clk = clk_get(&pdev->dev, "sdc_clk");
1054 if (IS_ERR(host->clk)) {
1055 ret = PTR_ERR(host->clk);
1056 goto pclk_disable;
1057 }
1058
1059 ret = clk_enable(host->clk);
1060 if (ret)
1061 goto clk_put;
1062
1063 ret = clk_set_rate(host->clk, msmsdcc_fmin);
1064 if (ret) {
0a7ff7c7 1065 pr_err("%s: Clock rate set failed (%d)\n", __func__, ret);
9d2bd738
SM		 1066 goto clk_disable;
1067 }
1068
1069 host->clk_rate = clk_get_rate(host->clk);
1070
1071 host->clks_on = 1;
1072
1073 /*
1074 * Setup MMC host structure
1075 */
1076 mmc->ops = &msmsdcc_ops;
1077 mmc->f_min = msmsdcc_fmin;
1078 mmc->f_max = msmsdcc_fmax;
1079 mmc->ocr_avail = plat->ocr_mask;
1080
1081 if (msmsdcc_4bit)
1082 mmc->caps |= MMC_CAP_4_BIT_DATA;
1083 if (msmsdcc_sdioirq)
1084 mmc->caps |= MMC_CAP_SDIO_IRQ;
1085 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1086
1087 mmc->max_phys_segs = NR_SG;
1088 mmc->max_hw_segs = NR_SG;
1089 mmc->max_blk_size = 4096; /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1090 mmc->max_blk_count = 65536;
1091
1092 mmc->max_req_size = 33554432; /* MCI_DATA_LENGTH is 25 bits */
1093 mmc->max_seg_size = mmc->max_req_size;
1094
1095 writel(0, host->base + MMCIMASK0);
1096 writel(0x5e007ff, host->base + MMCICLEAR); /* Add: 1 << 25 */
1097
1098 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1099 host->saved_irq0mask = MCI_IRQENABLE;
1100
1101 /*
1102 * Setup card detect change
1103 */
1104
1105 memset(&host->timer, 0, sizeof(host->timer));
1106
1107 if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) {
1108 unsigned long irqflags = IRQF_SHARED |
1109 (stat_irqres->flags & IRQF_TRIGGER_MASK);
1110
1111 host->stat_irq = stat_irqres->start;
1112 ret = request_irq(host->stat_irq,
1113 msmsdcc_platform_status_irq,
1114 irqflags,
1115 DRIVER_NAME " (slot)",
1116 host);
1117 if (ret) {
0a7ff7c7
JP		 1118 pr_err("%s: Unable to get slot IRQ %d (%d)\n",
1119 mmc_hostname(mmc), host->stat_irq, ret);
9d2bd738
SM		 1120 goto clk_disable;
1121 }
1122 } else if (plat->register_status_notify) {
1123 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1124 } else if (!plat->status)
0a7ff7c7 1125 pr_err("%s: No card detect facilities available\n",
9d2bd738
SM		 1126 mmc_hostname(mmc));
1127 else {
1128 init_timer(&host->timer);
1129 host->timer.data = (unsigned long)host;
1130 host->timer.function = msmsdcc_check_status;
1131 host->timer.expires = jiffies + HZ;
1132 add_timer(&host->timer);
1133 }
1134
1135 if (plat->status) {
1136 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1137 host->eject = !host->oldstat;
1138 }
1139
1140 /*
1141 * Setup a command timer. We currently need this due to
1142 * some 'strange' timeout / error handling situations.
1143 */
1144 init_timer(&host->command_timer);
1145 host->command_timer.data = (unsigned long) host;
1146 host->command_timer.function = msmsdcc_command_expired;
1147
1148 ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED,
1149 DRIVER_NAME " (cmd)", host);
1150 if (ret)
1151 goto stat_irq_free;
1152
1153 ret = request_irq(pio_irqres->start, msmsdcc_pio_irq, IRQF_SHARED,
1154 DRIVER_NAME " (pio)", host);
1155 if (ret)
1156 goto cmd_irq_free;
1157
1158 mmc_set_drvdata(pdev, mmc);
1159 mmc_add_host(mmc);
1160
0a7ff7c7
JP		 1161 pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1162 mmc_hostname(mmc), (unsigned long long)memres->start,
1163 (unsigned int) cmd_irqres->start,
1164 (unsigned int) host->stat_irq, host->dma.channel);
1165 pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc),
1166 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled"));
1167 pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1168 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1169 pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject);
1170 pr_info("%s: Power save feature enable = %d\n",
1171 mmc_hostname(mmc), msmsdcc_pwrsave);
9d2bd738
SM		 1172
1173 if (host->dma.channel != -1) {
0a7ff7c7
JP		 1174 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1175 mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1176 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1177 mmc_hostname(mmc), host->dma.cmd_busaddr,
1178 host->dma.cmdptr_busaddr);
9d2bd738 1179 } else
0a7ff7c7 1180 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc));
9d2bd738 1181 if (host->timer.function)
0a7ff7c7 1182 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc));
9d2bd738
SM		 1183
1184 return 0;
1185 cmd_irq_free:
1186 free_irq(cmd_irqres->start, host);
1187 stat_irq_free:
1188 if (host->stat_irq)
1189 free_irq(host->stat_irq, host);
1190 clk_disable:
1191 clk_disable(host->clk);
1192 clk_put:
1193 clk_put(host->clk);
1194 pclk_disable:
1195 clk_disable(host->pclk);
1196 pclk_put:
1197 clk_put(host->pclk);
1198 host_free:
1199 mmc_free_host(mmc);
1200 out:
1201 return ret;
1202}
1203
1204static int
1205msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
1206{
1207 struct mmc_host *mmc = mmc_get_drvdata(dev);
1208 int rc = 0;
1209
1210 if (mmc) {
1211 struct msmsdcc_host *host = mmc_priv(mmc);
1212
1213 if (host->stat_irq)
1214 disable_irq(host->stat_irq);
1215
1216 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1217 rc = mmc_suspend_host(mmc, state);
1218 if (!rc) {
1219 writel(0, host->base + MMCIMASK0);
1220
1221 if (host->clks_on) {
1222 clk_disable(host->clk);
1223 clk_disable(host->pclk);
1224 host->clks_on = 0;
1225 }
1226 }
1227 }
1228 return rc;
1229}
1230
1231static int
1232msmsdcc_resume(struct platform_device *dev)
1233{
1234 struct mmc_host *mmc = mmc_get_drvdata(dev);
1235 unsigned long flags;
1236
1237 if (mmc) {
1238 struct msmsdcc_host *host = mmc_priv(mmc);
1239
1240 spin_lock_irqsave(&host->lock, flags);
1241
1242 if (!host->clks_on) {
1243 clk_enable(host->pclk);
1244 clk_enable(host->clk);
1245 host->clks_on = 1;
1246 }
1247
1248 writel(host->saved_irq0mask, host->base + MMCIMASK0);
1249
1250 spin_unlock_irqrestore(&host->lock, flags);
1251
1252 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1253 mmc_resume_host(mmc);
5b8a2fb3 1254 if (host->stat_irq)
9d2bd738
SM		 1255 enable_irq(host->stat_irq);
1256 }
1257 return 0;
1258}
1259
1260static struct platform_driver msmsdcc_driver = {
1261 .probe = msmsdcc_probe,
1262 .suspend = msmsdcc_suspend,
1263 .resume = msmsdcc_resume,
1264 .driver = {
1265 .name = "msm_sdcc",
1266 },
1267};
1268
1269static int __init msmsdcc_init(void)
1270{
1271 return platform_driver_register(&msmsdcc_driver);
1272}
1273
1274static void __exit msmsdcc_exit(void)
1275{
1276 platform_driver_unregister(&msmsdcc_driver);
1277}
1278
1279module_init(msmsdcc_init);
1280module_exit(msmsdcc_exit);
1281
1282MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1283MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)