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cxl: remove redundant increment of hwirq
[linux-2.6-block.git] / drivers / misc / cxl / native.c
CommitLineData
f204e0b8
IM		 1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/spinlock.h>
11#include <linux/sched.h>
12#include <linux/slab.h>
13#include <linux/sched.h>
14#include <linux/mutex.h>
15#include <linux/mm.h>
16#include <linux/uaccess.h>
17#include <asm/synch.h>
18#include <misc/cxl.h>
19
20#include "cxl.h"
21
22static int afu_control(struct cxl_afu *afu, u64 command,
23 u64 result, u64 mask, bool enabled)
24{
25 u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
26 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
27
28 spin_lock(&afu->afu_cntl_lock);
29 pr_devel("AFU command starting: %llx\n", command);
30
31 cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl | command);
32
33 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
34 while ((AFU_Cntl & mask) != result) {
35 if (time_after_eq(jiffies, timeout)) {
36 dev_warn(&afu->dev, "WARNING: AFU control timed out!\n");
37 spin_unlock(&afu->afu_cntl_lock);
38 return -EBUSY;
39 }
40 pr_devel_ratelimited("AFU control... (0x%.16llx)\n",
41 AFU_Cntl | command);
42 cpu_relax();
43 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
44 };
45 pr_devel("AFU command complete: %llx\n", command);
46 afu->enabled = enabled;
47 spin_unlock(&afu->afu_cntl_lock);
48
49 return 0;
50}
51
52static int afu_enable(struct cxl_afu *afu)
53{
54 pr_devel("AFU enable request\n");
55
56 return afu_control(afu, CXL_AFU_Cntl_An_E,
57 CXL_AFU_Cntl_An_ES_Enabled,
58 CXL_AFU_Cntl_An_ES_MASK, true);
59}
60
61int cxl_afu_disable(struct cxl_afu *afu)
62{
63 pr_devel("AFU disable request\n");
64
65 return afu_control(afu, 0, CXL_AFU_Cntl_An_ES_Disabled,
66 CXL_AFU_Cntl_An_ES_MASK, false);
67}
68
69/* This will disable as well as reset */
70int cxl_afu_reset(struct cxl_afu *afu)
71{
72 pr_devel("AFU reset request\n");
73
74 return afu_control(afu, CXL_AFU_Cntl_An_RA,
75 CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled,
76 CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK,
77 false);
78}
79
80static int afu_check_and_enable(struct cxl_afu *afu)
81{
82 if (afu->enabled)
83 return 0;
84 return afu_enable(afu);
85}
86
87int cxl_psl_purge(struct cxl_afu *afu)
88{
89 u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
90 u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
91 u64 dsisr, dar;
92 u64 start, end;
93 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
94
95 pr_devel("PSL purge request\n");
96
97 if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
98 WARN(1, "psl_purge request while AFU not disabled!\n");
99 cxl_afu_disable(afu);
100 }
101
102 cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
103 PSL_CNTL | CXL_PSL_SCNTL_An_Pc);
104 start = local_clock();
105 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
106 while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK)
107 == CXL_PSL_SCNTL_An_Ps_Pending) {
108 if (time_after_eq(jiffies, timeout)) {
109 dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n");
110 return -EBUSY;
111 }
112 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
113 pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%.16llx PSL_DSISR: 0x%.16llx\n", PSL_CNTL, dsisr);
114 if (dsisr & CXL_PSL_DSISR_TRANS) {
115 dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
116 dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%.16llx, DAR: 0x%.16llx\n", dsisr, dar);
117 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
118 } else if (dsisr) {
119 dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%.16llx\n", dsisr);
120 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
121 } else {
122 cpu_relax();
123 }
124 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
125 };
126 end = local_clock();
127 pr_devel("PSL purged in %lld ns\n", end - start);
128
129 cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
130 PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc);
131 return 0;
132}
133
134static int spa_max_procs(int spa_size)
135{
136 /*
137 * From the CAIA:
138 * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255
139 * Most of that junk is really just an overly-complicated way of saying
140 * the last 256 bytes are __aligned(128), so it's really:
141 * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255
142 * and
143 * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1
144 * so
145 * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256
146 * Ignore the alignment (which is safe in this case as long as we are
147 * careful with our rounding) and solve for n:
148 */
149 return ((spa_size / 8) - 96) / 17;
150}
151
152static int alloc_spa(struct cxl_afu *afu)
153{
154 u64 spap;
155
156 /* Work out how many pages to allocate */
157 afu->spa_order = 0;
158 do {
159 afu->spa_order++;
160 afu->spa_size = (1 << afu->spa_order) * PAGE_SIZE;
161 afu->spa_max_procs = spa_max_procs(afu->spa_size);
162 } while (afu->spa_max_procs < afu->num_procs);
163
164 WARN_ON(afu->spa_size > 0x100000); /* Max size supported by the hardware */
165
166 if (!(afu->spa = (struct cxl_process_element *)
167 __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->spa_order))) {
168 pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n");
169 return -ENOMEM;
170 }
171 pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n",
172 1<<afu->spa_order, afu->spa_max_procs, afu->num_procs);
173
174 afu->sw_command_status = (__be64 *)((char *)afu->spa +
175 ((afu->spa_max_procs + 3) * 128));
176
177 spap = virt_to_phys(afu->spa) & CXL_PSL_SPAP_Addr;
178 spap |= ((afu->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size;
179 spap |= CXL_PSL_SPAP_V;
180 pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", afu->spa, afu->spa_max_procs, afu->sw_command_status, spap);
181 cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap);
182
183 return 0;
184}
185
186static void release_spa(struct cxl_afu *afu)
187{
db7933f3 188 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0);
f204e0b8
IM		 189 free_pages((unsigned long) afu->spa, afu->spa_order);
190}
191
192int cxl_tlb_slb_invalidate(struct cxl *adapter)
193{
194 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
195
196 pr_devel("CXL adapter wide TLBIA & SLBIA\n");
197
198 cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A);
199
200 cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL);
201 while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) {
202 if (time_after_eq(jiffies, timeout)) {
203 dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n");
204 return -EBUSY;
205 }
206 cpu_relax();
207 }
208
209 cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL);
210 while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) {
211 if (time_after_eq(jiffies, timeout)) {
212 dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n");
213 return -EBUSY;
214 }
215 cpu_relax();
216 }
217 return 0;
218}
219
220int cxl_afu_slbia(struct cxl_afu *afu)
221{
222 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
223
224 pr_devel("cxl_afu_slbia issuing SLBIA command\n");
225 cxl_p2n_write(afu, CXL_SLBIA_An, CXL_TLB_SLB_IQ_ALL);
226 while (cxl_p2n_read(afu, CXL_SLBIA_An) & CXL_TLB_SLB_P) {
227 if (time_after_eq(jiffies, timeout)) {
228 dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n");
229 return -EBUSY;
230 }
231 cpu_relax();
232 }
233 return 0;
234}
235
236static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1)
237{
238 int rc;
239
240 /* 1. Disable SSTP by writing 0 to SSTP1[V] */
241 cxl_p2n_write(afu, CXL_SSTP1_An, 0);
242
243 /* 2. Invalidate all SLB entries */
244 if ((rc = cxl_afu_slbia(afu)))
245 return rc;
246
247 /* 3. Set SSTP0_An */
248 cxl_p2n_write(afu, CXL_SSTP0_An, sstp0);
249
250 /* 4. Set SSTP1_An */
251 cxl_p2n_write(afu, CXL_SSTP1_An, sstp1);
252
253 return 0;
254}
255
256/* Using per slice version may improve performance here. (ie. SLBIA_An) */
257static void slb_invalid(struct cxl_context *ctx)
258{
259 struct cxl *adapter = ctx->afu->adapter;
260 u64 slbia;
261
262 WARN_ON(!mutex_is_locked(&ctx->afu->spa_mutex));
263
264 cxl_p1_write(adapter, CXL_PSL_LBISEL,
265 ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) |
266 be32_to_cpu(ctx->elem->lpid));
267 cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID);
268
269 while (1) {
270 slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA);
271 if (!(slbia & CXL_TLB_SLB_P))
272 break;
273 cpu_relax();
274 }
275}
276
277static int do_process_element_cmd(struct cxl_context *ctx,
278 u64 cmd, u64 pe_state)
279{
280 u64 state;
a98e6e9f 281 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
f204e0b8
IM		 282
283 WARN_ON(!ctx->afu->enabled);
284
285 ctx->elem->software_state = cpu_to_be32(pe_state);
286 smp_wmb();
287 *(ctx->afu->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe);
288 smp_mb();
289 cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe);
290 while (1) {
a98e6e9f
IM		 291 if (time_after_eq(jiffies, timeout)) {
292 dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n");
293 return -EBUSY;
294 }
f204e0b8
IM		 295 state = be64_to_cpup(ctx->afu->sw_command_status);
296 if (state == ~0ULL) {
297 pr_err("cxl: Error adding process element to AFU\n");
298 return -1;
299 }
300 if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) ==
301 (cmd | (cmd >> 16) | ctx->pe))
302 break;
303 /*
304 * The command won't finish in the PSL if there are
305 * outstanding DSIs. Hence we need to yield here in
306 * case there are outstanding DSIs that we need to
307 * service. Tuning possiblity: we could wait for a
308 * while before sched
309 */
310 schedule();
311
312 }
313 return 0;
314}
315
316static int add_process_element(struct cxl_context *ctx)
317{
318 int rc = 0;
319
320 mutex_lock(&ctx->afu->spa_mutex);
321 pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe);
322 if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V)))
323 ctx->pe_inserted = true;
324 pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe);
325 mutex_unlock(&ctx->afu->spa_mutex);
326 return rc;
327}
328
329static int terminate_process_element(struct cxl_context *ctx)
330{
331 int rc = 0;
332
333 /* fast path terminate if it's already invalid */
334 if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V)))
335 return rc;
336
337 mutex_lock(&ctx->afu->spa_mutex);
338 pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);
339 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE,
340 CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T);
341 ctx->elem->software_state = 0; /* Remove Valid bit */
342 pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe);
343 mutex_unlock(&ctx->afu->spa_mutex);
344 return rc;
345}
346
347static int remove_process_element(struct cxl_context *ctx)
348{
349 int rc = 0;
350
351 mutex_lock(&ctx->afu->spa_mutex);
352 pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe);
353 if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0)))
354 ctx->pe_inserted = false;
355 slb_invalid(ctx);
356 pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe);
357 mutex_unlock(&ctx->afu->spa_mutex);
358
359 return rc;
360}
361
362
363static void assign_psn_space(struct cxl_context *ctx)
364{
365 if (!ctx->afu->pp_size || ctx->master) {
366 ctx->psn_phys = ctx->afu->psn_phys;
367 ctx->psn_size = ctx->afu->adapter->ps_size;
368 } else {
369 ctx->psn_phys = ctx->afu->psn_phys +
370 (ctx->afu->pp_offset + ctx->afu->pp_size * ctx->pe);
371 ctx->psn_size = ctx->afu->pp_size;
372 }
373}
374
375static int activate_afu_directed(struct cxl_afu *afu)
376{
377 int rc;
378
379 dev_info(&afu->dev, "Activating AFU directed mode\n");
380
381 if (alloc_spa(afu))
382 return -ENOMEM;
383
384 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU);
385 cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
386 cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
387
388 afu->current_mode = CXL_MODE_DIRECTED;
389 afu->num_procs = afu->max_procs_virtualised;
390
391 if ((rc = cxl_chardev_m_afu_add(afu)))
392 return rc;
393
394 if ((rc = cxl_sysfs_afu_m_add(afu)))
395 goto err;
396
397 if ((rc = cxl_chardev_s_afu_add(afu)))
398 goto err1;
399
400 return 0;
401err1:
402 cxl_sysfs_afu_m_remove(afu);
403err:
404 cxl_chardev_afu_remove(afu);
405 return rc;
406}
407
408#ifdef CONFIG_CPU_LITTLE_ENDIAN
409#define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE)
410#else
411#define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE))
412#endif
413
414static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr)
415{
416 u64 sr;
417 int r, result;
418
419 assign_psn_space(ctx);
420
421 ctx->elem->ctxtime = 0; /* disable */
422 ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
423 ctx->elem->haurp = 0; /* disable */
424 ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1));
425
5100a9d6 426 sr = 0;
f204e0b8
IM		 427 if (ctx->master)
428 sr |= CXL_PSL_SR_An_MP;
429 if (mfspr(SPRN_LPCR) & LPCR_TC)
430 sr |= CXL_PSL_SR_An_TC;
431 /* HV=0, PR=1, R=1 for userspace
432 * For kernel contexts: this would need to change
433 */
434 sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
435 set_endian(sr);
436 sr &= ~(CXL_PSL_SR_An_HV);
437 if (!test_tsk_thread_flag(current, TIF_32BIT))
438 sr |= CXL_PSL_SR_An_SF;
439 ctx->elem->common.pid = cpu_to_be32(current->pid);
440 ctx->elem->common.tid = 0;
441 ctx->elem->sr = cpu_to_be64(sr);
442
443 ctx->elem->common.csrp = 0; /* disable */
444 ctx->elem->common.aurp0 = 0; /* disable */
445 ctx->elem->common.aurp1 = 0; /* disable */
446
447 cxl_prefault(ctx, wed);
448
449 ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0);
450 ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1);
451
452 for (r = 0; r < CXL_IRQ_RANGES; r++) {
453 ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
454 ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
455 }
456
457 ctx->elem->common.amr = cpu_to_be64(amr);
458 ctx->elem->common.wed = cpu_to_be64(wed);
459
460 /* first guy needs to enable */
461 if ((result = afu_check_and_enable(ctx->afu)))
462 return result;
463
464 add_process_element(ctx);
465
466 return 0;
467}
468
469static int deactivate_afu_directed(struct cxl_afu *afu)
470{
471 dev_info(&afu->dev, "Deactivating AFU directed mode\n");
472
473 afu->current_mode = 0;
474 afu->num_procs = 0;
475
476 cxl_sysfs_afu_m_remove(afu);
477 cxl_chardev_afu_remove(afu);
478
479 cxl_afu_reset(afu);
480 cxl_afu_disable(afu);
481 cxl_psl_purge(afu);
482
483 release_spa(afu);
484
485 return 0;
486}
487
488static int activate_dedicated_process(struct cxl_afu *afu)
489{
490 dev_info(&afu->dev, "Activating dedicated process mode\n");
491
492 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
493
494 cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */
495 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */
496 cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
497 cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID));
498 cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */
499 cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1));
500
501 cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */
502 cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */
503 cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */
504
505 afu->current_mode = CXL_MODE_DEDICATED;
506 afu->num_procs = 1;
507
508 return cxl_chardev_d_afu_add(afu);
509}
510
511static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr)
512{
513 struct cxl_afu *afu = ctx->afu;
514 u64 sr;
515 int rc;
516
5100a9d6 517 sr = 0;
f204e0b8
IM		 518 set_endian(sr);
519 if (ctx->master)
520 sr |= CXL_PSL_SR_An_MP;
521 if (mfspr(SPRN_LPCR) & LPCR_TC)
522 sr |= CXL_PSL_SR_An_TC;
523 sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
524 if (!test_tsk_thread_flag(current, TIF_32BIT))
525 sr |= CXL_PSL_SR_An_SF;
526 cxl_p2n_write(afu, CXL_PSL_PID_TID_An, (u64)current->pid << 32);
527 cxl_p1n_write(afu, CXL_PSL_SR_An, sr);
528
529 if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1)))
530 return rc;
531
532 cxl_prefault(ctx, wed);
533
534 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An,
535 (((u64)ctx->irqs.offset[0] & 0xffff) << 48) |
536 (((u64)ctx->irqs.offset[1] & 0xffff) << 32) |
537 (((u64)ctx->irqs.offset[2] & 0xffff) << 16) |
538 ((u64)ctx->irqs.offset[3] & 0xffff));
539 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64)
540 (((u64)ctx->irqs.range[0] & 0xffff) << 48) |
541 (((u64)ctx->irqs.range[1] & 0xffff) << 32) |
542 (((u64)ctx->irqs.range[2] & 0xffff) << 16) |
543 ((u64)ctx->irqs.range[3] & 0xffff));
544
545 cxl_p2n_write(afu, CXL_PSL_AMR_An, amr);
546
547 /* master only context for dedicated */
548 assign_psn_space(ctx);
549
550 if ((rc = cxl_afu_reset(afu)))
551 return rc;
552
553 cxl_p2n_write(afu, CXL_PSL_WED_An, wed);
554
555 return afu_enable(afu);
556}
557
558static int deactivate_dedicated_process(struct cxl_afu *afu)
559{
560 dev_info(&afu->dev, "Deactivating dedicated process mode\n");
561
562 afu->current_mode = 0;
563 afu->num_procs = 0;
564
565 cxl_chardev_afu_remove(afu);
566
567 return 0;
568}
569
570int _cxl_afu_deactivate_mode(struct cxl_afu *afu, int mode)
571{
572 if (mode == CXL_MODE_DIRECTED)
573 return deactivate_afu_directed(afu);
574 if (mode == CXL_MODE_DEDICATED)
575 return deactivate_dedicated_process(afu);
576 return 0;
577}
578
579int cxl_afu_deactivate_mode(struct cxl_afu *afu)
580{
581 return _cxl_afu_deactivate_mode(afu, afu->current_mode);
582}
583
584int cxl_afu_activate_mode(struct cxl_afu *afu, int mode)
585{
586 if (!mode)
587 return 0;
588 if (!(mode & afu->modes_supported))
589 return -EINVAL;
590
591 if (mode == CXL_MODE_DIRECTED)
592 return activate_afu_directed(afu);
593 if (mode == CXL_MODE_DEDICATED)
594 return activate_dedicated_process(afu);
595
596 return -EINVAL;
597}
598
599int cxl_attach_process(struct cxl_context *ctx, bool kernel, u64 wed, u64 amr)
600{
601 ctx->kernel = kernel;
602 if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
603 return attach_afu_directed(ctx, wed, amr);
604
605 if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
606 return attach_dedicated(ctx, wed, amr);
607
608 return -EINVAL;
609}
610
611static inline int detach_process_native_dedicated(struct cxl_context *ctx)
612{
613 cxl_afu_reset(ctx->afu);
614 cxl_afu_disable(ctx->afu);
615 cxl_psl_purge(ctx->afu);
616 return 0;
617}
618
f204e0b8
IM		 619static inline int detach_process_native_afu_directed(struct cxl_context *ctx)
620{
621 if (!ctx->pe_inserted)
622 return 0;
623 if (terminate_process_element(ctx))
624 return -1;
625 if (remove_process_element(ctx))
626 return -1;
627
628 return 0;
629}
630
631int cxl_detach_process(struct cxl_context *ctx)
632{
633 if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
634 return detach_process_native_dedicated(ctx);
635
636 return detach_process_native_afu_directed(ctx);
637}
638
bc78b05b 639int cxl_get_irq(struct cxl_afu *afu, struct cxl_irq_info *info)
f204e0b8
IM		 640{
641 u64 pidtid;
642
bc78b05b
IM		 643 info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
644 info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
645 info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);
646 pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An);
f204e0b8
IM		 647 info->pid = pidtid >> 32;
648 info->tid = pidtid & 0xffffffff;
bc78b05b
IM		 649 info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An);
650 info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
f204e0b8
IM		 651
652 return 0;
653}
654
655static void recover_psl_err(struct cxl_afu *afu, u64 errstat)
656{
657 u64 dsisr;
658
659 pr_devel("RECOVERING FROM PSL ERROR... (0x%.16llx)\n", errstat);
660
661 /* Clear PSL_DSISR[PE] */
662 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
663 cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE);
664
665 /* Write 1s to clear error status bits */
666 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat);
667}
668
669int cxl_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask)
670{
671 if (tfc)
672 cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc);
673 if (psl_reset_mask)
674 recover_psl_err(ctx->afu, psl_reset_mask);
675
676 return 0;
677}
678
679int cxl_check_error(struct cxl_afu *afu)
680{
681 return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL);
682}
Linux 6.x block layer and io_uring tree(s)