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cxl: New hcalls to support cxl adapters
[linux-2.6-block.git] / drivers / misc / cxl / native.c
CommitLineData
f204e0b8
IM		 1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/spinlock.h>
11#include <linux/sched.h>
12#include <linux/slab.h>
13#include <linux/sched.h>
14#include <linux/mutex.h>
15#include <linux/mm.h>
16#include <linux/uaccess.h>
17#include <asm/synch.h>
ec249dd8 18#include <misc/cxl-base.h>
f204e0b8
IM		 19
20#include "cxl.h"
9bcf28cd 21#include "trace.h"
f204e0b8
IM		 22
23static int afu_control(struct cxl_afu *afu, u64 command,
24 u64 result, u64 mask, bool enabled)
25{
26 u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
27 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
9bcf28cd 28 int rc = 0;
f204e0b8
IM		 29
30 spin_lock(&afu->afu_cntl_lock);
31 pr_devel("AFU command starting: %llx\n", command);
32
9bcf28cd
IM		 33 trace_cxl_afu_ctrl(afu, command);
34
f204e0b8
IM		 35 cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl | command);
36
37 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
38 while ((AFU_Cntl & mask) != result) {
39 if (time_after_eq(jiffies, timeout)) {
40 dev_warn(&afu->dev, "WARNING: AFU control timed out!\n");
9bcf28cd
IM		 41 rc = -EBUSY;
42 goto out;
f204e0b8 43 }
0b3f9c75 44
5be587b1 45 if (!cxl_ops->link_ok(afu->adapter)) {
0b3f9c75
DA		 46 afu->enabled = enabled;
47 rc = -EIO;
48 goto out;
49 }
50
de369538 51 pr_devel_ratelimited("AFU control... (0x%016llx)\n",
f204e0b8
IM		 52 AFU_Cntl | command);
53 cpu_relax();
54 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
55 };
56 pr_devel("AFU command complete: %llx\n", command);
57 afu->enabled = enabled;
9bcf28cd
IM		 58out:
59 trace_cxl_afu_ctrl_done(afu, command, rc);
f204e0b8
IM		 60 spin_unlock(&afu->afu_cntl_lock);
61
9bcf28cd 62 return rc;
f204e0b8
IM		 63}
64
65static int afu_enable(struct cxl_afu *afu)
66{
67 pr_devel("AFU enable request\n");
68
69 return afu_control(afu, CXL_AFU_Cntl_An_E,
70 CXL_AFU_Cntl_An_ES_Enabled,
71 CXL_AFU_Cntl_An_ES_MASK, true);
72}
73
74int cxl_afu_disable(struct cxl_afu *afu)
75{
76 pr_devel("AFU disable request\n");
77
78 return afu_control(afu, 0, CXL_AFU_Cntl_An_ES_Disabled,
79 CXL_AFU_Cntl_An_ES_MASK, false);
80}
81
82/* This will disable as well as reset */
2b04cf31 83static int native_afu_reset(struct cxl_afu *afu)
f204e0b8
IM		 84{
85 pr_devel("AFU reset request\n");
86
87 return afu_control(afu, CXL_AFU_Cntl_An_RA,
88 CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled,
89 CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK,
90 false);
91}
92
2b04cf31 93static int native_afu_check_and_enable(struct cxl_afu *afu)
f204e0b8 94{
5be587b1 95 if (!cxl_ops->link_ok(afu->adapter)) {
0b3f9c75
DA		 96 WARN(1, "Refusing to enable afu while link down!\n");
97 return -EIO;
98 }
f204e0b8
IM		 99 if (afu->enabled)
100 return 0;
101 return afu_enable(afu);
102}
103
104int cxl_psl_purge(struct cxl_afu *afu)
105{
106 u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
107 u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
108 u64 dsisr, dar;
109 u64 start, end;
110 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
9bcf28cd
IM		 111 int rc = 0;
112
113 trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc);
f204e0b8
IM		 114
115 pr_devel("PSL purge request\n");
116
5be587b1 117 if (!cxl_ops->link_ok(afu->adapter)) {
0b3f9c75
DA		 118 dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n");
119 rc = -EIO;
120 goto out;
121 }
122
f204e0b8
IM		 123 if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
124 WARN(1, "psl_purge request while AFU not disabled!\n");
125 cxl_afu_disable(afu);
126 }
127
128 cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
129 PSL_CNTL | CXL_PSL_SCNTL_An_Pc);
130 start = local_clock();
131 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
132 while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK)
133 == CXL_PSL_SCNTL_An_Ps_Pending) {
134 if (time_after_eq(jiffies, timeout)) {
135 dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n");
9bcf28cd
IM		 136 rc = -EBUSY;
137 goto out;
f204e0b8 138 }
5be587b1 139 if (!cxl_ops->link_ok(afu->adapter)) {
0b3f9c75
DA		 140 rc = -EIO;
141 goto out;
142 }
143
f204e0b8 144 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
de369538 145 pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr);
f204e0b8
IM		 146 if (dsisr & CXL_PSL_DSISR_TRANS) {
147 dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
de369538 148 dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar);
f204e0b8
IM		 149 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
150 } else if (dsisr) {
de369538 151 dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr);
f204e0b8
IM		 152 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
153 } else {
154 cpu_relax();
155 }
156 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
157 };
158 end = local_clock();
159 pr_devel("PSL purged in %lld ns\n", end - start);
160
161 cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
162 PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc);
9bcf28cd
IM		 163out:
164 trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc);
165 return rc;
f204e0b8
IM		 166}
167
168static int spa_max_procs(int spa_size)
169{
170 /*
171 * From the CAIA:
172 * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255
173 * Most of that junk is really just an overly-complicated way of saying
174 * the last 256 bytes are __aligned(128), so it's really:
175 * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255
176 * and
177 * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1
178 * so
179 * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256
180 * Ignore the alignment (which is safe in this case as long as we are
181 * careful with our rounding) and solve for n:
182 */
183 return ((spa_size / 8) - 96) / 17;
184}
185
05155772 186int cxl_alloc_spa(struct cxl_afu *afu)
f204e0b8 187{
f204e0b8
IM		 188 /* Work out how many pages to allocate */
189 afu->spa_order = 0;
190 do {
191 afu->spa_order++;
192 afu->spa_size = (1 << afu->spa_order) * PAGE_SIZE;
193 afu->spa_max_procs = spa_max_procs(afu->spa_size);
194 } while (afu->spa_max_procs < afu->num_procs);
195
196 WARN_ON(afu->spa_size > 0x100000); /* Max size supported by the hardware */
197
198 if (!(afu->spa = (struct cxl_process_element *)
199 __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->spa_order))) {
200 pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n");
201 return -ENOMEM;
202 }
203 pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n",
204 1<<afu->spa_order, afu->spa_max_procs, afu->num_procs);
205
05155772
DA		 206 return 0;
207}
208
209static void attach_spa(struct cxl_afu *afu)
210{
211 u64 spap;
212
f204e0b8
IM		 213 afu->sw_command_status = (__be64 *)((char *)afu->spa +
214 ((afu->spa_max_procs + 3) * 128));
215
216 spap = virt_to_phys(afu->spa) & CXL_PSL_SPAP_Addr;
217 spap |= ((afu->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size;
218 spap |= CXL_PSL_SPAP_V;
219 pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", afu->spa, afu->spa_max_procs, afu->sw_command_status, spap);
220 cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap);
f204e0b8
IM		 221}
222
05155772 223static inline void detach_spa(struct cxl_afu *afu)
f204e0b8 224{
db7933f3 225 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0);
05155772
DA		 226}
227
228void cxl_release_spa(struct cxl_afu *afu)
229{
230 if (afu->spa) {
231 free_pages((unsigned long) afu->spa, afu->spa_order);
232 afu->spa = NULL;
233 }
f204e0b8
IM		 234}
235
236int cxl_tlb_slb_invalidate(struct cxl *adapter)
237{
238 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
239
240 pr_devel("CXL adapter wide TLBIA & SLBIA\n");
241
242 cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A);
243
244 cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL);
245 while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) {
246 if (time_after_eq(jiffies, timeout)) {
247 dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n");
248 return -EBUSY;
249 }
5be587b1 250 if (!cxl_ops->link_ok(adapter))
0b3f9c75 251 return -EIO;
f204e0b8
IM		 252 cpu_relax();
253 }
254
255 cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL);
256 while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) {
257 if (time_after_eq(jiffies, timeout)) {
258 dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n");
259 return -EBUSY;
260 }
5be587b1 261 if (!cxl_ops->link_ok(adapter))
0b3f9c75 262 return -EIO;
f204e0b8
IM		 263 cpu_relax();
264 }
265 return 0;
266}
267
f204e0b8
IM		 268static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1)
269{
270 int rc;
271
272 /* 1. Disable SSTP by writing 0 to SSTP1[V] */
273 cxl_p2n_write(afu, CXL_SSTP1_An, 0);
274
275 /* 2. Invalidate all SLB entries */
276 if ((rc = cxl_afu_slbia(afu)))
277 return rc;
278
279 /* 3. Set SSTP0_An */
280 cxl_p2n_write(afu, CXL_SSTP0_An, sstp0);
281
282 /* 4. Set SSTP1_An */
283 cxl_p2n_write(afu, CXL_SSTP1_An, sstp1);
284
285 return 0;
286}
287
288/* Using per slice version may improve performance here. (ie. SLBIA_An) */
289static void slb_invalid(struct cxl_context *ctx)
290{
291 struct cxl *adapter = ctx->afu->adapter;
292 u64 slbia;
293
294 WARN_ON(!mutex_is_locked(&ctx->afu->spa_mutex));
295
296 cxl_p1_write(adapter, CXL_PSL_LBISEL,
297 ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) |
298 be32_to_cpu(ctx->elem->lpid));
299 cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID);
300
301 while (1) {
5be587b1 302 if (!cxl_ops->link_ok(adapter))
0b3f9c75 303 break;
f204e0b8
IM		 304 slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA);
305 if (!(slbia & CXL_TLB_SLB_P))
306 break;
307 cpu_relax();
308 }
309}
310
311static int do_process_element_cmd(struct cxl_context *ctx,
312 u64 cmd, u64 pe_state)
313{
314 u64 state;
a98e6e9f 315 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
9bcf28cd
IM		 316 int rc = 0;
317
318 trace_cxl_llcmd(ctx, cmd);
f204e0b8
IM		 319
320 WARN_ON(!ctx->afu->enabled);
321
322 ctx->elem->software_state = cpu_to_be32(pe_state);
323 smp_wmb();
324 *(ctx->afu->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe);
325 smp_mb();
326 cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe);
327 while (1) {
a98e6e9f
IM		 328 if (time_after_eq(jiffies, timeout)) {
329 dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n");
9bcf28cd
IM		 330 rc = -EBUSY;
331 goto out;
a98e6e9f 332 }
5be587b1 333 if (!cxl_ops->link_ok(ctx->afu->adapter)) {
0b3f9c75
DA		 334 dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n");
335 rc = -EIO;
336 goto out;
337 }
f204e0b8
IM		 338 state = be64_to_cpup(ctx->afu->sw_command_status);
339 if (state == ~0ULL) {
340 pr_err("cxl: Error adding process element to AFU\n");
9bcf28cd
IM		 341 rc = -1;
342 goto out;
f204e0b8
IM		 343 }
344 if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) ==
345 (cmd | (cmd >> 16) | ctx->pe))
346 break;
347 /*
348 * The command won't finish in the PSL if there are
349 * outstanding DSIs. Hence we need to yield here in
350 * case there are outstanding DSIs that we need to
351 * service. Tuning possiblity: we could wait for a
352 * while before sched
353 */
354 schedule();
355
356 }
9bcf28cd
IM		 357out:
358 trace_cxl_llcmd_done(ctx, cmd, rc);
359 return rc;
f204e0b8
IM		 360}
361
362static int add_process_element(struct cxl_context *ctx)
363{
364 int rc = 0;
365
366 mutex_lock(&ctx->afu->spa_mutex);
367 pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe);
368 if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V)))
369 ctx->pe_inserted = true;
370 pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe);
371 mutex_unlock(&ctx->afu->spa_mutex);
372 return rc;
373}
374
375static int terminate_process_element(struct cxl_context *ctx)
376{
377 int rc = 0;
378
379 /* fast path terminate if it's already invalid */
380 if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V)))
381 return rc;
382
383 mutex_lock(&ctx->afu->spa_mutex);
384 pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);
0b3f9c75
DA		 385 /* We could be asked to terminate when the hw is down. That
386 * should always succeed: it's not running if the hw has gone
387 * away and is being reset.
388 */
5be587b1 389 if (cxl_ops->link_ok(ctx->afu->adapter))
0b3f9c75
DA		 390 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE,
391 CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T);
f204e0b8
IM		 392 ctx->elem->software_state = 0; /* Remove Valid bit */
393 pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe);
394 mutex_unlock(&ctx->afu->spa_mutex);
395 return rc;
396}
397
398static int remove_process_element(struct cxl_context *ctx)
399{
400 int rc = 0;
401
402 mutex_lock(&ctx->afu->spa_mutex);
403 pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe);
0b3f9c75
DA		 404
405 /* We could be asked to remove when the hw is down. Again, if
406 * the hw is down, the PE is gone, so we succeed.
407 */
5be587b1 408 if (cxl_ops->link_ok(ctx->afu->adapter))
0b3f9c75
DA		 409 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0);
410
411 if (!rc)
f204e0b8
IM		 412 ctx->pe_inserted = false;
413 slb_invalid(ctx);
414 pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe);
415 mutex_unlock(&ctx->afu->spa_mutex);
416
417 return rc;
418}
419
420
1a1a94b8 421void cxl_assign_psn_space(struct cxl_context *ctx)
f204e0b8
IM		 422{
423 if (!ctx->afu->pp_size || ctx->master) {
424 ctx->psn_phys = ctx->afu->psn_phys;
425 ctx->psn_size = ctx->afu->adapter->ps_size;
426 } else {
427 ctx->psn_phys = ctx->afu->psn_phys +
428 (ctx->afu->pp_offset + ctx->afu->pp_size * ctx->pe);
429 ctx->psn_size = ctx->afu->pp_size;
430 }
431}
432
433static int activate_afu_directed(struct cxl_afu *afu)
434{
435 int rc;
436
437 dev_info(&afu->dev, "Activating AFU directed mode\n");
438
4108efb0 439 afu->num_procs = afu->max_procs_virtualised;
05155772
DA		 440 if (afu->spa == NULL) {
441 if (cxl_alloc_spa(afu))
442 return -ENOMEM;
443 }
444 attach_spa(afu);
f204e0b8
IM		 445
446 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU);
447 cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
448 cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
449
450 afu->current_mode = CXL_MODE_DIRECTED;
f204e0b8
IM		 451
452 if ((rc = cxl_chardev_m_afu_add(afu)))
453 return rc;
454
455 if ((rc = cxl_sysfs_afu_m_add(afu)))
456 goto err;
457
458 if ((rc = cxl_chardev_s_afu_add(afu)))
459 goto err1;
460
461 return 0;
462err1:
463 cxl_sysfs_afu_m_remove(afu);
464err:
465 cxl_chardev_afu_remove(afu);
466 return rc;
467}
468
469#ifdef CONFIG_CPU_LITTLE_ENDIAN
470#define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE)
471#else
472#define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE))
473#endif
474
2f663527
MN		 475static u64 calculate_sr(struct cxl_context *ctx)
476{
477 u64 sr = 0;
478
e606e035 479 set_endian(sr);
2f663527
MN		 480 if (ctx->master)
481 sr |= CXL_PSL_SR_An_MP;
482 if (mfspr(SPRN_LPCR) & LPCR_TC)
483 sr |= CXL_PSL_SR_An_TC;
484 if (ctx->kernel) {
485 sr |= CXL_PSL_SR_An_R | (mfmsr() & MSR_SF);
486 sr |= CXL_PSL_SR_An_HV;
487 } else {
488 sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
2f663527
MN		 489 sr &= ~(CXL_PSL_SR_An_HV);
490 if (!test_tsk_thread_flag(current, TIF_32BIT))
491 sr |= CXL_PSL_SR_An_SF;
492 }
493 return sr;
494}
495
f204e0b8
IM		 496static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr)
497{
2f663527 498 u32 pid;
f204e0b8
IM		 499 int r, result;
500
1a1a94b8 501 cxl_assign_psn_space(ctx);
f204e0b8
IM		 502
503 ctx->elem->ctxtime = 0; /* disable */
504 ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
505 ctx->elem->haurp = 0; /* disable */
506 ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1));
507
2f663527
MN		 508 pid = current->pid;
509 if (ctx->kernel)
510 pid = 0;
f204e0b8 511 ctx->elem->common.tid = 0;
2f663527
MN		 512 ctx->elem->common.pid = cpu_to_be32(pid);
513
514 ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
f204e0b8
IM		 515
516 ctx->elem->common.csrp = 0; /* disable */
517 ctx->elem->common.aurp0 = 0; /* disable */
518 ctx->elem->common.aurp1 = 0; /* disable */
519
520 cxl_prefault(ctx, wed);
521
522 ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0);
523 ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1);
524
525 for (r = 0; r < CXL_IRQ_RANGES; r++) {
526 ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
527 ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
528 }
529
530 ctx->elem->common.amr = cpu_to_be64(amr);
531 ctx->elem->common.wed = cpu_to_be64(wed);
532
533 /* first guy needs to enable */
5be587b1 534 if ((result = cxl_ops->afu_check_and_enable(ctx->afu)))
f204e0b8
IM		 535 return result;
536
368857c1 537 return add_process_element(ctx);
f204e0b8
IM		 538}
539
540static int deactivate_afu_directed(struct cxl_afu *afu)
541{
542 dev_info(&afu->dev, "Deactivating AFU directed mode\n");
543
544 afu->current_mode = 0;
545 afu->num_procs = 0;
546
547 cxl_sysfs_afu_m_remove(afu);
548 cxl_chardev_afu_remove(afu);
549
5be587b1 550 cxl_ops->afu_reset(afu);
f204e0b8
IM		 551 cxl_afu_disable(afu);
552 cxl_psl_purge(afu);
553
f204e0b8
IM		 554 return 0;
555}
556
557static int activate_dedicated_process(struct cxl_afu *afu)
558{
559 dev_info(&afu->dev, "Activating dedicated process mode\n");
560
561 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
562
563 cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */
564 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */
565 cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
566 cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID));
567 cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */
568 cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1));
569
570 cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */
571 cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */
572 cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */
573
574 afu->current_mode = CXL_MODE_DEDICATED;
575 afu->num_procs = 1;
576
577 return cxl_chardev_d_afu_add(afu);
578}
579
580static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr)
581{
582 struct cxl_afu *afu = ctx->afu;
2f663527 583 u64 pid;
f204e0b8
IM		 584 int rc;
585
2f663527
MN		 586 pid = (u64)current->pid << 32;
587 if (ctx->kernel)
588 pid = 0;
589 cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid);
590
591 cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx));
f204e0b8
IM		 592
593 if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1)))
594 return rc;
595
596 cxl_prefault(ctx, wed);
597
598 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An,
599 (((u64)ctx->irqs.offset[0] & 0xffff) << 48) |
600 (((u64)ctx->irqs.offset[1] & 0xffff) << 32) |
601 (((u64)ctx->irqs.offset[2] & 0xffff) << 16) |
602 ((u64)ctx->irqs.offset[3] & 0xffff));
603 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64)
604 (((u64)ctx->irqs.range[0] & 0xffff) << 48) |
605 (((u64)ctx->irqs.range[1] & 0xffff) << 32) |
606 (((u64)ctx->irqs.range[2] & 0xffff) << 16) |
607 ((u64)ctx->irqs.range[3] & 0xffff));
608
609 cxl_p2n_write(afu, CXL_PSL_AMR_An, amr);
610
611 /* master only context for dedicated */
1a1a94b8 612 cxl_assign_psn_space(ctx);
f204e0b8 613
5be587b1 614 if ((rc = cxl_ops->afu_reset(afu)))
f204e0b8
IM		 615 return rc;
616
617 cxl_p2n_write(afu, CXL_PSL_WED_An, wed);
618
619 return afu_enable(afu);
620}
621
622static int deactivate_dedicated_process(struct cxl_afu *afu)
623{
624 dev_info(&afu->dev, "Deactivating dedicated process mode\n");
625
626 afu->current_mode = 0;
627 afu->num_procs = 0;
628
629 cxl_chardev_afu_remove(afu);
630
631 return 0;
632}
633
2b04cf31 634static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode)
f204e0b8
IM		 635{
636 if (mode == CXL_MODE_DIRECTED)
637 return deactivate_afu_directed(afu);
638 if (mode == CXL_MODE_DEDICATED)
639 return deactivate_dedicated_process(afu);
640 return 0;
641}
642
2b04cf31 643static int native_afu_activate_mode(struct cxl_afu *afu, int mode)
f204e0b8
IM		 644{
645 if (!mode)
646 return 0;
647 if (!(mode & afu->modes_supported))
648 return -EINVAL;
649
5be587b1 650 if (!cxl_ops->link_ok(afu->adapter)) {
0b3f9c75
DA		 651 WARN(1, "Device link is down, refusing to activate!\n");
652 return -EIO;
653 }
654
f204e0b8
IM		 655 if (mode == CXL_MODE_DIRECTED)
656 return activate_afu_directed(afu);
657 if (mode == CXL_MODE_DEDICATED)
658 return activate_dedicated_process(afu);
659
660 return -EINVAL;
661}
662
2b04cf31
FB		 663static int native_attach_process(struct cxl_context *ctx, bool kernel,
664 u64 wed, u64 amr)
f204e0b8 665{
5be587b1 666 if (!cxl_ops->link_ok(ctx->afu->adapter)) {
0b3f9c75
DA		 667 WARN(1, "Device link is down, refusing to attach process!\n");
668 return -EIO;
669 }
670
f204e0b8
IM		 671 ctx->kernel = kernel;
672 if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
673 return attach_afu_directed(ctx, wed, amr);
674
675 if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
676 return attach_dedicated(ctx, wed, amr);
677
678 return -EINVAL;
679}
680
681static inline int detach_process_native_dedicated(struct cxl_context *ctx)
682{
5be587b1 683 cxl_ops->afu_reset(ctx->afu);
f204e0b8
IM		 684 cxl_afu_disable(ctx->afu);
685 cxl_psl_purge(ctx->afu);
686 return 0;
687}
688
f204e0b8
IM		 689static inline int detach_process_native_afu_directed(struct cxl_context *ctx)
690{
691 if (!ctx->pe_inserted)
692 return 0;
693 if (terminate_process_element(ctx))
694 return -1;
695 if (remove_process_element(ctx))
696 return -1;
697
698 return 0;
699}
700
2b04cf31 701static int native_detach_process(struct cxl_context *ctx)
f204e0b8 702{
9bcf28cd
IM		 703 trace_cxl_detach(ctx);
704
f204e0b8
IM		 705 if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
706 return detach_process_native_dedicated(ctx);
707
708 return detach_process_native_afu_directed(ctx);
709}
710
2b04cf31 711static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info)
f204e0b8
IM		 712{
713 u64 pidtid;
714
0b3f9c75
DA		 715 /* If the adapter has gone away, we can't get any meaningful
716 * information.
717 */
5be587b1 718 if (!cxl_ops->link_ok(afu->adapter))
0b3f9c75
DA		 719 return -EIO;
720
bc78b05b
IM		 721 info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
722 info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
723 info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);
724 pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An);
f204e0b8
IM		 725 info->pid = pidtid >> 32;
726 info->tid = pidtid & 0xffffffff;
bc78b05b
IM		 727 info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An);
728 info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
444c4ba4 729 info->proc_handle = 0;
f204e0b8
IM		 730
731 return 0;
732}
733
2b04cf31
FB		 734static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx,
735 u64 dsisr, u64 errstat)
d56d301b
FB		 736{
737 u64 fir1, fir2, fir_slice, serr, afu_debug;
738
739 fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1);
740 fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2);
741 fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An);
742 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
743 afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An);
744
745 dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat);
746 dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
747 dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
748 dev_crit(&ctx->afu->dev, "PSL_SERR_An: 0x%016llx\n", serr);
749 dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
750 dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
751
752 dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n");
753 cxl_stop_trace(ctx->afu->adapter);
754
5be587b1 755 return cxl_ops->ack_irq(ctx, 0, errstat);
d56d301b
FB		 756}
757
758static irqreturn_t fail_psl_irq(struct cxl_afu *afu, struct cxl_irq_info *irq_info)
759{
760 if (irq_info->dsisr & CXL_PSL_DSISR_TRANS)
761 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
762 else
763 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
764
765 return IRQ_HANDLED;
766}
767
2b04cf31 768static irqreturn_t native_irq_multiplexed(int irq, void *data)
d56d301b
FB		 769{
770 struct cxl_afu *afu = data;
771 struct cxl_context *ctx;
772 struct cxl_irq_info irq_info;
773 int ph = cxl_p2n_read(afu, CXL_PSL_PEHandle_An) & 0xffff;
774 int ret;
775
2b04cf31 776 if ((ret = native_get_irq_info(afu, &irq_info))) {
d56d301b
FB		 777 WARN(1, "Unable to get CXL IRQ Info: %i\n", ret);
778 return fail_psl_irq(afu, &irq_info);
779 }
780
781 rcu_read_lock();
782 ctx = idr_find(&afu->contexts_idr, ph);
783 if (ctx) {
784 ret = cxl_irq(irq, ctx, &irq_info);
785 rcu_read_unlock();
786 return ret;
787 }
788 rcu_read_unlock();
789
790 WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR"
791 " %016llx\n(Possible AFU HW issue - was a term/remove acked"
792 " with outstanding transactions?)\n", ph, irq_info.dsisr,
793 irq_info.dar);
794 return fail_psl_irq(afu, &irq_info);
795}
796
2b04cf31 797static irqreturn_t native_slice_irq_err(int irq, void *data)
d56d301b
FB		 798{
799 struct cxl_afu *afu = data;
800 u64 fir_slice, errstat, serr, afu_debug;
801
802 WARN(irq, "CXL SLICE ERROR interrupt %i\n", irq);
803
804 serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
805 fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An);
806 errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
807 afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An);
808 dev_crit(&afu->dev, "PSL_SERR_An: 0x%016llx\n", serr);
809 dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
810 dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat);
811 dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
812
813 cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
814
815 return IRQ_HANDLED;
816}
817
2b04cf31 818static irqreturn_t native_irq_err(int irq, void *data)
d56d301b
FB		 819{
820 struct cxl *adapter = data;
821 u64 fir1, fir2, err_ivte;
822
823 WARN(1, "CXL ERROR interrupt %i\n", irq);
824
825 err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE);
826 dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte);
827
828 dev_crit(&adapter->dev, "STOPPING CXL TRACE\n");
829 cxl_stop_trace(adapter);
830
831 fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
832 fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
833
834 dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2);
835
836 return IRQ_HANDLED;
837}
838
2b04cf31 839int cxl_native_register_psl_err_irq(struct cxl *adapter)
d56d301b
FB		 840{
841 int rc;
842
843 adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
844 dev_name(&adapter->dev));
845 if (!adapter->irq_name)
846 return -ENOMEM;
847
2b04cf31 848 if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter,
d56d301b
FB		 849 &adapter->err_hwirq,
850 &adapter->err_virq,
851 adapter->irq_name))) {
852 kfree(adapter->irq_name);
853 adapter->irq_name = NULL;
854 return rc;
855 }
856
857 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->err_hwirq & 0xffff);
858
859 return 0;
860}
861
2b04cf31 862void cxl_native_release_psl_err_irq(struct cxl *adapter)
d56d301b
FB		 863{
864 if (adapter->err_virq != irq_find_mapping(NULL, adapter->err_hwirq))
865 return;
866
867 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);
868 cxl_unmap_irq(adapter->err_virq, adapter);
5be587b1 869 cxl_ops->release_one_irq(adapter, adapter->err_hwirq);
d56d301b
FB		 870 kfree(adapter->irq_name);
871}
872
2b04cf31 873int cxl_native_register_serr_irq(struct cxl_afu *afu)
d56d301b
FB		 874{
875 u64 serr;
876 int rc;
877
878 afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
879 dev_name(&afu->dev));
880 if (!afu->err_irq_name)
881 return -ENOMEM;
882
2b04cf31 883 if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu,
d56d301b
FB		 884 &afu->serr_hwirq,
885 &afu->serr_virq, afu->err_irq_name))) {
886 kfree(afu->err_irq_name);
887 afu->err_irq_name = NULL;
888 return rc;
889 }
890
891 serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
892 serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff);
893 cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
894
895 return 0;
896}
897
2b04cf31 898void cxl_native_release_serr_irq(struct cxl_afu *afu)
d56d301b
FB		 899{
900 if (afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq))
901 return;
902
903 cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000);
904 cxl_unmap_irq(afu->serr_virq, afu);
5be587b1 905 cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq);
d56d301b
FB		 906 kfree(afu->err_irq_name);
907}
908
2b04cf31 909int cxl_native_register_psl_irq(struct cxl_afu *afu)
d56d301b
FB		 910{
911 int rc;
912
913 afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s",
914 dev_name(&afu->dev));
915 if (!afu->psl_irq_name)
916 return -ENOMEM;
917
2b04cf31 918 if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed, afu,
d56d301b
FB		 919 &afu->psl_hwirq, &afu->psl_virq,
920 afu->psl_irq_name))) {
921 kfree(afu->psl_irq_name);
922 afu->psl_irq_name = NULL;
923 }
924 return rc;
925}
926
2b04cf31 927void cxl_native_release_psl_irq(struct cxl_afu *afu)
d56d301b
FB		 928{
929 if (afu->psl_virq != irq_find_mapping(NULL, afu->psl_hwirq))
930 return;
931
932 cxl_unmap_irq(afu->psl_virq, afu);
5be587b1 933 cxl_ops->release_one_irq(afu->adapter, afu->psl_hwirq);
d56d301b
FB		 934 kfree(afu->psl_irq_name);
935}
936
f204e0b8
IM		 937static void recover_psl_err(struct cxl_afu *afu, u64 errstat)
938{
939 u64 dsisr;
940
de369538 941 pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat);
f204e0b8
IM		 942
943 /* Clear PSL_DSISR[PE] */
944 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
945 cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE);
946
947 /* Write 1s to clear error status bits */
948 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat);
949}
950
2b04cf31 951static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask)
f204e0b8 952{
9bcf28cd 953 trace_cxl_psl_irq_ack(ctx, tfc);
f204e0b8
IM		 954 if (tfc)
955 cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc);
956 if (psl_reset_mask)
957 recover_psl_err(ctx->afu, psl_reset_mask);
958
959 return 0;
960}
961
962int cxl_check_error(struct cxl_afu *afu)
963{
964 return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL);
965}
d56d301b 966
2b04cf31 967static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out)
d56d301b 968{
5be587b1
FB		 969 if (unlikely(!cxl_ops->link_ok(afu->adapter)))
970 return -EIO;
971 if (unlikely(off >= afu->crs_len))
972 return -ERANGE;
973 *out = in_le64(afu->afu_desc_mmio + afu->crs_offset +
974 (cr * afu->crs_len) + off);
975 return 0;
d56d301b
FB		 976}
977
2b04cf31 978static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out)
d56d301b 979{
5be587b1
FB		 980 if (unlikely(!cxl_ops->link_ok(afu->adapter)))
981 return -EIO;
982 if (unlikely(off >= afu->crs_len))
983 return -ERANGE;
984 *out = in_le32(afu->afu_desc_mmio + afu->crs_offset +
985 (cr * afu->crs_len) + off);
986 return 0;
d56d301b
FB		 987}
988
2b04cf31 989static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out)
d56d301b
FB		 990{
991 u64 aligned_off = off & ~0x3L;
992 u32 val;
5be587b1 993 int rc;
d56d301b 994
2b04cf31 995 rc = native_afu_cr_read32(afu, cr, aligned_off, &val);
5be587b1
FB		 996 if (!rc)
997 *out = (val >> ((off & 0x3) * 8)) & 0xffff;
998 return rc;
d56d301b
FB		 999}
1000
2b04cf31 1001static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out)
d56d301b
FB		 1002{
1003 u64 aligned_off = off & ~0x3L;
1004 u32 val;
5be587b1 1005 int rc;
d56d301b 1006
2b04cf31 1007 rc = native_afu_cr_read32(afu, cr, aligned_off, &val);
5be587b1
FB		 1008 if (!rc)
1009 *out = (val >> ((off & 0x3) * 8)) & 0xff;
1010 return rc;
d56d301b 1011}
5be587b1
FB		 1012
1013const struct cxl_backend_ops cxl_native_ops = {
1014 .module = THIS_MODULE,
2b04cf31
FB		 1015 .adapter_reset = cxl_pci_reset,
1016 .alloc_one_irq = cxl_pci_alloc_one_irq,
1017 .release_one_irq = cxl_pci_release_one_irq,
1018 .alloc_irq_ranges = cxl_pci_alloc_irq_ranges,
1019 .release_irq_ranges = cxl_pci_release_irq_ranges,
1020 .setup_irq = cxl_pci_setup_irq,
1021 .handle_psl_slice_error = native_handle_psl_slice_error,
5be587b1 1022 .psl_interrupt = NULL,
2b04cf31
FB		 1023 .ack_irq = native_ack_irq,
1024 .attach_process = native_attach_process,
1025 .detach_process = native_detach_process,
5be587b1 1026 .link_ok = cxl_adapter_link_ok,
2b04cf31
FB		 1027 .release_afu = cxl_pci_release_afu,
1028 .afu_read_err_buffer = cxl_pci_afu_read_err_buffer,
1029 .afu_check_and_enable = native_afu_check_and_enable,
1030 .afu_activate_mode = native_afu_activate_mode,
1031 .afu_deactivate_mode = native_afu_deactivate_mode,
1032 .afu_reset = native_afu_reset,
1033 .afu_cr_read8 = native_afu_cr_read8,
1034 .afu_cr_read16 = native_afu_cr_read16,
1035 .afu_cr_read32 = native_afu_cr_read32,
1036 .afu_cr_read64 = native_afu_cr_read64,
5be587b1 1037};
Linux 6.x block layer and io_uring tree(s)