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f204e0b8 IM |
1 | /* |
2 | * Copyright 2014 IBM Corp. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/interrupt.h> | |
11 | #include <linux/workqueue.h> | |
12 | #include <linux/sched.h> | |
13 | #include <linux/wait.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/pid.h> | |
16 | #include <asm/cputable.h> | |
ec249dd8 | 17 | #include <misc/cxl-base.h> |
f204e0b8 IM |
18 | |
19 | #include "cxl.h" | |
9bcf28cd | 20 | #include "trace.h" |
f204e0b8 | 21 | |
f204e0b8 IM |
22 | static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 dar) |
23 | { | |
24 | ctx->dsisr = dsisr; | |
25 | ctx->dar = dar; | |
26 | schedule_work(&ctx->fault_work); | |
27 | return IRQ_HANDLED; | |
28 | } | |
29 | ||
86331862 | 30 | irqreturn_t cxl_irq(int irq, void *data, struct cxl_irq_info *irq_info) |
f204e0b8 IM |
31 | { |
32 | struct cxl_context *ctx = data; | |
f204e0b8 | 33 | u64 dsisr, dar; |
f204e0b8 | 34 | |
bc78b05b IM |
35 | dsisr = irq_info->dsisr; |
36 | dar = irq_info->dar; | |
f204e0b8 | 37 | |
9bcf28cd IM |
38 | trace_cxl_psl_irq(ctx, irq, dsisr, dar); |
39 | ||
f204e0b8 IM |
40 | pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar); |
41 | ||
42 | if (dsisr & CXL_PSL_DSISR_An_DS) { | |
43 | /* | |
44 | * We don't inherently need to sleep to handle this, but we do | |
45 | * need to get a ref to the task's mm, which we can't do from | |
46 | * irq context without the potential for a deadlock since it | |
47 | * takes the task_lock. An alternate option would be to keep a | |
48 | * reference to the task's mm the entire time it has cxl open, | |
49 | * but to do that we need to solve the issue where we hold a | |
50 | * ref to the mm, but the mm can hold a ref to the fd after an | |
51 | * mmap preventing anything from being cleaned up. | |
52 | */ | |
53 | pr_devel("Scheduling segment miss handling for later pe: %i\n", ctx->pe); | |
54 | return schedule_cxl_fault(ctx, dsisr, dar); | |
55 | } | |
56 | ||
57 | if (dsisr & CXL_PSL_DSISR_An_M) | |
58 | pr_devel("CXL interrupt: PTE not found\n"); | |
59 | if (dsisr & CXL_PSL_DSISR_An_P) | |
60 | pr_devel("CXL interrupt: Storage protection violation\n"); | |
61 | if (dsisr & CXL_PSL_DSISR_An_A) | |
62 | pr_devel("CXL interrupt: AFU lock access to write through or cache inhibited storage\n"); | |
63 | if (dsisr & CXL_PSL_DSISR_An_S) | |
64 | pr_devel("CXL interrupt: Access was afu_wr or afu_zero\n"); | |
65 | if (dsisr & CXL_PSL_DSISR_An_K) | |
66 | pr_devel("CXL interrupt: Access not permitted by virtual page class key protection\n"); | |
67 | ||
68 | if (dsisr & CXL_PSL_DSISR_An_DM) { | |
69 | /* | |
70 | * In some cases we might be able to handle the fault | |
71 | * immediately if hash_page would succeed, but we still need | |
72 | * the task's mm, which as above we can't get without a lock | |
73 | */ | |
74 | pr_devel("Scheduling page fault handling for later pe: %i\n", ctx->pe); | |
75 | return schedule_cxl_fault(ctx, dsisr, dar); | |
76 | } | |
77 | if (dsisr & CXL_PSL_DSISR_An_ST) | |
78 | WARN(1, "CXL interrupt: Segment Table PTE not found\n"); | |
79 | if (dsisr & CXL_PSL_DSISR_An_UR) | |
80 | pr_devel("CXL interrupt: AURP PTE not found\n"); | |
81 | if (dsisr & CXL_PSL_DSISR_An_PE) | |
5be587b1 FB |
82 | return cxl_ops->handle_psl_slice_error(ctx, dsisr, |
83 | irq_info->errstat); | |
f204e0b8 | 84 | if (dsisr & CXL_PSL_DSISR_An_AE) { |
de369538 | 85 | pr_devel("CXL interrupt: AFU Error 0x%016llx\n", irq_info->afu_err); |
f204e0b8 IM |
86 | |
87 | if (ctx->pending_afu_err) { | |
88 | /* | |
89 | * This shouldn't happen - the PSL treats these errors | |
90 | * as fatal and will have reset the AFU, so there's not | |
91 | * much point buffering multiple AFU errors. | |
92 | * OTOH if we DO ever see a storm of these come in it's | |
93 | * probably best that we log them somewhere: | |
94 | */ | |
95 | dev_err_ratelimited(&ctx->afu->dev, "CXL AFU Error " | |
de369538 | 96 | "undelivered to pe %i: 0x%016llx\n", |
bc78b05b | 97 | ctx->pe, irq_info->afu_err); |
f204e0b8 IM |
98 | } else { |
99 | spin_lock(&ctx->lock); | |
bc78b05b | 100 | ctx->afu_err = irq_info->afu_err; |
f204e0b8 IM |
101 | ctx->pending_afu_err = 1; |
102 | spin_unlock(&ctx->lock); | |
103 | ||
104 | wake_up_all(&ctx->wq); | |
105 | } | |
106 | ||
5be587b1 | 107 | cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_A, 0); |
a6130ed2 | 108 | return IRQ_HANDLED; |
f204e0b8 IM |
109 | } |
110 | if (dsisr & CXL_PSL_DSISR_An_OC) | |
111 | pr_devel("CXL interrupt: OS Context Warning\n"); | |
112 | ||
113 | WARN(1, "Unhandled CXL PSL IRQ\n"); | |
114 | return IRQ_HANDLED; | |
115 | } | |
116 | ||
f204e0b8 IM |
117 | static irqreturn_t cxl_irq_afu(int irq, void *data) |
118 | { | |
119 | struct cxl_context *ctx = data; | |
120 | irq_hw_number_t hwirq = irqd_to_hwirq(irq_get_irq_data(irq)); | |
121 | int irq_off, afu_irq = 1; | |
122 | __u16 range; | |
123 | int r; | |
124 | ||
125 | for (r = 1; r < CXL_IRQ_RANGES; r++) { | |
126 | irq_off = hwirq - ctx->irqs.offset[r]; | |
127 | range = ctx->irqs.range[r]; | |
128 | if (irq_off >= 0 && irq_off < range) { | |
129 | afu_irq += irq_off; | |
130 | break; | |
131 | } | |
132 | afu_irq += range; | |
133 | } | |
134 | if (unlikely(r >= CXL_IRQ_RANGES)) { | |
135 | WARN(1, "Recieved AFU IRQ out of range for pe %i (virq %i hwirq %lx)\n", | |
136 | ctx->pe, irq, hwirq); | |
137 | return IRQ_HANDLED; | |
138 | } | |
139 | ||
9bcf28cd | 140 | trace_cxl_afu_irq(ctx, afu_irq, irq, hwirq); |
f204e0b8 IM |
141 | pr_devel("Received AFU interrupt %i for pe: %i (virq %i hwirq %lx)\n", |
142 | afu_irq, ctx->pe, irq, hwirq); | |
143 | ||
144 | if (unlikely(!ctx->irq_bitmap)) { | |
145 | WARN(1, "Recieved AFU IRQ for context with no IRQ bitmap\n"); | |
146 | return IRQ_HANDLED; | |
147 | } | |
148 | spin_lock(&ctx->lock); | |
149 | set_bit(afu_irq - 1, ctx->irq_bitmap); | |
150 | ctx->pending_irq = true; | |
151 | spin_unlock(&ctx->lock); | |
152 | ||
153 | wake_up_all(&ctx->wq); | |
154 | ||
155 | return IRQ_HANDLED; | |
156 | } | |
157 | ||
158 | unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq, | |
80fa93fc | 159 | irq_handler_t handler, void *cookie, const char *name) |
f204e0b8 IM |
160 | { |
161 | unsigned int virq; | |
162 | int result; | |
163 | ||
164 | /* IRQ Domain? */ | |
165 | virq = irq_create_mapping(NULL, hwirq); | |
166 | if (!virq) { | |
167 | dev_warn(&adapter->dev, "cxl_map_irq: irq_create_mapping failed\n"); | |
168 | return 0; | |
169 | } | |
170 | ||
5be587b1 FB |
171 | if (cxl_ops->setup_irq) |
172 | cxl_ops->setup_irq(adapter, hwirq, virq); | |
f204e0b8 IM |
173 | |
174 | pr_devel("hwirq %#lx mapped to virq %u\n", hwirq, virq); | |
175 | ||
80fa93fc | 176 | result = request_irq(virq, handler, 0, name, cookie); |
f204e0b8 IM |
177 | if (result) { |
178 | dev_warn(&adapter->dev, "cxl_map_irq: request_irq failed: %i\n", result); | |
179 | return 0; | |
180 | } | |
181 | ||
182 | return virq; | |
183 | } | |
184 | ||
185 | void cxl_unmap_irq(unsigned int virq, void *cookie) | |
186 | { | |
187 | free_irq(virq, cookie); | |
188 | irq_dispose_mapping(virq); | |
189 | } | |
190 | ||
86331862 CL |
191 | int cxl_register_one_irq(struct cxl *adapter, |
192 | irq_handler_t handler, | |
193 | void *cookie, | |
194 | irq_hw_number_t *dest_hwirq, | |
195 | unsigned int *dest_virq, | |
196 | const char *name) | |
f204e0b8 IM |
197 | { |
198 | int hwirq, virq; | |
199 | ||
5be587b1 | 200 | if ((hwirq = cxl_ops->alloc_one_irq(adapter)) < 0) |
f204e0b8 IM |
201 | return hwirq; |
202 | ||
80fa93fc | 203 | if (!(virq = cxl_map_irq(adapter, hwirq, handler, cookie, name))) |
f204e0b8 IM |
204 | goto err; |
205 | ||
206 | *dest_hwirq = hwirq; | |
207 | *dest_virq = virq; | |
208 | ||
209 | return 0; | |
210 | ||
211 | err: | |
5be587b1 | 212 | cxl_ops->release_one_irq(adapter, hwirq); |
f204e0b8 IM |
213 | return -ENOMEM; |
214 | } | |
215 | ||
8dde152e | 216 | void afu_irq_name_free(struct cxl_context *ctx) |
80fa93fc MN |
217 | { |
218 | struct cxl_irq_name *irq_name, *tmp; | |
219 | ||
220 | list_for_each_entry_safe(irq_name, tmp, &ctx->irq_names, list) { | |
221 | kfree(irq_name->name); | |
222 | list_del(&irq_name->list); | |
223 | kfree(irq_name); | |
224 | } | |
f204e0b8 IM |
225 | } |
226 | ||
c358d84b | 227 | int afu_allocate_irqs(struct cxl_context *ctx, u32 count) |
f204e0b8 | 228 | { |
80fa93fc MN |
229 | int rc, r, i, j = 1; |
230 | struct cxl_irq_name *irq_name; | |
f204e0b8 | 231 | |
a6897f39 VJ |
232 | /* Initialize the list head to hold irq names */ |
233 | INIT_LIST_HEAD(&ctx->irq_names); | |
234 | ||
5be587b1 FB |
235 | if ((rc = cxl_ops->alloc_irq_ranges(&ctx->irqs, ctx->afu->adapter, |
236 | count))) | |
f204e0b8 IM |
237 | return rc; |
238 | ||
239 | /* Multiplexed PSL Interrupt */ | |
240 | ctx->irqs.offset[0] = ctx->afu->psl_hwirq; | |
241 | ctx->irqs.range[0] = 1; | |
242 | ||
243 | ctx->irq_count = count; | |
244 | ctx->irq_bitmap = kcalloc(BITS_TO_LONGS(count), | |
245 | sizeof(*ctx->irq_bitmap), GFP_KERNEL); | |
246 | if (!ctx->irq_bitmap) | |
a6897f39 | 247 | goto out; |
80fa93fc MN |
248 | |
249 | /* | |
250 | * Allocate names first. If any fail, bail out before allocating | |
251 | * actual hardware IRQs. | |
252 | */ | |
80fa93fc | 253 | for (r = 1; r < CXL_IRQ_RANGES; r++) { |
d3383aaa | 254 | for (i = 0; i < ctx->irqs.range[r]; i++) { |
80fa93fc MN |
255 | irq_name = kmalloc(sizeof(struct cxl_irq_name), |
256 | GFP_KERNEL); | |
257 | if (!irq_name) | |
258 | goto out; | |
259 | irq_name->name = kasprintf(GFP_KERNEL, "cxl-%s-pe%i-%i", | |
260 | dev_name(&ctx->afu->dev), | |
261 | ctx->pe, j); | |
262 | if (!irq_name->name) { | |
263 | kfree(irq_name); | |
264 | goto out; | |
265 | } | |
266 | /* Add to tail so next look get the correct order */ | |
267 | list_add_tail(&irq_name->list, &ctx->irq_names); | |
268 | j++; | |
269 | } | |
270 | } | |
c358d84b MN |
271 | return 0; |
272 | ||
273 | out: | |
5be587b1 | 274 | cxl_ops->release_irq_ranges(&ctx->irqs, ctx->afu->adapter); |
c358d84b MN |
275 | afu_irq_name_free(ctx); |
276 | return -ENOMEM; | |
277 | } | |
278 | ||
3d6b040e | 279 | static void afu_register_hwirqs(struct cxl_context *ctx) |
c358d84b MN |
280 | { |
281 | irq_hw_number_t hwirq; | |
282 | struct cxl_irq_name *irq_name; | |
283 | int r,i; | |
80fa93fc MN |
284 | |
285 | /* We've allocated all memory now, so let's do the irq allocations */ | |
286 | irq_name = list_first_entry(&ctx->irq_names, struct cxl_irq_name, list); | |
f204e0b8 IM |
287 | for (r = 1; r < CXL_IRQ_RANGES; r++) { |
288 | hwirq = ctx->irqs.offset[r]; | |
289 | for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) { | |
290 | cxl_map_irq(ctx->afu->adapter, hwirq, | |
80fa93fc MN |
291 | cxl_irq_afu, ctx, irq_name->name); |
292 | irq_name = list_next_entry(irq_name, list); | |
f204e0b8 IM |
293 | } |
294 | } | |
c358d84b | 295 | } |
f204e0b8 | 296 | |
c358d84b MN |
297 | int afu_register_irqs(struct cxl_context *ctx, u32 count) |
298 | { | |
299 | int rc; | |
80fa93fc | 300 | |
c358d84b MN |
301 | rc = afu_allocate_irqs(ctx, count); |
302 | if (rc) | |
303 | return rc; | |
304 | ||
305 | afu_register_hwirqs(ctx); | |
306 | return 0; | |
d56d301b | 307 | } |
f204e0b8 | 308 | |
6428832a | 309 | void afu_release_irqs(struct cxl_context *ctx, void *cookie) |
f204e0b8 IM |
310 | { |
311 | irq_hw_number_t hwirq; | |
312 | unsigned int virq; | |
313 | int r, i; | |
314 | ||
315 | for (r = 1; r < CXL_IRQ_RANGES; r++) { | |
316 | hwirq = ctx->irqs.offset[r]; | |
317 | for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) { | |
318 | virq = irq_find_mapping(NULL, hwirq); | |
319 | if (virq) | |
6428832a | 320 | cxl_unmap_irq(virq, cookie); |
f204e0b8 IM |
321 | } |
322 | } | |
323 | ||
80fa93fc | 324 | afu_irq_name_free(ctx); |
5be587b1 | 325 | cxl_ops->release_irq_ranges(&ctx->irqs, ctx->afu->adapter); |
8c7dd08a | 326 | |
8c7dd08a | 327 | ctx->irq_count = 0; |
f204e0b8 | 328 | } |