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f204e0b8 IM |
1 | /* |
2 | * Copyright 2014 IBM Corp. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #ifndef _CXL_H_ | |
11 | #define _CXL_H_ | |
12 | ||
13 | #include <linux/interrupt.h> | |
14 | #include <linux/semaphore.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/cdev.h> | |
18 | #include <linux/pid.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/pci.h> | |
0520336a | 21 | #include <linux/fs.h> |
f204e0b8 IM |
22 | #include <asm/cputable.h> |
23 | #include <asm/mmu.h> | |
24 | #include <asm/reg.h> | |
ec249dd8 | 25 | #include <misc/cxl-base.h> |
f204e0b8 IM |
26 | |
27 | #include <uapi/misc/cxl.h> | |
28 | ||
29 | extern uint cxl_verbose; | |
30 | ||
31 | #define CXL_TIMEOUT 5 | |
32 | ||
33 | /* | |
34 | * Bump version each time a user API change is made, whether it is | |
35 | * backwards compatible ot not. | |
36 | */ | |
d9232a3d | 37 | #define CXL_API_VERSION 2 |
f204e0b8 IM |
38 | #define CXL_API_VERSION_COMPATIBLE 1 |
39 | ||
40 | /* | |
41 | * Opaque types to avoid accidentally passing registers for the wrong MMIO | |
42 | * | |
43 | * At the end of the day, I'm not married to using typedef here, but it might | |
44 | * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and | |
45 | * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write. | |
46 | * | |
47 | * I'm quite happy if these are changed back to #defines before upstreaming, it | |
48 | * should be little more than a regexp search+replace operation in this file. | |
49 | */ | |
50 | typedef struct { | |
51 | const int x; | |
52 | } cxl_p1_reg_t; | |
53 | typedef struct { | |
54 | const int x; | |
55 | } cxl_p1n_reg_t; | |
56 | typedef struct { | |
57 | const int x; | |
58 | } cxl_p2n_reg_t; | |
59 | #define cxl_reg_off(reg) \ | |
60 | (reg.x) | |
61 | ||
62 | /* Memory maps. Ref CXL Appendix A */ | |
63 | ||
64 | /* PSL Privilege 1 Memory Map */ | |
65 | /* Configuration and Control area */ | |
66 | static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000}; | |
67 | static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008}; | |
68 | static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010}; | |
69 | static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018}; | |
70 | static const cxl_p1_reg_t CXL_PSL_Control = {0x0020}; | |
71 | /* Downloading */ | |
72 | static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060}; | |
73 | static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068}; | |
74 | ||
75 | /* PSL Lookaside Buffer Management Area */ | |
76 | static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080}; | |
77 | static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088}; | |
78 | static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090}; | |
79 | static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0}; | |
80 | static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8}; | |
81 | static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0}; | |
82 | ||
83 | /* 0x00C0:7EFF Implementation dependent area */ | |
84 | static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100}; | |
85 | static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108}; | |
390fd592 | 86 | static const cxl_p1_reg_t CXL_PSL_Timebase = {0x0110}; |
f204e0b8 IM |
87 | static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118}; |
88 | static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128}; | |
390fd592 | 89 | static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140}; |
f204e0b8 IM |
90 | static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148}; |
91 | static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150}; | |
92 | static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158}; | |
93 | static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170}; | |
94 | /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */ | |
95 | /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */ | |
96 | ||
97 | /* PSL Slice Privilege 1 Memory Map */ | |
98 | /* Configuration Area */ | |
99 | static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00}; | |
100 | static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08}; | |
101 | static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10}; | |
102 | static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18}; | |
103 | static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20}; | |
104 | static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28}; | |
105 | /* Memory Management and Lookaside Buffer Management */ | |
106 | static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30}; | |
107 | static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38}; | |
108 | /* Pointer Area */ | |
109 | static const cxl_p1n_reg_t CXL_HAURP_An = {0x80}; | |
110 | static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88}; | |
111 | static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90}; | |
112 | /* Control Area */ | |
113 | static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0}; | |
114 | static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8}; | |
115 | static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0}; | |
116 | static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8}; | |
117 | /* 0xC0:FF Implementation Dependent Area */ | |
118 | static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0}; | |
119 | static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8}; | |
120 | static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0}; | |
121 | static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8}; | |
122 | static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0}; | |
123 | static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8}; | |
124 | ||
125 | /* PSL Slice Privilege 2 Memory Map */ | |
126 | /* Configuration and Control Area */ | |
127 | static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000}; | |
128 | static const cxl_p2n_reg_t CXL_CSRP_An = {0x008}; | |
129 | static const cxl_p2n_reg_t CXL_AURP0_An = {0x010}; | |
130 | static const cxl_p2n_reg_t CXL_AURP1_An = {0x018}; | |
131 | static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020}; | |
132 | static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028}; | |
133 | static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030}; | |
134 | /* Segment Lookaside Buffer Management */ | |
135 | static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040}; | |
136 | static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048}; | |
137 | static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050}; | |
138 | /* Interrupt Registers */ | |
139 | static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060}; | |
140 | static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068}; | |
141 | static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070}; | |
142 | static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078}; | |
143 | static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080}; | |
144 | static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088}; | |
145 | /* AFU Registers */ | |
146 | static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090}; | |
147 | static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098}; | |
148 | /* Work Element Descriptor */ | |
149 | static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0}; | |
150 | /* 0x0C0:FFF Implementation Dependent Area */ | |
151 | ||
152 | #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL | |
153 | #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL | |
154 | #define CXL_PSL_SPAP_Size_Shift 4 | |
155 | #define CXL_PSL_SPAP_V 0x0000000000000001ULL | |
156 | ||
390fd592 PB |
157 | /****** CXL_PSL_Control ****************************************************/ |
158 | #define CXL_PSL_Control_tb 0x0000000000000001ULL | |
159 | ||
f204e0b8 IM |
160 | /****** CXL_PSL_DLCNTL *****************************************************/ |
161 | #define CXL_PSL_DLCNTL_D (0x1ull << (63-28)) | |
162 | #define CXL_PSL_DLCNTL_C (0x1ull << (63-29)) | |
163 | #define CXL_PSL_DLCNTL_E (0x1ull << (63-30)) | |
164 | #define CXL_PSL_DLCNTL_S (0x1ull << (63-31)) | |
165 | #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E) | |
166 | #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S) | |
167 | ||
168 | /****** CXL_PSL_SR_An ******************************************************/ | |
169 | #define CXL_PSL_SR_An_SF MSR_SF /* 64bit */ | |
170 | #define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */ | |
171 | #define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */ | |
172 | #define CXL_PSL_SR_An_PR MSR_PR /* Problem state, GA1: 1 */ | |
173 | #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */ | |
174 | #define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */ | |
175 | #define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */ | |
176 | #define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */ | |
177 | #define CXL_PSL_SR_An_R MSR_DR /* Relocate, GA1: 1 */ | |
178 | #define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */ | |
179 | #define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */ | |
180 | ||
181 | /****** CXL_PSL_LLCMD_An ****************************************************/ | |
182 | #define CXL_LLCMD_TERMINATE 0x0001000000000000ULL | |
183 | #define CXL_LLCMD_REMOVE 0x0002000000000000ULL | |
184 | #define CXL_LLCMD_SUSPEND 0x0003000000000000ULL | |
185 | #define CXL_LLCMD_RESUME 0x0004000000000000ULL | |
186 | #define CXL_LLCMD_ADD 0x0005000000000000ULL | |
187 | #define CXL_LLCMD_UPDATE 0x0006000000000000ULL | |
188 | #define CXL_LLCMD_HANDLE_MASK 0x000000000000ffffULL | |
189 | ||
190 | /****** CXL_PSL_ID_An ****************************************************/ | |
191 | #define CXL_PSL_ID_An_F (1ull << (63-31)) | |
192 | #define CXL_PSL_ID_An_L (1ull << (63-30)) | |
193 | ||
194 | /****** CXL_PSL_SCNTL_An ****************************************************/ | |
195 | #define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15)) | |
196 | /* Programming Modes: */ | |
197 | #define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31)) | |
198 | #define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31)) | |
199 | #define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31)) | |
200 | #define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31)) | |
201 | #define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31)) | |
202 | #define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31)) | |
203 | /* Purge Status (ro) */ | |
204 | #define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39)) | |
205 | #define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39)) | |
206 | #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39)) | |
207 | /* Purge */ | |
208 | #define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48)) | |
209 | /* Suspend Status (ro) */ | |
210 | #define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55)) | |
211 | #define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55)) | |
212 | #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55)) | |
213 | /* Suspend Control */ | |
214 | #define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63)) | |
215 | ||
216 | /* AFU Slice Enable Status (ro) */ | |
217 | #define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2)) | |
218 | #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2)) | |
219 | #define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2)) | |
220 | /* AFU Slice Enable */ | |
221 | #define CXL_AFU_Cntl_An_E (0x1ull << (63-3)) | |
222 | /* AFU Slice Reset status (ro) */ | |
223 | #define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5)) | |
224 | #define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5)) | |
225 | #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5)) | |
226 | /* AFU Slice Reset */ | |
227 | #define CXL_AFU_Cntl_An_RA (0x1ull << (63-7)) | |
228 | ||
229 | /****** CXL_SSTP0/1_An ******************************************************/ | |
230 | /* These top bits are for the segment that CONTAINS the segment table */ | |
231 | #define CXL_SSTP0_An_B_SHIFT SLB_VSID_SSIZE_SHIFT | |
232 | #define CXL_SSTP0_An_KS (1ull << (63-2)) | |
233 | #define CXL_SSTP0_An_KP (1ull << (63-3)) | |
234 | #define CXL_SSTP0_An_N (1ull << (63-4)) | |
235 | #define CXL_SSTP0_An_L (1ull << (63-5)) | |
236 | #define CXL_SSTP0_An_C (1ull << (63-6)) | |
237 | #define CXL_SSTP0_An_TA (1ull << (63-7)) | |
238 | #define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */ | |
239 | /* And finally, the virtual address & size of the segment table: */ | |
240 | #define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */ | |
241 | #define CXL_SSTP0_An_SegTableSize_MASK \ | |
242 | (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT) | |
243 | #define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1) | |
244 | #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1)) | |
245 | #define CXL_SSTP1_An_V (1ull << (63-63)) | |
246 | ||
247 | /****** CXL_PSL_SLBIE_[An] **************************************************/ | |
248 | /* write: */ | |
249 | #define CXL_SLBIE_C PPC_BIT(36) /* Class */ | |
250 | #define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */ | |
251 | #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38) | |
252 | #define CXL_SLBIE_TA PPC_BIT(38) /* Tags Active */ | |
253 | /* read: */ | |
254 | #define CXL_SLBIE_MAX PPC_BITMASK(24, 31) | |
255 | #define CXL_SLBIE_PENDING PPC_BITMASK(56, 63) | |
256 | ||
257 | /****** Common to all CXL_TLBIA/SLBIA_[An] **********************************/ | |
258 | #define CXL_TLB_SLB_P (1ull) /* Pending (read) */ | |
259 | ||
260 | /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers **********************/ | |
261 | #define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */ | |
262 | #define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */ | |
263 | #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */ | |
264 | ||
265 | /****** CXL_PSL_AFUSEL ******************************************************/ | |
266 | #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */ | |
267 | ||
268 | /****** CXL_PSL_DSISR_An ****************************************************/ | |
269 | #define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */ | |
270 | #define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */ | |
271 | #define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */ | |
272 | #define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */ | |
273 | #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR) | |
274 | #define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */ | |
275 | #define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */ | |
276 | #define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */ | |
277 | /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */ | |
278 | #define CXL_PSL_DSISR_An_M DSISR_NOHPTE /* PTE not found */ | |
279 | #define CXL_PSL_DSISR_An_P DSISR_PROTFAULT /* Storage protection violation */ | |
280 | #define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */ | |
281 | #define CXL_PSL_DSISR_An_S DSISR_ISSTORE /* Access was afu_wr or afu_zero */ | |
282 | #define CXL_PSL_DSISR_An_K DSISR_KEYFAULT /* Access not permitted by virtual page class key protection */ | |
283 | ||
284 | /****** CXL_PSL_TFC_An ******************************************************/ | |
285 | #define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */ | |
286 | #define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */ | |
287 | #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */ | |
288 | #define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */ | |
289 | ||
290 | /* cxl_process_element->software_status */ | |
291 | #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */ | |
292 | #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */ | |
293 | #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */ | |
294 | #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */ | |
295 | ||
d6a6af2c IM |
296 | /****** CXL_PSL_RXCTL_An (Implementation Specific) ************************** |
297 | * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to | |
298 | * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x | |
299 | * of the hang pulse frequency. | |
300 | */ | |
301 | #define CXL_PSL_RXCTL_AFUHP_4S 0x7000000000000000ULL | |
302 | ||
f204e0b8 IM |
303 | /* SPA->sw_command_status */ |
304 | #define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL | |
305 | #define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL | |
306 | #define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL | |
307 | #define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL | |
308 | #define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL | |
309 | #define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL | |
310 | #define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL | |
311 | #define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL | |
312 | #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL | |
313 | #define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL | |
314 | #define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL | |
315 | #define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL | |
316 | #define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL | |
317 | #define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL | |
318 | #define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL | |
319 | #define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL | |
320 | ||
321 | #define CXL_MAX_SLICES 4 | |
322 | #define MAX_AFU_MMIO_REGS 3 | |
323 | ||
f204e0b8 IM |
324 | #define CXL_MODE_TIME_SLICED 0x4 |
325 | #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED) | |
326 | ||
594ff7d0 CL |
327 | #define CXL_DEV_MINORS 13 /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */ |
328 | #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS) | |
329 | #define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS) | |
330 | ||
f204e0b8 IM |
331 | enum cxl_context_status { |
332 | CLOSED, | |
333 | OPENED, | |
334 | STARTED | |
335 | }; | |
336 | ||
337 | enum prefault_modes { | |
338 | CXL_PREFAULT_NONE, | |
339 | CXL_PREFAULT_WED, | |
340 | CXL_PREFAULT_ALL, | |
341 | }; | |
342 | ||
4752876c CL |
343 | enum cxl_attrs { |
344 | CXL_ADAPTER_ATTRS, | |
345 | CXL_AFU_MASTER_ATTRS, | |
346 | CXL_AFU_ATTRS, | |
347 | }; | |
348 | ||
f204e0b8 IM |
349 | struct cxl_sste { |
350 | __be64 esid_data; | |
351 | __be64 vsid_data; | |
352 | }; | |
353 | ||
354 | #define to_cxl_adapter(d) container_of(d, struct cxl, dev) | |
355 | #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev) | |
356 | ||
cbffa3a5 CL |
357 | struct cxl_afu_native { |
358 | void __iomem *p1n_mmio; | |
359 | void __iomem *afu_desc_mmio; | |
f204e0b8 | 360 | irq_hw_number_t psl_hwirq; |
cbffa3a5 CL |
361 | unsigned int psl_virq; |
362 | struct mutex spa_mutex; | |
363 | /* | |
364 | * Only the first part of the SPA is used for the process element | |
365 | * linked list. The only other part that software needs to worry about | |
366 | * is sw_command_status, which we store a separate pointer to. | |
367 | * Everything else in the SPA is only used by hardware | |
368 | */ | |
369 | struct cxl_process_element *spa; | |
370 | __be64 *sw_command_status; | |
371 | unsigned int spa_size; | |
372 | int spa_order; | |
373 | int spa_max_procs; | |
374 | u64 pp_offset; | |
375 | }; | |
376 | ||
377 | struct cxl_afu_guest { | |
378 | u64 handle; | |
379 | phys_addr_t p2n_phys; | |
380 | u64 p2n_size; | |
381 | int max_ints; | |
0d400f77 CL |
382 | struct mutex recovery_lock; |
383 | int previous_state; | |
cbffa3a5 CL |
384 | }; |
385 | ||
386 | struct cxl_afu { | |
387 | struct cxl_afu_native *native; | |
388 | struct cxl_afu_guest *guest; | |
f204e0b8 IM |
389 | irq_hw_number_t serr_hwirq; |
390 | unsigned int serr_virq; | |
cbffa3a5 CL |
391 | char *psl_irq_name; |
392 | char *err_irq_name; | |
f204e0b8 IM |
393 | void __iomem *p2n_mmio; |
394 | phys_addr_t psn_phys; | |
f204e0b8 | 395 | u64 pp_size; |
cbffa3a5 | 396 | |
f204e0b8 IM |
397 | struct cxl *adapter; |
398 | struct device dev; | |
399 | struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d; | |
400 | struct device *chardev_s, *chardev_m, *chardev_d; | |
401 | struct idr contexts_idr; | |
402 | struct dentry *debugfs; | |
ee41d11d | 403 | struct mutex contexts_lock; |
f204e0b8 IM |
404 | spinlock_t afu_cntl_lock; |
405 | ||
e36f6fe1 VJ |
406 | /* AFU error buffer fields and bin attribute for sysfs */ |
407 | u64 eb_len, eb_offset; | |
408 | struct bin_attribute attr_eb; | |
409 | ||
6f7f0b3d MN |
410 | /* pointer to the vphb */ |
411 | struct pci_controller *phb; | |
412 | ||
f204e0b8 IM |
413 | int pp_irqs; |
414 | int irqs_max; | |
415 | int num_procs; | |
416 | int max_procs_virtualised; | |
417 | int slice; | |
418 | int modes_supported; | |
419 | int current_mode; | |
b087e619 IM |
420 | int crs_num; |
421 | u64 crs_len; | |
422 | u64 crs_offset; | |
423 | struct list_head crs; | |
f204e0b8 IM |
424 | enum prefault_modes prefault_mode; |
425 | bool psa; | |
426 | bool pp_psa; | |
427 | bool enabled; | |
428 | }; | |
429 | ||
1b5df59e VJ |
430 | /* AFU refcount management */ |
431 | static inline struct cxl_afu *cxl_afu_get(struct cxl_afu *afu) | |
432 | { | |
433 | ||
434 | return (get_device(&afu->dev) == NULL) ? NULL : afu; | |
435 | } | |
436 | ||
437 | static inline void cxl_afu_put(struct cxl_afu *afu) | |
438 | { | |
439 | put_device(&afu->dev); | |
440 | } | |
441 | ||
80fa93fc MN |
442 | |
443 | struct cxl_irq_name { | |
444 | struct list_head list; | |
445 | char *name; | |
446 | }; | |
447 | ||
14baf4d9 CL |
448 | struct irq_avail { |
449 | irq_hw_number_t offset; | |
450 | irq_hw_number_t range; | |
451 | unsigned long *bitmap; | |
452 | }; | |
453 | ||
f204e0b8 IM |
454 | /* |
455 | * This is a cxl context. If the PSL is in dedicated mode, there will be one | |
456 | * of these per AFU. If in AFU directed there can be lots of these. | |
457 | */ | |
458 | struct cxl_context { | |
459 | struct cxl_afu *afu; | |
460 | ||
461 | /* Problem state MMIO */ | |
462 | phys_addr_t psn_phys; | |
463 | u64 psn_size; | |
464 | ||
b123429e IM |
465 | /* Used to unmap any mmaps when force detaching */ |
466 | struct address_space *mapping; | |
467 | struct mutex mapping_lock; | |
d9232a3d IM |
468 | struct page *ff_page; |
469 | bool mmio_err_ff; | |
55e07668 | 470 | bool kernelapi; |
b123429e | 471 | |
f204e0b8 IM |
472 | spinlock_t sste_lock; /* Protects segment table entries */ |
473 | struct cxl_sste *sstp; | |
474 | u64 sstp0, sstp1; | |
475 | unsigned int sst_size, sst_lru; | |
476 | ||
477 | wait_queue_head_t wq; | |
7b8ad495 VJ |
478 | /* pid of the group leader associated with the pid */ |
479 | struct pid *glpid; | |
480 | /* use mm context associated with this pid for ds faults */ | |
f204e0b8 IM |
481 | struct pid *pid; |
482 | spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */ | |
483 | /* Only used in PR mode */ | |
484 | u64 process_token; | |
485 | ||
486 | unsigned long *irq_bitmap; /* Accessed from IRQ context */ | |
487 | struct cxl_irq_ranges irqs; | |
80fa93fc | 488 | struct list_head irq_names; |
f204e0b8 IM |
489 | u64 fault_addr; |
490 | u64 fault_dsisr; | |
491 | u64 afu_err; | |
492 | ||
493 | /* | |
494 | * This status and it's lock pretects start and detach context | |
495 | * from racing. It also prevents detach from racing with | |
496 | * itself | |
497 | */ | |
498 | enum cxl_context_status status; | |
499 | struct mutex status_mutex; | |
500 | ||
501 | ||
502 | /* XXX: Is it possible to need multiple work items at once? */ | |
503 | struct work_struct fault_work; | |
504 | u64 dsisr; | |
505 | u64 dar; | |
506 | ||
507 | struct cxl_process_element *elem; | |
508 | ||
14baf4d9 CL |
509 | /* |
510 | * pe is the process element handle, assigned by this driver when the | |
511 | * context is initialized. | |
512 | * | |
513 | * external_pe is the PE shown outside of cxl. | |
514 | * On bare-metal, pe=external_pe, because we decide what the handle is. | |
515 | * In a guest, we only find out about the pe used by pHyp when the | |
516 | * context is attached, and that's the value we want to report outside | |
517 | * of cxl. | |
518 | */ | |
519 | int pe; | |
520 | int external_pe; | |
521 | ||
f204e0b8 IM |
522 | u32 irq_count; |
523 | bool pe_inserted; | |
524 | bool master; | |
525 | bool kernel; | |
526 | bool pending_irq; | |
527 | bool pending_fault; | |
528 | bool pending_afu_err; | |
8ac75b96 IM |
529 | |
530 | struct rcu_head rcu; | |
f204e0b8 IM |
531 | }; |
532 | ||
cbffa3a5 CL |
533 | struct cxl_native { |
534 | u64 afu_desc_off; | |
535 | u64 afu_desc_size; | |
f204e0b8 IM |
536 | void __iomem *p1_mmio; |
537 | void __iomem *p2_mmio; | |
538 | irq_hw_number_t err_hwirq; | |
539 | unsigned int err_virq; | |
cbffa3a5 CL |
540 | u64 ps_off; |
541 | }; | |
542 | ||
543 | struct cxl_guest { | |
544 | struct platform_device *pdev; | |
545 | int irq_nranges; | |
546 | struct cdev cdev; | |
547 | irq_hw_number_t irq_base_offset; | |
548 | struct irq_avail *irq_avail; | |
549 | spinlock_t irq_alloc_lock; | |
550 | u64 handle; | |
551 | char *status; | |
552 | u16 vendor; | |
553 | u16 device; | |
554 | u16 subsystem_vendor; | |
555 | u16 subsystem; | |
556 | }; | |
557 | ||
558 | struct cxl { | |
559 | struct cxl_native *native; | |
560 | struct cxl_guest *guest; | |
f204e0b8 IM |
561 | spinlock_t afu_list_lock; |
562 | struct cxl_afu *afu[CXL_MAX_SLICES]; | |
563 | struct device dev; | |
564 | struct dentry *trace; | |
565 | struct dentry *psl_err_chk; | |
566 | struct dentry *debugfs; | |
80fa93fc | 567 | char *irq_name; |
f204e0b8 IM |
568 | struct bin_attribute cxl_attr; |
569 | int adapter_num; | |
570 | int user_irqs; | |
f204e0b8 IM |
571 | u64 ps_size; |
572 | u16 psl_rev; | |
573 | u16 base_image; | |
574 | u8 vsec_status; | |
575 | u8 caia_major; | |
576 | u8 caia_minor; | |
577 | u8 slices; | |
578 | bool user_image_loaded; | |
579 | bool perst_loads_image; | |
580 | bool perst_select_user; | |
13e68d8b | 581 | bool perst_same_image; |
f204e0b8 IM |
582 | }; |
583 | ||
2b04cf31 FB |
584 | int cxl_pci_alloc_one_irq(struct cxl *adapter); |
585 | void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq); | |
586 | int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num); | |
587 | void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter); | |
588 | int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq); | |
4beb5421 | 589 | int cxl_update_image_control(struct cxl *adapter); |
2b04cf31 FB |
590 | int cxl_pci_reset(struct cxl *adapter); |
591 | void cxl_pci_release_afu(struct device *dev); | |
d601ea91 | 592 | ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len); |
f204e0b8 IM |
593 | |
594 | /* common == phyp + powernv */ | |
595 | struct cxl_process_element_common { | |
596 | __be32 tid; | |
597 | __be32 pid; | |
598 | __be64 csrp; | |
599 | __be64 aurp0; | |
600 | __be64 aurp1; | |
601 | __be64 sstp0; | |
602 | __be64 sstp1; | |
603 | __be64 amr; | |
604 | u8 reserved3[4]; | |
605 | __be64 wed; | |
606 | } __packed; | |
607 | ||
608 | /* just powernv */ | |
609 | struct cxl_process_element { | |
610 | __be64 sr; | |
611 | __be64 SPOffset; | |
612 | __be64 sdr; | |
613 | __be64 haurp; | |
614 | __be32 ctxtime; | |
615 | __be16 ivte_offsets[4]; | |
616 | __be16 ivte_ranges[4]; | |
617 | __be32 lpid; | |
618 | struct cxl_process_element_common common; | |
619 | __be32 software_state; | |
620 | } __packed; | |
621 | ||
0d400f77 | 622 | static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu) |
0b3f9c75 DA |
623 | { |
624 | struct pci_dev *pdev; | |
625 | ||
ea2d1f95 FB |
626 | if (cpu_has_feature(CPU_FTR_HVMODE)) { |
627 | pdev = to_pci_dev(cxl->dev.parent); | |
628 | return !pci_channel_offline(pdev); | |
629 | } | |
630 | return true; | |
0b3f9c75 DA |
631 | } |
632 | ||
f204e0b8 IM |
633 | static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg) |
634 | { | |
635 | WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE)); | |
cbffa3a5 | 636 | return cxl->native->p1_mmio + cxl_reg_off(reg); |
f204e0b8 IM |
637 | } |
638 | ||
588b34be DA |
639 | static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val) |
640 | { | |
0d400f77 | 641 | if (likely(cxl_adapter_link_ok(cxl, NULL))) |
0b3f9c75 | 642 | out_be64(_cxl_p1_addr(cxl, reg), val); |
588b34be DA |
643 | } |
644 | ||
645 | static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg) | |
646 | { | |
0d400f77 | 647 | if (likely(cxl_adapter_link_ok(cxl, NULL))) |
0b3f9c75 DA |
648 | return in_be64(_cxl_p1_addr(cxl, reg)); |
649 | else | |
650 | return ~0ULL; | |
588b34be | 651 | } |
f204e0b8 IM |
652 | |
653 | static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg) | |
654 | { | |
655 | WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE)); | |
cbffa3a5 | 656 | return afu->native->p1n_mmio + cxl_reg_off(reg); |
f204e0b8 IM |
657 | } |
658 | ||
588b34be DA |
659 | static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val) |
660 | { | |
0d400f77 | 661 | if (likely(cxl_adapter_link_ok(afu->adapter, afu))) |
0b3f9c75 | 662 | out_be64(_cxl_p1n_addr(afu, reg), val); |
588b34be DA |
663 | } |
664 | ||
665 | static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg) | |
666 | { | |
0d400f77 | 667 | if (likely(cxl_adapter_link_ok(afu->adapter, afu))) |
0b3f9c75 DA |
668 | return in_be64(_cxl_p1n_addr(afu, reg)); |
669 | else | |
670 | return ~0ULL; | |
588b34be | 671 | } |
f204e0b8 IM |
672 | |
673 | static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg) | |
674 | { | |
675 | return afu->p2n_mmio + cxl_reg_off(reg); | |
676 | } | |
677 | ||
588b34be DA |
678 | static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val) |
679 | { | |
0d400f77 | 680 | if (likely(cxl_adapter_link_ok(afu->adapter, afu))) |
0b3f9c75 | 681 | out_be64(_cxl_p2n_addr(afu, reg), val); |
588b34be | 682 | } |
f204e0b8 | 683 | |
588b34be DA |
684 | static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg) |
685 | { | |
0d400f77 | 686 | if (likely(cxl_adapter_link_ok(afu->adapter, afu))) |
0b3f9c75 DA |
687 | return in_be64(_cxl_p2n_addr(afu, reg)); |
688 | else | |
689 | return ~0ULL; | |
588b34be | 690 | } |
b087e619 | 691 | |
2b04cf31 | 692 | ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf, |
e36f6fe1 VJ |
693 | loff_t off, size_t count); |
694 | ||
b087e619 | 695 | |
f204e0b8 IM |
696 | struct cxl_calls { |
697 | void (*cxl_slbia)(struct mm_struct *mm); | |
698 | struct module *owner; | |
699 | }; | |
700 | int register_cxl_calls(struct cxl_calls *calls); | |
701 | void unregister_cxl_calls(struct cxl_calls *calls); | |
594ff7d0 | 702 | int cxl_update_properties(struct device_node *dn, struct property *new_prop); |
f204e0b8 | 703 | |
f204e0b8 IM |
704 | void cxl_remove_adapter_nr(struct cxl *adapter); |
705 | ||
05155772 DA |
706 | int cxl_alloc_spa(struct cxl_afu *afu); |
707 | void cxl_release_spa(struct cxl_afu *afu); | |
708 | ||
594ff7d0 | 709 | dev_t cxl_get_dev(void); |
f204e0b8 IM |
710 | int cxl_file_init(void); |
711 | void cxl_file_exit(void); | |
712 | int cxl_register_adapter(struct cxl *adapter); | |
713 | int cxl_register_afu(struct cxl_afu *afu); | |
714 | int cxl_chardev_d_afu_add(struct cxl_afu *afu); | |
715 | int cxl_chardev_m_afu_add(struct cxl_afu *afu); | |
716 | int cxl_chardev_s_afu_add(struct cxl_afu *afu); | |
717 | void cxl_chardev_afu_remove(struct cxl_afu *afu); | |
718 | ||
719 | void cxl_context_detach_all(struct cxl_afu *afu); | |
720 | void cxl_context_free(struct cxl_context *ctx); | |
721 | void cxl_context_detach(struct cxl_context *ctx); | |
722 | ||
723 | int cxl_sysfs_adapter_add(struct cxl *adapter); | |
724 | void cxl_sysfs_adapter_remove(struct cxl *adapter); | |
725 | int cxl_sysfs_afu_add(struct cxl_afu *afu); | |
726 | void cxl_sysfs_afu_remove(struct cxl_afu *afu); | |
727 | int cxl_sysfs_afu_m_add(struct cxl_afu *afu); | |
728 | void cxl_sysfs_afu_m_remove(struct cxl_afu *afu); | |
729 | ||
86331862 CL |
730 | struct cxl *cxl_alloc_adapter(void); |
731 | struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice); | |
f204e0b8 IM |
732 | int cxl_afu_select_best_mode(struct cxl_afu *afu); |
733 | ||
2b04cf31 FB |
734 | int cxl_native_register_psl_irq(struct cxl_afu *afu); |
735 | void cxl_native_release_psl_irq(struct cxl_afu *afu); | |
736 | int cxl_native_register_psl_err_irq(struct cxl *adapter); | |
737 | void cxl_native_release_psl_err_irq(struct cxl *adapter); | |
738 | int cxl_native_register_serr_irq(struct cxl_afu *afu); | |
739 | void cxl_native_release_serr_irq(struct cxl_afu *afu); | |
f204e0b8 | 740 | int afu_register_irqs(struct cxl_context *ctx, u32 count); |
6428832a | 741 | void afu_release_irqs(struct cxl_context *ctx, void *cookie); |
8dde152e | 742 | void afu_irq_name_free(struct cxl_context *ctx); |
f204e0b8 IM |
743 | |
744 | int cxl_debugfs_init(void); | |
745 | void cxl_debugfs_exit(void); | |
746 | int cxl_debugfs_adapter_add(struct cxl *adapter); | |
747 | void cxl_debugfs_adapter_remove(struct cxl *adapter); | |
748 | int cxl_debugfs_afu_add(struct cxl_afu *afu); | |
749 | void cxl_debugfs_afu_remove(struct cxl_afu *afu); | |
750 | ||
751 | void cxl_handle_fault(struct work_struct *work); | |
752 | void cxl_prefault(struct cxl_context *ctx, u64 wed); | |
753 | ||
754 | struct cxl *get_cxl_adapter(int num); | |
755 | int cxl_alloc_sst(struct cxl_context *ctx); | |
444c4ba4 | 756 | void cxl_dump_debug_buffer(void *addr, size_t size); |
f204e0b8 IM |
757 | |
758 | void init_cxl_native(void); | |
759 | ||
760 | struct cxl_context *cxl_context_alloc(void); | |
b123429e IM |
761 | int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master, |
762 | struct address_space *mapping); | |
f204e0b8 IM |
763 | void cxl_context_free(struct cxl_context *ctx); |
764 | int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma); | |
1a1a94b8 MN |
765 | unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq, |
766 | irq_handler_t handler, void *cookie, const char *name); | |
767 | void cxl_unmap_irq(unsigned int virq, void *cookie); | |
eda3693c | 768 | int __detach_context(struct cxl_context *ctx); |
f204e0b8 | 769 | |
444c4ba4 CL |
770 | /* |
771 | * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined | |
772 | * in PAPR. | |
773 | * A word about endianness: a pointer to this structure is passed when | |
774 | * calling the hcall. However, it is not a block of memory filled up by | |
775 | * the hypervisor. The return values are found in registers, and copied | |
776 | * one by one when returning from the hcall. See the end of the call to | |
777 | * plpar_hcall9() in hvCall.S | |
778 | * As a consequence: | |
779 | * - we don't need to do any endianness conversion | |
780 | * - the pid and tid are an exception. They are 32-bit values returned in | |
781 | * the same 64-bit register. So we do need to worry about byte ordering. | |
782 | */ | |
f204e0b8 IM |
783 | struct cxl_irq_info { |
784 | u64 dsisr; | |
785 | u64 dar; | |
786 | u64 dsr; | |
444c4ba4 | 787 | #ifndef CONFIG_CPU_LITTLE_ENDIAN |
f204e0b8 IM |
788 | u32 pid; |
789 | u32 tid; | |
444c4ba4 CL |
790 | #else |
791 | u32 tid; | |
792 | u32 pid; | |
793 | #endif | |
f204e0b8 IM |
794 | u64 afu_err; |
795 | u64 errstat; | |
444c4ba4 CL |
796 | u64 proc_handle; |
797 | u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */ | |
f204e0b8 IM |
798 | }; |
799 | ||
1a1a94b8 | 800 | void cxl_assign_psn_space(struct cxl_context *ctx); |
6d625ed9 | 801 | irqreturn_t cxl_irq(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info); |
86331862 CL |
802 | int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler, |
803 | void *cookie, irq_hw_number_t *dest_hwirq, | |
804 | unsigned int *dest_virq, const char *name); | |
805 | ||
f204e0b8 IM |
806 | int cxl_check_error(struct cxl_afu *afu); |
807 | int cxl_afu_slbia(struct cxl_afu *afu); | |
808 | int cxl_tlb_slb_invalidate(struct cxl *adapter); | |
809 | int cxl_afu_disable(struct cxl_afu *afu); | |
f204e0b8 IM |
810 | int cxl_psl_purge(struct cxl_afu *afu); |
811 | ||
812 | void cxl_stop_trace(struct cxl *cxl); | |
6f7f0b3d MN |
813 | int cxl_pci_vphb_add(struct cxl_afu *afu); |
814 | void cxl_pci_vphb_remove(struct cxl_afu *afu); | |
f204e0b8 IM |
815 | |
816 | extern struct pci_driver cxl_pci_driver; | |
14baf4d9 | 817 | extern struct platform_driver cxl_of_driver; |
c358d84b | 818 | int afu_allocate_irqs(struct cxl_context *ctx, u32 count); |
f204e0b8 | 819 | |
0520336a MN |
820 | int afu_open(struct inode *inode, struct file *file); |
821 | int afu_release(struct inode *inode, struct file *file); | |
822 | long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg); | |
823 | int afu_mmap(struct file *file, struct vm_area_struct *vm); | |
824 | unsigned int afu_poll(struct file *file, struct poll_table_struct *poll); | |
825 | ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off); | |
826 | extern const struct file_operations afu_fops; | |
827 | ||
14baf4d9 CL |
828 | struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev); |
829 | void cxl_guest_remove_adapter(struct cxl *adapter); | |
830 | int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np); | |
831 | int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np); | |
832 | ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len); | |
833 | ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len); | |
834 | int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np); | |
835 | void cxl_guest_remove_afu(struct cxl_afu *afu); | |
836 | int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np); | |
837 | int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np); | |
838 | int cxl_guest_add_chardev(struct cxl *adapter); | |
839 | void cxl_guest_remove_chardev(struct cxl *adapter); | |
840 | void cxl_guest_reload_module(struct cxl *adapter); | |
841 | int cxl_of_probe(struct platform_device *pdev); | |
842 | ||
5be587b1 FB |
843 | struct cxl_backend_ops { |
844 | struct module *module; | |
845 | int (*adapter_reset)(struct cxl *adapter); | |
846 | int (*alloc_one_irq)(struct cxl *adapter); | |
847 | void (*release_one_irq)(struct cxl *adapter, int hwirq); | |
848 | int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs, | |
849 | struct cxl *adapter, unsigned int num); | |
850 | void (*release_irq_ranges)(struct cxl_irq_ranges *irqs, | |
851 | struct cxl *adapter); | |
852 | int (*setup_irq)(struct cxl *adapter, unsigned int hwirq, | |
853 | unsigned int virq); | |
854 | irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx, | |
855 | u64 dsisr, u64 errstat); | |
856 | irqreturn_t (*psl_interrupt)(int irq, void *data); | |
857 | int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask); | |
858 | int (*attach_process)(struct cxl_context *ctx, bool kernel, | |
859 | u64 wed, u64 amr); | |
860 | int (*detach_process)(struct cxl_context *ctx); | |
4752876c | 861 | bool (*support_attributes)(const char *attr_name, enum cxl_attrs type); |
0d400f77 | 862 | bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu); |
5be587b1 FB |
863 | void (*release_afu)(struct device *dev); |
864 | ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf, | |
865 | loff_t off, size_t count); | |
866 | int (*afu_check_and_enable)(struct cxl_afu *afu); | |
867 | int (*afu_activate_mode)(struct cxl_afu *afu, int mode); | |
868 | int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode); | |
869 | int (*afu_reset)(struct cxl_afu *afu); | |
870 | int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val); | |
871 | int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val); | |
872 | int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val); | |
873 | int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val); | |
d601ea91 FB |
874 | int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val); |
875 | int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val); | |
876 | int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val); | |
877 | ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count); | |
5be587b1 FB |
878 | }; |
879 | extern const struct cxl_backend_ops cxl_native_ops; | |
14baf4d9 | 880 | extern const struct cxl_backend_ops cxl_guest_ops; |
5be587b1 FB |
881 | extern const struct cxl_backend_ops *cxl_ops; |
882 | ||
17eb3eef VJ |
883 | /* check if the given pci_dev is on the the cxl vphb bus */ |
884 | bool cxl_pci_is_vphb_device(struct pci_dev *dev); | |
f204e0b8 | 885 | #endif |