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mfd: Add WM8350 interrupt support
[linux-2.6-block.git] / drivers / mfd / wm8350-core.c
CommitLineData
89b4012b
MB		 1/*
2 * wm8350-core.c -- Device access for Wolfson WM8350
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood, Mark Brown
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/init.h>
ebccec0f 18#include <linux/bug.h>
89b4012b
MB		 19#include <linux/device.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
ebccec0f 22#include <linux/workqueue.h>
89b4012b
MB		 23
24#include <linux/mfd/wm8350/core.h>
25#include <linux/mfd/wm8350/audio.h>
ebccec0f 26#include <linux/mfd/wm8350/comparator.h>
89b4012b
MB		 27#include <linux/mfd/wm8350/gpio.h>
28#include <linux/mfd/wm8350/pmic.h>
ebccec0f 29#include <linux/mfd/wm8350/rtc.h>
89b4012b 30#include <linux/mfd/wm8350/supply.h>
ebccec0f 31#include <linux/mfd/wm8350/wdt.h>
89b4012b
MB		 32
33#define WM8350_UNLOCK_KEY 0x0013
34#define WM8350_LOCK_KEY 0x0000
35
36#define WM8350_CLOCK_CONTROL_1 0x28
37#define WM8350_AIF_TEST 0x74
38
39/* debug */
40#define WM8350_BUS_DEBUG 0
41#if WM8350_BUS_DEBUG
42#define dump(regs, src) do { \
43 int i_; \
44 u16 *src_ = src; \
45 printk(KERN_DEBUG); \
46 for (i_ = 0; i_ < regs; i_++) \
47 printk(" 0x%4.4x", *src_++); \
48 printk("\n"); \
49} while (0);
50#else
51#define dump(bytes, src)
52#endif
53
54#define WM8350_LOCK_DEBUG 0
55#if WM8350_LOCK_DEBUG
56#define ldbg(format, arg...) printk(format, ## arg)
57#else
58#define ldbg(format, arg...)
59#endif
60
61/*
62 * WM8350 Device IO
63 */
64static DEFINE_MUTEX(io_mutex);
65static DEFINE_MUTEX(reg_lock_mutex);
66static DEFINE_MUTEX(auxadc_mutex);
67
68/* Perform a physical read from the device.
69 */
70static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
71 u16 *dest)
72{
73 int i, ret;
74 int bytes = num_regs * 2;
75
76 dev_dbg(wm8350->dev, "volatile read\n");
77 ret = wm8350->read_dev(wm8350, reg, bytes, (char *)dest);
78
79 for (i = reg; i < reg + num_regs; i++) {
80 /* Cache is CPU endian */
81 dest[i - reg] = be16_to_cpu(dest[i - reg]);
82
83 /* Satisfy non-volatile bits from cache */
84 dest[i - reg] &= wm8350_reg_io_map[i].vol;
85 dest[i - reg] |= wm8350->reg_cache[i];
86
87 /* Mask out non-readable bits */
88 dest[i - reg] &= wm8350_reg_io_map[i].readable;
89 }
90
91 dump(num_regs, dest);
92
93 return ret;
94}
95
96static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
97{
98 int i;
99 int end = reg + num_regs;
100 int ret = 0;
101 int bytes = num_regs * 2;
102
103 if (wm8350->read_dev == NULL)
104 return -ENODEV;
105
106 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
107 dev_err(wm8350->dev, "invalid reg %x\n",
108 reg + num_regs - 1);
109 return -EINVAL;
110 }
111
112 dev_dbg(wm8350->dev,
113 "%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
114
115#if WM8350_BUS_DEBUG
116 /* we can _safely_ read any register, but warn if read not supported */
117 for (i = reg; i < end; i++) {
118 if (!wm8350_reg_io_map[i].readable)
119 dev_warn(wm8350->dev,
120 "reg R%d is not readable\n", i);
121 }
122#endif
123
124 /* if any volatile registers are required, then read back all */
125 for (i = reg; i < end; i++)
126 if (wm8350_reg_io_map[i].vol)
127 return wm8350_phys_read(wm8350, reg, num_regs, dest);
128
129 /* no volatiles, then cache is good */
130 dev_dbg(wm8350->dev, "cache read\n");
131 memcpy(dest, &wm8350->reg_cache[reg], bytes);
132 dump(num_regs, dest);
133 return ret;
134}
135
136static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
137{
138 if (reg == WM8350_SECURITY ||
139 wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
140 return 0;
141
142 if ((reg == WM8350_GPIO_CONFIGURATION_I_O) ||
143 (reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
144 reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
145 (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
146 reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
147 return 1;
148 return 0;
149}
150
151static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
152{
153 int i;
154 int end = reg + num_regs;
155 int bytes = num_regs * 2;
156
157 if (wm8350->write_dev == NULL)
158 return -ENODEV;
159
160 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
161 dev_err(wm8350->dev, "invalid reg %x\n",
162 reg + num_regs - 1);
163 return -EINVAL;
164 }
165
166 /* it's generally not a good idea to write to RO or locked registers */
167 for (i = reg; i < end; i++) {
168 if (!wm8350_reg_io_map[i].writable) {
169 dev_err(wm8350->dev,
170 "attempted write to read only reg R%d\n", i);
171 return -EINVAL;
172 }
173
174 if (is_reg_locked(wm8350, i)) {
175 dev_err(wm8350->dev,
176 "attempted write to locked reg R%d\n", i);
177 return -EINVAL;
178 }
179
180 src[i - reg] &= wm8350_reg_io_map[i].writable;
181
182 wm8350->reg_cache[i] =
183 (wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
184 | src[i - reg];
185
186 src[i - reg] = cpu_to_be16(src[i - reg]);
187 }
188
189 /* Actually write it out */
190 return wm8350->write_dev(wm8350, reg, bytes, (char *)src);
191}
192
193/*
194 * Safe read, modify, write methods
195 */
196int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
197{
198 u16 data;
199 int err;
200
201 mutex_lock(&io_mutex);
202 err = wm8350_read(wm8350, reg, 1, &data);
203 if (err) {
204 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
205 goto out;
206 }
207
208 data &= ~mask;
209 err = wm8350_write(wm8350, reg, 1, &data);
210 if (err)
211 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
212out:
213 mutex_unlock(&io_mutex);
214 return err;
215}
216EXPORT_SYMBOL_GPL(wm8350_clear_bits);
217
218int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
219{
220 u16 data;
221 int err;
222
223 mutex_lock(&io_mutex);
224 err = wm8350_read(wm8350, reg, 1, &data);
225 if (err) {
226 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
227 goto out;
228 }
229
230 data |= mask;
231 err = wm8350_write(wm8350, reg, 1, &data);
232 if (err)
233 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
234out:
235 mutex_unlock(&io_mutex);
236 return err;
237}
238EXPORT_SYMBOL_GPL(wm8350_set_bits);
239
240u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
241{
242 u16 data;
243 int err;
244
245 mutex_lock(&io_mutex);
246 err = wm8350_read(wm8350, reg, 1, &data);
247 if (err)
248 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
249
250 mutex_unlock(&io_mutex);
251 return data;
252}
253EXPORT_SYMBOL_GPL(wm8350_reg_read);
254
255int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
256{
257 int ret;
258 u16 data = val;
259
260 mutex_lock(&io_mutex);
261 ret = wm8350_write(wm8350, reg, 1, &data);
262 if (ret)
263 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
264 mutex_unlock(&io_mutex);
265 return ret;
266}
267EXPORT_SYMBOL_GPL(wm8350_reg_write);
268
269int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
270 u16 *dest)
271{
272 int err = 0;
273
274 mutex_lock(&io_mutex);
275 err = wm8350_read(wm8350, start_reg, regs, dest);
276 if (err)
277 dev_err(wm8350->dev, "block read starting from R%d failed\n",
278 start_reg);
279 mutex_unlock(&io_mutex);
280 return err;
281}
282EXPORT_SYMBOL_GPL(wm8350_block_read);
283
284int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
285 u16 *src)
286{
287 int ret = 0;
288
289 mutex_lock(&io_mutex);
290 ret = wm8350_write(wm8350, start_reg, regs, src);
291 if (ret)
292 dev_err(wm8350->dev, "block write starting at R%d failed\n",
293 start_reg);
294 mutex_unlock(&io_mutex);
295 return ret;
296}
297EXPORT_SYMBOL_GPL(wm8350_block_write);
298
299int wm8350_reg_lock(struct wm8350 *wm8350)
300{
301 u16 key = WM8350_LOCK_KEY;
302 int ret;
303
304 ldbg(__func__);
305 mutex_lock(&io_mutex);
306 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
307 if (ret)
308 dev_err(wm8350->dev, "lock failed\n");
309 mutex_unlock(&io_mutex);
310 return ret;
311}
312EXPORT_SYMBOL_GPL(wm8350_reg_lock);
313
314int wm8350_reg_unlock(struct wm8350 *wm8350)
315{
316 u16 key = WM8350_UNLOCK_KEY;
317 int ret;
318
319 ldbg(__func__);
320 mutex_lock(&io_mutex);
321 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
322 if (ret)
323 dev_err(wm8350->dev, "unlock failed\n");
324 mutex_unlock(&io_mutex);
325 return ret;
326}
327EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
328
ebccec0f
MB		 329static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq)
330{
331 mutex_lock(&wm8350->irq_mutex);
332
333 if (wm8350->irq[irq].handler)
334 wm8350->irq[irq].handler(wm8350, irq, wm8350->irq[irq].data);
335 else {
336 dev_err(wm8350->dev, "irq %d nobody cared. now masked.\n",
337 irq);
338 wm8350_mask_irq(wm8350, irq);
339 }
340
341 mutex_unlock(&wm8350->irq_mutex);
342}
343
344/*
345 * wm8350_irq_worker actually handles the interrupts. Since all
346 * interrupts are clear on read the IRQ line will be reasserted and
347 * the physical IRQ will be handled again if another interrupt is
348 * asserted while we run - in the normal course of events this is a
349 * rare occurrence so we save I2C/SPI reads.
350 */
351static void wm8350_irq_worker(struct work_struct *work)
352{
353 struct wm8350 *wm8350 = container_of(work, struct wm8350, irq_work);
354 u16 level_one, status1, status2, comp;
355
356 /* TODO: Use block reads to improve performance? */
357 level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS)
358 & ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK);
359 status1 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_1)
360 & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_1_MASK);
361 status2 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_2)
362 & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_2_MASK);
363 comp = wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS)
364 & ~wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK);
365
366 /* over current */
367 if (level_one & WM8350_OC_INT) {
368 u16 oc;
369
370 oc = wm8350_reg_read(wm8350, WM8350_OVER_CURRENT_INT_STATUS);
371 oc &= ~wm8350_reg_read(wm8350,
372 WM8350_OVER_CURRENT_INT_STATUS_MASK);
373
374 if (oc & WM8350_OC_LS_EINT) /* limit switch */
375 wm8350_irq_call_handler(wm8350, WM8350_IRQ_OC_LS);
376 }
377
378 /* under voltage */
379 if (level_one & WM8350_UV_INT) {
380 u16 uv;
381
382 uv = wm8350_reg_read(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS);
383 uv &= ~wm8350_reg_read(wm8350,
384 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK);
385
386 if (uv & WM8350_UV_DC1_EINT)
387 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC1);
388 if (uv & WM8350_UV_DC2_EINT)
389 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC2);
390 if (uv & WM8350_UV_DC3_EINT)
391 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC3);
392 if (uv & WM8350_UV_DC4_EINT)
393 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC4);
394 if (uv & WM8350_UV_DC5_EINT)
395 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC5);
396 if (uv & WM8350_UV_DC6_EINT)
397 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC6);
398 if (uv & WM8350_UV_LDO1_EINT)
399 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO1);
400 if (uv & WM8350_UV_LDO2_EINT)
401 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO2);
402 if (uv & WM8350_UV_LDO3_EINT)
403 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO3);
404 if (uv & WM8350_UV_LDO4_EINT)
405 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO4);
406 }
407
408 /* charger, RTC */
409 if (status1) {
410 if (status1 & WM8350_CHG_BAT_HOT_EINT)
411 wm8350_irq_call_handler(wm8350,
412 WM8350_IRQ_CHG_BAT_HOT);
413 if (status1 & WM8350_CHG_BAT_COLD_EINT)
414 wm8350_irq_call_handler(wm8350,
415 WM8350_IRQ_CHG_BAT_COLD);
416 if (status1 & WM8350_CHG_BAT_FAIL_EINT)
417 wm8350_irq_call_handler(wm8350,
418 WM8350_IRQ_CHG_BAT_FAIL);
419 if (status1 & WM8350_CHG_TO_EINT)
420 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_TO);
421 if (status1 & WM8350_CHG_END_EINT)
422 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_END);
423 if (status1 & WM8350_CHG_START_EINT)
424 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_START);
425 if (status1 & WM8350_CHG_FAST_RDY_EINT)
426 wm8350_irq_call_handler(wm8350,
427 WM8350_IRQ_CHG_FAST_RDY);
428 if (status1 & WM8350_CHG_VBATT_LT_3P9_EINT)
429 wm8350_irq_call_handler(wm8350,
430 WM8350_IRQ_CHG_VBATT_LT_3P9);
431 if (status1 & WM8350_CHG_VBATT_LT_3P1_EINT)
432 wm8350_irq_call_handler(wm8350,
433 WM8350_IRQ_CHG_VBATT_LT_3P1);
434 if (status1 & WM8350_CHG_VBATT_LT_2P85_EINT)
435 wm8350_irq_call_handler(wm8350,
436 WM8350_IRQ_CHG_VBATT_LT_2P85);
437 if (status1 & WM8350_RTC_ALM_EINT)
438 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_ALM);
439 if (status1 & WM8350_RTC_SEC_EINT)
440 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_SEC);
441 if (status1 & WM8350_RTC_PER_EINT)
442 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_PER);
443 }
444
445 /* current sink, system, aux adc */
446 if (status2) {
447 if (status2 & WM8350_CS1_EINT)
448 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS1);
449 if (status2 & WM8350_CS2_EINT)
450 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS2);
451
452 if (status2 & WM8350_SYS_HYST_COMP_FAIL_EINT)
453 wm8350_irq_call_handler(wm8350,
454 WM8350_IRQ_SYS_HYST_COMP_FAIL);
455 if (status2 & WM8350_SYS_CHIP_GT115_EINT)
456 wm8350_irq_call_handler(wm8350,
457 WM8350_IRQ_SYS_CHIP_GT115);
458 if (status2 & WM8350_SYS_CHIP_GT140_EINT)
459 wm8350_irq_call_handler(wm8350,
460 WM8350_IRQ_SYS_CHIP_GT140);
461 if (status2 & WM8350_SYS_WDOG_TO_EINT)
462 wm8350_irq_call_handler(wm8350,
463 WM8350_IRQ_SYS_WDOG_TO);
464
465 if (status2 & WM8350_AUXADC_DATARDY_EINT)
466 wm8350_irq_call_handler(wm8350,
467 WM8350_IRQ_AUXADC_DATARDY);
468 if (status2 & WM8350_AUXADC_DCOMP4_EINT)
469 wm8350_irq_call_handler(wm8350,
470 WM8350_IRQ_AUXADC_DCOMP4);
471 if (status2 & WM8350_AUXADC_DCOMP3_EINT)
472 wm8350_irq_call_handler(wm8350,
473 WM8350_IRQ_AUXADC_DCOMP3);
474 if (status2 & WM8350_AUXADC_DCOMP2_EINT)
475 wm8350_irq_call_handler(wm8350,
476 WM8350_IRQ_AUXADC_DCOMP2);
477 if (status2 & WM8350_AUXADC_DCOMP1_EINT)
478 wm8350_irq_call_handler(wm8350,
479 WM8350_IRQ_AUXADC_DCOMP1);
480
481 if (status2 & WM8350_USB_LIMIT_EINT)
482 wm8350_irq_call_handler(wm8350, WM8350_IRQ_USB_LIMIT);
483 }
484
485 /* wake, codec, ext */
486 if (comp) {
487 if (comp & WM8350_WKUP_OFF_STATE_EINT)
488 wm8350_irq_call_handler(wm8350,
489 WM8350_IRQ_WKUP_OFF_STATE);
490 if (comp & WM8350_WKUP_HIB_STATE_EINT)
491 wm8350_irq_call_handler(wm8350,
492 WM8350_IRQ_WKUP_HIB_STATE);
493 if (comp & WM8350_WKUP_CONV_FAULT_EINT)
494 wm8350_irq_call_handler(wm8350,
495 WM8350_IRQ_WKUP_CONV_FAULT);
496 if (comp & WM8350_WKUP_WDOG_RST_EINT)
497 wm8350_irq_call_handler(wm8350,
498 WM8350_IRQ_WKUP_WDOG_RST);
499 if (comp & WM8350_WKUP_GP_PWR_ON_EINT)
500 wm8350_irq_call_handler(wm8350,
501 WM8350_IRQ_WKUP_GP_PWR_ON);
502 if (comp & WM8350_WKUP_ONKEY_EINT)
503 wm8350_irq_call_handler(wm8350, WM8350_IRQ_WKUP_ONKEY);
504 if (comp & WM8350_WKUP_GP_WAKEUP_EINT)
505 wm8350_irq_call_handler(wm8350,
506 WM8350_IRQ_WKUP_GP_WAKEUP);
507
508 if (comp & WM8350_CODEC_JCK_DET_L_EINT)
509 wm8350_irq_call_handler(wm8350,
510 WM8350_IRQ_CODEC_JCK_DET_L);
511 if (comp & WM8350_CODEC_JCK_DET_R_EINT)
512 wm8350_irq_call_handler(wm8350,
513 WM8350_IRQ_CODEC_JCK_DET_R);
514 if (comp & WM8350_CODEC_MICSCD_EINT)
515 wm8350_irq_call_handler(wm8350,
516 WM8350_IRQ_CODEC_MICSCD);
517 if (comp & WM8350_CODEC_MICD_EINT)
518 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CODEC_MICD);
519
520 if (comp & WM8350_EXT_USB_FB_EINT)
521 wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_USB_FB);
522 if (comp & WM8350_EXT_WALL_FB_EINT)
523 wm8350_irq_call_handler(wm8350,
524 WM8350_IRQ_EXT_WALL_FB);
525 if (comp & WM8350_EXT_BAT_FB_EINT)
526 wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_BAT_FB);
527 }
528
529 if (level_one & WM8350_GP_INT) {
530 int i;
531 u16 gpio;
532
533 gpio = wm8350_reg_read(wm8350, WM8350_GPIO_INT_STATUS);
534 gpio &= ~wm8350_reg_read(wm8350,
535 WM8350_GPIO_INT_STATUS_MASK);
536
537 for (i = 0; i < 12; i++) {
538 if (gpio & (1 << i))
539 wm8350_irq_call_handler(wm8350,
540 WM8350_IRQ_GPIO(i));
541 }
542 }
543
544 enable_irq(wm8350->chip_irq);
545}
546
547static irqreturn_t wm8350_irq(int irq, void *data)
548{
549 struct wm8350 *wm8350 = data;
550
551 disable_irq_nosync(irq);
552 schedule_work(&wm8350->irq_work);
553
554 return IRQ_HANDLED;
555}
556
557int wm8350_register_irq(struct wm8350 *wm8350, int irq,
558 void (*handler) (struct wm8350 *, int, void *),
559 void *data)
560{
561 if (irq < 0 || irq > WM8350_NUM_IRQ || !handler)
562 return -EINVAL;
563
564 if (wm8350->irq[irq].handler)
565 return -EBUSY;
566
567 mutex_lock(&wm8350->irq_mutex);
568 wm8350->irq[irq].handler = handler;
569 wm8350->irq[irq].data = data;
570 mutex_unlock(&wm8350->irq_mutex);
571
572 return 0;
573}
574EXPORT_SYMBOL_GPL(wm8350_register_irq);
575
576int wm8350_free_irq(struct wm8350 *wm8350, int irq)
577{
578 if (irq < 0 || irq > WM8350_NUM_IRQ)
579 return -EINVAL;
580
581 mutex_lock(&wm8350->irq_mutex);
582 wm8350->irq[irq].handler = NULL;
583 mutex_unlock(&wm8350->irq_mutex);
584 return 0;
585}
586EXPORT_SYMBOL_GPL(wm8350_free_irq);
587
588int wm8350_mask_irq(struct wm8350 *wm8350, int irq)
589{
590 switch (irq) {
591 case WM8350_IRQ_CHG_BAT_HOT:
592 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
593 WM8350_IM_CHG_BAT_HOT_EINT);
594 case WM8350_IRQ_CHG_BAT_COLD:
595 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
596 WM8350_IM_CHG_BAT_COLD_EINT);
597 case WM8350_IRQ_CHG_BAT_FAIL:
598 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
599 WM8350_IM_CHG_BAT_FAIL_EINT);
600 case WM8350_IRQ_CHG_TO:
601 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
602 WM8350_IM_CHG_TO_EINT);
603 case WM8350_IRQ_CHG_END:
604 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
605 WM8350_IM_CHG_END_EINT);
606 case WM8350_IRQ_CHG_START:
607 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
608 WM8350_IM_CHG_START_EINT);
609 case WM8350_IRQ_CHG_FAST_RDY:
610 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
611 WM8350_IM_CHG_FAST_RDY_EINT);
612 case WM8350_IRQ_RTC_PER:
613 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
614 WM8350_IM_RTC_PER_EINT);
615 case WM8350_IRQ_RTC_SEC:
616 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
617 WM8350_IM_RTC_SEC_EINT);
618 case WM8350_IRQ_RTC_ALM:
619 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
620 WM8350_IM_RTC_ALM_EINT);
621 case WM8350_IRQ_CHG_VBATT_LT_3P9:
622 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
623 WM8350_IM_CHG_VBATT_LT_3P9_EINT);
624 case WM8350_IRQ_CHG_VBATT_LT_3P1:
625 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
626 WM8350_IM_CHG_VBATT_LT_3P1_EINT);
627 case WM8350_IRQ_CHG_VBATT_LT_2P85:
628 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
629 WM8350_IM_CHG_VBATT_LT_2P85_EINT);
630 case WM8350_IRQ_CS1:
631 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
632 WM8350_IM_CS1_EINT);
633 case WM8350_IRQ_CS2:
634 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
635 WM8350_IM_CS2_EINT);
636 case WM8350_IRQ_USB_LIMIT:
637 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
638 WM8350_IM_USB_LIMIT_EINT);
639 case WM8350_IRQ_AUXADC_DATARDY:
640 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
641 WM8350_IM_AUXADC_DATARDY_EINT);
642 case WM8350_IRQ_AUXADC_DCOMP4:
643 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
644 WM8350_IM_AUXADC_DCOMP4_EINT);
645 case WM8350_IRQ_AUXADC_DCOMP3:
646 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
647 WM8350_IM_AUXADC_DCOMP3_EINT);
648 case WM8350_IRQ_AUXADC_DCOMP2:
649 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
650 WM8350_IM_AUXADC_DCOMP2_EINT);
651 case WM8350_IRQ_AUXADC_DCOMP1:
652 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
653 WM8350_IM_AUXADC_DCOMP1_EINT);
654 case WM8350_IRQ_SYS_HYST_COMP_FAIL:
655 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
656 WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
657 case WM8350_IRQ_SYS_CHIP_GT115:
658 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
659 WM8350_IM_SYS_CHIP_GT115_EINT);
660 case WM8350_IRQ_SYS_CHIP_GT140:
661 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
662 WM8350_IM_SYS_CHIP_GT140_EINT);
663 case WM8350_IRQ_SYS_WDOG_TO:
664 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
665 WM8350_IM_SYS_WDOG_TO_EINT);
666 case WM8350_IRQ_UV_LDO4:
667 return wm8350_set_bits(wm8350,
668 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
669 WM8350_IM_UV_LDO4_EINT);
670 case WM8350_IRQ_UV_LDO3:
671 return wm8350_set_bits(wm8350,
672 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
673 WM8350_IM_UV_LDO3_EINT);
674 case WM8350_IRQ_UV_LDO2:
675 return wm8350_set_bits(wm8350,
676 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
677 WM8350_IM_UV_LDO2_EINT);
678 case WM8350_IRQ_UV_LDO1:
679 return wm8350_set_bits(wm8350,
680 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
681 WM8350_IM_UV_LDO1_EINT);
682 case WM8350_IRQ_UV_DC6:
683 return wm8350_set_bits(wm8350,
684 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
685 WM8350_IM_UV_DC6_EINT);
686 case WM8350_IRQ_UV_DC5:
687 return wm8350_set_bits(wm8350,
688 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
689 WM8350_IM_UV_DC5_EINT);
690 case WM8350_IRQ_UV_DC4:
691 return wm8350_set_bits(wm8350,
692 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
693 WM8350_IM_UV_DC4_EINT);
694 case WM8350_IRQ_UV_DC3:
695 return wm8350_set_bits(wm8350,
696 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
697 WM8350_IM_UV_DC3_EINT);
698 case WM8350_IRQ_UV_DC2:
699 return wm8350_set_bits(wm8350,
700 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
701 WM8350_IM_UV_DC2_EINT);
702 case WM8350_IRQ_UV_DC1:
703 return wm8350_set_bits(wm8350,
704 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
705 WM8350_IM_UV_DC1_EINT);
706 case WM8350_IRQ_OC_LS:
707 return wm8350_set_bits(wm8350,
708 WM8350_OVER_CURRENT_INT_STATUS_MASK,
709 WM8350_IM_OC_LS_EINT);
710 case WM8350_IRQ_EXT_USB_FB:
711 return wm8350_set_bits(wm8350,
712 WM8350_COMPARATOR_INT_STATUS_MASK,
713 WM8350_IM_EXT_USB_FB_EINT);
714 case WM8350_IRQ_EXT_WALL_FB:
715 return wm8350_set_bits(wm8350,
716 WM8350_COMPARATOR_INT_STATUS_MASK,
717 WM8350_IM_EXT_WALL_FB_EINT);
718 case WM8350_IRQ_EXT_BAT_FB:
719 return wm8350_set_bits(wm8350,
720 WM8350_COMPARATOR_INT_STATUS_MASK,
721 WM8350_IM_EXT_BAT_FB_EINT);
722 case WM8350_IRQ_CODEC_JCK_DET_L:
723 return wm8350_set_bits(wm8350,
724 WM8350_COMPARATOR_INT_STATUS_MASK,
725 WM8350_IM_CODEC_JCK_DET_L_EINT);
726 case WM8350_IRQ_CODEC_JCK_DET_R:
727 return wm8350_set_bits(wm8350,
728 WM8350_COMPARATOR_INT_STATUS_MASK,
729 WM8350_IM_CODEC_JCK_DET_R_EINT);
730 case WM8350_IRQ_CODEC_MICSCD:
731 return wm8350_set_bits(wm8350,
732 WM8350_COMPARATOR_INT_STATUS_MASK,
733 WM8350_IM_CODEC_MICSCD_EINT);
734 case WM8350_IRQ_CODEC_MICD:
735 return wm8350_set_bits(wm8350,
736 WM8350_COMPARATOR_INT_STATUS_MASK,
737 WM8350_IM_CODEC_MICD_EINT);
738 case WM8350_IRQ_WKUP_OFF_STATE:
739 return wm8350_set_bits(wm8350,
740 WM8350_COMPARATOR_INT_STATUS_MASK,
741 WM8350_IM_WKUP_OFF_STATE_EINT);
742 case WM8350_IRQ_WKUP_HIB_STATE:
743 return wm8350_set_bits(wm8350,
744 WM8350_COMPARATOR_INT_STATUS_MASK,
745 WM8350_IM_WKUP_HIB_STATE_EINT);
746 case WM8350_IRQ_WKUP_CONV_FAULT:
747 return wm8350_set_bits(wm8350,
748 WM8350_COMPARATOR_INT_STATUS_MASK,
749 WM8350_IM_WKUP_CONV_FAULT_EINT);
750 case WM8350_IRQ_WKUP_WDOG_RST:
751 return wm8350_set_bits(wm8350,
752 WM8350_COMPARATOR_INT_STATUS_MASK,
753 WM8350_IM_WKUP_OFF_STATE_EINT);
754 case WM8350_IRQ_WKUP_GP_PWR_ON:
755 return wm8350_set_bits(wm8350,
756 WM8350_COMPARATOR_INT_STATUS_MASK,
757 WM8350_IM_WKUP_GP_PWR_ON_EINT);
758 case WM8350_IRQ_WKUP_ONKEY:
759 return wm8350_set_bits(wm8350,
760 WM8350_COMPARATOR_INT_STATUS_MASK,
761 WM8350_IM_WKUP_ONKEY_EINT);
762 case WM8350_IRQ_WKUP_GP_WAKEUP:
763 return wm8350_set_bits(wm8350,
764 WM8350_COMPARATOR_INT_STATUS_MASK,
765 WM8350_IM_WKUP_GP_WAKEUP_EINT);
766 case WM8350_IRQ_GPIO(0):
767 return wm8350_set_bits(wm8350,
768 WM8350_GPIO_INT_STATUS_MASK,
769 WM8350_IM_GP0_EINT);
770 case WM8350_IRQ_GPIO(1):
771 return wm8350_set_bits(wm8350,
772 WM8350_GPIO_INT_STATUS_MASK,
773 WM8350_IM_GP1_EINT);
774 case WM8350_IRQ_GPIO(2):
775 return wm8350_set_bits(wm8350,
776 WM8350_GPIO_INT_STATUS_MASK,
777 WM8350_IM_GP2_EINT);
778 case WM8350_IRQ_GPIO(3):
779 return wm8350_set_bits(wm8350,
780 WM8350_GPIO_INT_STATUS_MASK,
781 WM8350_IM_GP3_EINT);
782 case WM8350_IRQ_GPIO(4):
783 return wm8350_set_bits(wm8350,
784 WM8350_GPIO_INT_STATUS_MASK,
785 WM8350_IM_GP4_EINT);
786 case WM8350_IRQ_GPIO(5):
787 return wm8350_set_bits(wm8350,
788 WM8350_GPIO_INT_STATUS_MASK,
789 WM8350_IM_GP5_EINT);
790 case WM8350_IRQ_GPIO(6):
791 return wm8350_set_bits(wm8350,
792 WM8350_GPIO_INT_STATUS_MASK,
793 WM8350_IM_GP6_EINT);
794 case WM8350_IRQ_GPIO(7):
795 return wm8350_set_bits(wm8350,
796 WM8350_GPIO_INT_STATUS_MASK,
797 WM8350_IM_GP7_EINT);
798 case WM8350_IRQ_GPIO(8):
799 return wm8350_set_bits(wm8350,
800 WM8350_GPIO_INT_STATUS_MASK,
801 WM8350_IM_GP8_EINT);
802 case WM8350_IRQ_GPIO(9):
803 return wm8350_set_bits(wm8350,
804 WM8350_GPIO_INT_STATUS_MASK,
805 WM8350_IM_GP9_EINT);
806 case WM8350_IRQ_GPIO(10):
807 return wm8350_set_bits(wm8350,
808 WM8350_GPIO_INT_STATUS_MASK,
809 WM8350_IM_GP10_EINT);
810 case WM8350_IRQ_GPIO(11):
811 return wm8350_set_bits(wm8350,
812 WM8350_GPIO_INT_STATUS_MASK,
813 WM8350_IM_GP11_EINT);
814 case WM8350_IRQ_GPIO(12):
815 return wm8350_set_bits(wm8350,
816 WM8350_GPIO_INT_STATUS_MASK,
817 WM8350_IM_GP12_EINT);
818 default:
819 dev_warn(wm8350->dev, "Attempting to mask unknown IRQ %d\n",
820 irq);
821 return -EINVAL;
822 }
823 return 0;
824}
825EXPORT_SYMBOL_GPL(wm8350_mask_irq);
826
827int wm8350_unmask_irq(struct wm8350 *wm8350, int irq)
828{
829 switch (irq) {
830 case WM8350_IRQ_CHG_BAT_HOT:
831 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
832 WM8350_IM_CHG_BAT_HOT_EINT);
833 case WM8350_IRQ_CHG_BAT_COLD:
834 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
835 WM8350_IM_CHG_BAT_COLD_EINT);
836 case WM8350_IRQ_CHG_BAT_FAIL:
837 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
838 WM8350_IM_CHG_BAT_FAIL_EINT);
839 case WM8350_IRQ_CHG_TO:
840 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
841 WM8350_IM_CHG_TO_EINT);
842 case WM8350_IRQ_CHG_END:
843 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
844 WM8350_IM_CHG_END_EINT);
845 case WM8350_IRQ_CHG_START:
846 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
847 WM8350_IM_CHG_START_EINT);
848 case WM8350_IRQ_CHG_FAST_RDY:
849 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
850 WM8350_IM_CHG_FAST_RDY_EINT);
851 case WM8350_IRQ_RTC_PER:
852 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
853 WM8350_IM_RTC_PER_EINT);
854 case WM8350_IRQ_RTC_SEC:
855 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
856 WM8350_IM_RTC_SEC_EINT);
857 case WM8350_IRQ_RTC_ALM:
858 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
859 WM8350_IM_RTC_ALM_EINT);
860 case WM8350_IRQ_CHG_VBATT_LT_3P9:
861 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
862 WM8350_IM_CHG_VBATT_LT_3P9_EINT);
863 case WM8350_IRQ_CHG_VBATT_LT_3P1:
864 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
865 WM8350_IM_CHG_VBATT_LT_3P1_EINT);
866 case WM8350_IRQ_CHG_VBATT_LT_2P85:
867 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
868 WM8350_IM_CHG_VBATT_LT_2P85_EINT);
869 case WM8350_IRQ_CS1:
870 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
871 WM8350_IM_CS1_EINT);
872 case WM8350_IRQ_CS2:
873 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
874 WM8350_IM_CS2_EINT);
875 case WM8350_IRQ_USB_LIMIT:
876 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
877 WM8350_IM_USB_LIMIT_EINT);
878 case WM8350_IRQ_AUXADC_DATARDY:
879 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
880 WM8350_IM_AUXADC_DATARDY_EINT);
881 case WM8350_IRQ_AUXADC_DCOMP4:
882 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
883 WM8350_IM_AUXADC_DCOMP4_EINT);
884 case WM8350_IRQ_AUXADC_DCOMP3:
885 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
886 WM8350_IM_AUXADC_DCOMP3_EINT);
887 case WM8350_IRQ_AUXADC_DCOMP2:
888 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
889 WM8350_IM_AUXADC_DCOMP2_EINT);
890 case WM8350_IRQ_AUXADC_DCOMP1:
891 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
892 WM8350_IM_AUXADC_DCOMP1_EINT);
893 case WM8350_IRQ_SYS_HYST_COMP_FAIL:
894 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
895 WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
896 case WM8350_IRQ_SYS_CHIP_GT115:
897 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
898 WM8350_IM_SYS_CHIP_GT115_EINT);
899 case WM8350_IRQ_SYS_CHIP_GT140:
900 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
901 WM8350_IM_SYS_CHIP_GT140_EINT);
902 case WM8350_IRQ_SYS_WDOG_TO:
903 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
904 WM8350_IM_SYS_WDOG_TO_EINT);
905 case WM8350_IRQ_UV_LDO4:
906 return wm8350_clear_bits(wm8350,
907 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
908 WM8350_IM_UV_LDO4_EINT);
909 case WM8350_IRQ_UV_LDO3:
910 return wm8350_clear_bits(wm8350,
911 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
912 WM8350_IM_UV_LDO3_EINT);
913 case WM8350_IRQ_UV_LDO2:
914 return wm8350_clear_bits(wm8350,
915 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
916 WM8350_IM_UV_LDO2_EINT);
917 case WM8350_IRQ_UV_LDO1:
918 return wm8350_clear_bits(wm8350,
919 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
920 WM8350_IM_UV_LDO1_EINT);
921 case WM8350_IRQ_UV_DC6:
922 return wm8350_clear_bits(wm8350,
923 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
924 WM8350_IM_UV_DC6_EINT);
925 case WM8350_IRQ_UV_DC5:
926 return wm8350_clear_bits(wm8350,
927 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
928 WM8350_IM_UV_DC5_EINT);
929 case WM8350_IRQ_UV_DC4:
930 return wm8350_clear_bits(wm8350,
931 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
932 WM8350_IM_UV_DC4_EINT);
933 case WM8350_IRQ_UV_DC3:
934 return wm8350_clear_bits(wm8350,
935 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
936 WM8350_IM_UV_DC3_EINT);
937 case WM8350_IRQ_UV_DC2:
938 return wm8350_clear_bits(wm8350,
939 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
940 WM8350_IM_UV_DC2_EINT);
941 case WM8350_IRQ_UV_DC1:
942 return wm8350_clear_bits(wm8350,
943 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
944 WM8350_IM_UV_DC1_EINT);
945 case WM8350_IRQ_OC_LS:
946 return wm8350_clear_bits(wm8350,
947 WM8350_OVER_CURRENT_INT_STATUS_MASK,
948 WM8350_IM_OC_LS_EINT);
949 case WM8350_IRQ_EXT_USB_FB:
950 return wm8350_clear_bits(wm8350,
951 WM8350_COMPARATOR_INT_STATUS_MASK,
952 WM8350_IM_EXT_USB_FB_EINT);
953 case WM8350_IRQ_EXT_WALL_FB:
954 return wm8350_clear_bits(wm8350,
955 WM8350_COMPARATOR_INT_STATUS_MASK,
956 WM8350_IM_EXT_WALL_FB_EINT);
957 case WM8350_IRQ_EXT_BAT_FB:
958 return wm8350_clear_bits(wm8350,
959 WM8350_COMPARATOR_INT_STATUS_MASK,
960 WM8350_IM_EXT_BAT_FB_EINT);
961 case WM8350_IRQ_CODEC_JCK_DET_L:
962 return wm8350_clear_bits(wm8350,
963 WM8350_COMPARATOR_INT_STATUS_MASK,
964 WM8350_IM_CODEC_JCK_DET_L_EINT);
965 case WM8350_IRQ_CODEC_JCK_DET_R:
966 return wm8350_clear_bits(wm8350,
967 WM8350_COMPARATOR_INT_STATUS_MASK,
968 WM8350_IM_CODEC_JCK_DET_R_EINT);
969 case WM8350_IRQ_CODEC_MICSCD:
970 return wm8350_clear_bits(wm8350,
971 WM8350_COMPARATOR_INT_STATUS_MASK,
972 WM8350_IM_CODEC_MICSCD_EINT);
973 case WM8350_IRQ_CODEC_MICD:
974 return wm8350_clear_bits(wm8350,
975 WM8350_COMPARATOR_INT_STATUS_MASK,
976 WM8350_IM_CODEC_MICD_EINT);
977 case WM8350_IRQ_WKUP_OFF_STATE:
978 return wm8350_clear_bits(wm8350,
979 WM8350_COMPARATOR_INT_STATUS_MASK,
980 WM8350_IM_WKUP_OFF_STATE_EINT);
981 case WM8350_IRQ_WKUP_HIB_STATE:
982 return wm8350_clear_bits(wm8350,
983 WM8350_COMPARATOR_INT_STATUS_MASK,
984 WM8350_IM_WKUP_HIB_STATE_EINT);
985 case WM8350_IRQ_WKUP_CONV_FAULT:
986 return wm8350_clear_bits(wm8350,
987 WM8350_COMPARATOR_INT_STATUS_MASK,
988 WM8350_IM_WKUP_CONV_FAULT_EINT);
989 case WM8350_IRQ_WKUP_WDOG_RST:
990 return wm8350_clear_bits(wm8350,
991 WM8350_COMPARATOR_INT_STATUS_MASK,
992 WM8350_IM_WKUP_OFF_STATE_EINT);
993 case WM8350_IRQ_WKUP_GP_PWR_ON:
994 return wm8350_clear_bits(wm8350,
995 WM8350_COMPARATOR_INT_STATUS_MASK,
996 WM8350_IM_WKUP_GP_PWR_ON_EINT);
997 case WM8350_IRQ_WKUP_ONKEY:
998 return wm8350_clear_bits(wm8350,
999 WM8350_COMPARATOR_INT_STATUS_MASK,
1000 WM8350_IM_WKUP_ONKEY_EINT);
1001 case WM8350_IRQ_WKUP_GP_WAKEUP:
1002 return wm8350_clear_bits(wm8350,
1003 WM8350_COMPARATOR_INT_STATUS_MASK,
1004 WM8350_IM_WKUP_GP_WAKEUP_EINT);
1005 case WM8350_IRQ_GPIO(0):
1006 return wm8350_clear_bits(wm8350,
1007 WM8350_GPIO_INT_STATUS_MASK,
1008 WM8350_IM_GP0_EINT);
1009 case WM8350_IRQ_GPIO(1):
1010 return wm8350_clear_bits(wm8350,
1011 WM8350_GPIO_INT_STATUS_MASK,
1012 WM8350_IM_GP1_EINT);
1013 case WM8350_IRQ_GPIO(2):
1014 return wm8350_clear_bits(wm8350,
1015 WM8350_GPIO_INT_STATUS_MASK,
1016 WM8350_IM_GP2_EINT);
1017 case WM8350_IRQ_GPIO(3):
1018 return wm8350_clear_bits(wm8350,
1019 WM8350_GPIO_INT_STATUS_MASK,
1020 WM8350_IM_GP3_EINT);
1021 case WM8350_IRQ_GPIO(4):
1022 return wm8350_clear_bits(wm8350,
1023 WM8350_GPIO_INT_STATUS_MASK,
1024 WM8350_IM_GP4_EINT);
1025 case WM8350_IRQ_GPIO(5):
1026 return wm8350_clear_bits(wm8350,
1027 WM8350_GPIO_INT_STATUS_MASK,
1028 WM8350_IM_GP5_EINT);
1029 case WM8350_IRQ_GPIO(6):
1030 return wm8350_clear_bits(wm8350,
1031 WM8350_GPIO_INT_STATUS_MASK,
1032 WM8350_IM_GP6_EINT);
1033 case WM8350_IRQ_GPIO(7):
1034 return wm8350_clear_bits(wm8350,
1035 WM8350_GPIO_INT_STATUS_MASK,
1036 WM8350_IM_GP7_EINT);
1037 case WM8350_IRQ_GPIO(8):
1038 return wm8350_clear_bits(wm8350,
1039 WM8350_GPIO_INT_STATUS_MASK,
1040 WM8350_IM_GP8_EINT);
1041 case WM8350_IRQ_GPIO(9):
1042 return wm8350_clear_bits(wm8350,
1043 WM8350_GPIO_INT_STATUS_MASK,
1044 WM8350_IM_GP9_EINT);
1045 case WM8350_IRQ_GPIO(10):
1046 return wm8350_clear_bits(wm8350,
1047 WM8350_GPIO_INT_STATUS_MASK,
1048 WM8350_IM_GP10_EINT);
1049 case WM8350_IRQ_GPIO(11):
1050 return wm8350_clear_bits(wm8350,
1051 WM8350_GPIO_INT_STATUS_MASK,
1052 WM8350_IM_GP11_EINT);
1053 case WM8350_IRQ_GPIO(12):
1054 return wm8350_clear_bits(wm8350,
1055 WM8350_GPIO_INT_STATUS_MASK,
1056 WM8350_IM_GP12_EINT);
1057 default:
1058 dev_warn(wm8350->dev, "Attempting to unmask unknown IRQ %d\n",
1059 irq);
1060 return -EINVAL;
1061 }
1062 return 0;
1063}
1064EXPORT_SYMBOL_GPL(wm8350_unmask_irq);
1065
89b4012b
MB		 1066/*
1067 * Cache is always host endian.
1068 */
1069static int wm8350_create_cache(struct wm8350 *wm8350, int mode)
1070{
1071 int i, ret = 0;
1072 u16 value;
1073 const u16 *reg_map;
1074
1075 switch (mode) {
1076#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
1077 case 0:
1078 reg_map = wm8350_mode0_defaults;
1079 break;
1080#endif
1081#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
1082 case 1:
1083 reg_map = wm8350_mode1_defaults;
1084 break;
1085#endif
1086#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
1087 case 2:
1088 reg_map = wm8350_mode2_defaults;
1089 break;
1090#endif
1091#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
1092 case 3:
1093 reg_map = wm8350_mode3_defaults;
1094 break;
1095#endif
1096 default:
1097 dev_err(wm8350->dev, "Configuration mode %d not supported\n",
1098 mode);
1099 return -EINVAL;
1100 }
1101
1102 wm8350->reg_cache =
1103 kzalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
1104 if (wm8350->reg_cache == NULL)
1105 return -ENOMEM;
1106
1107 /* Read the initial cache state back from the device - this is
1108 * a PMIC so the device many not be in a virgin state and we
1109 * can't rely on the silicon values.
1110 */
1111 for (i = 0; i < WM8350_MAX_REGISTER; i++) {
1112 /* audio register range */
1113 if (wm8350_reg_io_map[i].readable &&
1114 (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
1115 ret = wm8350->read_dev(wm8350, i, 2, (char *)&value);
1116 if (ret < 0) {
1117 dev_err(wm8350->dev,
1118 "failed to read initial cache value\n");
1119 goto out;
1120 }
1121 value = be16_to_cpu(value);
1122 value &= wm8350_reg_io_map[i].readable;
1123 wm8350->reg_cache[i] = value;
1124 } else
1125 wm8350->reg_cache[i] = reg_map[i];
1126 }
1127
1128out:
1129 return ret;
1130}
1131EXPORT_SYMBOL_GPL(wm8350_create_cache);
1132
ebccec0f 1133int wm8350_device_init(struct wm8350 *wm8350, int irq,
bcdd4efc 1134 struct wm8350_platform_data *pdata)
89b4012b
MB		 1135{
1136 int ret = -EINVAL;
1137 u16 id1, id2, mask, mode;
ebccec0f 1138 int i;
89b4012b
MB		 1139
1140 /* get WM8350 revision and config mode */
1141 wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1);
1142 wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2);
1143
1144 id1 = be16_to_cpu(id1);
1145 id2 = be16_to_cpu(id2);
1146
ebccec0f 1147 if (id1 == 0x6143) {
89b4012b
MB		 1148 switch ((id2 & WM8350_CHIP_REV_MASK) >> 12) {
1149 case WM8350_REV_E:
1150 dev_info(wm8350->dev, "Found Rev E device\n");
1151 wm8350->rev = WM8350_REV_E;
1152 break;
1153 case WM8350_REV_F:
1154 dev_info(wm8350->dev, "Found Rev F device\n");
1155 wm8350->rev = WM8350_REV_F;
1156 break;
1157 case WM8350_REV_G:
1158 dev_info(wm8350->dev, "Found Rev G device\n");
1159 wm8350->rev = WM8350_REV_G;
1160 break;
1161 default:
1162 /* For safety we refuse to run on unknown hardware */
1163 dev_info(wm8350->dev, "Found unknown rev\n");
1164 ret = -ENODEV;
1165 goto err;
1166 }
1167 } else {
1168 dev_info(wm8350->dev, "Device with ID %x is not a WM8350\n",
1169 id1);
1170 ret = -ENODEV;
1171 goto err;
1172 }
1173
1174 mode = id2 & WM8350_CONF_STS_MASK >> 10;
1175 mask = id2 & WM8350_CUST_ID_MASK;
1176 dev_info(wm8350->dev, "Config mode %d, ROM mask %d\n", mode, mask);
1177
1178 ret = wm8350_create_cache(wm8350, mode);
1179 if (ret < 0) {
1180 printk(KERN_ERR "wm8350: failed to create register cache\n");
1181 return ret;
1182 }
1183
bcdd4efc
MB		 1184 if (pdata->init) {
1185 ret = pdata->init(wm8350);
1186 if (ret != 0) {
1187 dev_err(wm8350->dev, "Platform init() failed: %d\n",
1188 ret);
1189 goto err;
1190 }
1191 }
1192
ebccec0f
MB		 1193 mutex_init(&wm8350->irq_mutex);
1194 INIT_WORK(&wm8350->irq_work, wm8350_irq_worker);
1195 if (irq != NO_IRQ) {
1196 ret = request_irq(irq, wm8350_irq, 0,
1197 "wm8350", wm8350);
1198 if (ret != 0) {
1199 dev_err(wm8350->dev, "Failed to request IRQ: %d\n",
1200 ret);
1201 goto err;
1202 }
1203 } else {
1204 dev_err(wm8350->dev, "No IRQ configured\n");
1205 goto err;
1206 }
1207 wm8350->chip_irq = irq;
1208
1209 wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
1210
89b4012b
MB		 1211 return 0;
1212
1213err:
1214 kfree(wm8350->reg_cache);
1215 return ret;
1216}
1217EXPORT_SYMBOL_GPL(wm8350_device_init);
1218
1219void wm8350_device_exit(struct wm8350 *wm8350)
1220{
ebccec0f
MB		 1221 free_irq(wm8350->chip_irq, wm8350);
1222 flush_work(&wm8350->irq_work);
89b4012b
MB		 1223 kfree(wm8350->reg_cache);
1224}
1225EXPORT_SYMBOL_GPL(wm8350_device_exit);
1226
ebccec0f 1227MODULE_DESCRIPTION("WM8350 AudioPlus PMIC core driver");
89b4012b 1228MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)