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Merge branch 'pm-cpufreq'
[linux-2.6-block.git] / drivers / mfd / twl-core.c
CommitLineData
a603a7fa 1/*
fc7b92fc
B		 2 * twl_core.c - driver for TWL4030/TWL5030/TWL60X0/TPS659x0 PM
3 * and audio CODEC devices
a603a7fa
DB		 4 *
5 * Copyright (C) 2005-2006 Texas Instruments, Inc.
6 *
7 * Modifications to defer interrupt handling to a kernel thread:
8 * Copyright (C) 2006 MontaVista Software, Inc.
9 *
10 * Based on tlv320aic23.c:
11 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
12 *
13 * Code cleanup and modifications to IRQ handler.
14 * by syed khasim <x0khasim@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 */
30
a603a7fa
DB		 31#include <linux/init.h>
32#include <linux/mutex.h>
4e36dd33 33#include <linux/module.h>
a603a7fa 34#include <linux/platform_device.h>
2473d25a 35#include <linux/regmap.h>
a603a7fa 36#include <linux/clk.h>
a30d46c0 37#include <linux/err.h>
aeb5032b
BC		 38#include <linux/device.h>
39#include <linux/of.h>
40#include <linux/of_irq.h>
41#include <linux/of_platform.h>
e7cc3aca 42#include <linux/irq.h>
aeb5032b 43#include <linux/irqdomain.h>
a603a7fa 44
dad759ff
DB		 45#include <linux/regulator/machine.h>
46
a603a7fa 47#include <linux/i2c.h>
b07682b6 48#include <linux/i2c/twl.h>
a603a7fa 49
91460700
PU		 50/* Register descriptions for audio */
51#include <linux/mfd/twl4030-audio.h>
52
1b8f333f 53#include "twl-core.h"
a603a7fa
DB		 54
55/*
56 * The TWL4030 "Triton 2" is one of a family of a multi-function "Power
57 * Management and System Companion Device" chips originally designed for
58 * use in OMAP2 and OMAP 3 based systems. Its control interfaces use I2C,
59 * often at around 3 Mbit/sec, including for interrupt handling.
60 *
61 * This driver core provides genirq support for the interrupts emitted,
62 * by the various modules, and exports register access primitives.
63 *
64 * FIXME this driver currently requires use of the first interrupt line
65 * (and associated registers).
66 */
67
fc7b92fc 68#define DRIVER_NAME "twl"
a603a7fa 69
a603a7fa
DB		 70/* Triton Core internal information (BEGIN) */
71
a603a7fa
DB		 72/* Base Address defns for twl4030_map[] */
73
74/* subchip/slave 0 - USB ID */
75#define TWL4030_BASEADD_USB 0x0000
76
77/* subchip/slave 1 - AUD ID */
78#define TWL4030_BASEADD_AUDIO_VOICE 0x0000
79#define TWL4030_BASEADD_GPIO 0x0098
80#define TWL4030_BASEADD_INTBR 0x0085
81#define TWL4030_BASEADD_PIH 0x0080
82#define TWL4030_BASEADD_TEST 0x004C
83
84/* subchip/slave 2 - AUX ID */
85#define TWL4030_BASEADD_INTERRUPTS 0x00B9
86#define TWL4030_BASEADD_LED 0x00EE
87#define TWL4030_BASEADD_MADC 0x0000
88#define TWL4030_BASEADD_MAIN_CHARGE 0x0074
89#define TWL4030_BASEADD_PRECHARGE 0x00AA
5d4e9bd7 90#define TWL4030_BASEADD_PWM 0x00F8
a603a7fa
DB		 91#define TWL4030_BASEADD_KEYPAD 0x00D2
92
1920a61e
IK		 93#define TWL5031_BASEADD_ACCESSORY 0x0074 /* Replaces Main Charge */
94#define TWL5031_BASEADD_INTERRUPTS 0x00B9 /* Different than TWL4030's
95 one */
96
a603a7fa
DB		 97/* subchip/slave 3 - POWER ID */
98#define TWL4030_BASEADD_BACKUP 0x0014
99#define TWL4030_BASEADD_INT 0x002E
100#define TWL4030_BASEADD_PM_MASTER 0x0036
a613b739 101
a603a7fa 102#define TWL4030_BASEADD_PM_RECEIVER 0x005B
a613b739
TL		 103#define TWL4030_DCDC_GLOBAL_CFG 0x06
104#define SMARTREFLEX_ENABLE BIT(3)
105
a603a7fa
DB		 106#define TWL4030_BASEADD_RTC 0x001C
107#define TWL4030_BASEADD_SECURED_REG 0x0000
108
109/* Triton Core internal information (END) */
110
111
e8deb28c
B		 112/* subchip/slave 0 0x48 - POWER */
113#define TWL6030_BASEADD_RTC 0x0000
5d4e9bd7 114#define TWL6030_BASEADD_SECURED_REG 0x0017
e8deb28c
B		 115#define TWL6030_BASEADD_PM_MASTER 0x001F
116#define TWL6030_BASEADD_PM_SLAVE_MISC 0x0030 /* PM_RECEIVER */
117#define TWL6030_BASEADD_PM_MISC 0x00E2
118#define TWL6030_BASEADD_PM_PUPD 0x00F0
119
120/* subchip/slave 1 0x49 - FEATURE */
121#define TWL6030_BASEADD_USB 0x0000
122#define TWL6030_BASEADD_GPADC_CTRL 0x002E
123#define TWL6030_BASEADD_AUX 0x0090
124#define TWL6030_BASEADD_PWM 0x00BA
125#define TWL6030_BASEADD_GASGAUGE 0x00C0
126#define TWL6030_BASEADD_PIH 0x00D0
127#define TWL6030_BASEADD_CHARGER 0x00E0
89ce43fb 128#define TWL6032_BASEADD_CHARGER 0x00DA
5d4e9bd7 129#define TWL6030_BASEADD_LED 0x00F4
e8deb28c
B		 130
131/* subchip/slave 2 0x4A - DFT */
132#define TWL6030_BASEADD_DIEID 0x00C0
133
134/* subchip/slave 3 0x4B - AUDIO */
135#define TWL6030_BASEADD_AUDIO 0x0000
136#define TWL6030_BASEADD_RSV 0x0000
fa0d9762 137#define TWL6030_BASEADD_ZERO 0x0000
e8deb28c 138
a603a7fa
DB		 139/* Few power values */
140#define R_CFG_BOOT 0x05
a603a7fa
DB		 141
142/* some fields in R_CFG_BOOT */
143#define HFCLK_FREQ_19p2_MHZ (1 << 0)
144#define HFCLK_FREQ_26_MHZ (2 << 0)
145#define HFCLK_FREQ_38p4_MHZ (3 << 0)
146#define HIGH_PERF_SQ (1 << 3)
38a68496 147#define CK32K_LOWPWR_EN (1 << 7)
a603a7fa 148
a603a7fa
DB		 149/*----------------------------------------------------------------------*/
150
e8deb28c 151/* Structure for each TWL4030/TWL6030 Slave */
fc7b92fc 152struct twl_client {
a603a7fa 153 struct i2c_client *client;
2473d25a 154 struct regmap *regmap;
a603a7fa
DB		 155};
156
a603a7fa 157/* mapping the module id to slave id and base address */
fc7b92fc 158struct twl_mapping {
a603a7fa
DB		 159 unsigned char sid; /* Slave ID */
160 unsigned char base; /* base address */
161};
80a97ccd
PU		 162
163struct twl_private {
164 bool ready; /* The core driver is ready to be used */
165 u32 twl_idcode; /* TWL IDCODE Register value */
166 unsigned int twl_id;
167
168 struct twl_mapping *twl_map;
169 struct twl_client *twl_modules;
170};
171
172static struct twl_private *twl_priv;
a603a7fa 173
da059ecf 174static struct twl_mapping twl4030_map[] = {
a603a7fa
DB		 175 /*
176 * NOTE: don't change this table without updating the
e8deb28c 177 * <linux/i2c/twl.h> defines for TWL4030_MODULE_*
a603a7fa
DB		 178 * so they continue to match the order in this table.
179 */
180
5d4e9bd7 181 /* Common IPs */
a603a7fa 182 { 0, TWL4030_BASEADD_USB },
5d4e9bd7
PU		 183 { 1, TWL4030_BASEADD_PIH },
184 { 2, TWL4030_BASEADD_MAIN_CHARGE },
185 { 3, TWL4030_BASEADD_PM_MASTER },
186 { 3, TWL4030_BASEADD_PM_RECEIVER },
187
188 { 3, TWL4030_BASEADD_RTC },
189 { 2, TWL4030_BASEADD_PWM },
190 { 2, TWL4030_BASEADD_LED },
191 { 3, TWL4030_BASEADD_SECURED_REG },
192
193 /* TWL4030 specific IPs */
a603a7fa
DB		 194 { 1, TWL4030_BASEADD_AUDIO_VOICE },
195 { 1, TWL4030_BASEADD_GPIO },
196 { 1, TWL4030_BASEADD_INTBR },
6691ccd0 197 { 1, TWL4030_BASEADD_TEST },
a603a7fa 198 { 2, TWL4030_BASEADD_KEYPAD },
5d4e9bd7 199
a603a7fa
DB		 200 { 2, TWL4030_BASEADD_MADC },
201 { 2, TWL4030_BASEADD_INTERRUPTS },
a603a7fa 202 { 2, TWL4030_BASEADD_PRECHARGE },
a603a7fa
DB		 203 { 3, TWL4030_BASEADD_BACKUP },
204 { 3, TWL4030_BASEADD_INT },
6691ccd0 205
5d4e9bd7
PU		 206 { 2, TWL5031_BASEADD_ACCESSORY },
207 { 2, TWL5031_BASEADD_INTERRUPTS },
a603a7fa
DB		 208};
209
d842b61b 210static const struct reg_default twl4030_49_defaults[] = {
91460700
PU		 211 /* Audio Registers */
212 { 0x01, 0x00}, /* CODEC_MODE */
213 { 0x02, 0x00}, /* OPTION */
214 /* 0x03 Unused */
215 { 0x04, 0x00}, /* MICBIAS_CTL */
216 { 0x05, 0x00}, /* ANAMICL */
217 { 0x06, 0x00}, /* ANAMICR */
218 { 0x07, 0x00}, /* AVADC_CTL */
219 { 0x08, 0x00}, /* ADCMICSEL */
220 { 0x09, 0x00}, /* DIGMIXING */
221 { 0x0a, 0x0f}, /* ATXL1PGA */
222 { 0x0b, 0x0f}, /* ATXR1PGA */
223 { 0x0c, 0x0f}, /* AVTXL2PGA */
224 { 0x0d, 0x0f}, /* AVTXR2PGA */
225 { 0x0e, 0x00}, /* AUDIO_IF */
226 { 0x0f, 0x00}, /* VOICE_IF */
227 { 0x10, 0x3f}, /* ARXR1PGA */
228 { 0x11, 0x3f}, /* ARXL1PGA */
229 { 0x12, 0x3f}, /* ARXR2PGA */
230 { 0x13, 0x3f}, /* ARXL2PGA */
231 { 0x14, 0x25}, /* VRXPGA */
232 { 0x15, 0x00}, /* VSTPGA */
233 { 0x16, 0x00}, /* VRX2ARXPGA */
234 { 0x17, 0x00}, /* AVDAC_CTL */
235 { 0x18, 0x00}, /* ARX2VTXPGA */
236 { 0x19, 0x32}, /* ARXL1_APGA_CTL*/
237 { 0x1a, 0x32}, /* ARXR1_APGA_CTL*/
238 { 0x1b, 0x32}, /* ARXL2_APGA_CTL*/
239 { 0x1c, 0x32}, /* ARXR2_APGA_CTL*/
240 { 0x1d, 0x00}, /* ATX2ARXPGA */
241 { 0x1e, 0x00}, /* BT_IF */
242 { 0x1f, 0x55}, /* BTPGA */
243 { 0x20, 0x00}, /* BTSTPGA */
244 { 0x21, 0x00}, /* EAR_CTL */
245 { 0x22, 0x00}, /* HS_SEL */
246 { 0x23, 0x00}, /* HS_GAIN_SET */
247 { 0x24, 0x00}, /* HS_POPN_SET */
248 { 0x25, 0x00}, /* PREDL_CTL */
249 { 0x26, 0x00}, /* PREDR_CTL */
250 { 0x27, 0x00}, /* PRECKL_CTL */
251 { 0x28, 0x00}, /* PRECKR_CTL */
252 { 0x29, 0x00}, /* HFL_CTL */
253 { 0x2a, 0x00}, /* HFR_CTL */
254 { 0x2b, 0x05}, /* ALC_CTL */
255 { 0x2c, 0x00}, /* ALC_SET1 */
256 { 0x2d, 0x00}, /* ALC_SET2 */
257 { 0x2e, 0x00}, /* BOOST_CTL */
258 { 0x2f, 0x00}, /* SOFTVOL_CTL */
259 { 0x30, 0x13}, /* DTMF_FREQSEL */
260 { 0x31, 0x00}, /* DTMF_TONEXT1H */
261 { 0x32, 0x00}, /* DTMF_TONEXT1L */
262 { 0x33, 0x00}, /* DTMF_TONEXT2H */
263 { 0x34, 0x00}, /* DTMF_TONEXT2L */
264 { 0x35, 0x79}, /* DTMF_TONOFF */
265 { 0x36, 0x11}, /* DTMF_WANONOFF */
266 { 0x37, 0x00}, /* I2S_RX_SCRAMBLE_H */
267 { 0x38, 0x00}, /* I2S_RX_SCRAMBLE_M */
268 { 0x39, 0x00}, /* I2S_RX_SCRAMBLE_L */
269 { 0x3a, 0x06}, /* APLL_CTL */
270 { 0x3b, 0x00}, /* DTMF_CTL */
271 { 0x3c, 0x44}, /* DTMF_PGA_CTL2 (0x3C) */
272 { 0x3d, 0x69}, /* DTMF_PGA_CTL1 (0x3D) */
273 { 0x3e, 0x00}, /* MISC_SET_1 */
274 { 0x3f, 0x00}, /* PCMBTMUX */
275 /* 0x40 - 0x42 Unused */
276 { 0x43, 0x00}, /* RX_PATH_SEL */
277 { 0x44, 0x32}, /* VDL_APGA_CTL */
278 { 0x45, 0x00}, /* VIBRA_CTL */
279 { 0x46, 0x00}, /* VIBRA_SET */
280 { 0x47, 0x00}, /* VIBRA_PWM_SET */
281 { 0x48, 0x00}, /* ANAMIC_GAIN */
282 { 0x49, 0x00}, /* MISC_SET_2 */
283 /* End of Audio Registers */
284};
285
286static bool twl4030_49_nop_reg(struct device *dev, unsigned int reg)
287{
288 switch (reg) {
56816b70
TN		 289 case 0x00:
290 case 0x03:
291 case 0x40:
292 case 0x41:
293 case 0x42:
91460700
PU		 294 return false;
295 default:
296 return true;
297 }
298}
299
300static const struct regmap_range twl4030_49_volatile_ranges[] = {
301 regmap_reg_range(TWL4030_BASEADD_TEST, 0xff),
302};
303
304static const struct regmap_access_table twl4030_49_volatile_table = {
305 .yes_ranges = twl4030_49_volatile_ranges,
306 .n_yes_ranges = ARRAY_SIZE(twl4030_49_volatile_ranges),
307};
308
d842b61b 309static const struct regmap_config twl4030_regmap_config[4] = {
2473d25a
PU		 310 {
311 /* Address 0x48 */
312 .reg_bits = 8,
313 .val_bits = 8,
314 .max_register = 0xff,
315 },
316 {
317 /* Address 0x49 */
318 .reg_bits = 8,
319 .val_bits = 8,
320 .max_register = 0xff,
91460700
PU		 321
322 .readable_reg = twl4030_49_nop_reg,
323 .writeable_reg = twl4030_49_nop_reg,
324
325 .volatile_table = &twl4030_49_volatile_table,
326
327 .reg_defaults = twl4030_49_defaults,
328 .num_reg_defaults = ARRAY_SIZE(twl4030_49_defaults),
329 .cache_type = REGCACHE_RBTREE,
2473d25a
PU		 330 },
331 {
332 /* Address 0x4a */
333 .reg_bits = 8,
334 .val_bits = 8,
335 .max_register = 0xff,
336 },
337 {
338 /* Address 0x4b */
339 .reg_bits = 8,
340 .val_bits = 8,
341 .max_register = 0xff,
342 },
343};
344
e8deb28c
B		 345static struct twl_mapping twl6030_map[] = {
346 /*
347 * NOTE: don't change this table without updating the
348 * <linux/i2c/twl.h> defines for TWL4030_MODULE_*
349 * so they continue to match the order in this table.
350 */
5d4e9bd7
PU		 351
352 /* Common IPs */
353 { 1, TWL6030_BASEADD_USB },
354 { 1, TWL6030_BASEADD_PIH },
355 { 1, TWL6030_BASEADD_CHARGER },
356 { 0, TWL6030_BASEADD_PM_MASTER },
357 { 0, TWL6030_BASEADD_PM_SLAVE_MISC },
358
359 { 0, TWL6030_BASEADD_RTC },
360 { 1, TWL6030_BASEADD_PWM },
361 { 1, TWL6030_BASEADD_LED },
362 { 0, TWL6030_BASEADD_SECURED_REG },
363
364 /* TWL6030 specific IPs */
365 { 0, TWL6030_BASEADD_ZERO },
366 { 1, TWL6030_BASEADD_ZERO },
367 { 2, TWL6030_BASEADD_ZERO },
368 { 1, TWL6030_BASEADD_GPADC_CTRL },
369 { 1, TWL6030_BASEADD_GASGAUGE },
e8deb28c
B		 370};
371
d842b61b 372static const struct regmap_config twl6030_regmap_config[3] = {
2473d25a
PU		 373 {
374 /* Address 0x48 */
375 .reg_bits = 8,
376 .val_bits = 8,
377 .max_register = 0xff,
378 },
379 {
380 /* Address 0x49 */
381 .reg_bits = 8,
382 .val_bits = 8,
383 .max_register = 0xff,
384 },
385 {
386 /* Address 0x4a */
387 .reg_bits = 8,
388 .val_bits = 8,
389 .max_register = 0xff,
390 },
391};
392
a603a7fa
DB		 393/*----------------------------------------------------------------------*/
394
6dd810b5
PU		 395static inline int twl_get_num_slaves(void)
396{
397 if (twl_class_is_4030())
398 return 4; /* TWL4030 class have four slave address */
399 else
400 return 3; /* TWL6030 class have three slave address */
401}
402
5d4e9bd7
PU		 403static inline int twl_get_last_module(void)
404{
405 if (twl_class_is_4030())
406 return TWL4030_MODULE_LAST;
407 else
408 return TWL6030_MODULE_LAST;
409}
410
a603a7fa
DB		 411/* Exported Functions */
412
80a97ccd
PU		 413unsigned int twl_rev(void)
414{
415 return twl_priv ? twl_priv->twl_id : 0;
416}
417EXPORT_SYMBOL(twl_rev);
418
a603a7fa 419/**
8daf3540 420 * twl_get_regmap - Get the regmap associated with the given module
a603a7fa 421 * @mod_no: module number
a603a7fa 422 *
8daf3540 423 * Returns the regmap pointer or NULL in case of failure.
a603a7fa 424 */
8daf3540 425static struct regmap *twl_get_regmap(u8 mod_no)
a603a7fa 426{
a603a7fa 427 int sid;
fc7b92fc 428 struct twl_client *twl;
a603a7fa 429
1765dbcc
JH		 430 if (unlikely(!twl_priv || !twl_priv->ready)) {
431 pr_err("%s: not initialized\n", DRIVER_NAME);
8daf3540 432 return NULL;
a603a7fa 433 }
1765dbcc
JH		 434 if (unlikely(mod_no >= twl_get_last_module())) {
435 pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no);
8daf3540 436 return NULL;
a603a7fa 437 }
050cde13 438
80a97ccd
PU		 439 sid = twl_priv->twl_map[mod_no].sid;
440 twl = &twl_priv->twl_modules[sid];
8653be1a 441
8daf3540
PU		 442 return twl->regmap;
443}
444
445/**
446 * twl_i2c_write - Writes a n bit register in TWL4030/TWL5030/TWL60X0
447 * @mod_no: module number
448 * @value: an array of num_bytes+1 containing data to write
449 * @reg: register address (just offset will do)
450 * @num_bytes: number of bytes to transfer
451 *
452 * Returns the result of operation - 0 is success
453 */
454int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
455{
456 struct regmap *regmap = twl_get_regmap(mod_no);
457 int ret;
458
459 if (!regmap)
460 return -EPERM;
461
462 ret = regmap_bulk_write(regmap, twl_priv->twl_map[mod_no].base + reg,
463 value, num_bytes);
2473d25a
PU		 464
465 if (ret)
466 pr_err("%s: Write failed (mod %d, reg 0x%02x count %d)\n",
467 DRIVER_NAME, mod_no, reg, num_bytes);
468
469 return ret;
a603a7fa 470}
fc7b92fc 471EXPORT_SYMBOL(twl_i2c_write);
a603a7fa
DB		 472
473/**
fc7b92fc 474 * twl_i2c_read - Reads a n bit register in TWL4030/TWL5030/TWL60X0
a603a7fa
DB		 475 * @mod_no: module number
476 * @value: an array of num_bytes containing data to be read
477 * @reg: register address (just offset will do)
478 * @num_bytes: number of bytes to transfer
479 *
480 * Returns result of operation - num_bytes is success else failure.
481 */
fc7b92fc 482int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
a603a7fa 483{
8daf3540 484 struct regmap *regmap = twl_get_regmap(mod_no);
a603a7fa 485 int ret;
a603a7fa 486
8daf3540 487 if (!regmap)
a603a7fa 488 return -EPERM;
8653be1a 489
8daf3540
PU		 490 ret = regmap_bulk_read(regmap, twl_priv->twl_map[mod_no].base + reg,
491 value, num_bytes);
2473d25a
PU		 492
493 if (ret)
494 pr_err("%s: Read failed (mod %d, reg 0x%02x count %d)\n",
495 DRIVER_NAME, mod_no, reg, num_bytes);
496
497 return ret;
a603a7fa 498}
fc7b92fc 499EXPORT_SYMBOL(twl_i2c_read);
a603a7fa 500
3def927e
PU		 501/**
502 * twl_regcache_bypass - Configure the regcache bypass for the regmap associated
503 * with the module
504 * @mod_no: module number
505 * @enable: Regcache bypass state
506 *
507 * Returns 0 else failure.
508 */
509int twl_set_regcache_bypass(u8 mod_no, bool enable)
510{
511 struct regmap *regmap = twl_get_regmap(mod_no);
512
513 if (!regmap)
514 return -EPERM;
515
516 regcache_cache_bypass(regmap, enable);
517
518 return 0;
519}
520EXPORT_SYMBOL(twl_set_regcache_bypass);
521
a603a7fa
DB		 522/*----------------------------------------------------------------------*/
523
ca972d13
L		 524/**
525 * twl_read_idcode_register - API to read the IDCODE register.
526 *
527 * Unlocks the IDCODE register and read the 32 bit value.
528 */
529static int twl_read_idcode_register(void)
530{
531 int err;
532
533 err = twl_i2c_write_u8(TWL4030_MODULE_INTBR, TWL_EEPROM_R_UNLOCK,
534 REG_UNLOCK_TEST_REG);
535 if (err) {
536 pr_err("TWL4030 Unable to unlock IDCODE registers -%d\n", err);
537 goto fail;
538 }
539
80a97ccd 540 err = twl_i2c_read(TWL4030_MODULE_INTBR, (u8 *)(&twl_priv->twl_idcode),
ca972d13
L		 541 REG_IDCODE_7_0, 4);
542 if (err) {
543 pr_err("TWL4030: unable to read IDCODE -%d\n", err);
544 goto fail;
545 }
546
547 err = twl_i2c_write_u8(TWL4030_MODULE_INTBR, 0x0, REG_UNLOCK_TEST_REG);
548 if (err)
549 pr_err("TWL4030 Unable to relock IDCODE registers -%d\n", err);
550fail:
551 return err;
552}
553
554/**
555 * twl_get_type - API to get TWL Si type.
556 *
557 * Api to get the TWL Si type from IDCODE value.
558 */
559int twl_get_type(void)
560{
80a97ccd 561 return TWL_SIL_TYPE(twl_priv->twl_idcode);
ca972d13
L		 562}
563EXPORT_SYMBOL_GPL(twl_get_type);
564
565/**
566 * twl_get_version - API to get TWL Si version.
567 *
568 * Api to get the TWL Si version from IDCODE value.
569 */
570int twl_get_version(void)
571{
80a97ccd 572 return TWL_SIL_REV(twl_priv->twl_idcode);
ca972d13
L		 573}
574EXPORT_SYMBOL_GPL(twl_get_version);
575
2275c544
PU		 576/**
577 * twl_get_hfclk_rate - API to get TWL external HFCLK clock rate.
578 *
579 * Api to get the TWL HFCLK rate based on BOOT_CFG register.
580 */
581int twl_get_hfclk_rate(void)
582{
583 u8 ctrl;
584 int rate;
585
586 twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &ctrl, R_CFG_BOOT);
587
588 switch (ctrl & 0x3) {
589 case HFCLK_FREQ_19p2_MHZ:
590 rate = 19200000;
591 break;
592 case HFCLK_FREQ_26_MHZ:
593 rate = 26000000;
594 break;
595 case HFCLK_FREQ_38p4_MHZ:
596 rate = 38400000;
597 break;
598 default:
599 pr_err("TWL4030: HFCLK is not configured\n");
600 rate = -EINVAL;
601 break;
602 }
603
604 return rate;
605}
606EXPORT_SYMBOL_GPL(twl_get_hfclk_rate);
607
dad759ff 608static struct device *
3c330279 609add_numbered_child(unsigned mod_no, const char *name, int num,
5725d66b
DB		 610 void *pdata, unsigned pdata_len,
611 bool can_wakeup, int irq0, int irq1)
a603a7fa 612{
5725d66b 613 struct platform_device *pdev;
3c330279
PU		 614 struct twl_client *twl;
615 int status, sid;
616
617 if (unlikely(mod_no >= twl_get_last_module())) {
618 pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no);
619 return ERR_PTR(-EPERM);
620 }
80a97ccd
PU		 621 sid = twl_priv->twl_map[mod_no].sid;
622 twl = &twl_priv->twl_modules[sid];
5725d66b 623
dad759ff 624 pdev = platform_device_alloc(name, num);
5725d66b
DB		 625 if (!pdev) {
626 dev_dbg(&twl->client->dev, "can't alloc dev\n");
627 status = -ENOMEM;
628 goto err;
629 }
a603a7fa 630
5725d66b 631 pdev->dev.parent = &twl->client->dev;
a603a7fa 632
5725d66b
DB		 633 if (pdata) {
634 status = platform_device_add_data(pdev, pdata, pdata_len);
635 if (status < 0) {
636 dev_dbg(&pdev->dev, "can't add platform_data\n");
a603a7fa
DB		 637 goto err;
638 }
5725d66b 639 }
a603a7fa 640
5725d66b
DB		 641 if (irq0) {
642 struct resource r[2] = {
643 { .start = irq0, .flags = IORESOURCE_IRQ, },
644 { .start = irq1, .flags = IORESOURCE_IRQ, },
645 };
a603a7fa 646
5725d66b 647 status = platform_device_add_resources(pdev, r, irq1 ? 2 : 1);
a603a7fa 648 if (status < 0) {
5725d66b 649 dev_dbg(&pdev->dev, "can't add irqs\n");
a603a7fa
DB		 650 goto err;
651 }
652 }
653
5725d66b 654 status = platform_device_add(pdev);
17ffba6a
N		 655 if (status == 0)
656 device_init_wakeup(&pdev->dev, can_wakeup);
a603a7fa 657
5725d66b
DB		 658err:
659 if (status < 0) {
660 platform_device_put(pdev);
661 dev_err(&twl->client->dev, "can't add %s dev\n", name);
662 return ERR_PTR(status);
663 }
664 return &pdev->dev;
665}
a603a7fa 666
3c330279 667static inline struct device *add_child(unsigned mod_no, const char *name,
dad759ff
DB		 668 void *pdata, unsigned pdata_len,
669 bool can_wakeup, int irq0, int irq1)
670{
3c330279 671 return add_numbered_child(mod_no, name, -1, pdata, pdata_len,
dad759ff
DB		 672 can_wakeup, irq0, irq1);
673}
674
675static struct device *
676add_regulator_linked(int num, struct regulator_init_data *pdata,
677 struct regulator_consumer_supply *consumers,
521d8ec3 678 unsigned num_consumers, unsigned long features)
dad759ff 679{
63bfff4e
TK		 680 struct twl_regulator_driver_data drv_data;
681
dad759ff
DB		 682 /* regulator framework demands init_data ... */
683 if (!pdata)
684 return NULL;
685
b73eac78 686 if (consumers) {
dad759ff
DB		 687 pdata->consumer_supplies = consumers;
688 pdata->num_consumer_supplies = num_consumers;
689 }
690
63bfff4e
TK		 691 if (pdata->driver_data) {
692 /* If we have existing drv_data, just add the flags */
693 struct twl_regulator_driver_data *tmp;
694 tmp = pdata->driver_data;
695 tmp->features |= features;
696 } else {
697 /* add new driver data struct, used only during init */
698 drv_data.features = features;
699 drv_data.set_voltage = NULL;
700 drv_data.get_voltage = NULL;
701 drv_data.data = NULL;
702 pdata->driver_data = &drv_data;
703 }
521d8ec3 704
dad759ff 705 /* NOTE: we currently ignore regulator IRQs, e.g. for short circuits */
3c330279 706 return add_numbered_child(TWL_MODULE_PM_MASTER, "twl_reg", num,
dad759ff
DB		 707 pdata, sizeof(*pdata), false, 0, 0);
708}
709
710static struct device *
521d8ec3
GG		 711add_regulator(int num, struct regulator_init_data *pdata,
712 unsigned long features)
dad759ff 713{
521d8ec3 714 return add_regulator_linked(num, pdata, NULL, 0, features);
dad759ff
DB		 715}
716
5725d66b
DB		 717/*
718 * NOTE: We know the first 8 IRQs after pdata->base_irq are
719 * for the PIH, and the next are for the PWR_INT SIH, since
720 * that's how twl_init_irq() sets things up.
721 */
a603a7fa 722
dad759ff 723static int
9e178620
FB		 724add_children(struct twl4030_platform_data *pdata, unsigned irq_base,
725 unsigned long features)
5725d66b
DB		 726{
727 struct device *child;
a603a7fa 728
f78959cf 729 if (IS_ENABLED(CONFIG_GPIO_TWL4030) && pdata->gpio) {
3c330279 730 child = add_child(TWL4030_MODULE_GPIO, "twl4030_gpio",
5725d66b 731 pdata->gpio, sizeof(*pdata->gpio),
9e178620 732 false, irq_base + GPIO_INTR_OFFSET, 0);
5725d66b
DB		 733 if (IS_ERR(child))
734 return PTR_ERR(child);
a603a7fa
DB		 735 }
736
f78959cf 737 if (IS_ENABLED(CONFIG_KEYBOARD_TWL4030) && pdata->keypad) {
3c330279 738 child = add_child(TWL4030_MODULE_KEYPAD, "twl4030_keypad",
5725d66b 739 pdata->keypad, sizeof(*pdata->keypad),
9e178620 740 true, irq_base + KEYPAD_INTR_OFFSET, 0);
5725d66b
DB		 741 if (IS_ERR(child))
742 return PTR_ERR(child);
a603a7fa
DB		 743 }
744
24ae36f5
PU		 745 if (IS_ENABLED(CONFIG_TWL4030_MADC) && pdata->madc &&
746 twl_class_is_4030()) {
3c330279 747 child = add_child(TWL4030_MODULE_MADC, "twl4030_madc",
5725d66b 748 pdata->madc, sizeof(*pdata->madc),
9e178620 749 true, irq_base + MADC_INTR_OFFSET, 0);
5725d66b
DB		 750 if (IS_ERR(child))
751 return PTR_ERR(child);
a603a7fa
DB		 752 }
753
f78959cf 754 if (IS_ENABLED(CONFIG_RTC_DRV_TWL4030)) {
a603a7fa 755 /*
5725d66b 756 * REVISIT platform_data here currently might expose the
a603a7fa 757 * "msecure" line ... but for now we just expect board
5725d66b 758 * setup to tell the chip "it's always ok to SET_TIME".
a603a7fa
DB		 759 * Eventually, Linux might become more aware of such
760 * HW security concerns, and "least privilege".
761 */
3c330279 762 child = add_child(TWL_MODULE_RTC, "twl_rtc", NULL, 0,
9e178620 763 true, irq_base + RTC_INTR_OFFSET, 0);
5725d66b
DB		 764 if (IS_ERR(child))
765 return PTR_ERR(child);
a603a7fa
DB		 766 }
767
afc45898 768 if (IS_ENABLED(CONFIG_PWM_TWL)) {
3c330279 769 child = add_child(TWL_MODULE_PWM, "twl-pwm", NULL, 0,
afc45898
PU		 770 false, 0, 0);
771 if (IS_ERR(child))
772 return PTR_ERR(child);
773 }
774
775 if (IS_ENABLED(CONFIG_PWM_TWL_LED)) {
3c330279 776 child = add_child(TWL_MODULE_LED, "twl-pwmled", NULL, 0,
48a364b7
TR		 777 false, 0, 0);
778 if (IS_ERR(child))
779 return PTR_ERR(child);
780 }
781
f78959cf
TR		 782 if (IS_ENABLED(CONFIG_TWL4030_USB) && pdata->usb &&
783 twl_class_is_4030()) {
f8ebdff0
RQ		 784
785 static struct regulator_consumer_supply usb1v5 = {
786 .supply = "usb1v5",
787 };
788 static struct regulator_consumer_supply usb1v8 = {
789 .supply = "usb1v8",
790 };
e57c4a67
N		 791 static struct regulator_consumer_supply usb3v1 = {
792 .supply = "usb3v1",
f8ebdff0
RQ		 793 };
794
795 /* First add the regulators so that they can be used by transceiver */
f78959cf 796 if (IS_ENABLED(CONFIG_REGULATOR_TWL4030)) {
f8ebdff0
RQ		 797 /* this is a template that gets copied */
798 struct regulator_init_data usb_fixed = {
799 .constraints.valid_modes_mask =
800 REGULATOR_MODE_NORMAL
801 | REGULATOR_MODE_STANDBY,
802 .constraints.valid_ops_mask =
803 REGULATOR_CHANGE_MODE
804 | REGULATOR_CHANGE_STATUS,
805 };
806
807 child = add_regulator_linked(TWL4030_REG_VUSB1V5,
521d8ec3
GG		 808 &usb_fixed, &usb1v5, 1,
809 features);
f8ebdff0
RQ		 810 if (IS_ERR(child))
811 return PTR_ERR(child);
812
813 child = add_regulator_linked(TWL4030_REG_VUSB1V8,
521d8ec3
GG		 814 &usb_fixed, &usb1v8, 1,
815 features);
f8ebdff0
RQ		 816 if (IS_ERR(child))
817 return PTR_ERR(child);
818
819 child = add_regulator_linked(TWL4030_REG_VUSB3V1,
e57c4a67 820 &usb_fixed, &usb3v1, 1,
521d8ec3 821 features);
f8ebdff0
RQ		 822 if (IS_ERR(child))
823 return PTR_ERR(child);
824
825 }
826
3c330279 827 child = add_child(TWL_MODULE_USB, "twl4030_usb",
2d86ad37 828 pdata->usb, sizeof(*pdata->usb), true,
5725d66b 829 /* irq0 = USB_PRES, irq1 = USB */
9e178620
FB		 830 irq_base + USB_PRES_INTR_OFFSET,
831 irq_base + USB_INTR_OFFSET);
f8ebdff0 832
5725d66b
DB		 833 if (IS_ERR(child))
834 return PTR_ERR(child);
dad759ff
DB		 835
836 /* we need to connect regulators to this transceiver */
f78959cf 837 if (IS_ENABLED(CONFIG_REGULATOR_TWL4030) && child) {
1b65fa84
MB		 838 usb1v5.dev_name = dev_name(child);
839 usb1v8.dev_name = dev_name(child);
e57c4a67 840 usb3v1.dev_name = dev_name(child);
f8ebdff0 841 }
dad759ff
DB		 842 }
843
f78959cf 844 if (IS_ENABLED(CONFIG_TWL4030_WATCHDOG) && twl_class_is_4030()) {
3c330279
PU		 845 child = add_child(TWL_MODULE_PM_RECEIVER, "twl4030_wdt", NULL,
846 0, false, 0, 0);
80e45b1e 847 if (IS_ERR(child))
9c3664dd
FB		 848 return PTR_ERR(child);
849 }
850
f78959cf 851 if (IS_ENABLED(CONFIG_INPUT_TWL4030_PWRBUTTON) && twl_class_is_4030()) {
3c330279
PU		 852 child = add_child(TWL_MODULE_PM_MASTER, "twl4030_pwrbutton",
853 NULL, 0, true, irq_base + 8 + 0, 0);
9c3664dd 854 if (IS_ERR(child))
80e45b1e
TK		 855 return PTR_ERR(child);
856 }
857
f78959cf
TR		 858 if (IS_ENABLED(CONFIG_MFD_TWL4030_AUDIO) && pdata->audio &&
859 twl_class_is_4030()) {
3c330279 860 child = add_child(TWL4030_MODULE_AUDIO_VOICE, "twl4030-audio",
4ae6df5e 861 pdata->audio, sizeof(*pdata->audio),
d62abe56
MLC		 862 false, 0, 0);
863 if (IS_ERR(child))
864 return PTR_ERR(child);
865 }
866
9da66539 867 /* twl4030 regulators */
f78959cf 868 if (IS_ENABLED(CONFIG_REGULATOR_TWL4030) && twl_class_is_4030()) {
521d8ec3
GG		 869 child = add_regulator(TWL4030_REG_VPLL1, pdata->vpll1,
870 features);
dad759ff
DB		 871 if (IS_ERR(child))
872 return PTR_ERR(child);
ab4abe05 873
521d8ec3
GG		 874 child = add_regulator(TWL4030_REG_VIO, pdata->vio,
875 features);
ab4abe05
JKS		 876 if (IS_ERR(child))
877 return PTR_ERR(child);
878
521d8ec3
GG		 879 child = add_regulator(TWL4030_REG_VDD1, pdata->vdd1,
880 features);
ab4abe05
JKS		 881 if (IS_ERR(child))
882 return PTR_ERR(child);
883
521d8ec3
GG		 884 child = add_regulator(TWL4030_REG_VDD2, pdata->vdd2,
885 features);
ab4abe05
JKS		 886 if (IS_ERR(child))
887 return PTR_ERR(child);
dad759ff 888
521d8ec3
GG		 889 child = add_regulator(TWL4030_REG_VMMC1, pdata->vmmc1,
890 features);
dad759ff
DB		 891 if (IS_ERR(child))
892 return PTR_ERR(child);
893
521d8ec3
GG		 894 child = add_regulator(TWL4030_REG_VDAC, pdata->vdac,
895 features);
dad759ff
DB		 896 if (IS_ERR(child))
897 return PTR_ERR(child);
898
899 child = add_regulator((features & TWL4030_VAUX2)
900 ? TWL4030_REG_VAUX2_4030
901 : TWL4030_REG_VAUX2,
521d8ec3 902 pdata->vaux2, features);
dad759ff
DB		 903 if (IS_ERR(child))
904 return PTR_ERR(child);
ab4abe05 905
521d8ec3
GG		 906 child = add_regulator(TWL4030_REG_VINTANA1, pdata->vintana1,
907 features);
ab4abe05
JKS		 908 if (IS_ERR(child))
909 return PTR_ERR(child);
910
521d8ec3
GG		 911 child = add_regulator(TWL4030_REG_VINTANA2, pdata->vintana2,
912 features);
ab4abe05
JKS		 913 if (IS_ERR(child))
914 return PTR_ERR(child);
915
521d8ec3
GG		 916 child = add_regulator(TWL4030_REG_VINTDIG, pdata->vintdig,
917 features);
ab4abe05
JKS		 918 if (IS_ERR(child))
919 return PTR_ERR(child);
dad759ff
DB		 920 }
921
dad759ff 922 /* maybe add LDOs that are omitted on cost-reduced parts */
f78959cf 923 if (IS_ENABLED(CONFIG_REGULATOR_TWL4030) && !(features & TPS_SUBSET)
9da66539 924 && twl_class_is_4030()) {
521d8ec3
GG		 925 child = add_regulator(TWL4030_REG_VPLL2, pdata->vpll2,
926 features);
dad759ff
DB		 927 if (IS_ERR(child))
928 return PTR_ERR(child);
dad759ff 929
521d8ec3
GG		 930 child = add_regulator(TWL4030_REG_VMMC2, pdata->vmmc2,
931 features);
dad759ff
DB		 932 if (IS_ERR(child))
933 return PTR_ERR(child);
934
521d8ec3
GG		 935 child = add_regulator(TWL4030_REG_VSIM, pdata->vsim,
936 features);
dad759ff
DB		 937 if (IS_ERR(child))
938 return PTR_ERR(child);
939
521d8ec3
GG		 940 child = add_regulator(TWL4030_REG_VAUX1, pdata->vaux1,
941 features);
dad759ff
DB		 942 if (IS_ERR(child))
943 return PTR_ERR(child);
944
521d8ec3
GG		 945 child = add_regulator(TWL4030_REG_VAUX3, pdata->vaux3,
946 features);
dad759ff
DB		 947 if (IS_ERR(child))
948 return PTR_ERR(child);
949
521d8ec3
GG		 950 child = add_regulator(TWL4030_REG_VAUX4, pdata->vaux4,
951 features);
dad759ff
DB		 952 if (IS_ERR(child))
953 return PTR_ERR(child);
a603a7fa
DB		 954 }
955
f78959cf 956 if (IS_ENABLED(CONFIG_CHARGER_TWL4030) && pdata->bci &&
11c39c4b 957 !(features & (TPS_SUBSET | TWL5031))) {
3c330279 958 child = add_child(TWL_MODULE_MAIN_CHARGE, "twl4030_bci",
11c39c4b
GI		 959 pdata->bci, sizeof(*pdata->bci), false,
960 /* irq0 = CHG_PRES, irq1 = BCI */
9e178620
FB		 961 irq_base + BCI_PRES_INTR_OFFSET,
962 irq_base + BCI_INTR_OFFSET);
11c39c4b
GI		 963 if (IS_ERR(child))
964 return PTR_ERR(child);
965 }
966
637d6895
FV		 967 if (IS_ENABLED(CONFIG_TWL4030_POWER) && pdata->power) {
968 child = add_child(TWL_MODULE_PM_MASTER, "twl4030_power",
969 pdata->power, sizeof(*pdata->power), false,
970 0, 0);
971 if (IS_ERR(child))
972 return PTR_ERR(child);
973 }
974
5725d66b 975 return 0;
a603a7fa
DB		 976}
977
978/*----------------------------------------------------------------------*/
979
980/*
981 * These three functions initialize the on-chip clock framework,
982 * letting it generate the right frequencies for USB, MADC, and
983 * other purposes.
984 */
985static inline int __init protect_pm_master(void)
986{
987 int e = 0;
988
d640e757
PU		 989 e = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
990 TWL4030_PM_MASTER_PROTECT_KEY);
a603a7fa
DB		 991 return e;
992}
993
994static inline int __init unprotect_pm_master(void)
995{
996 int e = 0;
997
d640e757
PU		 998 e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
999 TWL4030_PM_MASTER_PROTECT_KEY);
1000 e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
1001 TWL4030_PM_MASTER_PROTECT_KEY);
49e6f87e 1002
a603a7fa
DB		 1003 return e;
1004}
1005
38a68496
IK		 1006static void clocks_init(struct device *dev,
1007 struct twl4030_clock_init_data *clock)
a603a7fa
DB		 1008{
1009 int e = 0;
1010 struct clk *osc;
1011 u32 rate;
1012 u8 ctrl = HFCLK_FREQ_26_MHZ;
1013
defa6be1 1014 osc = clk_get(dev, "fck");
a603a7fa 1015 if (IS_ERR(osc)) {
fc7b92fc 1016 printk(KERN_WARNING "Skipping twl internal clock init and "
a603a7fa
DB		 1017 "using bootloader value (unknown osc rate)\n");
1018 return;
1019 }
1020
1021 rate = clk_get_rate(osc);
1022 clk_put(osc);
1023
1024 switch (rate) {
1025 case 19200000:
1026 ctrl = HFCLK_FREQ_19p2_MHZ;
1027 break;
1028 case 26000000:
1029 ctrl = HFCLK_FREQ_26_MHZ;
1030 break;
1031 case 38400000:
1032 ctrl = HFCLK_FREQ_38p4_MHZ;
1033 break;
1034 }
1035
1036 ctrl |= HIGH_PERF_SQ;
38a68496
IK		 1037 if (clock && clock->ck32k_lowpwr_enable)
1038 ctrl |= CK32K_LOWPWR_EN;
1039
a603a7fa
DB		 1040 e |= unprotect_pm_master();
1041 /* effect->MADC+USB ck en */
fc7b92fc 1042 e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, ctrl, R_CFG_BOOT);
a603a7fa
DB		 1043 e |= protect_pm_master();
1044
1045 if (e < 0)
1046 pr_err("%s: clock init err [%d]\n", DRIVER_NAME, e);
1047}
1048
1049/*----------------------------------------------------------------------*/
1050
a603a7fa 1051
fc7b92fc 1052static int twl_remove(struct i2c_client *client)
a603a7fa 1053{
364cedb2 1054 unsigned i, num_slaves;
a30d46c0 1055 int status;
a603a7fa 1056
6dd810b5 1057 if (twl_class_is_4030())
e8deb28c 1058 status = twl4030_exit_irq();
6dd810b5 1059 else
e8deb28c
B		 1060 status = twl6030_exit_irq();
1061
a30d46c0
DB		 1062 if (status < 0)
1063 return status;
a603a7fa 1064
6dd810b5 1065 num_slaves = twl_get_num_slaves();
364cedb2 1066 for (i = 0; i < num_slaves; i++) {
80a97ccd 1067 struct twl_client *twl = &twl_priv->twl_modules[i];
a603a7fa
DB		 1068
1069 if (twl->client && twl->client != client)
1070 i2c_unregister_device(twl->client);
80a97ccd 1071 twl->client = NULL;
a603a7fa 1072 }
80a97ccd 1073 twl_priv->ready = false;
a603a7fa
DB		 1074 return 0;
1075}
1076
80ec831e
TL		 1077static struct of_dev_auxdata twl_auxdata_lookup[] = {
1078 OF_DEV_AUXDATA("ti,twl4030-gpio", 0, "twl4030-gpio", NULL),
1079 { /* sentinel */ },
1080};
1081
ec1a07b3 1082/* NOTE: This driver only handles a single twl4030/tps659x0 chip */
f791be49 1083static int
fc7b92fc 1084twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
a603a7fa 1085{
334a41ce 1086 struct twl4030_platform_data *pdata = dev_get_platdata(&client->dev);
aeb5032b 1087 struct device_node *node = client->dev.of_node;
defa6be1 1088 struct platform_device *pdev;
d842b61b 1089 const struct regmap_config *twl_regmap_config;
ec1a07b3
BC		 1090 int irq_base = 0;
1091 int status;
364cedb2 1092 unsigned i, num_slaves;
aeb5032b 1093
7e2e6c57
PU		 1094 if (!node && !pdata) {
1095 dev_err(&client->dev, "no platform data\n");
1096 return -EINVAL;
1097 }
1098
80a97ccd 1099 if (twl_priv) {
6382a061
PU		 1100 dev_dbg(&client->dev, "only one instance of %s allowed\n",
1101 DRIVER_NAME);
1102 return -EBUSY;
1103 }
1104
defa6be1
TL		 1105 pdev = platform_device_alloc(DRIVER_NAME, -1);
1106 if (!pdev) {
1107 dev_err(&client->dev, "can't alloc pdev\n");
1108 return -ENOMEM;
1109 }
1110
1111 status = platform_device_add(pdev);
1112 if (status) {
1113 platform_device_put(pdev);
1114 return status;
1115 }
1116
a603a7fa
DB		 1117 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) == 0) {
1118 dev_dbg(&client->dev, "can't talk I2C?\n");
defa6be1
TL		 1119 status = -EIO;
1120 goto free;
a603a7fa
DB		 1121 }
1122
80a97ccd
PU		 1123 twl_priv = devm_kzalloc(&client->dev, sizeof(struct twl_private),
1124 GFP_KERNEL);
1125 if (!twl_priv) {
1126 status = -ENOMEM;
1127 goto free;
1128 }
1129
364cedb2 1130 if ((id->driver_data) & TWL6030_CLASS) {
80a97ccd
PU		 1131 twl_priv->twl_id = TWL6030_CLASS_ID;
1132 twl_priv->twl_map = &twl6030_map[0];
89ce43fb
GG		 1133 /* The charger base address is different in twl6032 */
1134 if ((id->driver_data) & TWL6032_SUBCLASS)
80a97ccd 1135 twl_priv->twl_map[TWL_MODULE_MAIN_CHARGE].base =
89ce43fb 1136 TWL6032_BASEADD_CHARGER;
2473d25a 1137 twl_regmap_config = twl6030_regmap_config;
364cedb2 1138 } else {
80a97ccd
PU		 1139 twl_priv->twl_id = TWL4030_CLASS_ID;
1140 twl_priv->twl_map = &twl4030_map[0];
2473d25a 1141 twl_regmap_config = twl4030_regmap_config;
6dd810b5
PU		 1142 }
1143
1144 num_slaves = twl_get_num_slaves();
80a97ccd
PU		 1145 twl_priv->twl_modules = devm_kzalloc(&client->dev,
1146 sizeof(struct twl_client) * num_slaves,
1147 GFP_KERNEL);
1148 if (!twl_priv->twl_modules) {
6dd810b5
PU		 1149 status = -ENOMEM;
1150 goto free;
364cedb2
PU		 1151 }
1152
1153 for (i = 0; i < num_slaves; i++) {
80a97ccd 1154 struct twl_client *twl = &twl_priv->twl_modules[i];
a603a7fa 1155
ec1a07b3 1156 if (i == 0) {
a603a7fa 1157 twl->client = client;
ec1a07b3 1158 } else {
a603a7fa 1159 twl->client = i2c_new_dummy(client->adapter,
2473d25a 1160 client->addr + i);
a603a7fa 1161 if (!twl->client) {
a8643430 1162 dev_err(&client->dev,
a603a7fa
DB		 1163 "can't attach client %d\n", i);
1164 status = -ENOMEM;
1165 goto fail;
1166 }
a603a7fa 1167 }
2473d25a
PU		 1168
1169 twl->regmap = devm_regmap_init_i2c(twl->client,
1170 &twl_regmap_config[i]);
1171 if (IS_ERR(twl->regmap)) {
1172 status = PTR_ERR(twl->regmap);
1173 dev_err(&client->dev,
1174 "Failed to allocate regmap %d, err: %d\n", i,
1175 status);
1176 goto fail;
1177 }
a603a7fa 1178 }
ec1a07b3 1179
80a97ccd 1180 twl_priv->ready = true;
a603a7fa
DB		 1181
1182 /* setup clock framework */
7e2e6c57 1183 clocks_init(&pdev->dev, pdata ? pdata->clock : NULL);
a603a7fa 1184
ca972d13 1185 /* read TWL IDCODE Register */
80a97ccd 1186 if (twl_class_is_4030()) {
ec1a07b3
BC		 1187 status = twl_read_idcode_register();
1188 WARN(status < 0, "Error: reading twl_idcode register value\n");
ca972d13
L		 1189 }
1190
a603a7fa 1191 /* Maybe init the T2 Interrupt subsystem */
9e178620 1192 if (client->irq) {
e8deb28c
B		 1193 if (twl_class_is_4030()) {
1194 twl4030_init_chip_irq(id->name);
78518ffa 1195 irq_base = twl4030_init_irq(&client->dev, client->irq);
e8deb28c 1196 } else {
78518ffa 1197 irq_base = twl6030_init_irq(&client->dev, client->irq);
e8deb28c
B		 1198 }
1199
78518ffa
BC		 1200 if (irq_base < 0) {
1201 status = irq_base;
a30d46c0 1202 goto fail;
78518ffa 1203 }
a603a7fa
DB		 1204 }
1205
ec1a07b3
BC		 1206 /*
1207 * Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
a29aaf55
MS		 1208 * Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0,
1209 * SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0.
a613b739
TL		 1210 *
1211 * Also, always enable SmartReflex bit as that's needed for omaps to
1212 * to do anything over I2C4 for voltage scaling even if SmartReflex
1213 * is disabled. Without the SmartReflex bit omap sys_clkreq idle
1214 * signal will never trigger for retention idle.
a29aaf55 1215 */
a29aaf55 1216 if (twl_class_is_4030()) {
ec1a07b3
BC		 1217 u8 temp;
1218
a29aaf55
MS		 1219 twl_i2c_read_u8(TWL4030_MODULE_INTBR, &temp, REG_GPPUPDCTR1);
1220 temp &= ~(SR_I2C_SDA_CTRL_PU | SR_I2C_SCL_CTRL_PU | \
ec1a07b3 1221 I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
a29aaf55 1222 twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1);
a613b739
TL		 1223
1224 twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
1225 TWL4030_DCDC_GLOBAL_CFG);
1226 temp |= SMARTREFLEX_ENABLE;
1227 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
1228 TWL4030_DCDC_GLOBAL_CFG);
a29aaf55
MS		 1229 }
1230
80ec831e
TL		 1231 if (node) {
1232 if (pdata)
1233 twl_auxdata_lookup[0].platform_data = pdata->gpio;
1234 status = of_platform_populate(node, NULL, twl_auxdata_lookup,
1235 &client->dev);
1236 } else {
9e178620 1237 status = add_children(pdata, irq_base, id->driver_data);
80ec831e 1238 }
aeb5032b 1239
a603a7fa
DB		 1240fail:
1241 if (status < 0)
fc7b92fc 1242 twl_remove(client);
defa6be1
TL		 1243free:
1244 if (status < 0)
1245 platform_device_unregister(pdev);
ec1a07b3 1246
a603a7fa
DB		 1247 return status;
1248}
1249
fc7b92fc 1250static const struct i2c_device_id twl_ids[] = {
dad759ff
DB		 1251 { "twl4030", TWL4030_VAUX2 }, /* "Triton 2" */
1252 { "twl5030", 0 }, /* T2 updated */
1920a61e 1253 { "twl5031", TWL5031 }, /* TWL5030 updated */
dad759ff
DB		 1254 { "tps65950", 0 }, /* catalog version of twl5030 */
1255 { "tps65930", TPS_SUBSET }, /* fewer LDOs and DACs; no charger */
1256 { "tps65920", TPS_SUBSET }, /* fewer LDOs; no codec or charger */
59dead5a
OD		 1257 { "tps65921", TPS_SUBSET }, /* fewer LDOs; no codec, no LED
1258 and vibrator. Charger in USB module*/
e8deb28c 1259 { "twl6030", TWL6030_CLASS }, /* "Phoenix power chip" */
89ce43fb 1260 { "twl6032", TWL6030_CLASS | TWL6032_SUBCLASS }, /* "Phoenix lite" */
a603a7fa
DB		 1261 { /* end of list */ },
1262};
fc7b92fc 1263MODULE_DEVICE_TABLE(i2c, twl_ids);
a603a7fa
DB		 1264
1265/* One Client Driver , 4 Clients */
fc7b92fc 1266static struct i2c_driver twl_driver = {
a603a7fa 1267 .driver.name = DRIVER_NAME,
fc7b92fc
B		 1268 .id_table = twl_ids,
1269 .probe = twl_probe,
1270 .remove = twl_remove,
a603a7fa
DB		 1271};
1272
032fa16d 1273module_i2c_driver(twl_driver);
a603a7fa
DB		 1274
1275MODULE_AUTHOR("Texas Instruments, Inc.");
fc7b92fc 1276MODULE_DESCRIPTION("I2C Core interface for TWL");
a603a7fa 1277MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)