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libceph: move r_reply_op_{len,result} into struct ceph_osd_req_op
[linux-2.6-block.git] / drivers / mfd / sm501.c
CommitLineData
b6d6454f
BD		 1/* linux/drivers/mfd/sm501.c
2 *
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * Vincent Sanders <vince@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * SM501 MFD driver
12*/
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/list.h>
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/pci.h>
42cd2366 22#include <linux/i2c-gpio.h>
5a0e3ad6 23#include <linux/slab.h>
b6d6454f
BD		 24
25#include <linux/sm501.h>
26#include <linux/sm501-regs.h>
61711f8f 27#include <linux/serial_8250.h>
b6d6454f 28
f77401d4 29#include <linux/io.h>
b6d6454f
BD		 30
31struct sm501_device {
32 struct list_head list;
33 struct platform_device pdev;
34};
35
f61be273
BD		 36struct sm501_gpio;
37
f2999209
BD		 38#ifdef CONFIG_MFD_SM501_GPIO
39#include <linux/gpio.h>
40
f61be273
BD		 41struct sm501_gpio_chip {
42 struct gpio_chip gpio;
43 struct sm501_gpio *ourgpio; /* to get back to parent. */
44 void __iomem *regbase;
98325f8f 45 void __iomem *control; /* address of control reg. */
f61be273
BD		 46};
47
48struct sm501_gpio {
49 struct sm501_gpio_chip low;
50 struct sm501_gpio_chip high;
51 spinlock_t lock;
52
53 unsigned int registered : 1;
54 void __iomem *regs;
55 struct resource *regs_res;
56};
f2999209
BD		 57#else
58struct sm501_gpio {
59 /* no gpio support, empty definition for sm501_devdata. */
60};
61#endif
f61be273 62
b6d6454f
BD		 63struct sm501_devdata {
64 spinlock_t reg_lock;
65 struct mutex clock_lock;
66 struct list_head devices;
f61be273 67 struct sm501_gpio gpio;
b6d6454f
BD		 68
69 struct device *dev;
70 struct resource *io_res;
71 struct resource *mem_res;
72 struct resource *regs_claim;
73 struct sm501_platdata *platdata;
74
f61be273 75
331d7475
BD		 76 unsigned int in_suspend;
77 unsigned long pm_misc;
78
b6d6454f
BD		 79 int unit_power[20];
80 unsigned int pdev_id;
81 unsigned int irq;
82 void __iomem *regs;
3149be50 83 unsigned int rev;
b6d6454f
BD		 84};
85
f61be273 86
b6d6454f
BD		 87#define MHZ (1000 * 1000)
88
89#ifdef DEBUG
245904a4 90static const unsigned int div_tab[] = {
b6d6454f
BD		 91 [0] = 1,
92 [1] = 2,
93 [2] = 4,
94 [3] = 8,
95 [4] = 16,
96 [5] = 32,
97 [6] = 64,
98 [7] = 128,
99 [8] = 3,
100 [9] = 6,
101 [10] = 12,
102 [11] = 24,
103 [12] = 48,
104 [13] = 96,
105 [14] = 192,
106 [15] = 384,
107 [16] = 5,
108 [17] = 10,
109 [18] = 20,
110 [19] = 40,
111 [20] = 80,
112 [21] = 160,
113 [22] = 320,
114 [23] = 604,
115};
116
117static unsigned long decode_div(unsigned long pll2, unsigned long val,
118 unsigned int lshft, unsigned int selbit,
245904a4 119 unsigned long mask)
b6d6454f
BD		 120{
121 if (val & selbit)
122 pll2 = 288 * MHZ;
123
245904a4 124 return pll2 / div_tab[(val >> lshft) & mask];
b6d6454f
BD		 125}
126
127#define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
128
129/* sm501_dump_clk
130 *
131 * Print out the current clock configuration for the device
132*/
133
134static void sm501_dump_clk(struct sm501_devdata *sm)
135{
bf5f0019
HS		 136 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING);
137 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
138 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
139 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
b6d6454f
BD		 140 unsigned long sdclk0, sdclk1;
141 unsigned long pll2 = 0;
142
143 switch (misct & 0x30) {
144 case 0x00:
145 pll2 = 336 * MHZ;
146 break;
147 case 0x10:
148 pll2 = 288 * MHZ;
149 break;
150 case 0x20:
151 pll2 = 240 * MHZ;
152 break;
153 case 0x30:
154 pll2 = 192 * MHZ;
155 break;
156 }
157
158 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
245904a4 159 sdclk0 /= div_tab[((misct >> 8) & 0xf)];
b6d6454f
BD		 160
161 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
245904a4 162 sdclk1 /= div_tab[((misct >> 16) & 0xf)];
b6d6454f
BD		 163
164 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
165 misct, pm0, pm1);
166
167 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
168 fmt_freq(pll2), sdclk0, sdclk1);
169
170 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
171
172 dev_dbg(sm->dev, "PM0[%c]: "
173 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
48986f06 174 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
b6d6454f 175 (pmc & 3 ) == 0 ? '*' : '-',
245904a4
VS		 176 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
177 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
178 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)),
179 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15)));
b6d6454f
BD		 180
181 dev_dbg(sm->dev, "PM1[%c]: "
182 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
183 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
184 (pmc & 3 ) == 1 ? '*' : '-',
245904a4
VS		 185 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
186 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
187 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)),
188 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15)));
b6d6454f 189}
331d7475
BD		 190
191static void sm501_dump_regs(struct sm501_devdata *sm)
192{
193 void __iomem *regs = sm->regs;
194
195 dev_info(sm->dev, "System Control %08x\n",
bf5f0019 196 smc501_readl(regs + SM501_SYSTEM_CONTROL));
331d7475 197 dev_info(sm->dev, "Misc Control %08x\n",
bf5f0019 198 smc501_readl(regs + SM501_MISC_CONTROL));
331d7475 199 dev_info(sm->dev, "GPIO Control Low %08x\n",
bf5f0019 200 smc501_readl(regs + SM501_GPIO31_0_CONTROL));
331d7475 201 dev_info(sm->dev, "GPIO Control Hi %08x\n",
bf5f0019 202 smc501_readl(regs + SM501_GPIO63_32_CONTROL));
331d7475 203 dev_info(sm->dev, "DRAM Control %08x\n",
bf5f0019 204 smc501_readl(regs + SM501_DRAM_CONTROL));
331d7475 205 dev_info(sm->dev, "Arbitration Ctrl %08x\n",
bf5f0019 206 smc501_readl(regs + SM501_ARBTRTN_CONTROL));
331d7475 207 dev_info(sm->dev, "Misc Timing %08x\n",
bf5f0019 208 smc501_readl(regs + SM501_MISC_TIMING));
331d7475
BD		 209}
210
211static void sm501_dump_gate(struct sm501_devdata *sm)
b6d6454f 212{
331d7475 213 dev_info(sm->dev, "CurrentGate %08x\n",
bf5f0019 214 smc501_readl(sm->regs + SM501_CURRENT_GATE));
331d7475 215 dev_info(sm->dev, "CurrentClock %08x\n",
bf5f0019 216 smc501_readl(sm->regs + SM501_CURRENT_CLOCK));
331d7475 217 dev_info(sm->dev, "PowerModeControl %08x\n",
bf5f0019 218 smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL));
b6d6454f 219}
331d7475
BD		 220
221#else
222static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
223static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
224static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
b6d6454f
BD		 225#endif
226
227/* sm501_sync_regs
228 *
229 * ensure the
230*/
231
232static void sm501_sync_regs(struct sm501_devdata *sm)
233{
bf5f0019 234 smc501_readl(sm->regs);
b6d6454f
BD		 235}
236
331d7475
BD		 237static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
238{
239 /* during suspend/resume, we are currently not allowed to sleep,
240 * so change to using mdelay() instead of msleep() if we
241 * are in one of these paths */
242
243 if (sm->in_suspend)
244 mdelay(delay);
245 else
246 msleep(delay);
247}
248
b6d6454f
BD		 249/* sm501_misc_control
250 *
331d7475 251 * alters the miscellaneous control parameters
b6d6454f
BD		 252*/
253
254int sm501_misc_control(struct device *dev,
255 unsigned long set, unsigned long clear)
256{
257 struct sm501_devdata *sm = dev_get_drvdata(dev);
258 unsigned long misc;
259 unsigned long save;
260 unsigned long to;
261
262 spin_lock_irqsave(&sm->reg_lock, save);
263
bf5f0019 264 misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
b6d6454f
BD		 265 to = (misc & ~clear) | set;
266
267 if (to != misc) {
bf5f0019 268 smc501_writel(to, sm->regs + SM501_MISC_CONTROL);
b6d6454f
BD		 269 sm501_sync_regs(sm);
270
271 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
272 }
273
274 spin_unlock_irqrestore(&sm->reg_lock, save);
275 return to;
276}
277
278EXPORT_SYMBOL_GPL(sm501_misc_control);
279
280/* sm501_modify_reg
281 *
282 * Modify a register in the SM501 which may be shared with other
283 * drivers.
284*/
285
286unsigned long sm501_modify_reg(struct device *dev,
287 unsigned long reg,
288 unsigned long set,
289 unsigned long clear)
290{
291 struct sm501_devdata *sm = dev_get_drvdata(dev);
292 unsigned long data;
293 unsigned long save;
294
295 spin_lock_irqsave(&sm->reg_lock, save);
296
bf5f0019 297 data = smc501_readl(sm->regs + reg);
b6d6454f
BD		 298 data |= set;
299 data &= ~clear;
300
bf5f0019 301 smc501_writel(data, sm->regs + reg);
b6d6454f
BD		 302 sm501_sync_regs(sm);
303
304 spin_unlock_irqrestore(&sm->reg_lock, save);
305
306 return data;
307}
308
309EXPORT_SYMBOL_GPL(sm501_modify_reg);
310
b6d6454f
BD		 311/* sm501_unit_power
312 *
313 * alters the power active gate to set specific units on or off
314 */
315
316int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
317{
318 struct sm501_devdata *sm = dev_get_drvdata(dev);
319 unsigned long mode;
320 unsigned long gate;
321 unsigned long clock;
322
323 mutex_lock(&sm->clock_lock);
324
bf5f0019
HS		 325 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
326 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
327 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
b6d6454f
BD		 328
329 mode &= 3; /* get current power mode */
330
bf703c3f 331 if (unit >= ARRAY_SIZE(sm->unit_power)) {
145980a0 332 dev_err(dev, "%s: bad unit %d\n", __func__, unit);
b6d6454f
BD		 333 goto already;
334 }
335
145980a0 336 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
b6d6454f
BD		 337 sm->unit_power[unit], to);
338
339 if (to == 0 && sm->unit_power[unit] == 0) {
340 dev_err(sm->dev, "unit %d is already shutdown\n", unit);
341 goto already;
342 }
343
344 sm->unit_power[unit] += to ? 1 : -1;
345 to = sm->unit_power[unit] ? 1 : 0;
346
347 if (to) {
348 if (gate & (1 << unit))
349 goto already;
350 gate |= (1 << unit);
351 } else {
352 if (!(gate & (1 << unit)))
353 goto already;
354 gate &= ~(1 << unit);
355 }
356
357 switch (mode) {
358 case 1:
bf5f0019
HS		 359 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
360 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
b6d6454f
BD		 361 mode = 0;
362 break;
363 case 2:
364 case 0:
bf5f0019
HS		 365 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
366 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
b6d6454f
BD		 367 mode = 1;
368 break;
369
370 default:
992bb253
JS		 371 gate = -1;
372 goto already;
b6d6454f
BD		 373 }
374
bf5f0019 375 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
b6d6454f
BD		 376 sm501_sync_regs(sm);
377
378 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
379 gate, clock, mode);
380
331d7475 381 sm501_mdelay(sm, 16);
b6d6454f
BD		 382
383 already:
384 mutex_unlock(&sm->clock_lock);
385 return gate;
386}
387
388EXPORT_SYMBOL_GPL(sm501_unit_power);
389
b6d6454f
BD		 390/* clock value structure. */
391struct sm501_clock {
392 unsigned long mclk;
393 int divider;
394 int shift;
3149be50 395 unsigned int m, n, k;
b6d6454f
BD		 396};
397
3149be50
VS		 398/* sm501_calc_clock
399 *
400 * Calculates the nearest discrete clock frequency that
401 * can be achieved with the specified input clock.
402 * the maximum divisor is 3 or 5
403 */
404
405static int sm501_calc_clock(unsigned long freq,
406 struct sm501_clock *clock,
407 int max_div,
408 unsigned long mclk,
409 long *best_diff)
410{
411 int ret = 0;
412 int divider;
413 int shift;
414 long diff;
415
416 /* try dividers 1 and 3 for CRT and for panel,
417 try divider 5 for panel only.*/
418
419 for (divider = 1; divider <= max_div; divider += 2) {
420 /* try all 8 shift values.*/
421 for (shift = 0; shift < 8; shift++) {
422 /* Calculate difference to requested clock */
829ecbcb 423 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
3149be50
VS		 424 if (diff < 0)
425 diff = -diff;
426
427 /* If it is less than the current, use it */
428 if (diff < *best_diff) {
429 *best_diff = diff;
430
431 clock->mclk = mclk;
432 clock->divider = divider;
433 clock->shift = shift;
434 ret = 1;
435 }
436 }
437 }
438
439 return ret;
440}
441
442/* sm501_calc_pll
443 *
444 * Calculates the nearest discrete clock frequency that can be
445 * achieved using the programmable PLL.
446 * the maximum divisor is 3 or 5
447 */
448
449static unsigned long sm501_calc_pll(unsigned long freq,
450 struct sm501_clock *clock,
451 int max_div)
452{
453 unsigned long mclk;
454 unsigned int m, n, k;
455 long best_diff = 999999999;
456
457 /*
458 * The SM502 datasheet doesn't specify the min/max values for M and N.
459 * N = 1 at least doesn't work in practice.
460 */
461 for (m = 2; m <= 255; m++) {
462 for (n = 2; n <= 127; n++) {
463 for (k = 0; k <= 1; k++) {
464 mclk = (24000000UL * m / n) >> k;
465
466 if (sm501_calc_clock(freq, clock, max_div,
467 mclk, &best_diff)) {
468 clock->m = m;
469 clock->n = n;
470 clock->k = k;
471 }
472 }
473 }
474 }
475
476 /* Return best clock. */
477 return clock->mclk / (clock->divider << clock->shift);
478}
479
b6d6454f
BD		 480/* sm501_select_clock
481 *
3149be50
VS		 482 * Calculates the nearest discrete clock frequency that can be
483 * achieved using the 288MHz and 336MHz PLLs.
b6d6454f
BD		 484 * the maximum divisor is 3 or 5
485 */
3149be50 486
b6d6454f
BD		 487static unsigned long sm501_select_clock(unsigned long freq,
488 struct sm501_clock *clock,
489 int max_div)
490{
491 unsigned long mclk;
b6d6454f
BD		 492 long best_diff = 999999999;
493
494 /* Try 288MHz and 336MHz clocks. */
495 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
3149be50 496 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
b6d6454f
BD		 497 }
498
499 /* Return best clock. */
500 return clock->mclk / (clock->divider << clock->shift);
501}
502
503/* sm501_set_clock
504 *
505 * set one of the four clock sources to the closest available frequency to
506 * the one specified
507*/
508
509unsigned long sm501_set_clock(struct device *dev,
510 int clksrc,
511 unsigned long req_freq)
512{
513 struct sm501_devdata *sm = dev_get_drvdata(dev);
bf5f0019
HS		 514 unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
515 unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
516 unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
3149be50 517 unsigned int pll_reg = 0;
3ad2f3fb 518 unsigned long sm501_freq; /* the actual frequency achieved */
5f114ebc 519 u64 reg;
b6d6454f
BD		 520
521 struct sm501_clock to;
522
523 /* find achivable discrete frequency and setup register value
524 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
525 * has an extra bit for the divider */
526
527 switch (clksrc) {
528 case SM501_CLOCK_P2XCLK:
3ad2f3fb 529 /* This clock is divided in half so to achieve the
b6d6454f
BD		 530 * requested frequency the value must be multiplied by
531 * 2. This clock also has an additional pre divisor */
532
3149be50
VS		 533 if (sm->rev >= 0xC0) {
534 /* SM502 -> use the programmable PLL */
535 sm501_freq = (sm501_calc_pll(2 * req_freq,
536 &to, 5) / 2);
537 reg = to.shift & 0x07;/* bottom 3 bits are shift */
538 if (to.divider == 3)
539 reg |= 0x08; /* /3 divider required */
540 else if (to.divider == 5)
541 reg |= 0x10; /* /5 divider required */
542 reg |= 0x40; /* select the programmable PLL */
543 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
544 } else {
545 sm501_freq = (sm501_select_clock(2 * req_freq,
546 &to, 5) / 2);
547 reg = to.shift & 0x07;/* bottom 3 bits are shift */
548 if (to.divider == 3)
549 reg |= 0x08; /* /3 divider required */
550 else if (to.divider == 5)
551 reg |= 0x10; /* /5 divider required */
552 if (to.mclk != 288000000)
553 reg |= 0x20; /* which mclk pll is source */
554 }
b6d6454f
BD		 555 break;
556
557 case SM501_CLOCK_V2XCLK:
3ad2f3fb 558 /* This clock is divided in half so to achieve the
b6d6454f
BD		 559 * requested frequency the value must be multiplied by 2. */
560
561 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
562 reg=to.shift & 0x07; /* bottom 3 bits are shift */
563 if (to.divider == 3)
564 reg |= 0x08; /* /3 divider required */
565 if (to.mclk != 288000000)
566 reg |= 0x10; /* which mclk pll is source */
567 break;
568
569 case SM501_CLOCK_MCLK:
570 case SM501_CLOCK_M1XCLK:
571 /* These clocks are the same and not further divided */
572
573 sm501_freq = sm501_select_clock( req_freq, &to, 3);
574 reg=to.shift & 0x07; /* bottom 3 bits are shift */
575 if (to.divider == 3)
576 reg |= 0x08; /* /3 divider required */
577 if (to.mclk != 288000000)
578 reg |= 0x10; /* which mclk pll is source */
579 break;
580
581 default:
582 return 0; /* this is bad */
583 }
584
585 mutex_lock(&sm->clock_lock);
586
bf5f0019
HS		 587 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
588 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
589 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
b6d6454f
BD		 590
591 clock = clock & ~(0xFF << clksrc);
592 clock |= reg<<clksrc;
593
594 mode &= 3; /* find current mode */
595
596 switch (mode) {
597 case 1:
bf5f0019
HS		 598 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
599 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
b6d6454f
BD		 600 mode = 0;
601 break;
602 case 2:
603 case 0:
bf5f0019
HS		 604 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
605 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
b6d6454f
BD		 606 mode = 1;
607 break;
608
609 default:
610 mutex_unlock(&sm->clock_lock);
611 return -1;
612 }
613
bf5f0019 614 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
3149be50
VS		 615
616 if (pll_reg)
bf5f0019
HS		 617 smc501_writel(pll_reg,
618 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
3149be50 619
b6d6454f
BD		 620 sm501_sync_regs(sm);
621
80e74a80
BD		 622 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
623 gate, clock, mode);
b6d6454f 624
331d7475 625 sm501_mdelay(sm, 16);
b6d6454f
BD		 626 mutex_unlock(&sm->clock_lock);
627
628 sm501_dump_clk(sm);
629
630 return sm501_freq;
631}
632
633EXPORT_SYMBOL_GPL(sm501_set_clock);
634
635/* sm501_find_clock
636 *
637 * finds the closest available frequency for a given clock
638*/
639
3149be50
VS		 640unsigned long sm501_find_clock(struct device *dev,
641 int clksrc,
b6d6454f
BD		 642 unsigned long req_freq)
643{
3149be50 644 struct sm501_devdata *sm = dev_get_drvdata(dev);
3ad2f3fb 645 unsigned long sm501_freq; /* the frequency achieveable by the 501 */
b6d6454f
BD		 646 struct sm501_clock to;
647
648 switch (clksrc) {
649 case SM501_CLOCK_P2XCLK:
3149be50
VS		 650 if (sm->rev >= 0xC0) {
651 /* SM502 -> use the programmable PLL */
652 sm501_freq = (sm501_calc_pll(2 * req_freq,
653 &to, 5) / 2);
654 } else {
655 sm501_freq = (sm501_select_clock(2 * req_freq,
656 &to, 5) / 2);
657 }
b6d6454f
BD		 658 break;
659
660 case SM501_CLOCK_V2XCLK:
661 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
662 break;
663
664 case SM501_CLOCK_MCLK:
665 case SM501_CLOCK_M1XCLK:
666 sm501_freq = sm501_select_clock(req_freq, &to, 3);
667 break;
668
669 default:
670 sm501_freq = 0; /* error */
671 }
672
673 return sm501_freq;
674}
675
676EXPORT_SYMBOL_GPL(sm501_find_clock);
677
678static struct sm501_device *to_sm_device(struct platform_device *pdev)
679{
680 return container_of(pdev, struct sm501_device, pdev);
681}
682
683/* sm501_device_release
684 *
685 * A release function for the platform devices we create to allow us to
686 * free any items we allocated
687*/
688
689static void sm501_device_release(struct device *dev)
690{
691 kfree(to_sm_device(to_platform_device(dev)));
692}
693
694/* sm501_create_subdev
695 *
696 * Create a skeleton platform device with resources for passing to a
697 * sub-driver
698*/
699
700static struct platform_device *
61711f8f
MD		 701sm501_create_subdev(struct sm501_devdata *sm, char *name,
702 unsigned int res_count, unsigned int platform_data_size)
b6d6454f
BD		 703{
704 struct sm501_device *smdev;
705
706 smdev = kzalloc(sizeof(struct sm501_device) +
61711f8f
MD		 707 (sizeof(struct resource) * res_count) +
708 platform_data_size, GFP_KERNEL);
b6d6454f
BD		 709 if (!smdev)
710 return NULL;
711
712 smdev->pdev.dev.release = sm501_device_release;
713
714 smdev->pdev.name = name;
715 smdev->pdev.id = sm->pdev_id;
b6d6454f
BD		 716 smdev->pdev.dev.parent = sm->dev;
717
61711f8f
MD		 718 if (res_count) {
719 smdev->pdev.resource = (struct resource *)(smdev+1);
720 smdev->pdev.num_resources = res_count;
721 }
722 if (platform_data_size)
723 smdev->pdev.dev.platform_data = (void *)(smdev+1);
724
b6d6454f
BD		 725 return &smdev->pdev;
726}
727
728/* sm501_register_device
729 *
730 * Register a platform device created with sm501_create_subdev()
731*/
732
733static int sm501_register_device(struct sm501_devdata *sm,
734 struct platform_device *pdev)
735{
736 struct sm501_device *smdev = to_sm_device(pdev);
737 int ptr;
738 int ret;
739
740 for (ptr = 0; ptr < pdev->num_resources; ptr++) {
3f3d4310
JP		 741 printk(KERN_DEBUG "%s[%d] %pR\n",
742 pdev->name, ptr, &pdev->resource[ptr]);
b6d6454f
BD		 743 }
744
745 ret = platform_device_register(pdev);
746
747 if (ret >= 0) {
748 dev_dbg(sm->dev, "registered %s\n", pdev->name);
749 list_add_tail(&smdev->list, &sm->devices);
750 } else
751 dev_err(sm->dev, "error registering %s (%d)\n",
752 pdev->name, ret);
753
754 return ret;
755}
756
757/* sm501_create_subio
758 *
759 * Fill in an IO resource for a sub device
760*/
761
762static void sm501_create_subio(struct sm501_devdata *sm,
763 struct resource *res,
764 resource_size_t offs,
765 resource_size_t size)
766{
767 res->flags = IORESOURCE_MEM;
768 res->parent = sm->io_res;
769 res->start = sm->io_res->start + offs;
770 res->end = res->start + size - 1;
771}
772
773/* sm501_create_mem
774 *
775 * Fill in an MEM resource for a sub device
776*/
777
778static void sm501_create_mem(struct sm501_devdata *sm,
779 struct resource *res,
780 resource_size_t *offs,
781 resource_size_t size)
782{
783 *offs -= size; /* adjust memory size */
784
785 res->flags = IORESOURCE_MEM;
786 res->parent = sm->mem_res;
787 res->start = sm->mem_res->start + *offs;
788 res->end = res->start + size - 1;
789}
790
791/* sm501_create_irq
792 *
793 * Fill in an IRQ resource for a sub device
794*/
795
796static void sm501_create_irq(struct sm501_devdata *sm,
797 struct resource *res)
798{
799 res->flags = IORESOURCE_IRQ;
800 res->parent = NULL;
801 res->start = res->end = sm->irq;
802}
803
804static int sm501_register_usbhost(struct sm501_devdata *sm,
805 resource_size_t *mem_avail)
806{
807 struct platform_device *pdev;
808
61711f8f 809 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
b6d6454f
BD		 810 if (!pdev)
811 return -ENOMEM;
812
813 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
814 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
815 sm501_create_irq(sm, &pdev->resource[2]);
816
817 return sm501_register_device(sm, pdev);
818}
819
61711f8f
MD		 820static void sm501_setup_uart_data(struct sm501_devdata *sm,
821 struct plat_serial8250_port *uart_data,
822 unsigned int offset)
823{
824 uart_data->membase = sm->regs + offset;
825 uart_data->mapbase = sm->io_res->start + offset;
826 uart_data->iotype = UPIO_MEM;
827 uart_data->irq = sm->irq;
828 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
829 uart_data->regshift = 2;
830 uart_data->uartclk = (9600 * 16);
831}
832
833static int sm501_register_uart(struct sm501_devdata *sm, int devices)
834{
835 struct platform_device *pdev;
836 struct plat_serial8250_port *uart_data;
837
838 pdev = sm501_create_subdev(sm, "serial8250", 0,
839 sizeof(struct plat_serial8250_port) * 3);
840 if (!pdev)
841 return -ENOMEM;
842
334a41ce 843 uart_data = dev_get_platdata(&pdev->dev);
61711f8f
MD		 844
845 if (devices & SM501_USE_UART0) {
846 sm501_setup_uart_data(sm, uart_data++, 0x30000);
847 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
848 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
849 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
850 }
851 if (devices & SM501_USE_UART1) {
852 sm501_setup_uart_data(sm, uart_data++, 0x30020);
853 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
854 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
855 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
856 }
857
858 pdev->id = PLAT8250_DEV_SM501;
859
860 return sm501_register_device(sm, pdev);
861}
862
b6d6454f
BD		 863static int sm501_register_display(struct sm501_devdata *sm,
864 resource_size_t *mem_avail)
865{
866 struct platform_device *pdev;
867
61711f8f 868 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
b6d6454f
BD		 869 if (!pdev)
870 return -ENOMEM;
871
872 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
873 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
874 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
875 sm501_create_irq(sm, &pdev->resource[3]);
876
877 return sm501_register_device(sm, pdev);
878}
879
f61be273
BD		 880#ifdef CONFIG_MFD_SM501_GPIO
881
882static inline struct sm501_gpio_chip *to_sm501_gpio(struct gpio_chip *gc)
883{
884 return container_of(gc, struct sm501_gpio_chip, gpio);
885}
886
887static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
888{
889 return container_of(gpio, struct sm501_devdata, gpio);
890}
891
892static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
893
894{
895 struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip);
896 unsigned long result;
897
bf5f0019 898 result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
f61be273
BD		 899 result >>= offset;
900
901 return result & 1UL;
902}
903
98325f8f
BD		 904static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,
905 unsigned long bit)
906{
907 unsigned long ctrl;
908
909 /* check and modify if this pin is not set as gpio. */
910
bf5f0019 911 if (smc501_readl(smchip->control) & bit) {
98325f8f
BD		 912 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
913 "changing mode of gpio, bit %08lx\n", bit);
914
bf5f0019 915 ctrl = smc501_readl(smchip->control);
98325f8f 916 ctrl &= ~bit;
bf5f0019 917 smc501_writel(ctrl, smchip->control);
98325f8f
BD		 918
919 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
920 }
921}
922
f61be273
BD		 923static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
924
925{
926 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
927 struct sm501_gpio *smgpio = smchip->ourgpio;
928 unsigned long bit = 1 << offset;
929 void __iomem *regs = smchip->regbase;
930 unsigned long save;
931 unsigned long val;
932
933 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
934 __func__, chip, offset);
935
936 spin_lock_irqsave(&smgpio->lock, save);
937
bf5f0019 938 val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
f61be273
BD		 939 if (value)
940 val |= bit;
bf5f0019 941 smc501_writel(val, regs);
f61be273
BD		 942
943 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
98325f8f
BD		 944 sm501_gpio_ensure_gpio(smchip, bit);
945
f61be273
BD		 946 spin_unlock_irqrestore(&smgpio->lock, save);
947}
948
949static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
950{
951 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
952 struct sm501_gpio *smgpio = smchip->ourgpio;
953 void __iomem *regs = smchip->regbase;
954 unsigned long bit = 1 << offset;
955 unsigned long save;
956 unsigned long ddr;
957
98325f8f
BD		 958 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
959 __func__, chip, offset);
f61be273
BD		 960
961 spin_lock_irqsave(&smgpio->lock, save);
962
bf5f0019
HS		 963 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
964 smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
f61be273
BD		 965
966 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
98325f8f
BD		 967 sm501_gpio_ensure_gpio(smchip, bit);
968
f61be273
BD		 969 spin_unlock_irqrestore(&smgpio->lock, save);
970
971 return 0;
972}
973
974static int sm501_gpio_output(struct gpio_chip *chip,
975 unsigned offset, int value)
976{
977 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
978 struct sm501_gpio *smgpio = smchip->ourgpio;
979 unsigned long bit = 1 << offset;
980 void __iomem *regs = smchip->regbase;
981 unsigned long save;
982 unsigned long val;
983 unsigned long ddr;
984
985 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
986 __func__, chip, offset, value);
987
988 spin_lock_irqsave(&smgpio->lock, save);
989
bf5f0019 990 val = smc501_readl(regs + SM501_GPIO_DATA_LOW);
f61be273
BD		 991 if (value)
992 val |= bit;
993 else
994 val &= ~bit;
bf5f0019 995 smc501_writel(val, regs);
f61be273 996
bf5f0019
HS		 997 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
998 smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
f61be273
BD		 999
1000 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
bf5f0019 1001 smc501_writel(val, regs + SM501_GPIO_DATA_LOW);
f61be273
BD		 1002
1003 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
1004 spin_unlock_irqrestore(&smgpio->lock, save);
1005
1006 return 0;
1007}
1008
1009static struct gpio_chip gpio_chip_template = {
1010 .ngpio = 32,
1011 .direction_input = sm501_gpio_input,
1012 .direction_output = sm501_gpio_output,
1013 .set = sm501_gpio_set,
1014 .get = sm501_gpio_get,
1015};
1016
f791be49 1017static int sm501_gpio_register_chip(struct sm501_devdata *sm,
f61be273
BD		 1018 struct sm501_gpio *gpio,
1019 struct sm501_gpio_chip *chip)
1020{
1021 struct sm501_platdata *pdata = sm->platdata;
1022 struct gpio_chip *gchip = &chip->gpio;
60e540d6 1023 int base = pdata->gpio_base;
f61be273 1024
28130bea 1025 chip->gpio = gpio_chip_template;
f61be273
BD		 1026
1027 if (chip == &gpio->high) {
60e540d6
AP		 1028 if (base > 0)
1029 base += 32;
f61be273 1030 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
98325f8f 1031 chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
f61be273
BD		 1032 gchip->label = "SM501-HIGH";
1033 } else {
1034 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
98325f8f 1035 chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
f61be273
BD		 1036 gchip->label = "SM501-LOW";
1037 }
1038
1039 gchip->base = base;
1040 chip->ourgpio = gpio;
1041
1042 return gpiochip_add(gchip);
1043}
1044
f791be49 1045static int sm501_register_gpio(struct sm501_devdata *sm)
f61be273
BD		 1046{
1047 struct sm501_gpio *gpio = &sm->gpio;
1048 resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1049 int ret;
f61be273
BD		 1050
1051 dev_dbg(sm->dev, "registering gpio block %08llx\n",
1052 (unsigned long long)iobase);
1053
1054 spin_lock_init(&gpio->lock);
1055
1056 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1057 if (gpio->regs_res == NULL) {
1058 dev_err(sm->dev, "gpio: failed to request region\n");
1059 return -ENXIO;
1060 }
1061
1062 gpio->regs = ioremap(iobase, 0x20);
1063 if (gpio->regs == NULL) {
1064 dev_err(sm->dev, "gpio: failed to remap registers\n");
1065 ret = -ENXIO;
28130bea 1066 goto err_claimed;
f61be273
BD		 1067 }
1068
1069 /* Register both our chips. */
1070
1071 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1072 if (ret) {
1073 dev_err(sm->dev, "failed to add low chip\n");
1074 goto err_mapped;
1075 }
1076
1077 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1078 if (ret) {
1079 dev_err(sm->dev, "failed to add high chip\n");
1080 goto err_low_chip;
1081 }
1082
1083 gpio->registered = 1;
1084
1085 return 0;
1086
1087 err_low_chip:
88d5e520 1088 gpiochip_remove(&gpio->low.gpio);
f61be273
BD		 1089
1090 err_mapped:
28130bea
BD		 1091 iounmap(gpio->regs);
1092
1093 err_claimed:
f61be273
BD		 1094 release_resource(gpio->regs_res);
1095 kfree(gpio->regs_res);
1096
1097 return ret;
1098}
1099
1100static void sm501_gpio_remove(struct sm501_devdata *sm)
1101{
28130bea 1102 struct sm501_gpio *gpio = &sm->gpio;
f61be273 1103
f2999209
BD		 1104 if (!sm->gpio.registered)
1105 return;
1106
88d5e520 1107 gpiochip_remove(&gpio->low.gpio);
1108 gpiochip_remove(&gpio->high.gpio);
28130bea
BD		 1109
1110 iounmap(gpio->regs);
1111 release_resource(gpio->regs_res);
1112 kfree(gpio->regs_res);
f61be273
BD		 1113}
1114
28130bea 1115static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
42cd2366
BD		 1116{
1117 struct sm501_gpio *gpio = &sm->gpio;
53a9600c
BD		 1118 int base = (pin < 32) ? gpio->low.gpio.base : gpio->high.gpio.base;
1119
1120 return (pin % 32) + base;
42cd2366 1121}
f2999209
BD		 1122
1123static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1124{
1125 return sm->gpio.registered;
1126}
f61be273 1127#else
28130bea 1128static inline int sm501_register_gpio(struct sm501_devdata *sm)
f61be273
BD		 1129{
1130 return 0;
1131}
1132
28130bea 1133static inline void sm501_gpio_remove(struct sm501_devdata *sm)
f61be273
BD		 1134{
1135}
42cd2366 1136
28130bea 1137static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
42cd2366
BD		 1138{
1139 return -1;
1140}
f2999209
BD		 1141
1142static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1143{
1144 return 0;
1145}
f61be273
BD		 1146#endif
1147
42cd2366
BD		 1148static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
1149 struct sm501_platdata_gpio_i2c *iic)
1150{
1151 struct i2c_gpio_platform_data *icd;
1152 struct platform_device *pdev;
1153
1154 pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
1155 sizeof(struct i2c_gpio_platform_data));
1156 if (!pdev)
1157 return -ENOMEM;
1158
334a41ce 1159 icd = dev_get_platdata(&pdev->dev);
42cd2366
BD		 1160
1161 /* We keep the pin_sda and pin_scl fields relative in case the
1162 * same platform data is passed to >1 SM501.
1163 */
1164
1165 icd->sda_pin = sm501_gpio_pin2nr(sm, iic->pin_sda);
1166 icd->scl_pin = sm501_gpio_pin2nr(sm, iic->pin_scl);
1167 icd->timeout = iic->timeout;
1168 icd->udelay = iic->udelay;
1169
1170 /* note, we can't use either of the pin numbers, as the i2c-gpio
1171 * driver uses the platform.id field to generate the bus number
1172 * to register with the i2c core; The i2c core doesn't have enough
1173 * entries to deal with anything we currently use.
1174 */
1175
1176 pdev->id = iic->bus_num;
1177
1178 dev_info(sm->dev, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n",
1179 iic->bus_num,
1180 icd->sda_pin, iic->pin_sda, icd->scl_pin, iic->pin_scl);
1181
1182 return sm501_register_device(sm, pdev);
1183}
1184
1185static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
1186 struct sm501_platdata *pdata)
1187{
1188 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
1189 int index;
1190 int ret;
1191
1192 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
1193 ret = sm501_register_gpio_i2c_instance(sm, iic);
1194 if (ret < 0)
1195 return ret;
1196 }
1197
1198 return 0;
1199}
1200
b6d6454f
BD		 1201/* sm501_dbg_regs
1202 *
1203 * Debug attribute to attach to parent device to show core registers
1204*/
1205
1206static ssize_t sm501_dbg_regs(struct device *dev,
1207 struct device_attribute *attr, char *buff)
1208{
1209 struct sm501_devdata *sm = dev_get_drvdata(dev) ;
1210 unsigned int reg;
1211 char *ptr = buff;
1212 int ret;
1213
1214 for (reg = 0x00; reg < 0x70; reg += 4) {
1215 ret = sprintf(ptr, "%08x = %08x\n",
bf5f0019 1216 reg, smc501_readl(sm->regs + reg));
b6d6454f
BD		 1217 ptr += ret;
1218 }
1219
1220 return ptr - buff;
1221}
1222
1223
8a8320c2 1224static DEVICE_ATTR(dbg_regs, 0444, sm501_dbg_regs, NULL);
b6d6454f
BD		 1225
1226/* sm501_init_reg
1227 *
1228 * Helper function for the init code to setup a register
5136237b
BD		 1229 *
1230 * clear the bits which are set in r->mask, and then set
1231 * the bits set in r->set.
b6d6454f
BD		 1232*/
1233
1234static inline void sm501_init_reg(struct sm501_devdata *sm,
1235 unsigned long reg,
1236 struct sm501_reg_init *r)
1237{
1238 unsigned long tmp;
1239
bf5f0019 1240 tmp = smc501_readl(sm->regs + reg);
b6d6454f 1241 tmp &= ~r->mask;
5136237b 1242 tmp |= r->set;
bf5f0019 1243 smc501_writel(tmp, sm->regs + reg);
b6d6454f
BD		 1244}
1245
1246/* sm501_init_regs
1247 *
1248 * Setup core register values
1249*/
1250
1251static void sm501_init_regs(struct sm501_devdata *sm,
1252 struct sm501_initdata *init)
1253{
1254 sm501_misc_control(sm->dev,
1255 init->misc_control.set,
1256 init->misc_control.mask);
1257
1258 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1259 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1260 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1261
b6d6454f
BD		 1262 if (init->m1xclk) {
1263 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1264 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1265 }
b5913bbd
BD		 1266
1267 if (init->mclk) {
1268 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1269 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1270 }
81906221
BD		 1271
1272}
1273
1274/* Check the PLL sources for the M1CLK and M1XCLK
1275 *
1276 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1277 * there is a risk (see errata AB-5) that the SM501 will cease proper
1278 * function. If this happens, then it is likely the SM501 will
1279 * hang the system.
1280*/
1281
1282static int sm501_check_clocks(struct sm501_devdata *sm)
1283{
bf5f0019 1284 unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
81906221
BD		 1285 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1286 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1287
1288 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
b6d6454f
BD		 1289}
1290
1291static unsigned int sm501_mem_local[] = {
1292 [0] = 4*1024*1024,
1293 [1] = 8*1024*1024,
1294 [2] = 16*1024*1024,
1295 [3] = 32*1024*1024,
1296 [4] = 64*1024*1024,
1297 [5] = 2*1024*1024,
1298};
1299
1300/* sm501_init_dev
1301 *
1302 * Common init code for an SM501
1303*/
1304
f791be49 1305static int sm501_init_dev(struct sm501_devdata *sm)
b6d6454f 1306{
61711f8f 1307 struct sm501_initdata *idata;
42cd2366 1308 struct sm501_platdata *pdata;
b6d6454f
BD		 1309 resource_size_t mem_avail;
1310 unsigned long dramctrl;
1e27dbe7 1311 unsigned long devid;
b6d6454f
BD		 1312 int ret;
1313
1314 mutex_init(&sm->clock_lock);
1315 spin_lock_init(&sm->reg_lock);
1316
1317 INIT_LIST_HEAD(&sm->devices);
1318
bf5f0019 1319 devid = smc501_readl(sm->regs + SM501_DEVICEID);
b6d6454f 1320
1e27dbe7
BD		 1321 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1322 dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1323 return -EINVAL;
1324 }
1325
61711f8f 1326 /* disable irqs */
bf5f0019 1327 smc501_writel(0, sm->regs + SM501_IRQ_MASK);
61711f8f 1328
bf5f0019 1329 dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL);
b6d6454f
BD		 1330 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1331
1e27dbe7
BD		 1332 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1333 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
b6d6454f 1334
3149be50
VS		 1335 sm->rev = devid & SM501_DEVICEID_REVMASK;
1336
331d7475 1337 sm501_dump_gate(sm);
b6d6454f
BD		 1338
1339 ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1340 if (ret)
1341 dev_err(sm->dev, "failed to create debug regs file\n");
1342
1343 sm501_dump_clk(sm);
1344
1345 /* check to see if we have some device initialisation */
1346
42cd2366
BD		 1347 pdata = sm->platdata;
1348 idata = pdata ? pdata->init : NULL;
1349
61711f8f
MD		 1350 if (idata) {
1351 sm501_init_regs(sm, idata);
b6d6454f 1352
61711f8f
MD		 1353 if (idata->devices & SM501_USE_USB_HOST)
1354 sm501_register_usbhost(sm, &mem_avail);
1355 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1356 sm501_register_uart(sm, idata->devices);
f61be273
BD		 1357 if (idata->devices & SM501_USE_GPIO)
1358 sm501_register_gpio(sm);
b6d6454f
BD		 1359 }
1360
4295f9bf 1361 if (pdata && pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) {
f2999209
BD		 1362 if (!sm501_gpio_isregistered(sm))
1363 dev_err(sm->dev, "no gpio available for i2c gpio.\n");
42cd2366
BD		 1364 else
1365 sm501_register_gpio_i2c(sm, pdata);
1366 }
1367
81906221
BD		 1368 ret = sm501_check_clocks(sm);
1369 if (ret) {
1370 dev_err(sm->dev, "M1X and M clocks sourced from different "
1371 "PLLs\n");
1372 return -EINVAL;
1373 }
1374
b6d6454f
BD		 1375 /* always create a framebuffer */
1376 sm501_register_display(sm, &mem_avail);
1377
1378 return 0;
1379}
1380
f791be49 1381static int sm501_plat_probe(struct platform_device *dev)
b6d6454f
BD		 1382{
1383 struct sm501_devdata *sm;
7cf5244c 1384 int ret;
b6d6454f
BD		 1385
1386 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1387 if (sm == NULL) {
1388 dev_err(&dev->dev, "no memory for device data\n");
7cf5244c 1389 ret = -ENOMEM;
b6d6454f
BD		 1390 goto err1;
1391 }
1392
1393 sm->dev = &dev->dev;
1394 sm->pdev_id = dev->id;
334a41ce 1395 sm->platdata = dev_get_platdata(&dev->dev);
b6d6454f 1396
7cf5244c
RK		 1397 ret = platform_get_irq(dev, 0);
1398 if (ret < 0) {
b6d6454f 1399 dev_err(&dev->dev, "failed to get irq resource\n");
b6d6454f
BD		 1400 goto err_res;
1401 }
7cf5244c 1402 sm->irq = ret;
b6d6454f 1403
7cf5244c
RK		 1404 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1405 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
4295f9bf 1406
b6d6454f
BD		 1407 if (sm->io_res == NULL || sm->mem_res == NULL) {
1408 dev_err(&dev->dev, "failed to get IO resource\n");
7cf5244c 1409 ret = -ENOENT;
b6d6454f
BD		 1410 goto err_res;
1411 }
1412
1413 sm->regs_claim = request_mem_region(sm->io_res->start,
a5300dcb 1414 0x100, "sm501");
b6d6454f
BD		 1415
1416 if (sm->regs_claim == NULL) {
1417 dev_err(&dev->dev, "cannot claim registers\n");
7cf5244c 1418 ret = -EBUSY;
b6d6454f
BD		 1419 goto err_res;
1420 }
1421
1422 platform_set_drvdata(dev, sm);
1423
311e54c0 1424 sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
b6d6454f
BD		 1425
1426 if (sm->regs == NULL) {
1427 dev_err(&dev->dev, "cannot remap registers\n");
7cf5244c 1428 ret = -EIO;
b6d6454f
BD		 1429 goto err_claim;
1430 }
1431
1432 return sm501_init_dev(sm);
1433
1434 err_claim:
1435 release_resource(sm->regs_claim);
1436 kfree(sm->regs_claim);
1437 err_res:
1438 kfree(sm);
1439 err1:
7cf5244c 1440 return ret;
b6d6454f
BD		 1441
1442}
1443
331d7475 1444#ifdef CONFIG_PM
472dba7d 1445
331d7475
BD		 1446/* power management support */
1447
472dba7d
BD		 1448static void sm501_set_power(struct sm501_devdata *sm, int on)
1449{
1450 struct sm501_platdata *pd = sm->platdata;
1451
1452 if (pd == NULL)
1453 return;
1454
1455 if (pd->get_power) {
1456 if (pd->get_power(sm->dev) == on) {
1457 dev_dbg(sm->dev, "is already %d\n", on);
1458 return;
1459 }
1460 }
1461
1462 if (pd->set_power) {
1463 dev_dbg(sm->dev, "setting power to %d\n", on);
1464
1465 pd->set_power(sm->dev, on);
1466 sm501_mdelay(sm, 10);
1467 }
1468}
1469
331d7475
BD		 1470static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1471{
1472 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1473
1474 sm->in_suspend = 1;
bf5f0019 1475 sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
331d7475
BD		 1476
1477 sm501_dump_regs(sm);
472dba7d
BD		 1478
1479 if (sm->platdata) {
1480 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1481 sm501_set_power(sm, 0);
1482 }
1483
331d7475
BD		 1484 return 0;
1485}
1486
1487static int sm501_plat_resume(struct platform_device *pdev)
1488{
1489 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1490
472dba7d
BD		 1491 sm501_set_power(sm, 1);
1492
331d7475
BD		 1493 sm501_dump_regs(sm);
1494 sm501_dump_gate(sm);
1495 sm501_dump_clk(sm);
1496
1497 /* check to see if we are in the same state as when suspended */
1498
bf5f0019 1499 if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
331d7475 1500 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
bf5f0019 1501 smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
331d7475
BD		 1502
1503 /* our suspend causes the controller state to change,
1504 * either by something attempting setup, power loss,
1505 * or an external reset event on power change */
1506
1507 if (sm->platdata && sm->platdata->init) {
1508 sm501_init_regs(sm, sm->platdata->init);
1509 }
1510 }
1511
1512 /* dump our state from resume */
1513
1514 sm501_dump_regs(sm);
1515 sm501_dump_clk(sm);
1516
1517 sm->in_suspend = 0;
1518
1519 return 0;
1520}
1521#else
1522#define sm501_plat_suspend NULL
1523#define sm501_plat_resume NULL
1524#endif
1525
b6d6454f
BD		 1526/* Initialisation data for PCI devices */
1527
1528static struct sm501_initdata sm501_pci_initdata = {
1529 .gpio_high = {
1530 .set = 0x3F000000, /* 24bit panel */
1531 .mask = 0x0,
1532 },
1533 .misc_timing = {
1534 .set = 0x010100, /* SDRAM timing */
1535 .mask = 0x1F1F00,
1536 },
1537 .misc_control = {
1538 .set = SM501_MISC_PNL_24BIT,
1539 .mask = 0,
1540 },
1541
1542 .devices = SM501_USE_ALL,
81906221
BD		 1543
1544 /* Errata AB-3 says that 72MHz is the fastest available
1545 * for 33MHZ PCI with proper bus-mastering operation */
1546
1547 .mclk = 72 * MHZ,
1548 .m1xclk = 144 * MHZ,
b6d6454f
BD		 1549};
1550
1551static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1552 .flags = (SM501FB_FLAG_USE_INIT_MODE |
1553 SM501FB_FLAG_USE_HWCURSOR |
1554 SM501FB_FLAG_USE_HWACCEL |
1555 SM501FB_FLAG_DISABLE_AT_EXIT),
1556};
1557
1558static struct sm501_platdata_fb sm501_fb_pdata = {
1559 .fb_route = SM501_FB_OWN,
1560 .fb_crt = &sm501_pdata_fbsub,
1561 .fb_pnl = &sm501_pdata_fbsub,
1562};
1563
1564static struct sm501_platdata sm501_pci_platdata = {
1565 .init = &sm501_pci_initdata,
1566 .fb = &sm501_fb_pdata,
60e540d6 1567 .gpio_base = -1,
b6d6454f
BD		 1568};
1569
f791be49 1570static int sm501_pci_probe(struct pci_dev *dev,
158abca5 1571 const struct pci_device_id *id)
b6d6454f
BD		 1572{
1573 struct sm501_devdata *sm;
1574 int err;
1575
1576 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1577 if (sm == NULL) {
1578 dev_err(&dev->dev, "no memory for device data\n");
1579 err = -ENOMEM;
1580 goto err1;
1581 }
1582
1583 /* set a default set of platform data */
1584 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1585
1586 /* set a hopefully unique id for our child platform devices */
1587 sm->pdev_id = 32 + dev->devfn;
1588
1589 pci_set_drvdata(dev, sm);
1590
1591 err = pci_enable_device(dev);
1592 if (err) {
1593 dev_err(&dev->dev, "cannot enable device\n");
1594 goto err2;
1595 }
1596
1597 sm->dev = &dev->dev;
1598 sm->irq = dev->irq;
1599
1600#ifdef __BIG_ENDIAN
1601 /* if the system is big-endian, we most probably have a
1602 * translation in the IO layer making the PCI bus little endian
1603 * so make the framebuffer swapped pixels */
1604
1605 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1606#endif
1607
1608 /* check our resources */
1609
1610 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1611 dev_err(&dev->dev, "region #0 is not memory?\n");
1612 err = -EINVAL;
1613 goto err3;
1614 }
1615
1616 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1617 dev_err(&dev->dev, "region #1 is not memory?\n");
1618 err = -EINVAL;
1619 goto err3;
1620 }
1621
1622 /* make our resources ready for sharing */
1623
1624 sm->io_res = &dev->resource[1];
1625 sm->mem_res = &dev->resource[0];
1626
1627 sm->regs_claim = request_mem_region(sm->io_res->start,
a5300dcb 1628 0x100, "sm501");
b6d6454f
BD		 1629 if (sm->regs_claim == NULL) {
1630 dev_err(&dev->dev, "cannot claim registers\n");
1631 err= -EBUSY;
1632 goto err3;
1633 }
1634
7ab18995 1635 sm->regs = pci_ioremap_bar(dev, 1);
b6d6454f
BD		 1636
1637 if (sm->regs == NULL) {
1638 dev_err(&dev->dev, "cannot remap registers\n");
1639 err = -EIO;
1640 goto err4;
1641 }
1642
1643 sm501_init_dev(sm);
1644 return 0;
1645
1646 err4:
1647 release_resource(sm->regs_claim);
1648 kfree(sm->regs_claim);
1649 err3:
1650 pci_disable_device(dev);
1651 err2:
b6d6454f
BD		 1652 kfree(sm);
1653 err1:
1654 return err;
1655}
1656
1657static void sm501_remove_sub(struct sm501_devdata *sm,
1658 struct sm501_device *smdev)
1659{
1660 list_del(&smdev->list);
1661 platform_device_unregister(&smdev->pdev);
1662}
1663
1664static void sm501_dev_remove(struct sm501_devdata *sm)
1665{
1666 struct sm501_device *smdev, *tmp;
1667
1668 list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1669 sm501_remove_sub(sm, smdev);
1670
1671 device_remove_file(sm->dev, &dev_attr_dbg_regs);
f61be273 1672
f2999209 1673 sm501_gpio_remove(sm);
b6d6454f
BD		 1674}
1675
4740f73f 1676static void sm501_pci_remove(struct pci_dev *dev)
b6d6454f
BD		 1677{
1678 struct sm501_devdata *sm = pci_get_drvdata(dev);
1679
1680 sm501_dev_remove(sm);
1681 iounmap(sm->regs);
1682
1683 release_resource(sm->regs_claim);
1684 kfree(sm->regs_claim);
1685
b6d6454f
BD		 1686 pci_disable_device(dev);
1687}
1688
1689static int sm501_plat_remove(struct platform_device *dev)
1690{
1691 struct sm501_devdata *sm = platform_get_drvdata(dev);
1692
1693 sm501_dev_remove(sm);
1694 iounmap(sm->regs);
1695
1696 release_resource(sm->regs_claim);
1697 kfree(sm->regs_claim);
1698
1699 return 0;
1700}
1701
36fcd06c 1702static const struct pci_device_id sm501_pci_tbl[] = {
b6d6454f
BD		 1703 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1704 { 0, },
1705};
1706
1707MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1708
158abca5 1709static struct pci_driver sm501_pci_driver = {
b6d6454f
BD		 1710 .name = "sm501",
1711 .id_table = sm501_pci_tbl,
1712 .probe = sm501_pci_probe,
84449216 1713 .remove = sm501_pci_remove,
b6d6454f
BD		 1714};
1715
4f46d6e7
KS		 1716MODULE_ALIAS("platform:sm501");
1717
ae6eee3c 1718static const struct of_device_id of_sm501_match_tbl[] = {
4295f9bf
HS		 1719 { .compatible = "smi,sm501", },
1720 { /* end */ }
1721};
327cc18e 1722MODULE_DEVICE_TABLE(of, of_sm501_match_tbl);
4295f9bf 1723
158abca5 1724static struct platform_driver sm501_plat_driver = {
b6d6454f
BD		 1725 .driver = {
1726 .name = "sm501",
4295f9bf 1727 .of_match_table = of_sm501_match_tbl,
b6d6454f
BD		 1728 },
1729 .probe = sm501_plat_probe,
1730 .remove = sm501_plat_remove,
331d7475
BD		 1731 .suspend = sm501_plat_suspend,
1732 .resume = sm501_plat_resume,
b6d6454f
BD		 1733};
1734
1735static int __init sm501_base_init(void)
1736{
158abca5
AD		 1737 platform_driver_register(&sm501_plat_driver);
1738 return pci_register_driver(&sm501_pci_driver);
b6d6454f
BD		 1739}
1740
1741static void __exit sm501_base_exit(void)
1742{
158abca5
AD		 1743 platform_driver_unregister(&sm501_plat_driver);
1744 pci_unregister_driver(&sm501_pci_driver);
b6d6454f
BD		 1745}
1746
1747module_init(sm501_base_init);
1748module_exit(sm501_base_exit);
1749
1750MODULE_DESCRIPTION("SM501 Core Driver");
1751MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1752MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)