[linux-2.6-block.git] / drivers / mfd / palmas.c

/*
 * TI Palmas MFD Driver
 *
 * Copyright 2011-2012 Texas Instruments Inc.
 *
 * Author: Graeme Gregory <gg@slimlogic.co.uk>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under  the terms of the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the License, or (at your
 *  option) any later version.
 *
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/regmap.h>
#include <linux/err.h>
#include <linux/mfd/core.h>
#include <linux/mfd/palmas.h>
#include <linux/of_device.h>

static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
	{
		.reg_bits = 8,
		.val_bits = 8,
		.max_register = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
					PALMAS_PRIMARY_SECONDARY_PAD3),
	},
	{
		.reg_bits = 8,
		.val_bits = 8,
		.max_register = PALMAS_BASE_TO_REG(PALMAS_GPADC_BASE,
					PALMAS_GPADC_SMPS_VSEL_MONITORING),
	},
	{
		.reg_bits = 8,
		.val_bits = 8,
		.max_register = PALMAS_BASE_TO_REG(PALMAS_TRIM_GPADC_BASE,
					PALMAS_GPADC_TRIM16),
	},
};

static const struct regmap_irq tps65917_irqs[] = {
	/* INT1 IRQs */
	[TPS65917_RESERVED1] = {
		.mask = TPS65917_RESERVED,
	},
	[TPS65917_PWRON_IRQ] = {
		.mask = TPS65917_INT1_STATUS_PWRON,
	},
	[TPS65917_LONG_PRESS_KEY_IRQ] = {
		.mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
	},
	[TPS65917_RESERVED2] = {
		.mask = TPS65917_RESERVED,
	},
	[TPS65917_PWRDOWN_IRQ] = {
		.mask = TPS65917_INT1_STATUS_PWRDOWN,
	},
	[TPS65917_HOTDIE_IRQ] = {
		.mask = TPS65917_INT1_STATUS_HOTDIE,
	},
	[TPS65917_VSYS_MON_IRQ] = {
		.mask = TPS65917_INT1_STATUS_VSYS_MON,
	},
	[TPS65917_RESERVED3] = {
		.mask = TPS65917_RESERVED,
	},
	/* INT2 IRQs*/
	[TPS65917_RESERVED4] = {
		.mask = TPS65917_RESERVED,
		.reg_offset = 1,
	},
	[TPS65917_OTP_ERROR_IRQ] = {
		.mask = TPS65917_INT2_STATUS_OTP_ERROR,
		.reg_offset = 1,
	},
	[TPS65917_WDT_IRQ] = {
		.mask = TPS65917_INT2_STATUS_WDT,
		.reg_offset = 1,
	},
	[TPS65917_RESERVED5] = {
		.mask = TPS65917_RESERVED,
		.reg_offset = 1,
	},
	[TPS65917_RESET_IN_IRQ] = {
		.mask = TPS65917_INT2_STATUS_RESET_IN,
		.reg_offset = 1,
	},
	[TPS65917_FSD_IRQ] = {
		.mask = TPS65917_INT2_STATUS_FSD,
		.reg_offset = 1,
	},
	[TPS65917_SHORT_IRQ] = {
		.mask = TPS65917_INT2_STATUS_SHORT,
		.reg_offset = 1,
	},
	[TPS65917_RESERVED6] = {
		.mask = TPS65917_RESERVED,
		.reg_offset = 1,
	},
	/* INT3 IRQs */
	[TPS65917_GPADC_AUTO_0_IRQ] = {
		.mask = TPS65917_INT3_STATUS_GPADC_AUTO_0,
		.reg_offset = 2,
	},
	[TPS65917_GPADC_AUTO_1_IRQ] = {
		.mask = TPS65917_INT3_STATUS_GPADC_AUTO_1,
		.reg_offset = 2,
	},
	[TPS65917_GPADC_EOC_SW_IRQ] = {
		.mask = TPS65917_INT3_STATUS_GPADC_EOC_SW,
		.reg_offset = 2,
	},
	[TPS65917_RESREVED6] = {
		.mask = TPS65917_RESERVED6,
		.reg_offset = 2,
	},
	[TPS65917_RESERVED7] = {
		.mask = TPS65917_RESERVED,
		.reg_offset = 2,
	},
	[TPS65917_RESERVED8] = {
		.mask = TPS65917_RESERVED,
		.reg_offset = 2,
	},
	[TPS65917_RESERVED9] = {
		.mask = TPS65917_RESERVED,
		.reg_offset = 2,
	},
	[TPS65917_VBUS_IRQ] = {
		.mask = TPS65917_INT3_STATUS_VBUS,
		.reg_offset = 2,
	},
	/* INT4 IRQs */
	[TPS65917_GPIO_0_IRQ] = {
		.mask = TPS65917_INT4_STATUS_GPIO_0,
		.reg_offset = 3,
	},
	[TPS65917_GPIO_1_IRQ] = {
		.mask = TPS65917_INT4_STATUS_GPIO_1,
		.reg_offset = 3,
	},
	[TPS65917_GPIO_2_IRQ] = {
		.mask = TPS65917_INT4_STATUS_GPIO_2,
		.reg_offset = 3,
	},
	[TPS65917_GPIO_3_IRQ] = {
		.mask = TPS65917_INT4_STATUS_GPIO_3,
		.reg_offset = 3,
	},
	[TPS65917_GPIO_4_IRQ] = {
		.mask = TPS65917_INT4_STATUS_GPIO_4,
		.reg_offset = 3,
	},
	[TPS65917_GPIO_5_IRQ] = {
		.mask = TPS65917_INT4_STATUS_GPIO_5,
		.reg_offset = 3,
	},
	[TPS65917_GPIO_6_IRQ] = {
		.mask = TPS65917_INT4_STATUS_GPIO_6,
		.reg_offset = 3,
	},
	[TPS65917_RESERVED10] = {
		.mask = TPS65917_RESERVED10,
		.reg_offset = 3,
	},
};

static const struct regmap_irq palmas_irqs[] = {
	/* INT1 IRQs */
	[PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = {
		.mask = PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV,
	},
	[PALMAS_PWRON_IRQ] = {
		.mask = PALMAS_INT1_STATUS_PWRON,
	},
	[PALMAS_LONG_PRESS_KEY_IRQ] = {
		.mask = PALMAS_INT1_STATUS_LONG_PRESS_KEY,
	},
	[PALMAS_RPWRON_IRQ] = {
		.mask = PALMAS_INT1_STATUS_RPWRON,
	},
	[PALMAS_PWRDOWN_IRQ] = {
		.mask = PALMAS_INT1_STATUS_PWRDOWN,
	},
	[PALMAS_HOTDIE_IRQ] = {
		.mask = PALMAS_INT1_STATUS_HOTDIE,
	},
	[PALMAS_VSYS_MON_IRQ] = {
		.mask = PALMAS_INT1_STATUS_VSYS_MON,
	},
	[PALMAS_VBAT_MON_IRQ] = {
		.mask = PALMAS_INT1_STATUS_VBAT_MON,
	},
	/* INT2 IRQs*/
	[PALMAS_RTC_ALARM_IRQ] = {
		.mask = PALMAS_INT2_STATUS_RTC_ALARM,
		.reg_offset = 1,
	},
	[PALMAS_RTC_TIMER_IRQ] = {
		.mask = PALMAS_INT2_STATUS_RTC_TIMER,
		.reg_offset = 1,
	},
	[PALMAS_WDT_IRQ] = {
		.mask = PALMAS_INT2_STATUS_WDT,
		.reg_offset = 1,
	},
	[PALMAS_BATREMOVAL_IRQ] = {
		.mask = PALMAS_INT2_STATUS_BATREMOVAL,
		.reg_offset = 1,
	},
	[PALMAS_RESET_IN_IRQ] = {
		.mask = PALMAS_INT2_STATUS_RESET_IN,
		.reg_offset = 1,
	},
	[PALMAS_FBI_BB_IRQ] = {
		.mask = PALMAS_INT2_STATUS_FBI_BB,
		.reg_offset = 1,
	},
	[PALMAS_SHORT_IRQ] = {
		.mask = PALMAS_INT2_STATUS_SHORT,
		.reg_offset = 1,
	},
	[PALMAS_VAC_ACOK_IRQ] = {
		.mask = PALMAS_INT2_STATUS_VAC_ACOK,
		.reg_offset = 1,
	},
	/* INT3 IRQs */
	[PALMAS_GPADC_AUTO_0_IRQ] = {
		.mask = PALMAS_INT3_STATUS_GPADC_AUTO_0,
		.reg_offset = 2,
	},
	[PALMAS_GPADC_AUTO_1_IRQ] = {
		.mask = PALMAS_INT3_STATUS_GPADC_AUTO_1,
		.reg_offset = 2,
	},
	[PALMAS_GPADC_EOC_SW_IRQ] = {
		.mask = PALMAS_INT3_STATUS_GPADC_EOC_SW,
		.reg_offset = 2,
	},
	[PALMAS_GPADC_EOC_RT_IRQ] = {
		.mask = PALMAS_INT3_STATUS_GPADC_EOC_RT,
		.reg_offset = 2,
	},
	[PALMAS_ID_OTG_IRQ] = {
		.mask = PALMAS_INT3_STATUS_ID_OTG,
		.reg_offset = 2,
	},
	[PALMAS_ID_IRQ] = {
		.mask = PALMAS_INT3_STATUS_ID,
		.reg_offset = 2,
	},
	[PALMAS_VBUS_OTG_IRQ] = {
		.mask = PALMAS_INT3_STATUS_VBUS_OTG,
		.reg_offset = 2,
	},
	[PALMAS_VBUS_IRQ] = {
		.mask = PALMAS_INT3_STATUS_VBUS,
		.reg_offset = 2,
	},
	/* INT4 IRQs */
	[PALMAS_GPIO_0_IRQ] = {
		.mask = PALMAS_INT4_STATUS_GPIO_0,
		.reg_offset = 3,
	},
	[PALMAS_GPIO_1_IRQ] = {
		.mask = PALMAS_INT4_STATUS_GPIO_1,
		.reg_offset = 3,
	},
	[PALMAS_GPIO_2_IRQ] = {
		.mask = PALMAS_INT4_STATUS_GPIO_2,
		.reg_offset = 3,
	},
	[PALMAS_GPIO_3_IRQ] = {
		.mask = PALMAS_INT4_STATUS_GPIO_3,
		.reg_offset = 3,
	},
	[PALMAS_GPIO_4_IRQ] = {
		.mask = PALMAS_INT4_STATUS_GPIO_4,
		.reg_offset = 3,
	},
	[PALMAS_GPIO_5_IRQ] = {
		.mask = PALMAS_INT4_STATUS_GPIO_5,
		.reg_offset = 3,
	},
	[PALMAS_GPIO_6_IRQ] = {
		.mask = PALMAS_INT4_STATUS_GPIO_6,
		.reg_offset = 3,
	},
	[PALMAS_GPIO_7_IRQ] = {
		.mask = PALMAS_INT4_STATUS_GPIO_7,
		.reg_offset = 3,
	},
};

static struct regmap_irq_chip palmas_irq_chip = {
	.name = "palmas",
	.irqs = palmas_irqs,
	.num_irqs = ARRAY_SIZE(palmas_irqs),

	.num_regs = 4,
	.irq_reg_stride = 5,
	.status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
			PALMAS_INT1_STATUS),
	.mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
			PALMAS_INT1_MASK),
};

static struct regmap_irq_chip tps65917_irq_chip = {
	.name = "tps65917",
	.irqs = tps65917_irqs,
	.num_irqs = ARRAY_SIZE(tps65917_irqs),

	.num_regs = 4,
	.irq_reg_stride = 5,
	.status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
			PALMAS_INT1_STATUS),
	.mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
			PALMAS_INT1_MASK),
};

int palmas_ext_control_req_config(struct palmas *palmas,
	enum palmas_external_requestor_id id,  int ext_ctrl, bool enable)
{
	struct palmas_pmic_driver_data *pmic_ddata = palmas->pmic_ddata;
	int preq_mask_bit = 0;
	int reg_add = 0;
	int bit_pos, ret;

	if (!(ext_ctrl & PALMAS_EXT_REQ))
		return 0;

	if (id >= PALMAS_EXTERNAL_REQSTR_ID_MAX)
		return 0;

	if (ext_ctrl & PALMAS_EXT_CONTROL_NSLEEP) {
		reg_add = PALMAS_NSLEEP_RES_ASSIGN;
		preq_mask_bit = 0;
	} else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE1) {
		reg_add = PALMAS_ENABLE1_RES_ASSIGN;
		preq_mask_bit = 1;
	} else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE2) {
		reg_add = PALMAS_ENABLE2_RES_ASSIGN;
		preq_mask_bit = 2;
	}

	bit_pos = pmic_ddata->sleep_req_info[id].bit_pos;
	reg_add += pmic_ddata->sleep_req_info[id].reg_offset;
	if (enable)
		ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
				reg_add, BIT(bit_pos), BIT(bit_pos));
	else
		ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
				reg_add, BIT(bit_pos), 0);
	if (ret < 0) {
		dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
			reg_add, ret);
		return ret;
	}

	/* Unmask the PREQ */
	ret = palmas_update_bits(palmas, PALMAS_PMU_CONTROL_BASE,
			PALMAS_POWER_CTRL, BIT(preq_mask_bit), 0);
	if (ret < 0) {
		dev_err(palmas->dev, "POWER_CTRL register update failed %d\n",
			ret);
		return ret;
	}
	return ret;
}
EXPORT_SYMBOL_GPL(palmas_ext_control_req_config);

static int palmas_set_pdata_irq_flag(struct i2c_client *i2c,
		struct palmas_platform_data *pdata)
{
	struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
	if (!irq_data) {
		dev_err(&i2c->dev, "Invalid IRQ: %d\n", i2c->irq);
		return -EINVAL;
	}

	pdata->irq_flags = irqd_get_trigger_type(irq_data);
	dev_info(&i2c->dev, "Irq flag is 0x%08x\n", pdata->irq_flags);
	return 0;
}

static void palmas_dt_to_pdata(struct i2c_client *i2c,
		struct palmas_platform_data *pdata)
{
	struct device_node *node = i2c->dev.of_node;
	int ret;
	u32 prop;

	ret = of_property_read_u32(node, "ti,mux-pad1", &prop);
	if (!ret) {
		pdata->mux_from_pdata = 1;
		pdata->pad1 = prop;
	}

	ret = of_property_read_u32(node, "ti,mux-pad2", &prop);
	if (!ret) {
		pdata->mux_from_pdata = 1;
		pdata->pad2 = prop;
	}

	/* The default for this register is all masked */
	ret = of_property_read_u32(node, "ti,power-ctrl", &prop);
	if (!ret)
		pdata->power_ctrl = prop;
	else
		pdata->power_ctrl = PALMAS_POWER_CTRL_NSLEEP_MASK |
					PALMAS_POWER_CTRL_ENABLE1_MASK |
					PALMAS_POWER_CTRL_ENABLE2_MASK;
	if (i2c->irq)
		palmas_set_pdata_irq_flag(i2c, pdata);

	pdata->pm_off = of_property_read_bool(node,
			"ti,system-power-controller");
}

static struct palmas *palmas_dev;
static void palmas_power_off(void)
{
	unsigned int addr;
	int ret, slave;

	if (!palmas_dev)
		return;

	slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
	addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_DEV_CTRL);

	ret = regmap_update_bits(
			palmas_dev->regmap[slave],
			addr,
			PALMAS_DEV_CTRL_DEV_ON,
			0);

	if (ret)
		pr_err("%s: Unable to write to DEV_CTRL_DEV_ON: %d\n",
				__func__, ret);
}

static unsigned int palmas_features = PALMAS_PMIC_FEATURE_SMPS10_BOOST;
static unsigned int tps659038_features;

struct palmas_driver_data {
	unsigned int *features;
	struct regmap_irq_chip *irq_chip;
};

static struct palmas_driver_data palmas_data = {
	.features = &palmas_features,
	.irq_chip = &palmas_irq_chip,
};

static struct palmas_driver_data tps659038_data = {
	.features = &tps659038_features,
	.irq_chip = &palmas_irq_chip,
};

static struct palmas_driver_data tps65917_data = {
	.features = &tps659038_features,
	.irq_chip = &tps65917_irq_chip,
};

static const struct of_device_id of_palmas_match_tbl[] = {
	{
		.compatible = "ti,palmas",
		.data = &palmas_data,
	},
	{
		.compatible = "ti,tps659038",
		.data = &tps659038_data,
	},
	{
		.compatible = "ti,tps65917",
		.data = &tps65917_data,
	},
	{ },
};
MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);

static int palmas_i2c_probe(struct i2c_client *i2c,
			    const struct i2c_device_id *id)
{
	struct palmas *palmas;
	struct palmas_platform_data *pdata;
	struct palmas_driver_data *driver_data;
	struct device_node *node = i2c->dev.of_node;
	int ret = 0, i;
	unsigned int reg, addr;
	int slave;
	const struct of_device_id *match;

	pdata = dev_get_platdata(&i2c->dev);

	if (node && !pdata) {
		pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL);

		if (!pdata)
			return -ENOMEM;

		palmas_dt_to_pdata(i2c, pdata);
	}

	if (!pdata)
		return -EINVAL;

	palmas = devm_kzalloc(&i2c->dev, sizeof(struct palmas), GFP_KERNEL);
	if (palmas == NULL)
		return -ENOMEM;

	i2c_set_clientdata(i2c, palmas);
	palmas->dev = &i2c->dev;
	palmas->irq = i2c->irq;

	match = of_match_device(of_palmas_match_tbl, &i2c->dev);

	if (!match)
		return -ENODATA;

	driver_data = (struct palmas_driver_data *)match->data;
	palmas->features = *driver_data->features;

	for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
		if (i == 0)
			palmas->i2c_clients[i] = i2c;
		else {
			palmas->i2c_clients[i] =
					i2c_new_dummy(i2c->adapter,
							i2c->addr + i);
			if (!palmas->i2c_clients[i]) {
				dev_err(palmas->dev,
					"can't attach client %d\n", i);
				ret = -ENOMEM;
				goto err_i2c;
			}
			palmas->i2c_clients[i]->dev.of_node = of_node_get(node);
		}
		palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i],
				&palmas_regmap_config[i]);
		if (IS_ERR(palmas->regmap[i])) {
			ret = PTR_ERR(palmas->regmap[i]);
			dev_err(palmas->dev,
				"Failed to allocate regmap %d, err: %d\n",
				i, ret);
			goto err_i2c;
		}
	}

	if (!palmas->irq) {
		dev_warn(palmas->dev, "IRQ missing: skipping irq request\n");
		goto no_irq;
	}

	/* Change interrupt line output polarity */
	if (pdata->irq_flags & IRQ_TYPE_LEVEL_HIGH)
		reg = PALMAS_POLARITY_CTRL_INT_POLARITY;
	else
		reg = 0;
	ret = palmas_update_bits(palmas, PALMAS_PU_PD_OD_BASE,
			PALMAS_POLARITY_CTRL, PALMAS_POLARITY_CTRL_INT_POLARITY,
			reg);
	if (ret < 0) {
		dev_err(palmas->dev, "POLARITY_CTRL updat failed: %d\n", ret);
		goto err_i2c;
	}

	/* Change IRQ into clear on read mode for efficiency */
	slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE);
	addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, PALMAS_INT_CTRL);
	reg = PALMAS_INT_CTRL_INT_CLEAR;

	regmap_write(palmas->regmap[slave], addr, reg);

	ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
				  IRQF_ONESHOT | pdata->irq_flags, 0,
				  driver_data->irq_chip, &palmas->irq_data);
	if (ret < 0)
		goto err_i2c;

no_irq:
	slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
	addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
			PALMAS_PRIMARY_SECONDARY_PAD1);

	if (pdata->mux_from_pdata) {
		reg = pdata->pad1;
		ret = regmap_write(palmas->regmap[slave], addr, reg);
		if (ret)
			goto err_irq;
	} else {
		ret = regmap_read(palmas->regmap[slave], addr, &reg);
		if (ret)
			goto err_irq;
	}

	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0))
		palmas->gpio_muxed |= PALMAS_GPIO_0_MUXED;
	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK))
		palmas->gpio_muxed |= PALMAS_GPIO_1_MUXED;
	else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
			(2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
		palmas->led_muxed |= PALMAS_LED1_MUXED;
	else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
			(3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
		palmas->pwm_muxed |= PALMAS_PWM1_MUXED;
	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK))
		palmas->gpio_muxed |= PALMAS_GPIO_2_MUXED;
	else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
			(2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
		palmas->led_muxed |= PALMAS_LED2_MUXED;
	else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
			(3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
		palmas->pwm_muxed |= PALMAS_PWM2_MUXED;
	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3))
		palmas->gpio_muxed |= PALMAS_GPIO_3_MUXED;

	addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
			PALMAS_PRIMARY_SECONDARY_PAD2);

	if (pdata->mux_from_pdata) {
		reg = pdata->pad2;
		ret = regmap_write(palmas->regmap[slave], addr, reg);
		if (ret)
			goto err_irq;
	} else {
		ret = regmap_read(palmas->regmap[slave], addr, &reg);
		if (ret)
			goto err_irq;
	}

	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4))
		palmas->gpio_muxed |= PALMAS_GPIO_4_MUXED;
	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK))
		palmas->gpio_muxed |= PALMAS_GPIO_5_MUXED;
	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6))
		palmas->gpio_muxed |= PALMAS_GPIO_6_MUXED;
	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK))
		palmas->gpio_muxed |= PALMAS_GPIO_7_MUXED;

	dev_info(palmas->dev, "Muxing GPIO %x, PWM %x, LED %x\n",
			palmas->gpio_muxed, palmas->pwm_muxed,
			palmas->led_muxed);

	reg = pdata->power_ctrl;

	slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
	addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_POWER_CTRL);

	ret = regmap_write(palmas->regmap[slave], addr, reg);
	if (ret)
		goto err_irq;

	/*
	 * If we are probing with DT do this the DT way and return here
	 * otherwise continue and add devices using mfd helpers.
	 */
	if (node) {
		ret = of_platform_populate(node, NULL, NULL, &i2c->dev);
		if (ret < 0) {
			goto err_irq;
		} else if (pdata->pm_off && !pm_power_off) {
			palmas_dev = palmas;
			pm_power_off = palmas_power_off;
		}
	}

	return ret;

err_irq:
	regmap_del_irq_chip(palmas->irq, palmas->irq_data);
err_i2c:
	for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
		if (palmas->i2c_clients[i])
			i2c_unregister_device(palmas->i2c_clients[i]);
	}
	return ret;
}

static int palmas_i2c_remove(struct i2c_client *i2c)
{
	struct palmas *palmas = i2c_get_clientdata(i2c);
	int i;

	regmap_del_irq_chip(palmas->irq, palmas->irq_data);

	for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
		if (palmas->i2c_clients[i])
			i2c_unregister_device(palmas->i2c_clients[i]);
	}

	if (palmas == palmas_dev) {
		pm_power_off = NULL;
		palmas_dev = NULL;
	}

	return 0;
}

static const struct i2c_device_id palmas_i2c_id[] = {
	{ "palmas", },
	{ "twl6035", },
	{ "twl6037", },
	{ "tps65913", },
	{ /* end */ }
};
MODULE_DEVICE_TABLE(i2c, palmas_i2c_id);

static struct i2c_driver palmas_i2c_driver = {
	.driver = {
		   .name = "palmas",
		   .of_match_table = of_palmas_match_tbl,
	},
	.probe = palmas_i2c_probe,
	.remove = palmas_i2c_remove,
	.id_table = palmas_i2c_id,
};

static int __init palmas_i2c_init(void)
{
	return i2c_add_driver(&palmas_i2c_driver);
}
/* init early so consumer devices can complete system boot */
subsys_initcall(palmas_i2c_init);

static void __exit palmas_i2c_exit(void)
{
	i2c_del_driver(&palmas_i2c_driver);
}
module_exit(palmas_i2c_exit);

MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
MODULE_DESCRIPTION("Palmas chip family multi-function driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2945fbc2 GG	1	/*
	2	* TI Palmas MFD Driver
	3	*
	4	* Copyright 2011-2012 Texas Instruments Inc.
	5	*
	6	* Author: Graeme Gregory <gg@slimlogic.co.uk>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	*/
	14
	15	#include <linux/module.h>
	16	#include <linux/moduleparam.h>
	17	#include <linux/init.h>
	18	#include <linux/slab.h>
	19	#include <linux/i2c.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/irq.h>
	22	#include <linux/regmap.h>
	23	#include <linux/err.h>
	24	#include <linux/mfd/core.h>
	25	#include <linux/mfd/palmas.h>
1ffb0be3	26	#include <linux/of_device.h>
2945fbc2	27
2945fbc2 GG	28	static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
	29	{
	30	.reg_bits = 8,
	31	.val_bits = 8,
	32	.max_register = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
	33	PALMAS_PRIMARY_SECONDARY_PAD3),
	34	},
	35	{
	36	.reg_bits = 8,
	37	.val_bits = 8,
	38	.max_register = PALMAS_BASE_TO_REG(PALMAS_GPADC_BASE,
	39	PALMAS_GPADC_SMPS_VSEL_MONITORING),
	40	},
	41	{
	42	.reg_bits = 8,
	43	.val_bits = 8,
	44	.max_register = PALMAS_BASE_TO_REG(PALMAS_TRIM_GPADC_BASE,
	45	PALMAS_GPADC_TRIM16),
	46	},
	47	};
	48
1c113d83 K	49	static const struct regmap_irq tps65917_irqs[] = {
	50	/* INT1 IRQs */
	51	[TPS65917_RESERVED1] = {
	52	.mask = TPS65917_RESERVED,
	53	},
	54	[TPS65917_PWRON_IRQ] = {
	55	.mask = TPS65917_INT1_STATUS_PWRON,
	56	},
	57	[TPS65917_LONG_PRESS_KEY_IRQ] = {
	58	.mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
	59	},
	60	[TPS65917_RESERVED2] = {
	61	.mask = TPS65917_RESERVED,
	62	},
	63	[TPS65917_PWRDOWN_IRQ] = {
	64	.mask = TPS65917_INT1_STATUS_PWRDOWN,
	65	},
	66	[TPS65917_HOTDIE_IRQ] = {
	67	.mask = TPS65917_INT1_STATUS_HOTDIE,
	68	},
	69	[TPS65917_VSYS_MON_IRQ] = {
	70	.mask = TPS65917_INT1_STATUS_VSYS_MON,
	71	},
	72	[TPS65917_RESERVED3] = {
	73	.mask = TPS65917_RESERVED,
	74	},
	75	/* INT2 IRQs*/
	76	[TPS65917_RESERVED4] = {
	77	.mask = TPS65917_RESERVED,
	78	.reg_offset = 1,
	79	},
	80	[TPS65917_OTP_ERROR_IRQ] = {
	81	.mask = TPS65917_INT2_STATUS_OTP_ERROR,
	82	.reg_offset = 1,
	83	},
	84	[TPS65917_WDT_IRQ] = {
	85	.mask = TPS65917_INT2_STATUS_WDT,
	86	.reg_offset = 1,
	87	},
	88	[TPS65917_RESERVED5] = {
	89	.mask = TPS65917_RESERVED,
	90	.reg_offset = 1,
	91	},
	92	[TPS65917_RESET_IN_IRQ] = {
	93	.mask = TPS65917_INT2_STATUS_RESET_IN,
	94	.reg_offset = 1,
	95	},
	96	[TPS65917_FSD_IRQ] = {
	97	.mask = TPS65917_INT2_STATUS_FSD,
	98	.reg_offset = 1,
	99	},
	100	[TPS65917_SHORT_IRQ] = {
	101	.mask = TPS65917_INT2_STATUS_SHORT,
	102	.reg_offset = 1,
	103	},
	104	[TPS65917_RESERVED6] = {
	105	.mask = TPS65917_RESERVED,
	106	.reg_offset = 1,
	107	},
	108	/* INT3 IRQs */
	109	[TPS65917_GPADC_AUTO_0_IRQ] = {
	110	.mask = TPS65917_INT3_STATUS_GPADC_AUTO_0,
	111	.reg_offset = 2,
	112	},
113	[TPS65917_GPADC_AUTO_1_IRQ] = {
114	.mask = TPS65917_INT3_STATUS_GPADC_AUTO_1,
115	.reg_offset = 2,
116	},
117	[TPS65917_GPADC_EOC_SW_IRQ] = {
118	.mask = TPS65917_INT3_STATUS_GPADC_EOC_SW,
119	.reg_offset = 2,
120	},
121	[TPS65917_RESREVED6] = {
122	.mask = TPS65917_RESERVED6,
123	.reg_offset = 2,
124	},
125	[TPS65917_RESERVED7] = {
126	.mask = TPS65917_RESERVED,
127	.reg_offset = 2,
128	},
129	[TPS65917_RESERVED8] = {
130	.mask = TPS65917_RESERVED,
131	.reg_offset = 2,
132	},
133	[TPS65917_RESERVED9] = {
134	.mask = TPS65917_RESERVED,
135	.reg_offset = 2,
136	},
137	[TPS65917_VBUS_IRQ] = {
138	.mask = TPS65917_INT3_STATUS_VBUS,
139	.reg_offset = 2,
140	},
141	/* INT4 IRQs */
142	[TPS65917_GPIO_0_IRQ] = {
143	.mask = TPS65917_INT4_STATUS_GPIO_0,
144	.reg_offset = 3,
145	},
146	[TPS65917_GPIO_1_IRQ] = {
147	.mask = TPS65917_INT4_STATUS_GPIO_1,
148	.reg_offset = 3,
149	},
150	[TPS65917_GPIO_2_IRQ] = {
151	.mask = TPS65917_INT4_STATUS_GPIO_2,
152	.reg_offset = 3,
153	},
154	[TPS65917_GPIO_3_IRQ] = {
155	.mask = TPS65917_INT4_STATUS_GPIO_3,
156	.reg_offset = 3,
157	},
158	[TPS65917_GPIO_4_IRQ] = {
159	.mask = TPS65917_INT4_STATUS_GPIO_4,
160	.reg_offset = 3,
161	},
162	[TPS65917_GPIO_5_IRQ] = {
163	.mask = TPS65917_INT4_STATUS_GPIO_5,
164	.reg_offset = 3,
165	},
166	[TPS65917_GPIO_6_IRQ] = {
167	.mask = TPS65917_INT4_STATUS_GPIO_6,
168	.reg_offset = 3,
169	},
170	[TPS65917_RESERVED10] = {
171	.mask = TPS65917_RESERVED10,
172	.reg_offset = 3,
173	},
174	};
175
2945fbc2 GG	176	static const struct regmap_irq palmas_irqs[] = {
	177	/* INT1 IRQs */
	178	[PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = {
	179	.mask = PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV,
	180	},
	181	[PALMAS_PWRON_IRQ] = {
	182	.mask = PALMAS_INT1_STATUS_PWRON,
	183	},
	184	[PALMAS_LONG_PRESS_KEY_IRQ] = {
	185	.mask = PALMAS_INT1_STATUS_LONG_PRESS_KEY,
	186	},
	187	[PALMAS_RPWRON_IRQ] = {
	188	.mask = PALMAS_INT1_STATUS_RPWRON,
	189	},
	190	[PALMAS_PWRDOWN_IRQ] = {
	191	.mask = PALMAS_INT1_STATUS_PWRDOWN,
	192	},
	193	[PALMAS_HOTDIE_IRQ] = {
	194	.mask = PALMAS_INT1_STATUS_HOTDIE,
	195	},
	196	[PALMAS_VSYS_MON_IRQ] = {
	197	.mask = PALMAS_INT1_STATUS_VSYS_MON,
	198	},
	199	[PALMAS_VBAT_MON_IRQ] = {
	200	.mask = PALMAS_INT1_STATUS_VBAT_MON,
	201	},
	202	/* INT2 IRQs*/
	203	[PALMAS_RTC_ALARM_IRQ] = {
	204	.mask = PALMAS_INT2_STATUS_RTC_ALARM,
	205	.reg_offset = 1,
	206	},
	207	[PALMAS_RTC_TIMER_IRQ] = {
	208	.mask = PALMAS_INT2_STATUS_RTC_TIMER,
	209	.reg_offset = 1,
	210	},
	211	[PALMAS_WDT_IRQ] = {
	212	.mask = PALMAS_INT2_STATUS_WDT,
	213	.reg_offset = 1,
	214	},
	215	[PALMAS_BATREMOVAL_IRQ] = {
	216	.mask = PALMAS_INT2_STATUS_BATREMOVAL,
	217	.reg_offset = 1,
	218	},
	219	[PALMAS_RESET_IN_IRQ] = {
	220	.mask = PALMAS_INT2_STATUS_RESET_IN,
	221	.reg_offset = 1,
	222	},
	223	[PALMAS_FBI_BB_IRQ] = {
	224	.mask = PALMAS_INT2_STATUS_FBI_BB,
	225	.reg_offset = 1,
	226	},
	227	[PALMAS_SHORT_IRQ] = {
	228	.mask = PALMAS_INT2_STATUS_SHORT,
	229	.reg_offset = 1,
	230	},
	231	[PALMAS_VAC_ACOK_IRQ] = {
	232	.mask = PALMAS_INT2_STATUS_VAC_ACOK,
	233	.reg_offset = 1,
	234	},
	235	/* INT3 IRQs */
	236	[PALMAS_GPADC_AUTO_0_IRQ] = {
	237	.mask = PALMAS_INT3_STATUS_GPADC_AUTO_0,
	238	.reg_offset = 2,
	239	},
240	[PALMAS_GPADC_AUTO_1_IRQ] = {
241	.mask = PALMAS_INT3_STATUS_GPADC_AUTO_1,
242	.reg_offset = 2,
243	},
244	[PALMAS_GPADC_EOC_SW_IRQ] = {
245	.mask = PALMAS_INT3_STATUS_GPADC_EOC_SW,
246	.reg_offset = 2,
247	},
248	[PALMAS_GPADC_EOC_RT_IRQ] = {
249	.mask = PALMAS_INT3_STATUS_GPADC_EOC_RT,
250	.reg_offset = 2,
251	},
252	[PALMAS_ID_OTG_IRQ] = {
253	.mask = PALMAS_INT3_STATUS_ID_OTG,
254	.reg_offset = 2,
255	},
256	[PALMAS_ID_IRQ] = {
257	.mask = PALMAS_INT3_STATUS_ID,
258	.reg_offset = 2,
259	},
260	[PALMAS_VBUS_OTG_IRQ] = {
261	.mask = PALMAS_INT3_STATUS_VBUS_OTG,
262	.reg_offset = 2,
263	},
264	[PALMAS_VBUS_IRQ] = {
265	.mask = PALMAS_INT3_STATUS_VBUS,
266	.reg_offset = 2,
267	},
268	/* INT4 IRQs */
269	[PALMAS_GPIO_0_IRQ] = {
270	.mask = PALMAS_INT4_STATUS_GPIO_0,
271	.reg_offset = 3,
272	},
273	[PALMAS_GPIO_1_IRQ] = {
274	.mask = PALMAS_INT4_STATUS_GPIO_1,
275	.reg_offset = 3,
276	},
277	[PALMAS_GPIO_2_IRQ] = {
278	.mask = PALMAS_INT4_STATUS_GPIO_2,
279	.reg_offset = 3,
280	},
281	[PALMAS_GPIO_3_IRQ] = {
282	.mask = PALMAS_INT4_STATUS_GPIO_3,
283	.reg_offset = 3,
284	},
285	[PALMAS_GPIO_4_IRQ] = {
286	.mask = PALMAS_INT4_STATUS_GPIO_4,
287	.reg_offset = 3,
288	},
289	[PALMAS_GPIO_5_IRQ] = {
290	.mask = PALMAS_INT4_STATUS_GPIO_5,
291	.reg_offset = 3,
292	},
293	[PALMAS_GPIO_6_IRQ] = {
294	.mask = PALMAS_INT4_STATUS_GPIO_6,
295	.reg_offset = 3,
296	},
297	[PALMAS_GPIO_7_IRQ] = {
298	.mask = PALMAS_INT4_STATUS_GPIO_7,
299	.reg_offset = 3,
300	},
301	};
302
303	static struct regmap_irq_chip palmas_irq_chip = {
304	.name = "palmas",
305	.irqs = palmas_irqs,
306	.num_irqs = ARRAY_SIZE(palmas_irqs),
307
308	.num_regs = 4,
309	.irq_reg_stride = 5,
310	.status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
311	PALMAS_INT1_STATUS),
312	.mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
313	PALMAS_INT1_MASK),
314	};
315
1c113d83 K	316	static struct regmap_irq_chip tps65917_irq_chip = {
	317	.name = "tps65917",
	318	.irqs = tps65917_irqs,
	319	.num_irqs = ARRAY_SIZE(tps65917_irqs),
	320
	321	.num_regs = 4,
	322	.irq_reg_stride = 5,
	323	.status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
	324	PALMAS_INT1_STATUS),
	325	.mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
	326	PALMAS_INT1_MASK),
	327	};
	328
cc01b463 LD	329	int palmas_ext_control_req_config(struct palmas *palmas,
	330	enum palmas_external_requestor_id id, int ext_ctrl, bool enable)
	331	{
cac9e916	332	struct palmas_pmic_driver_data *pmic_ddata = palmas->pmic_ddata;
cc01b463 LD	333	int preq_mask_bit = 0;
cc01b463 LD	334	int reg_add = 0;
cac9e916	335	int bit_pos, ret;
cc01b463 LD	336
	337	if (!(ext_ctrl & PALMAS_EXT_REQ))
	338	return 0;
	339
	340	if (id >= PALMAS_EXTERNAL_REQSTR_ID_MAX)
	341	return 0;
	342
	343	if (ext_ctrl & PALMAS_EXT_CONTROL_NSLEEP) {
	344	reg_add = PALMAS_NSLEEP_RES_ASSIGN;
	345	preq_mask_bit = 0;
	346	} else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE1) {
	347	reg_add = PALMAS_ENABLE1_RES_ASSIGN;
	348	preq_mask_bit = 1;
	349	} else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE2) {
	350	reg_add = PALMAS_ENABLE2_RES_ASSIGN;
	351	preq_mask_bit = 2;
	352	}
	353
cac9e916 K	354	bit_pos = pmic_ddata->sleep_req_info[id].bit_pos;
cac9e916 K	355	reg_add += pmic_ddata->sleep_req_info[id].reg_offset;
cc01b463 LD	356	if (enable)
	357	ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
	358	reg_add, BIT(bit_pos), BIT(bit_pos));
	359	else
	360	ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
	361	reg_add, BIT(bit_pos), 0);
	362	if (ret < 0) {
	363	dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
	364	reg_add, ret);
	365	return ret;
	366	}
	367
	368	/* Unmask the PREQ */
	369	ret = palmas_update_bits(palmas, PALMAS_PMU_CONTROL_BASE,
	370	PALMAS_POWER_CTRL, BIT(preq_mask_bit), 0);
	371	if (ret < 0) {
	372	dev_err(palmas->dev, "POWER_CTRL register update failed %d\n",
	373	ret);
	374	return ret;
	375	}
	376	return ret;
	377	}
	378	EXPORT_SYMBOL_GPL(palmas_ext_control_req_config);
	379
df545d1c	380	static int palmas_set_pdata_irq_flag(struct i2c_client *i2c,
9c14ac33 GG	381	struct palmas_platform_data *pdata)
9c14ac33 GG	382	{
df545d1c LD	383	struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
	384	if (!irq_data) {
	385	dev_err(&i2c->dev, "Invalid IRQ: %d\n", i2c->irq);
	386	return -EINVAL;
	387	}
	388
	389	pdata->irq_flags = irqd_get_trigger_type(irq_data);
	390	dev_info(&i2c->dev, "Irq flag is 0x%08x\n", pdata->irq_flags);
	391	return 0;
	392	}
	393
	394	static void palmas_dt_to_pdata(struct i2c_client *i2c,
	395	struct palmas_platform_data *pdata)
	396	{
	397	struct device_node *node = i2c->dev.of_node;
9c14ac33 GG	398	int ret;
	399	u32 prop;
	400
2154a2b3	401	ret = of_property_read_u32(node, "ti,mux-pad1", &prop);
9c14ac33 GG	402	if (!ret) {
	403	pdata->mux_from_pdata = 1;
	404	pdata->pad1 = prop;
	405	}
	406
2154a2b3	407	ret = of_property_read_u32(node, "ti,mux-pad2", &prop);
9c14ac33 GG	408	if (!ret) {
	409	pdata->mux_from_pdata = 1;
	410	pdata->pad2 = prop;
	411	}
	412
	413	/* The default for this register is all masked */
2154a2b3	414	ret = of_property_read_u32(node, "ti,power-ctrl", &prop);
9c14ac33 GG	415	if (!ret)
	416	pdata->power_ctrl = prop;
	417	else
	418	pdata->power_ctrl = PALMAS_POWER_CTRL_NSLEEP_MASK \|
	419	PALMAS_POWER_CTRL_ENABLE1_MASK \|
	420	PALMAS_POWER_CTRL_ENABLE2_MASK;
df545d1c LD	421	if (i2c->irq)
df545d1c LD	422	palmas_set_pdata_irq_flag(i2c, pdata);
b81eec09 BH	423
	424	pdata->pm_off = of_property_read_bool(node,
	425	"ti,system-power-controller");
	426	}
	427
	428	static struct palmas *palmas_dev;
	429	static void palmas_power_off(void)
	430	{
	431	unsigned int addr;
	432	int ret, slave;
	433
	434	if (!palmas_dev)
	435	return;
	436
	437	slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
	438	addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_DEV_CTRL);
	439
	440	ret = regmap_update_bits(
	441	palmas_dev->regmap[slave],
	442	addr,
	443	PALMAS_DEV_CTRL_DEV_ON,
	444	0);
	445
	446	if (ret)
	447	pr_err("%s: Unable to write to DEV_CTRL_DEV_ON: %d\n",
	448	__func__, ret);
9c14ac33 GG	449	}
9c14ac33 GG	450
1ffb0be3	451	static unsigned int palmas_features = PALMAS_PMIC_FEATURE_SMPS10_BOOST;
4124e6e2	452	static unsigned int tps659038_features;
1ffb0be3	453
1c113d83 K	454	struct palmas_driver_data {
	455	unsigned int *features;
	456	struct regmap_irq_chip *irq_chip;
	457	};
	458
	459	static struct palmas_driver_data palmas_data = {
	460	.features = &palmas_features,
	461	.irq_chip = &palmas_irq_chip,
	462	};
	463
	464	static struct palmas_driver_data tps659038_data = {
	465	.features = &tps659038_features,
	466	.irq_chip = &palmas_irq_chip,
	467	};
	468
	469	static struct palmas_driver_data tps65917_data = {
	470	.features = &tps659038_features,
	471	.irq_chip = &tps65917_irq_chip,
	472	};
	473
1ffb0be3 K	474	static const struct of_device_id of_palmas_match_tbl[] = {
	475	{
	476	.compatible = "ti,palmas",
1c113d83	477	.data = &palmas_data,
1ffb0be3	478	},
4124e6e2 K	479	{
4124e6e2 K	480	.compatible = "ti,tps659038",
1c113d83 K	481	.data = &tps659038_data,
	482	},
	483	{
	484	.compatible = "ti,tps65917",
	485	.data = &tps65917_data,
4124e6e2	486	},
1ffb0be3 K	487	{ },
1ffb0be3 K	488	};
2d8edaf0	489	MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
1ffb0be3	490
f791be49	491	static int palmas_i2c_probe(struct i2c_client *i2c,
2945fbc2 GG	492	const struct i2c_device_id *id)
	493	{
	494	struct palmas *palmas;
	495	struct palmas_platform_data *pdata;
1c113d83	496	struct palmas_driver_data *driver_data;
9c14ac33	497	struct device_node *node = i2c->dev.of_node;
2945fbc2	498	int ret = 0, i;
1c113d83	499	unsigned int reg, addr;
2945fbc2	500	int slave;
1ffb0be3	501	const struct of_device_id *match;
2945fbc2 GG	502
2945fbc2 GG	503	pdata = dev_get_platdata(&i2c->dev);
9c14ac33 GG	504
	505	if (node && !pdata) {
	506	pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL);
	507
	508	if (!pdata)
	509	return -ENOMEM;
	510
df545d1c	511	palmas_dt_to_pdata(i2c, pdata);
9c14ac33 GG	512	}
9c14ac33 GG	513
2945fbc2 GG	514	if (!pdata)
	515	return -EINVAL;
	516
	517	palmas = devm_kzalloc(&i2c->dev, sizeof(struct palmas), GFP_KERNEL);
	518	if (palmas == NULL)
	519	return -ENOMEM;
	520
	521	i2c_set_clientdata(i2c, palmas);
	522	palmas->dev = &i2c->dev;
2945fbc2 GG	523	palmas->irq = i2c->irq;
2945fbc2 GG	524
84195b77	525	match = of_match_device(of_palmas_match_tbl, &i2c->dev);
1ffb0be3 K	526
	527	if (!match)
	528	return -ENODATA;
	529
1c113d83 K	530	driver_data = (struct palmas_driver_data *)match->data;
1c113d83 K	531	palmas->features = *driver_data->features;
1ffb0be3	532
2945fbc2 GG	533	for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
	534	if (i == 0)
	535	palmas->i2c_clients[i] = i2c;
	536	else {
	537	palmas->i2c_clients[i] =
	538	i2c_new_dummy(i2c->adapter,
	539	i2c->addr + i);
	540	if (!palmas->i2c_clients[i]) {
	541	dev_err(palmas->dev,
	542	"can't attach client %d\n", i);
	543	ret = -ENOMEM;
5e172d75	544	goto err_i2c;
2945fbc2	545	}
c4fbec3c	546	palmas->i2c_clients[i]->dev.of_node = of_node_get(node);
2945fbc2 GG	547	}
	548	palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i],
	549	&palmas_regmap_config[i]);
	550	if (IS_ERR(palmas->regmap[i])) {
	551	ret = PTR_ERR(palmas->regmap[i]);
	552	dev_err(palmas->dev,
	553	"Failed to allocate regmap %d, err: %d\n",
	554	i, ret);
5e172d75	555	goto err_i2c;
2945fbc2 GG	556	}
	557	}
	558
ad522f4e K	559	if (!palmas->irq) {
	560	dev_warn(palmas->dev, "IRQ missing: skipping irq request\n");
	561	goto no_irq;
	562	}
	563
df545d1c LD	564	/* Change interrupt line output polarity */
	565	if (pdata->irq_flags & IRQ_TYPE_LEVEL_HIGH)
	566	reg = PALMAS_POLARITY_CTRL_INT_POLARITY;
	567	else
	568	reg = 0;
	569	ret = palmas_update_bits(palmas, PALMAS_PU_PD_OD_BASE,
	570	PALMAS_POLARITY_CTRL, PALMAS_POLARITY_CTRL_INT_POLARITY,
	571	reg);
	572	if (ret < 0) {
	573	dev_err(palmas->dev, "POLARITY_CTRL updat failed: %d\n", ret);
5e172d75	574	goto err_i2c;
df545d1c LD	575	}
df545d1c LD	576
b330f85d GG	577	/* Change IRQ into clear on read mode for efficiency */
	578	slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE);
	579	addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, PALMAS_INT_CTRL);
	580	reg = PALMAS_INT_CTRL_INT_CLEAR;
	581
	582	regmap_write(palmas->regmap[slave], addr, reg);
	583
	584	ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
1c113d83 K	585	IRQF_ONESHOT \| pdata->irq_flags, 0,
1c113d83 K	586	driver_data->irq_chip, &palmas->irq_data);
2945fbc2	587	if (ret < 0)
5e172d75	588	goto err_i2c;
2945fbc2	589
ad522f4e	590	no_irq:
2945fbc2 GG	591	slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
	592	addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
	593	PALMAS_PRIMARY_SECONDARY_PAD1);
	594
	595	if (pdata->mux_from_pdata) {
	596	reg = pdata->pad1;
	597	ret = regmap_write(palmas->regmap[slave], addr, reg);
	598	if (ret)
3f78decc	599	goto err_irq;
2945fbc2 GG	600	} else {
	601	ret = regmap_read(palmas->regmap[slave], addr, &reg);
	602	if (ret)
3f78decc	603	goto err_irq;
2945fbc2 GG	604	}
	605
	606	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0))
	607	palmas->gpio_muxed \|= PALMAS_GPIO_0_MUXED;
	608	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK))
	609	palmas->gpio_muxed \|= PALMAS_GPIO_1_MUXED;
	610	else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
	611	(2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
	612	palmas->led_muxed \|= PALMAS_LED1_MUXED;
	613	else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
	614	(3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
	615	palmas->pwm_muxed \|= PALMAS_PWM1_MUXED;
	616	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK))
	617	palmas->gpio_muxed \|= PALMAS_GPIO_2_MUXED;
	618	else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
	619	(2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
	620	palmas->led_muxed \|= PALMAS_LED2_MUXED;
	621	else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
	622	(3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
	623	palmas->pwm_muxed \|= PALMAS_PWM2_MUXED;
	624	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3))
	625	palmas->gpio_muxed \|= PALMAS_GPIO_3_MUXED;
	626
	627	addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
	628	PALMAS_PRIMARY_SECONDARY_PAD2);
	629
	630	if (pdata->mux_from_pdata) {
	631	reg = pdata->pad2;
	632	ret = regmap_write(palmas->regmap[slave], addr, reg);
	633	if (ret)
3f78decc	634	goto err_irq;
2945fbc2 GG	635	} else {
	636	ret = regmap_read(palmas->regmap[slave], addr, &reg);
	637	if (ret)
3f78decc	638	goto err_irq;
2945fbc2 GG	639	}
	640
	641	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4))
	642	palmas->gpio_muxed \|= PALMAS_GPIO_4_MUXED;
	643	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK))
	644	palmas->gpio_muxed \|= PALMAS_GPIO_5_MUXED;
	645	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6))
	646	palmas->gpio_muxed \|= PALMAS_GPIO_6_MUXED;
	647	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK))
	648	palmas->gpio_muxed \|= PALMAS_GPIO_7_MUXED;
	649
	650	dev_info(palmas->dev, "Muxing GPIO %x, PWM %x, LED %x\n",
	651	palmas->gpio_muxed, palmas->pwm_muxed,
	652	palmas->led_muxed);
	653
	654	reg = pdata->power_ctrl;
	655
	656	slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
	657	addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_POWER_CTRL);
	658
	659	ret = regmap_write(palmas->regmap[slave], addr, reg);
	660	if (ret)
3f78decc	661	goto err_irq;
2945fbc2	662
9c14ac33 GG	663	/*
	664	* If we are probing with DT do this the DT way and return here
	665	* otherwise continue and add devices using mfd helpers.
	666	*/
	667	if (node) {
	668	ret = of_platform_populate(node, NULL, NULL, &i2c->dev);
b81eec09	669	if (ret < 0) {
9c14ac33	670	goto err_irq;
b81eec09 BH	671	} else if (pdata->pm_off && !pm_power_off) {
	672	palmas_dev = palmas;
	673	pm_power_off = palmas_power_off;
b81eec09	674	}
9c14ac33 GG	675	}
9c14ac33 GG	676
2945fbc2 GG	677	return ret;
2945fbc2 GG	678
3f78decc GG	679	err_irq:
3f78decc GG	680	regmap_del_irq_chip(palmas->irq, palmas->irq_data);
5e172d75 LD	681	err_i2c:
	682	for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
	683	if (palmas->i2c_clients[i])
	684	i2c_unregister_device(palmas->i2c_clients[i]);
	685	}
2945fbc2 GG	686	return ret;
	687	}
	688
	689	static int palmas_i2c_remove(struct i2c_client *i2c)
	690	{
	691	struct palmas *palmas = i2c_get_clientdata(i2c);
5e172d75	692	int i;
2945fbc2	693
2945fbc2 GG	694	regmap_del_irq_chip(palmas->irq, palmas->irq_data);
2945fbc2 GG	695
5e172d75 LD	696	for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
	697	if (palmas->i2c_clients[i])
	698	i2c_unregister_device(palmas->i2c_clients[i]);
	699	}
	700
7178347e LD	701	if (palmas == palmas_dev) {
	702	pm_power_off = NULL;
	703	palmas_dev = NULL;
	704	}
	705
2945fbc2 GG	706	return 0;
	707	}
	708
	709	static const struct i2c_device_id palmas_i2c_id[] = {
	710	{ "palmas", },
	711	{ "twl6035", },
	712	{ "twl6037", },
	713	{ "tps65913", },
00ba81c1	714	{ /* end */ }
2945fbc2 GG	715	};
	716	MODULE_DEVICE_TABLE(i2c, palmas_i2c_id);
	717
2945fbc2 GG	718	static struct i2c_driver palmas_i2c_driver = {
	719	.driver = {
	720	.name = "palmas",
	721	.of_match_table = of_palmas_match_tbl,
2945fbc2 GG	722	},
	723	.probe = palmas_i2c_probe,
	724	.remove = palmas_i2c_remove,
	725	.id_table = palmas_i2c_id,
	726	};
	727
	728	static int __init palmas_i2c_init(void)
	729	{
	730	return i2c_add_driver(&palmas_i2c_driver);
	731	}
	732	/* init early so consumer devices can complete system boot */
	733	subsys_initcall(palmas_i2c_init);
	734
	735	static void __exit palmas_i2c_exit(void)
	736	{
	737	i2c_del_driver(&palmas_i2c_driver);
	738	}
	739	module_exit(palmas_i2c_exit);
	740
	741	MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
	742	MODULE_DESCRIPTION("Palmas chip family multi-function driver");
	743	MODULE_LICENSE("GPL");