[linux-2.6-block.git] / drivers / mfd / intel_soc_pmic_crc.c

/*
 * intel_soc_pmic_crc.c - Device access for Crystal Cove PMIC
 *
 * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version
 * 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * Author: Yang, Bin <bin.yang@intel.com>
 * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
 */

#include <linux/mfd/core.h>
#include <linux/interrupt.h>
#include <linux/regmap.h>
#include <linux/mfd/intel_soc_pmic.h>
#include "intel_soc_pmic_core.h"

#define CRYSTAL_COVE_MAX_REGISTER	0xC6

#define CRYSTAL_COVE_REG_IRQLVL1	0x02
#define CRYSTAL_COVE_REG_MIRQLVL1	0x0E

#define CRYSTAL_COVE_IRQ_PWRSRC		0
#define CRYSTAL_COVE_IRQ_THRM		1
#define CRYSTAL_COVE_IRQ_BCU		2
#define CRYSTAL_COVE_IRQ_ADC		3
#define CRYSTAL_COVE_IRQ_CHGR		4
#define CRYSTAL_COVE_IRQ_GPIO		5
#define CRYSTAL_COVE_IRQ_VHDMIOCP	6

static struct resource gpio_resources[] = {
	{
		.name	= "GPIO",
		.start	= CRYSTAL_COVE_IRQ_GPIO,
		.end	= CRYSTAL_COVE_IRQ_GPIO,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct resource pwrsrc_resources[] = {
	{
		.name  = "PWRSRC",
		.start = CRYSTAL_COVE_IRQ_PWRSRC,
		.end   = CRYSTAL_COVE_IRQ_PWRSRC,
		.flags = IORESOURCE_IRQ,
	},
};

static struct resource adc_resources[] = {
	{
		.name  = "ADC",
		.start = CRYSTAL_COVE_IRQ_ADC,
		.end   = CRYSTAL_COVE_IRQ_ADC,
		.flags = IORESOURCE_IRQ,
	},
};

static struct resource thermal_resources[] = {
	{
		.name  = "THERMAL",
		.start = CRYSTAL_COVE_IRQ_THRM,
		.end   = CRYSTAL_COVE_IRQ_THRM,
		.flags = IORESOURCE_IRQ,
	},
};

static struct resource bcu_resources[] = {
	{
		.name  = "BCU",
		.start = CRYSTAL_COVE_IRQ_BCU,
		.end   = CRYSTAL_COVE_IRQ_BCU,
		.flags = IORESOURCE_IRQ,
	},
};

static struct mfd_cell crystal_cove_dev[] = {
	{
		.name = "crystal_cove_pwrsrc",
		.num_resources = ARRAY_SIZE(pwrsrc_resources),
		.resources = pwrsrc_resources,
	},
	{
		.name = "crystal_cove_adc",
		.num_resources = ARRAY_SIZE(adc_resources),
		.resources = adc_resources,
	},
	{
		.name = "crystal_cove_thermal",
		.num_resources = ARRAY_SIZE(thermal_resources),
		.resources = thermal_resources,
	},
	{
		.name = "crystal_cove_bcu",
		.num_resources = ARRAY_SIZE(bcu_resources),
		.resources = bcu_resources,
	},
	{
		.name = "crystal_cove_gpio",
		.num_resources = ARRAY_SIZE(gpio_resources),
		.resources = gpio_resources,
	},
	{
		.name = "crystal_cove_pmic",
	},
	{
		.name = "crystal_cove_pwm",
	},
};

static const struct regmap_config crystal_cove_regmap_config = {
	.reg_bits = 8,
	.val_bits = 8,

	.max_register = CRYSTAL_COVE_MAX_REGISTER,
	.cache_type = REGCACHE_NONE,
};

static const struct regmap_irq crystal_cove_irqs[] = {
	[CRYSTAL_COVE_IRQ_PWRSRC] = {
		.mask = BIT(CRYSTAL_COVE_IRQ_PWRSRC),
	},
	[CRYSTAL_COVE_IRQ_THRM] = {
		.mask = BIT(CRYSTAL_COVE_IRQ_THRM),
	},
	[CRYSTAL_COVE_IRQ_BCU] = {
		.mask = BIT(CRYSTAL_COVE_IRQ_BCU),
	},
	[CRYSTAL_COVE_IRQ_ADC] = {
		.mask = BIT(CRYSTAL_COVE_IRQ_ADC),
	},
	[CRYSTAL_COVE_IRQ_CHGR] = {
		.mask = BIT(CRYSTAL_COVE_IRQ_CHGR),
	},
	[CRYSTAL_COVE_IRQ_GPIO] = {
		.mask = BIT(CRYSTAL_COVE_IRQ_GPIO),
	},
	[CRYSTAL_COVE_IRQ_VHDMIOCP] = {
		.mask = BIT(CRYSTAL_COVE_IRQ_VHDMIOCP),
	},
};

static const struct regmap_irq_chip crystal_cove_irq_chip = {
	.name = "Crystal Cove",
	.irqs = crystal_cove_irqs,
	.num_irqs = ARRAY_SIZE(crystal_cove_irqs),
	.num_regs = 1,
	.status_base = CRYSTAL_COVE_REG_IRQLVL1,
	.mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
};

struct intel_soc_pmic_config intel_soc_pmic_config_crc = {
	.irq_flags = IRQF_TRIGGER_RISING,
	.cell_dev = crystal_cove_dev,
	.n_cell_devs = ARRAY_SIZE(crystal_cove_dev),
	.regmap_config = &crystal_cove_regmap_config,
	.irq_chip = &crystal_cove_irq_chip,
};
Commit	Line	Data
7cf0a66f ZL	1	/*
	2	* intel_soc_pmic_crc.c - Device access for Crystal Cove PMIC
	3	*
	4	* Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License version
	8	* 2 as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* Author: Yang, Bin <bin.yang@intel.com>
	16	* Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
	17	*/
	18
	19	#include <linux/mfd/core.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/regmap.h>
	22	#include <linux/mfd/intel_soc_pmic.h>
	23	#include "intel_soc_pmic_core.h"
	24
	25	#define CRYSTAL_COVE_MAX_REGISTER 0xC6
	26
	27	#define CRYSTAL_COVE_REG_IRQLVL1 0x02
	28	#define CRYSTAL_COVE_REG_MIRQLVL1 0x0E
	29
	30	#define CRYSTAL_COVE_IRQ_PWRSRC 0
	31	#define CRYSTAL_COVE_IRQ_THRM 1
	32	#define CRYSTAL_COVE_IRQ_BCU 2
	33	#define CRYSTAL_COVE_IRQ_ADC 3
	34	#define CRYSTAL_COVE_IRQ_CHGR 4
	35	#define CRYSTAL_COVE_IRQ_GPIO 5
	36	#define CRYSTAL_COVE_IRQ_VHDMIOCP 6
	37
	38	static struct resource gpio_resources[] = {
	39	{
	40	.name = "GPIO",
	41	.start = CRYSTAL_COVE_IRQ_GPIO,
	42	.end = CRYSTAL_COVE_IRQ_GPIO,
	43	.flags = IORESOURCE_IRQ,
	44	},
	45	};
	46
	47	static struct resource pwrsrc_resources[] = {
	48	{
	49	.name = "PWRSRC",
	50	.start = CRYSTAL_COVE_IRQ_PWRSRC,
	51	.end = CRYSTAL_COVE_IRQ_PWRSRC,
	52	.flags = IORESOURCE_IRQ,
	53	},
	54	};
	55
	56	static struct resource adc_resources[] = {
	57	{
	58	.name = "ADC",
	59	.start = CRYSTAL_COVE_IRQ_ADC,
	60	.end = CRYSTAL_COVE_IRQ_ADC,
	61	.flags = IORESOURCE_IRQ,
	62	},
	63	};
	64
65	static struct resource thermal_resources[] = {
66	{
67	.name = "THERMAL",
68	.start = CRYSTAL_COVE_IRQ_THRM,
69	.end = CRYSTAL_COVE_IRQ_THRM,
70	.flags = IORESOURCE_IRQ,
71	},
72	};
73
74	static struct resource bcu_resources[] = {
75	{
76	.name = "BCU",
77	.start = CRYSTAL_COVE_IRQ_BCU,
78	.end = CRYSTAL_COVE_IRQ_BCU,
79	.flags = IORESOURCE_IRQ,
80	},
81	};
82
83	static struct mfd_cell crystal_cove_dev[] = {
84	{
85	.name = "crystal_cove_pwrsrc",
86	.num_resources = ARRAY_SIZE(pwrsrc_resources),
87	.resources = pwrsrc_resources,
88	},
89	{
90	.name = "crystal_cove_adc",
91	.num_resources = ARRAY_SIZE(adc_resources),
92	.resources = adc_resources,
93	},
94	{
95	.name = "crystal_cove_thermal",
96	.num_resources = ARRAY_SIZE(thermal_resources),
97	.resources = thermal_resources,
98	},
99	{
100	.name = "crystal_cove_bcu",
101	.num_resources = ARRAY_SIZE(bcu_resources),
102	.resources = bcu_resources,
103	},
104	{
105	.name = "crystal_cove_gpio",
106	.num_resources = ARRAY_SIZE(gpio_resources),
107	.resources = gpio_resources,
108	},
b1eea857 AL	109	{
	110	.name = "crystal_cove_pmic",
	111	},
3d5e10ec SK	112	{
	113	.name = "crystal_cove_pwm",
	114	},
7cf0a66f ZL	115	};
7cf0a66f ZL	116
172cb301	117	static const struct regmap_config crystal_cove_regmap_config = {
7cf0a66f ZL	118	.reg_bits = 8,
	119	.val_bits = 8,
	120
	121	.max_register = CRYSTAL_COVE_MAX_REGISTER,
	122	.cache_type = REGCACHE_NONE,
	123	};
	124
	125	static const struct regmap_irq crystal_cove_irqs[] = {
	126	[CRYSTAL_COVE_IRQ_PWRSRC] = {
	127	.mask = BIT(CRYSTAL_COVE_IRQ_PWRSRC),
	128	},
	129	[CRYSTAL_COVE_IRQ_THRM] = {
	130	.mask = BIT(CRYSTAL_COVE_IRQ_THRM),
	131	},
	132	[CRYSTAL_COVE_IRQ_BCU] = {
	133	.mask = BIT(CRYSTAL_COVE_IRQ_BCU),
	134	},
	135	[CRYSTAL_COVE_IRQ_ADC] = {
	136	.mask = BIT(CRYSTAL_COVE_IRQ_ADC),
	137	},
	138	[CRYSTAL_COVE_IRQ_CHGR] = {
	139	.mask = BIT(CRYSTAL_COVE_IRQ_CHGR),
	140	},
	141	[CRYSTAL_COVE_IRQ_GPIO] = {
	142	.mask = BIT(CRYSTAL_COVE_IRQ_GPIO),
	143	},
	144	[CRYSTAL_COVE_IRQ_VHDMIOCP] = {
	145	.mask = BIT(CRYSTAL_COVE_IRQ_VHDMIOCP),
	146	},
	147	};
	148
7ce7b26f	149	static const struct regmap_irq_chip crystal_cove_irq_chip = {
7cf0a66f ZL	150	.name = "Crystal Cove",
	151	.irqs = crystal_cove_irqs,
	152	.num_irqs = ARRAY_SIZE(crystal_cove_irqs),
	153	.num_regs = 1,
	154	.status_base = CRYSTAL_COVE_REG_IRQLVL1,
	155	.mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
	156	};
	157
	158	struct intel_soc_pmic_config intel_soc_pmic_config_crc = {
	159	.irq_flags = IRQF_TRIGGER_RISING,
	160	.cell_dev = crystal_cove_dev,
	161	.n_cell_devs = ARRAY_SIZE(crystal_cove_dev),
	162	.regmap_config = &crystal_cove_regmap_config,
	163	.irq_chip = &crystal_cove_irq_chip,
	164	};