[linux-2.6-block.git] / drivers / mfd / intel_soc_pmic_bxtwc.c

/*
 * MFD core driver for Intel Broxton Whiskey Cove PMIC
 *
 * Copyright (C) 2015 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/module.h>
#include <linux/acpi.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_bxtwc.h>
#include <asm/intel_pmc_ipc.h>

/* PMIC device registers */
#define REG_ADDR_MASK		0xFF00
#define REG_ADDR_SHIFT		8
#define REG_OFFSET_MASK		0xFF

/* Interrupt Status Registers */
#define BXTWC_IRQLVL1		0x4E02
#define BXTWC_PWRBTNIRQ		0x4E03

#define BXTWC_THRM0IRQ		0x4E04
#define BXTWC_THRM1IRQ		0x4E05
#define BXTWC_THRM2IRQ		0x4E06
#define BXTWC_BCUIRQ		0x4E07
#define BXTWC_ADCIRQ		0x4E08
#define BXTWC_CHGR0IRQ		0x4E09
#define BXTWC_CHGR1IRQ		0x4E0A
#define BXTWC_GPIOIRQ0		0x4E0B
#define BXTWC_GPIOIRQ1		0x4E0C
#define BXTWC_CRITIRQ		0x4E0D

/* Interrupt MASK Registers */
#define BXTWC_MIRQLVL1		0x4E0E
#define BXTWC_MPWRTNIRQ		0x4E0F

#define BXTWC_MTHRM0IRQ		0x4E12
#define BXTWC_MTHRM1IRQ		0x4E13
#define BXTWC_MTHRM2IRQ		0x4E14
#define BXTWC_MBCUIRQ		0x4E15
#define BXTWC_MADCIRQ		0x4E16
#define BXTWC_MCHGR0IRQ		0x4E17
#define BXTWC_MCHGR1IRQ		0x4E18
#define BXTWC_MGPIO0IRQ		0x4E19
#define BXTWC_MGPIO1IRQ		0x4E1A
#define BXTWC_MCRITIRQ		0x4E1B

/* Whiskey Cove PMIC share same ACPI ID between different platforms */
#define BROXTON_PMIC_WC_HRV	4

/* Manage in two IRQ chips since mask registers are not consecutive */
enum bxtwc_irqs {
	/* Level 1 */
	BXTWC_PWRBTN_LVL1_IRQ = 0,
	BXTWC_TMU_LVL1_IRQ,
	BXTWC_THRM_LVL1_IRQ,
	BXTWC_BCU_LVL1_IRQ,
	BXTWC_ADC_LVL1_IRQ,
	BXTWC_CHGR_LVL1_IRQ,
	BXTWC_GPIO_LVL1_IRQ,
	BXTWC_CRIT_LVL1_IRQ,

	/* Level 2 */
	BXTWC_PWRBTN_IRQ,
};

enum bxtwc_irqs_level2 {
	/* Level 2 */
	BXTWC_THRM0_IRQ = 0,
	BXTWC_THRM1_IRQ,
	BXTWC_THRM2_IRQ,
	BXTWC_BCU_IRQ,
	BXTWC_ADC_IRQ,
	BXTWC_CHGR0_IRQ,
	BXTWC_CHGR1_IRQ,
	BXTWC_GPIO0_IRQ,
	BXTWC_GPIO1_IRQ,
	BXTWC_CRIT_IRQ,
};

static const struct regmap_irq bxtwc_regmap_irqs[] = {
	REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
	REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
	REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
	REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
	REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
	REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
	REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
	REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
	REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03),
};

static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
	REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff),
	REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf),
	REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff),
	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f),
	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff),
	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f),
	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f),
	REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff),
	REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f),
	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03),
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
	.name = "bxtwc_irq_chip",
	.status_base = BXTWC_IRQLVL1,
	.mask_base = BXTWC_MIRQLVL1,
	.irqs = bxtwc_regmap_irqs,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
	.num_regs = 2,
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
	.name = "bxtwc_irq_chip_level2",
	.status_base = BXTWC_THRM0IRQ,
	.mask_base = BXTWC_MTHRM0IRQ,
	.irqs = bxtwc_regmap_irqs_level2,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
	.num_regs = 10,
};

static struct resource gpio_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"),
	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"),
};

static struct resource adc_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
};

static struct resource charger_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
};

static struct resource thermal_resources[] = {
	DEFINE_RES_IRQ(BXTWC_THRM0_IRQ),
	DEFINE_RES_IRQ(BXTWC_THRM1_IRQ),
	DEFINE_RES_IRQ(BXTWC_THRM2_IRQ),
};

static struct resource bcu_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
};

static struct mfd_cell bxt_wc_dev[] = {
	{
		.name = "bxt_wcove_gpadc",
		.num_resources = ARRAY_SIZE(adc_resources),
		.resources = adc_resources,
	},
	{
		.name = "bxt_wcove_thermal",
		.num_resources = ARRAY_SIZE(thermal_resources),
		.resources = thermal_resources,
	},
	{
		.name = "bxt_wcove_ext_charger",
		.num_resources = ARRAY_SIZE(charger_resources),
		.resources = charger_resources,
	},
	{
		.name = "bxt_wcove_bcu",
		.num_resources = ARRAY_SIZE(bcu_resources),
		.resources = bcu_resources,
	},
	{
		.name = "bxt_wcove_gpio",
		.num_resources = ARRAY_SIZE(gpio_resources),
		.resources = gpio_resources,
	},
	{
		.name = "bxt_wcove_region",
	},
};

static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
				    unsigned int *val)
{
	int ret;
	int i2c_addr;
	u8 ipc_in[2];
	u8 ipc_out[4];
	struct intel_soc_pmic *pmic = context;

	if (reg & REG_ADDR_MASK)
		i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
	else {
		i2c_addr = BXTWC_DEVICE1_ADDR;
		if (!i2c_addr) {
			dev_err(pmic->dev, "I2C address not set\n");
			return -EINVAL;
		}
	}
	reg &= REG_OFFSET_MASK;

	ipc_in[0] = reg;
	ipc_in[1] = i2c_addr;
	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
			PMC_IPC_PMIC_ACCESS_READ,
			ipc_in, sizeof(ipc_in), (u32 *)ipc_out, 1);
	if (ret) {
		dev_err(pmic->dev, "Failed to read from PMIC\n");
		return ret;
	}
	*val = ipc_out[0];

	return 0;
}

static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
				       unsigned int val)
{
	int ret;
	int i2c_addr;
	u8 ipc_in[3];
	struct intel_soc_pmic *pmic = context;

	if (reg & REG_ADDR_MASK)
		i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
	else {
		i2c_addr = BXTWC_DEVICE1_ADDR;
		if (!i2c_addr) {
			dev_err(pmic->dev, "I2C address not set\n");
			return -EINVAL;
		}
	}
	reg &= REG_OFFSET_MASK;

	ipc_in[0] = reg;
	ipc_in[1] = i2c_addr;
	ipc_in[2] = val;
	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
			PMC_IPC_PMIC_ACCESS_WRITE,
			ipc_in, sizeof(ipc_in), NULL, 0);
	if (ret) {
		dev_err(pmic->dev, "Failed to write to PMIC\n");
		return ret;
	}

	return 0;
}

/* sysfs interfaces to r/w PMIC registers, required by initial script */
static unsigned long bxtwc_reg_addr;
static ssize_t bxtwc_reg_show(struct device *dev,
		struct device_attribute *attr, char *buf)
{
	return sprintf(buf, "0x%lx\n", bxtwc_reg_addr);
}

static ssize_t bxtwc_reg_store(struct device *dev,
	struct device_attribute *attr, const char *buf, size_t count)
{
	if (kstrtoul(buf, 0, &bxtwc_reg_addr)) {
		dev_err(dev, "Invalid register address\n");
		return -EINVAL;
	}
	return (ssize_t)count;
}

static ssize_t bxtwc_val_show(struct device *dev,
		struct device_attribute *attr, char *buf)
{
	int ret;
	unsigned int val;
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
	if (ret < 0) {
		dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
		return -EIO;
	}

	return sprintf(buf, "0x%02x\n", val);
}

static ssize_t bxtwc_val_store(struct device *dev,
	struct device_attribute *attr, const char *buf, size_t count)
{
	int ret;
	unsigned int val;
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	ret = kstrtouint(buf, 0, &val);
	if (ret)
		return ret;

	ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
	if (ret) {
		dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
			val, bxtwc_reg_addr);
		return -EIO;
	}
	return count;
}

static DEVICE_ATTR(addr, S_IWUSR | S_IRUSR, bxtwc_reg_show, bxtwc_reg_store);
static DEVICE_ATTR(val, S_IWUSR | S_IRUSR, bxtwc_val_show, bxtwc_val_store);
static struct attribute *bxtwc_attrs[] = {
	&dev_attr_addr.attr,
	&dev_attr_val.attr,
	NULL
};

static const struct attribute_group bxtwc_group = {
	.attrs = bxtwc_attrs,
};

static const struct regmap_config bxtwc_regmap_config = {
	.reg_bits = 16,
	.val_bits = 8,
	.reg_write = regmap_ipc_byte_reg_write,
	.reg_read = regmap_ipc_byte_reg_read,
};

static int bxtwc_probe(struct platform_device *pdev)
{
	int ret;
	acpi_handle handle;
	acpi_status status;
	unsigned long long hrv;
	struct intel_soc_pmic *pmic;

	handle = ACPI_HANDLE(&pdev->dev);
	status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
	if (ACPI_FAILURE(status)) {
		dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n");
		return -ENODEV;
	}
	if (hrv != BROXTON_PMIC_WC_HRV) {
		dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n",
			hrv);
		return -ENODEV;
	}

	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
	if (!pmic)
		return -ENOMEM;

	ret = platform_get_irq(pdev, 0);
	if (ret < 0) {
		dev_err(&pdev->dev, "Invalid IRQ\n");
		return ret;
	}
	pmic->irq = ret;

	dev_set_drvdata(&pdev->dev, pmic);
	pmic->dev = &pdev->dev;

	pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic,
					&bxtwc_regmap_config);
	if (IS_ERR(pmic->regmap)) {
		ret = PTR_ERR(pmic->regmap);
		dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret);
		return ret;
	}

	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
				  IRQF_ONESHOT | IRQF_SHARED,
				  0, &bxtwc_regmap_irq_chip,
				  &pmic->irq_chip_data);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add IRQ chip\n");
		return ret;
	}

	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
				  IRQF_ONESHOT | IRQF_SHARED,
				  0, &bxtwc_regmap_irq_chip_level2,
				  &pmic->irq_chip_data_level2);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n");
		goto err_irq_chip_level2;
	}

	ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
			      ARRAY_SIZE(bxt_wc_dev), NULL, 0,
			      NULL);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add devices\n");
		goto err_mfd;
	}

	ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
	if (ret) {
		dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
		goto err_sysfs;
	}

	return 0;

err_sysfs:
	mfd_remove_devices(&pdev->dev);
err_mfd:
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
err_irq_chip_level2:
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);

	return ret;
}

static int bxtwc_remove(struct platform_device *pdev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);

	sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);
	mfd_remove_devices(&pdev->dev);
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);

	return 0;
}

static void bxtwc_shutdown(struct platform_device *pdev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);

	disable_irq(pmic->irq);
}

#ifdef CONFIG_PM_SLEEP
static int bxtwc_suspend(struct device *dev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	disable_irq(pmic->irq);

	return 0;
}

static int bxtwc_resume(struct device *dev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	enable_irq(pmic->irq);
	return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);

static const struct acpi_device_id bxtwc_acpi_ids[] = {
	{ "INT34D3", },
	{ }
};
MODULE_DEVICE_TABLE(acpi, pmic_acpi_ids);

static struct platform_driver bxtwc_driver = {
	.probe = bxtwc_probe,
	.remove	= bxtwc_remove,
	.shutdown = bxtwc_shutdown,
	.driver	= {
		.name	= "BXTWC PMIC",
		.pm     = &bxtwc_pm_ops,
		.acpi_match_table = ACPI_PTR(bxtwc_acpi_ids),
	},
};

module_platform_driver(bxtwc_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>");
Commit	Line	Data
39d047c0 QZ	1	/*
	2	* MFD core driver for Intel Broxton Whiskey Cove PMIC
	3	*
	4	* Copyright (C) 2015 Intel Corporation. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/acpi.h>
	18	#include <linux/err.h>
	19	#include <linux/delay.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/kernel.h>
	22	#include <linux/mfd/core.h>
	23	#include <linux/mfd/intel_bxtwc.h>
	24	#include <asm/intel_pmc_ipc.h>
	25
	26	/* PMIC device registers */
	27	#define REG_ADDR_MASK 0xFF00
	28	#define REG_ADDR_SHIFT 8
	29	#define REG_OFFSET_MASK 0xFF
	30
	31	/* Interrupt Status Registers */
	32	#define BXTWC_IRQLVL1 0x4E02
	33	#define BXTWC_PWRBTNIRQ 0x4E03
	34
	35	#define BXTWC_THRM0IRQ 0x4E04
	36	#define BXTWC_THRM1IRQ 0x4E05
	37	#define BXTWC_THRM2IRQ 0x4E06
	38	#define BXTWC_BCUIRQ 0x4E07
	39	#define BXTWC_ADCIRQ 0x4E08
	40	#define BXTWC_CHGR0IRQ 0x4E09
	41	#define BXTWC_CHGR1IRQ 0x4E0A
	42	#define BXTWC_GPIOIRQ0 0x4E0B
	43	#define BXTWC_GPIOIRQ1 0x4E0C
	44	#define BXTWC_CRITIRQ 0x4E0D
	45
	46	/* Interrupt MASK Registers */
	47	#define BXTWC_MIRQLVL1 0x4E0E
	48	#define BXTWC_MPWRTNIRQ 0x4E0F
	49
	50	#define BXTWC_MTHRM0IRQ 0x4E12
	51	#define BXTWC_MTHRM1IRQ 0x4E13
	52	#define BXTWC_MTHRM2IRQ 0x4E14
	53	#define BXTWC_MBCUIRQ 0x4E15
	54	#define BXTWC_MADCIRQ 0x4E16
	55	#define BXTWC_MCHGR0IRQ 0x4E17
	56	#define BXTWC_MCHGR1IRQ 0x4E18
	57	#define BXTWC_MGPIO0IRQ 0x4E19
	58	#define BXTWC_MGPIO1IRQ 0x4E1A
	59	#define BXTWC_MCRITIRQ 0x4E1B
	60
	61	/* Whiskey Cove PMIC share same ACPI ID between different platforms */
	62	#define BROXTON_PMIC_WC_HRV 4
	63
	64	/* Manage in two IRQ chips since mask registers are not consecutive */
65	enum bxtwc_irqs {
66	/* Level 1 */
67	BXTWC_PWRBTN_LVL1_IRQ = 0,
68	BXTWC_TMU_LVL1_IRQ,
69	BXTWC_THRM_LVL1_IRQ,
70	BXTWC_BCU_LVL1_IRQ,
71	BXTWC_ADC_LVL1_IRQ,
72	BXTWC_CHGR_LVL1_IRQ,
73	BXTWC_GPIO_LVL1_IRQ,
74	BXTWC_CRIT_LVL1_IRQ,
75
76	/* Level 2 */
77	BXTWC_PWRBTN_IRQ,
78	};
79
80	enum bxtwc_irqs_level2 {
81	/* Level 2 */
82	BXTWC_THRM0_IRQ = 0,
83	BXTWC_THRM1_IRQ,
84	BXTWC_THRM2_IRQ,
85	BXTWC_BCU_IRQ,
86	BXTWC_ADC_IRQ,
87	BXTWC_CHGR0_IRQ,
88	BXTWC_CHGR1_IRQ,
89	BXTWC_GPIO0_IRQ,
90	BXTWC_GPIO1_IRQ,
91	BXTWC_CRIT_IRQ,
92	};
93
94	static const struct regmap_irq bxtwc_regmap_irqs[] = {
95	REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
96	REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
97	REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
98	REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
99	REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
100	REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
101	REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
102	REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
103	REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03),
104	};
105
106	static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
107	REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff),
108	REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf),
109	REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff),
110	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f),
111	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff),
112	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f),
113	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f),
114	REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff),
115	REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f),
116	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03),
117	};
118
119	static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
120	.name = "bxtwc_irq_chip",
121	.status_base = BXTWC_IRQLVL1,
122	.mask_base = BXTWC_MIRQLVL1,
123	.irqs = bxtwc_regmap_irqs,
124	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
125	.num_regs = 2,
126	};
127
128	static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
129	.name = "bxtwc_irq_chip_level2",
130	.status_base = BXTWC_THRM0IRQ,
131	.mask_base = BXTWC_MTHRM0IRQ,
132	.irqs = bxtwc_regmap_irqs_level2,
133	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
134	.num_regs = 10,
135	};
136
137	static struct resource gpio_resources[] = {
138	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"),
139	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"),
140	};
141
142	static struct resource adc_resources[] = {
143	DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
144	};
145
146	static struct resource charger_resources[] = {
147	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
148	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
149	};
150
151	static struct resource thermal_resources[] = {
152	DEFINE_RES_IRQ(BXTWC_THRM0_IRQ),
153	DEFINE_RES_IRQ(BXTWC_THRM1_IRQ),
154	DEFINE_RES_IRQ(BXTWC_THRM2_IRQ),
155	};
156
157	static struct resource bcu_resources[] = {
158	DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
159	};
160
161	static struct mfd_cell bxt_wc_dev[] = {
162	{
163	.name = "bxt_wcove_gpadc",
164	.num_resources = ARRAY_SIZE(adc_resources),
165	.resources = adc_resources,
166	},
167	{
168	.name = "bxt_wcove_thermal",
169	.num_resources = ARRAY_SIZE(thermal_resources),
170	.resources = thermal_resources,
171	},
172	{
173	.name = "bxt_wcove_ext_charger",
174	.num_resources = ARRAY_SIZE(charger_resources),
175	.resources = charger_resources,
176	},
177	{
178	.name = "bxt_wcove_bcu",
179	.num_resources = ARRAY_SIZE(bcu_resources),
180	.resources = bcu_resources,
181	},
182	{
183	.name = "bxt_wcove_gpio",
184	.num_resources = ARRAY_SIZE(gpio_resources),
185	.resources = gpio_resources,
186	},
187	{
188	.name = "bxt_wcove_region",
189	},
190	};
191
192	static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
193	unsigned int *val)
194	{
195	int ret;
196	int i2c_addr;
197	u8 ipc_in[2];
198	u8 ipc_out[4];
199	struct intel_soc_pmic *pmic = context;
200
201	if (reg & REG_ADDR_MASK)
202	i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
203	else {
204	i2c_addr = BXTWC_DEVICE1_ADDR;
205	if (!i2c_addr) {
206	dev_err(pmic->dev, "I2C address not set\n");
207	return -EINVAL;
208	}
209	}
210	reg &= REG_OFFSET_MASK;
211
212	ipc_in[0] = reg;
213	ipc_in[1] = i2c_addr;
214	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
215	PMC_IPC_PMIC_ACCESS_READ,
216	ipc_in, sizeof(ipc_in), (u32 *)ipc_out, 1);
217	if (ret) {
218	dev_err(pmic->dev, "Failed to read from PMIC\n");
219	return ret;
220	}
221	*val = ipc_out[0];
222
223	return 0;
224	}
225
226	static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
227	unsigned int val)
228	{
229	int ret;
230	int i2c_addr;
231	u8 ipc_in[3];
232	struct intel_soc_pmic *pmic = context;
233
234	if (reg & REG_ADDR_MASK)
235	i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
236	else {
237	i2c_addr = BXTWC_DEVICE1_ADDR;
238	if (!i2c_addr) {
239	dev_err(pmic->dev, "I2C address not set\n");
240	return -EINVAL;
241	}
242	}
243	reg &= REG_OFFSET_MASK;
244
245	ipc_in[0] = reg;
246	ipc_in[1] = i2c_addr;
247	ipc_in[2] = val;
248	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
249	PMC_IPC_PMIC_ACCESS_WRITE,
250	ipc_in, sizeof(ipc_in), NULL, 0);
251	if (ret) {
252	dev_err(pmic->dev, "Failed to write to PMIC\n");
253	return ret;
254	}
255
256	return 0;
257	}
258
259	/* sysfs interfaces to r/w PMIC registers, required by initial script */
260	static unsigned long bxtwc_reg_addr;
261	static ssize_t bxtwc_reg_show(struct device *dev,
262	struct device_attribute attr, char buf)
263	{
264	return sprintf(buf, "0x%lx\n", bxtwc_reg_addr);
265	}
266
267	static ssize_t bxtwc_reg_store(struct device *dev,
268	struct device_attribute attr, const char buf, size_t count)
269	{
270	if (kstrtoul(buf, 0, &bxtwc_reg_addr)) {
271	dev_err(dev, "Invalid register address\n");
272	return -EINVAL;
273	}
274	return (ssize_t)count;
275	}
276
277	static ssize_t bxtwc_val_show(struct device *dev,
278	struct device_attribute attr, char buf)
279	{
280	int ret;
281	unsigned int val;
282	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
283
284	ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
285	if (ret < 0) {
286	dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
287	return -EIO;
288	}
289
290	return sprintf(buf, "0x%02x\n", val);
291	}
292
293	static ssize_t bxtwc_val_store(struct device *dev,
294	struct device_attribute attr, const char buf, size_t count)
295	{
296	int ret;
297	unsigned int val;
298	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
299
f3a654c5 DC	300	ret = kstrtouint(buf, 0, &val);
	301	if (ret)
	302	return ret;
39d047c0 QZ	303
	304	ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
	305	if (ret) {
	306	dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
	307	val, bxtwc_reg_addr);
	308	return -EIO;
	309	}
	310	return count;
	311	}
	312
	313	static DEVICE_ATTR(addr, S_IWUSR \| S_IRUSR, bxtwc_reg_show, bxtwc_reg_store);
	314	static DEVICE_ATTR(val, S_IWUSR \| S_IRUSR, bxtwc_val_show, bxtwc_val_store);
	315	static struct attribute *bxtwc_attrs[] = {
	316	&dev_attr_addr.attr,
	317	&dev_attr_val.attr,
	318	NULL
	319	};
	320
	321	static const struct attribute_group bxtwc_group = {
	322	.attrs = bxtwc_attrs,
	323	};
	324
	325	static const struct regmap_config bxtwc_regmap_config = {
	326	.reg_bits = 16,
	327	.val_bits = 8,
	328	.reg_write = regmap_ipc_byte_reg_write,
	329	.reg_read = regmap_ipc_byte_reg_read,
	330	};
	331
	332	static int bxtwc_probe(struct platform_device *pdev)
	333	{
	334	int ret;
	335	acpi_handle handle;
	336	acpi_status status;
	337	unsigned long long hrv;
	338	struct intel_soc_pmic *pmic;
	339
	340	handle = ACPI_HANDLE(&pdev->dev);
	341	status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
	342	if (ACPI_FAILURE(status)) {
	343	dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n");
	344	return -ENODEV;
	345	}
	346	if (hrv != BROXTON_PMIC_WC_HRV) {
	347	dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n",
	348	hrv);
	349	return -ENODEV;
	350	}
	351
	352	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
	353	if (!pmic)
	354	return -ENOMEM;
	355
	356	ret = platform_get_irq(pdev, 0);
	357	if (ret < 0) {
	358	dev_err(&pdev->dev, "Invalid IRQ\n");
	359	return ret;
	360	}
	361	pmic->irq = ret;
	362
	363	dev_set_drvdata(&pdev->dev, pmic);
	364	pmic->dev = &pdev->dev;
	365
	366	pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic,
367	&bxtwc_regmap_config);
368	if (IS_ERR(pmic->regmap)) {
369	ret = PTR_ERR(pmic->regmap);
370	dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret);
371	return ret;
372	}
373
374	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
375	IRQF_ONESHOT \| IRQF_SHARED,
376	0, &bxtwc_regmap_irq_chip,
377	&pmic->irq_chip_data);
378	if (ret) {
379	dev_err(&pdev->dev, "Failed to add IRQ chip\n");
380	return ret;
381	}
382
383	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
384	IRQF_ONESHOT \| IRQF_SHARED,
385	0, &bxtwc_regmap_irq_chip_level2,
386	&pmic->irq_chip_data_level2);
387	if (ret) {
388	dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n");
389	goto err_irq_chip_level2;
390	}
391
392	ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
393	ARRAY_SIZE(bxt_wc_dev), NULL, 0,
394	NULL);
395	if (ret) {
396	dev_err(&pdev->dev, "Failed to add devices\n");
397	goto err_mfd;
398	}
399
400	ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
401	if (ret) {
402	dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
403	goto err_sysfs;
404	}
405
406	return 0;
407
408	err_sysfs:
409	mfd_remove_devices(&pdev->dev);
410	err_mfd:
411	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
412	err_irq_chip_level2:
413	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
414
415	return ret;
416	}
417
418	static int bxtwc_remove(struct platform_device *pdev)
419	{
420	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);
421
422	sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);
423	mfd_remove_devices(&pdev->dev);
424	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
425	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
426
427	return 0;
428	}
429
430	static void bxtwc_shutdown(struct platform_device *pdev)
431	{
432	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);
433
434	disable_irq(pmic->irq);
435	}
436
437	#ifdef CONFIG_PM_SLEEP
438	static int bxtwc_suspend(struct device *dev)
439	{
440	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
441
442	disable_irq(pmic->irq);
443
444	return 0;
445	}
446
447	static int bxtwc_resume(struct device *dev)
448	{
449	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
450
451	enable_irq(pmic->irq);
452	return 0;
453	}
454	#endif
455	static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);
456
457	static const struct acpi_device_id bxtwc_acpi_ids[] = {
458	{ "INT34D3", },
459	{ }
460	};
461	MODULE_DEVICE_TABLE(acpi, pmic_acpi_ids);
462
463	static struct platform_driver bxtwc_driver = {
464	.probe = bxtwc_probe,
465	.remove = bxtwc_remove,
466	.shutdown = bxtwc_shutdown,
467	.driver = {
468	.name = "BXTWC PMIC",
469	.pm = &bxtwc_pm_ops,
470	.acpi_match_table = ACPI_PTR(bxtwc_acpi_ids),
471	},
472	};
473
474	module_platform_driver(bxtwc_driver);
475
476	MODULE_LICENSE("GPL v2");
477	MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>");