[linux-2.6-block.git] / drivers / mfd / intel-lpss.c

/*
 * Intel Sunrisepoint LPSS core support.
 *
 * Copyright (C) 2015, Intel Corporation
 *
 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 *          Mika Westerberg <mika.westerberg@linux.intel.com>
 *          Heikki Krogerus <heikki.krogerus@linux.intel.com>
 *          Jarkko Nikula <jarkko.nikula@linux.intel.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/debugfs.h>
#include <linux/idr.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mfd/core.h>
#include <linux/pm_qos.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/seq_file.h>
#include <linux/io-64-nonatomic-lo-hi.h>

#include "intel-lpss.h"

#define LPSS_DEV_OFFSET		0x000
#define LPSS_DEV_SIZE		0x200
#define LPSS_PRIV_OFFSET	0x200
#define LPSS_PRIV_SIZE		0x100
#define LPSS_IDMA64_OFFSET	0x800
#define LPSS_IDMA64_SIZE	0x800

/* Offsets from lpss->priv */
#define LPSS_PRIV_RESETS		0x04
#define LPSS_PRIV_RESETS_FUNC		BIT(2)
#define LPSS_PRIV_RESETS_IDMA		0x3

#define LPSS_PRIV_ACTIVELTR		0x10
#define LPSS_PRIV_IDLELTR		0x14

#define LPSS_PRIV_LTR_REQ		BIT(15)
#define LPSS_PRIV_LTR_SCALE_MASK	0xc00
#define LPSS_PRIV_LTR_SCALE_1US		0x800
#define LPSS_PRIV_LTR_SCALE_32US	0xc00
#define LPSS_PRIV_LTR_VALUE_MASK	0x3ff

#define LPSS_PRIV_SSP_REG		0x20
#define LPSS_PRIV_SSP_REG_DIS_DMA_FIN	BIT(0)

#define LPSS_PRIV_REMAP_ADDR		0x40

#define LPSS_PRIV_CAPS			0xfc
#define LPSS_PRIV_CAPS_NO_IDMA		BIT(8)
#define LPSS_PRIV_CAPS_TYPE_SHIFT	4
#define LPSS_PRIV_CAPS_TYPE_MASK	(0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)

/* This matches the type field in CAPS register */
enum intel_lpss_dev_type {
	LPSS_DEV_I2C = 0,
	LPSS_DEV_UART,
	LPSS_DEV_SPI,
};

struct intel_lpss {
	const struct intel_lpss_platform_info *info;
	enum intel_lpss_dev_type type;
	struct clk *clk;
	struct clk_lookup *clock;
	struct mfd_cell *cell;
	struct device *dev;
	void __iomem *priv;
	int devid;
	u32 caps;
	u32 active_ltr;
	u32 idle_ltr;
	struct dentry *debugfs;
};

static const struct resource intel_lpss_dev_resources[] = {
	DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
	DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
	DEFINE_RES_IRQ(0),
};

static const struct resource intel_lpss_idma64_resources[] = {
	DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
	DEFINE_RES_IRQ(0),
};

#define LPSS_IDMA64_DRIVER_NAME		"idma64"

/*
 * Cells needs to be ordered so that the iDMA is created first. This is
 * because we need to be sure the DMA is available when the host controller
 * driver is probed.
 */
static const struct mfd_cell intel_lpss_idma64_cell = {
	.name = LPSS_IDMA64_DRIVER_NAME,
	.num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
	.resources = intel_lpss_idma64_resources,
};

static const struct mfd_cell intel_lpss_i2c_cell = {
	.name = "i2c_designware",
	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	.resources = intel_lpss_dev_resources,
};

static const struct mfd_cell intel_lpss_uart_cell = {
	.name = "dw-apb-uart",
	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	.resources = intel_lpss_dev_resources,
};

static const struct mfd_cell intel_lpss_spi_cell = {
	.name = "pxa2xx-spi",
	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	.resources = intel_lpss_dev_resources,
};

static DEFINE_IDA(intel_lpss_devid_ida);
static struct dentry *intel_lpss_debugfs;

static int intel_lpss_request_dma_module(const char *name)
{
	static bool intel_lpss_dma_requested;

	if (intel_lpss_dma_requested)
		return 0;

	intel_lpss_dma_requested = true;
	return request_module("%s", name);
}

static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
{
	lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
	lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
}

static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
{
	struct dentry *dir;

	dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
	if (IS_ERR(dir))
		return PTR_ERR(dir);

	/* Cache the values into lpss structure */
	intel_lpss_cache_ltr(lpss);

	debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
	debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
	debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);

	lpss->debugfs = dir;
	return 0;
}

static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
{
	debugfs_remove_recursive(lpss->debugfs);
}

static void intel_lpss_ltr_set(struct device *dev, s32 val)
{
	struct intel_lpss *lpss = dev_get_drvdata(dev);
	u32 ltr;

	/*
	 * Program latency tolerance (LTR) accordingly what has been asked
	 * by the PM QoS layer or disable it in case we were passed
	 * negative value or PM_QOS_LATENCY_ANY.
	 */
	ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);

	if (val == PM_QOS_LATENCY_ANY || val < 0) {
		ltr &= ~LPSS_PRIV_LTR_REQ;
	} else {
		ltr |= LPSS_PRIV_LTR_REQ;
		ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
		ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;

		if (val > LPSS_PRIV_LTR_VALUE_MASK)
			ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
		else
			ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
	}

	if (ltr == lpss->active_ltr)
		return;

	writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
	writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);

	/* Cache the values into lpss structure */
	intel_lpss_cache_ltr(lpss);
}

static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
{
	lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
	dev_pm_qos_expose_latency_tolerance(lpss->dev);
}

static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
{
	dev_pm_qos_hide_latency_tolerance(lpss->dev);
	lpss->dev->power.set_latency_tolerance = NULL;
}

static int intel_lpss_assign_devs(struct intel_lpss *lpss)
{
	const struct mfd_cell *cell;
	unsigned int type;

	type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
	type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;

	switch (type) {
	case LPSS_DEV_I2C:
		cell = &intel_lpss_i2c_cell;
		break;
	case LPSS_DEV_UART:
		cell = &intel_lpss_uart_cell;
		break;
	case LPSS_DEV_SPI:
		cell = &intel_lpss_spi_cell;
		break;
	default:
		return -ENODEV;
	}

	lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
	if (!lpss->cell)
		return -ENOMEM;

	lpss->type = type;

	return 0;
}

static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
{
	return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
}

static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
{
	resource_size_t addr = lpss->info->mem->start;

	lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
}

static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
{
	u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;

	/* Bring out the device from reset */
	writel(value, lpss->priv + LPSS_PRIV_RESETS);
}

static void intel_lpss_init_dev(const struct intel_lpss *lpss)
{
	u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;

	intel_lpss_deassert_reset(lpss);

	if (!intel_lpss_has_idma(lpss))
		return;

	intel_lpss_set_remap_addr(lpss);

	/* Make sure that SPI multiblock DMA transfers are re-enabled */
	if (lpss->type == LPSS_DEV_SPI)
		writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
}

static void intel_lpss_unregister_clock_tree(struct clk *clk)
{
	struct clk *parent;

	while (clk) {
		parent = clk_get_parent(clk);
		clk_unregister(clk);
		clk = parent;
	}
}

static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
					     const char *devname,
					     struct clk **clk)
{
	char name[32];
	struct clk *tmp = *clk;

	snprintf(name, sizeof(name), "%s-enable", devname);
	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
				lpss->priv, 0, 0, NULL);
	if (IS_ERR(tmp))
		return PTR_ERR(tmp);

	snprintf(name, sizeof(name), "%s-div", devname);
	tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
					      0, lpss->priv, 1, 15, 16, 15, 0,
					      NULL);
	if (IS_ERR(tmp))
		return PTR_ERR(tmp);
	*clk = tmp;

	snprintf(name, sizeof(name), "%s-update", devname);
	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
				CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
	if (IS_ERR(tmp))
		return PTR_ERR(tmp);
	*clk = tmp;

	return 0;
}

static int intel_lpss_register_clock(struct intel_lpss *lpss)
{
	const struct mfd_cell *cell = lpss->cell;
	struct clk *clk;
	char devname[24];
	int ret;

	if (!lpss->info->clk_rate)
		return 0;

	/* Root clock */
	clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL,
				      CLK_IS_ROOT, lpss->info->clk_rate);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);

	/*
	 * Support for clock divider only if it has some preset value.
	 * Otherwise we assume that the divider is not used.
	 */
	if (lpss->type != LPSS_DEV_I2C) {
		ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
		if (ret)
			goto err_clk_register;
	}

	ret = -ENOMEM;

	/* Clock for the host controller */
	lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
	if (!lpss->clock)
		goto err_clk_register;

	lpss->clk = clk;

	return 0;

err_clk_register:
	intel_lpss_unregister_clock_tree(clk);

	return ret;
}

static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
{
	if (IS_ERR_OR_NULL(lpss->clk))
		return;

	clkdev_drop(lpss->clock);
	intel_lpss_unregister_clock_tree(lpss->clk);
}

int intel_lpss_probe(struct device *dev,
		     const struct intel_lpss_platform_info *info)
{
	struct intel_lpss *lpss;
	int ret;

	if (!info || !info->mem || info->irq <= 0)
		return -EINVAL;

	lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
	if (!lpss)
		return -ENOMEM;

	lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET,
				  LPSS_PRIV_SIZE);
	if (!lpss->priv)
		return -ENOMEM;

	lpss->info = info;
	lpss->dev = dev;
	lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);

	dev_set_drvdata(dev, lpss);

	ret = intel_lpss_assign_devs(lpss);
	if (ret)
		return ret;

	lpss->cell->properties = info->properties;

	intel_lpss_init_dev(lpss);

	lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
	if (lpss->devid < 0)
		return lpss->devid;

	ret = intel_lpss_register_clock(lpss);
	if (ret)
		goto err_clk_register;

	intel_lpss_ltr_expose(lpss);

	ret = intel_lpss_debugfs_add(lpss);
	if (ret)
		dev_warn(dev, "Failed to create debugfs entries\n");

	if (intel_lpss_has_idma(lpss)) {
		/*
		 * Ensure the DMA driver is loaded before the host
		 * controller device appears, so that the host controller
		 * driver can request its DMA channels as early as
		 * possible.
		 *
		 * If the DMA module is not there that's OK as well.
		 */
		intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);

		ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
				      1, info->mem, info->irq, NULL);
		if (ret)
			dev_warn(dev, "Failed to add %s, fallback to PIO\n",
				 LPSS_IDMA64_DRIVER_NAME);
	}

	ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
			      1, info->mem, info->irq, NULL);
	if (ret)
		goto err_remove_ltr;

	return 0;

err_remove_ltr:
	intel_lpss_debugfs_remove(lpss);
	intel_lpss_ltr_hide(lpss);
	intel_lpss_unregister_clock(lpss);

err_clk_register:
	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);

	return ret;
}
EXPORT_SYMBOL_GPL(intel_lpss_probe);

void intel_lpss_remove(struct device *dev)
{
	struct intel_lpss *lpss = dev_get_drvdata(dev);

	mfd_remove_devices(dev);
	intel_lpss_debugfs_remove(lpss);
	intel_lpss_ltr_hide(lpss);
	intel_lpss_unregister_clock(lpss);
	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
}
EXPORT_SYMBOL_GPL(intel_lpss_remove);

static int resume_lpss_device(struct device *dev, void *data)
{
	pm_runtime_resume(dev);
	return 0;
}

int intel_lpss_prepare(struct device *dev)
{
	/*
	 * Resume both child devices before entering system sleep. This
	 * ensures that they are in proper state before they get suspended.
	 */
	device_for_each_child_reverse(dev, NULL, resume_lpss_device);
	return 0;
}
EXPORT_SYMBOL_GPL(intel_lpss_prepare);

int intel_lpss_suspend(struct device *dev)
{
	return 0;
}
EXPORT_SYMBOL_GPL(intel_lpss_suspend);

int intel_lpss_resume(struct device *dev)
{
	struct intel_lpss *lpss = dev_get_drvdata(dev);

	intel_lpss_init_dev(lpss);

	return 0;
}
EXPORT_SYMBOL_GPL(intel_lpss_resume);

static int __init intel_lpss_init(void)
{
	intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
	return 0;
}
module_init(intel_lpss_init);

static void __exit intel_lpss_exit(void)
{
	debugfs_remove(intel_lpss_debugfs);
}
module_exit(intel_lpss_exit);

MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
MODULE_DESCRIPTION("Intel LPSS core driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
4b45efe8 AS	1	/*
	2	* Intel Sunrisepoint LPSS core support.
	3	*
	4	* Copyright (C) 2015, Intel Corporation
	5	*
	6	* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
	7	* Mika Westerberg <mika.westerberg@linux.intel.com>
	8	* Heikki Krogerus <heikki.krogerus@linux.intel.com>
	9	* Jarkko Nikula <jarkko.nikula@linux.intel.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/clk.h>
	17	#include <linux/clkdev.h>
	18	#include <linux/clk-provider.h>
	19	#include <linux/debugfs.h>
	20	#include <linux/idr.h>
	21	#include <linux/ioport.h>
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/mfd/core.h>
	25	#include <linux/pm_qos.h>
	26	#include <linux/pm_runtime.h>
e15ad215	27	#include <linux/property.h>
4b45efe8	28	#include <linux/seq_file.h>
9cf5c095	29	#include <linux/io-64-nonatomic-lo-hi.h>
689d4453	30
4b45efe8 AS	31	#include "intel-lpss.h"
	32
	33	#define LPSS_DEV_OFFSET 0x000
	34	#define LPSS_DEV_SIZE 0x200
	35	#define LPSS_PRIV_OFFSET 0x200
	36	#define LPSS_PRIV_SIZE 0x100
	37	#define LPSS_IDMA64_OFFSET 0x800
	38	#define LPSS_IDMA64_SIZE 0x800
	39
	40	/* Offsets from lpss->priv */
	41	#define LPSS_PRIV_RESETS 0x04
	42	#define LPSS_PRIV_RESETS_FUNC BIT(2)
	43	#define LPSS_PRIV_RESETS_IDMA 0x3
	44
	45	#define LPSS_PRIV_ACTIVELTR 0x10
	46	#define LPSS_PRIV_IDLELTR 0x14
	47
	48	#define LPSS_PRIV_LTR_REQ BIT(15)
	49	#define LPSS_PRIV_LTR_SCALE_MASK 0xc00
	50	#define LPSS_PRIV_LTR_SCALE_1US 0x800
	51	#define LPSS_PRIV_LTR_SCALE_32US 0xc00
	52	#define LPSS_PRIV_LTR_VALUE_MASK 0x3ff
	53
	54	#define LPSS_PRIV_SSP_REG 0x20
	55	#define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
	56
689d4453	57	#define LPSS_PRIV_REMAP_ADDR 0x40
4b45efe8 AS	58
	59	#define LPSS_PRIV_CAPS 0xfc
	60	#define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
	61	#define LPSS_PRIV_CAPS_TYPE_SHIFT 4
	62	#define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
	63
	64	/* This matches the type field in CAPS register */
	65	enum intel_lpss_dev_type {
	66	LPSS_DEV_I2C = 0,
	67	LPSS_DEV_UART,
	68	LPSS_DEV_SPI,
	69	};
	70
	71	struct intel_lpss {
	72	const struct intel_lpss_platform_info *info;
	73	enum intel_lpss_dev_type type;
	74	struct clk *clk;
	75	struct clk_lookup *clock;
e15ad215	76	struct mfd_cell *cell;
4b45efe8 AS	77	struct device *dev;
	78	void __iomem *priv;
	79	int devid;
	80	u32 caps;
	81	u32 active_ltr;
	82	u32 idle_ltr;
	83	struct dentry *debugfs;
	84	};
	85
	86	static const struct resource intel_lpss_dev_resources[] = {
	87	DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
	88	DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
	89	DEFINE_RES_IRQ(0),
	90	};
	91
	92	static const struct resource intel_lpss_idma64_resources[] = {
	93	DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
	94	DEFINE_RES_IRQ(0),
	95	};
	96
	97	#define LPSS_IDMA64_DRIVER_NAME "idma64"
	98
	99	/*
	100	* Cells needs to be ordered so that the iDMA is created first. This is
	101	* because we need to be sure the DMA is available when the host controller
	102	* driver is probed.
	103	*/
	104	static const struct mfd_cell intel_lpss_idma64_cell = {
	105	.name = LPSS_IDMA64_DRIVER_NAME,
	106	.num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
	107	.resources = intel_lpss_idma64_resources,
	108	};
	109
	110	static const struct mfd_cell intel_lpss_i2c_cell = {
	111	.name = "i2c_designware",
	112	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	113	.resources = intel_lpss_dev_resources,
	114	};
	115
	116	static const struct mfd_cell intel_lpss_uart_cell = {
	117	.name = "dw-apb-uart",
	118	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	119	.resources = intel_lpss_dev_resources,
	120	};
	121
	122	static const struct mfd_cell intel_lpss_spi_cell = {
	123	.name = "pxa2xx-spi",
	124	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	125	.resources = intel_lpss_dev_resources,
	126	};
	127
	128	static DEFINE_IDA(intel_lpss_devid_ida);
	129	static struct dentry *intel_lpss_debugfs;
	130
	131	static int intel_lpss_request_dma_module(const char *name)
	132	{
	133	static bool intel_lpss_dma_requested;
	134
	135	if (intel_lpss_dma_requested)
	136	return 0;
	137
	138	intel_lpss_dma_requested = true;
	139	return request_module("%s", name);
	140	}
141
142	static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
143	{
144	lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
145	lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
146	}
147
148	static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
149	{
150	struct dentry *dir;
151
152	dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
153	if (IS_ERR(dir))
154	return PTR_ERR(dir);
155
156	/* Cache the values into lpss structure */
157	intel_lpss_cache_ltr(lpss);
158
159	debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
160	debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
161	debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
162
163	lpss->debugfs = dir;
164	return 0;
165	}
166
167	static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
168	{
169	debugfs_remove_recursive(lpss->debugfs);
170	}
171
172	static void intel_lpss_ltr_set(struct device *dev, s32 val)
173	{
174	struct intel_lpss *lpss = dev_get_drvdata(dev);
175	u32 ltr;
176
177	/*
178	* Program latency tolerance (LTR) accordingly what has been asked
179	* by the PM QoS layer or disable it in case we were passed
180	* negative value or PM_QOS_LATENCY_ANY.
181	*/
182	ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
183
184	if (val == PM_QOS_LATENCY_ANY \|\| val < 0) {
185	ltr &= ~LPSS_PRIV_LTR_REQ;
186	} else {
187	ltr \|= LPSS_PRIV_LTR_REQ;
188	ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
189	ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
190
191	if (val > LPSS_PRIV_LTR_VALUE_MASK)
192	ltr \|= LPSS_PRIV_LTR_SCALE_32US \| val >> 5;
193	else
194	ltr \|= LPSS_PRIV_LTR_SCALE_1US \| val;
195	}
196
197	if (ltr == lpss->active_ltr)
198	return;
199
200	writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
201	writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
202
203	/* Cache the values into lpss structure */
204	intel_lpss_cache_ltr(lpss);
205	}
206
207	static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
208	{
209	lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
210	dev_pm_qos_expose_latency_tolerance(lpss->dev);
211	}
212
213	static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
214	{
215	dev_pm_qos_hide_latency_tolerance(lpss->dev);
216	lpss->dev->power.set_latency_tolerance = NULL;
217	}
218
219	static int intel_lpss_assign_devs(struct intel_lpss *lpss)
220	{
e15ad215	221	const struct mfd_cell *cell;
4b45efe8 AS	222	unsigned int type;
	223
	224	type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
	225	type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
	226
	227	switch (type) {
	228	case LPSS_DEV_I2C:
e15ad215	229	cell = &intel_lpss_i2c_cell;
4b45efe8 AS	230	break;
4b45efe8 AS	231	case LPSS_DEV_UART:
e15ad215	232	cell = &intel_lpss_uart_cell;
4b45efe8 AS	233	break;
4b45efe8 AS	234	case LPSS_DEV_SPI:
e15ad215	235	cell = &intel_lpss_spi_cell;
4b45efe8 AS	236	break;
	237	default:
	238	return -ENODEV;
	239	}
	240
e15ad215 MW	241	lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
	242	if (!lpss->cell)
	243	return -ENOMEM;
	244
4b45efe8 AS	245	lpss->type = type;
	246
	247	return 0;
	248	}
	249
	250	static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
	251	{
	252	return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
	253	}
	254
	255	static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
	256	{
	257	resource_size_t addr = lpss->info->mem->start;
	258
689d4453	259	lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
4b45efe8 AS	260	}
	261
	262	static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
	263	{
	264	u32 value = LPSS_PRIV_RESETS_FUNC \| LPSS_PRIV_RESETS_IDMA;
	265
	266	/* Bring out the device from reset */
	267	writel(value, lpss->priv + LPSS_PRIV_RESETS);
	268	}
	269
	270	static void intel_lpss_init_dev(const struct intel_lpss *lpss)
	271	{
	272	u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
	273
	274	intel_lpss_deassert_reset(lpss);
	275
	276	if (!intel_lpss_has_idma(lpss))
	277	return;
	278
	279	intel_lpss_set_remap_addr(lpss);
	280
	281	/* Make sure that SPI multiblock DMA transfers are re-enabled */
	282	if (lpss->type == LPSS_DEV_SPI)
	283	writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
	284	}
	285
	286	static void intel_lpss_unregister_clock_tree(struct clk *clk)
	287	{
	288	struct clk *parent;
	289
	290	while (clk) {
	291	parent = clk_get_parent(clk);
	292	clk_unregister(clk);
	293	clk = parent;
	294	}
	295	}
	296
	297	static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
	298	const char *devname,
	299	struct clk **clk)
	300	{
	301	char name[32];
	302	struct clk tmp = clk;
	303
	304	snprintf(name, sizeof(name), "%s-enable", devname);
	305	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
	306	lpss->priv, 0, 0, NULL);
	307	if (IS_ERR(tmp))
	308	return PTR_ERR(tmp);
	309
	310	snprintf(name, sizeof(name), "%s-div", devname);
	311	tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
	312	0, lpss->priv, 1, 15, 16, 15, 0,
	313	NULL);
	314	if (IS_ERR(tmp))
	315	return PTR_ERR(tmp);
	316	*clk = tmp;
	317
	318	snprintf(name, sizeof(name), "%s-update", devname);
	319	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
	320	CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
	321	if (IS_ERR(tmp))
	322	return PTR_ERR(tmp);
	323	*clk = tmp;
324
325	return 0;
326	}
327
328	static int intel_lpss_register_clock(struct intel_lpss *lpss)
329	{
330	const struct mfd_cell *cell = lpss->cell;
331	struct clk *clk;
332	char devname[24];
333	int ret;
334
335	if (!lpss->info->clk_rate)
336	return 0;
337
338	/* Root clock */
339	clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL,
340	CLK_IS_ROOT, lpss->info->clk_rate);
341	if (IS_ERR(clk))
342	return PTR_ERR(clk);
343
344	snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
345
346	/*
347	* Support for clock divider only if it has some preset value.
348	* Otherwise we assume that the divider is not used.
349	*/
350	if (lpss->type != LPSS_DEV_I2C) {
351	ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
352	if (ret)
353	goto err_clk_register;
354	}
355
356	ret = -ENOMEM;
357
358	/* Clock for the host controller */
359	lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
360	if (!lpss->clock)
361	goto err_clk_register;
362
363	lpss->clk = clk;
364
365	return 0;
366
367	err_clk_register:
368	intel_lpss_unregister_clock_tree(clk);
369
370	return ret;
371	}
372
373	static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
374	{
375	if (IS_ERR_OR_NULL(lpss->clk))
376	return;
377
378	clkdev_drop(lpss->clock);
379	intel_lpss_unregister_clock_tree(lpss->clk);
380	}
381
382	int intel_lpss_probe(struct device *dev,
383	const struct intel_lpss_platform_info *info)
384	{
385	struct intel_lpss *lpss;
386	int ret;
387
388	if (!info \|\| !info->mem \|\| info->irq <= 0)
389	return -EINVAL;
390
391	lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
392	if (!lpss)
393	return -ENOMEM;
394
395	lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET,
396	LPSS_PRIV_SIZE);
397	if (!lpss->priv)
398	return -ENOMEM;
399
400	lpss->info = info;
401	lpss->dev = dev;
402	lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
403
404	dev_set_drvdata(dev, lpss);
405
406	ret = intel_lpss_assign_devs(lpss);
407	if (ret)
408	return ret;
409
f4d05266	410	lpss->cell->properties = info->properties;
e15ad215	411
4b45efe8 AS	412	intel_lpss_init_dev(lpss);
	413
	414	lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
	415	if (lpss->devid < 0)
	416	return lpss->devid;
	417
	418	ret = intel_lpss_register_clock(lpss);
	419	if (ret)
	420	goto err_clk_register;
	421
	422	intel_lpss_ltr_expose(lpss);
	423
	424	ret = intel_lpss_debugfs_add(lpss);
	425	if (ret)
	426	dev_warn(dev, "Failed to create debugfs entries\n");
	427
	428	if (intel_lpss_has_idma(lpss)) {
	429	/*
	430	* Ensure the DMA driver is loaded before the host
	431	* controller device appears, so that the host controller
	432	* driver can request its DMA channels as early as
	433	* possible.
	434	*
	435	* If the DMA module is not there that's OK as well.
	436	*/
	437	intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);
	438
	439	ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
	440	1, info->mem, info->irq, NULL);
	441	if (ret)
	442	dev_warn(dev, "Failed to add %s, fallback to PIO\n",
	443	LPSS_IDMA64_DRIVER_NAME);
	444	}
	445
	446	ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
	447	1, info->mem, info->irq, NULL);
	448	if (ret)
	449	goto err_remove_ltr;
	450
	451	return 0;
	452
	453	err_remove_ltr:
	454	intel_lpss_debugfs_remove(lpss);
	455	intel_lpss_ltr_hide(lpss);
84cb36ca	456	intel_lpss_unregister_clock(lpss);
4b45efe8 AS	457
	458	err_clk_register:
	459	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
	460
	461	return ret;
	462	}
	463	EXPORT_SYMBOL_GPL(intel_lpss_probe);
	464
	465	void intel_lpss_remove(struct device *dev)
	466	{
	467	struct intel_lpss *lpss = dev_get_drvdata(dev);
	468
	469	mfd_remove_devices(dev);
	470	intel_lpss_debugfs_remove(lpss);
	471	intel_lpss_ltr_hide(lpss);
	472	intel_lpss_unregister_clock(lpss);
	473	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
	474	}
	475	EXPORT_SYMBOL_GPL(intel_lpss_remove);
	476
	477	static int resume_lpss_device(struct device dev, void data)
	478	{
	479	pm_runtime_resume(dev);
	480	return 0;
	481	}
	482
	483	int intel_lpss_prepare(struct device *dev)
	484	{
	485	/*
	486	* Resume both child devices before entering system sleep. This
	487	* ensures that they are in proper state before they get suspended.
	488	*/
	489	device_for_each_child_reverse(dev, NULL, resume_lpss_device);
	490	return 0;
	491	}
	492	EXPORT_SYMBOL_GPL(intel_lpss_prepare);
	493
	494	int intel_lpss_suspend(struct device *dev)
	495	{
	496	return 0;
	497	}
	498	EXPORT_SYMBOL_GPL(intel_lpss_suspend);
	499
	500	int intel_lpss_resume(struct device *dev)
	501	{
	502	struct intel_lpss *lpss = dev_get_drvdata(dev);
	503
	504	intel_lpss_init_dev(lpss);
	505
	506	return 0;
	507	}
	508	EXPORT_SYMBOL_GPL(intel_lpss_resume);
	509
	510	static int __init intel_lpss_init(void)
	511	{
	512	intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
	513	return 0;
	514	}
	515	module_init(intel_lpss_init);
	516
	517	static void __exit intel_lpss_exit(void)
	518	{
	519	debugfs_remove(intel_lpss_debugfs);
	520	}
521	module_exit(intel_lpss_exit);
522
523	MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
524	MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
525	MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
526	MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
527	MODULE_DESCRIPTION("Intel LPSS core driver");
528	MODULE_LICENSE("GPL v2");